Yan He | 50222ad | 2017-11-17 18:22:17 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | /* |
| 14 | * MSM PCIe PHY endpoint mode |
| 15 | */ |
| 16 | |
| 17 | #include "ep_pcie_com.h" |
| 18 | #include "ep_pcie_phy.h" |
| 19 | |
| 20 | void ep_pcie_phy_init(struct ep_pcie_dev_t *dev) |
| 21 | { |
| 22 | switch (dev->phy_rev) { |
| 23 | case 3: |
| 24 | EP_PCIE_DBG(dev, |
| 25 | "PCIe V%d: PHY V%d: Initializing 20nm QMP phy - 100MHz\n", |
| 26 | dev->rev, dev->phy_rev); |
| 27 | break; |
| 28 | case 4: |
| 29 | EP_PCIE_DBG(dev, |
| 30 | "PCIe V%d: PHY V%d: Initializing 14nm QMP phy - 100MHz\n", |
| 31 | dev->rev, dev->phy_rev); |
| 32 | break; |
| 33 | case 5: |
| 34 | EP_PCIE_DBG(dev, |
| 35 | "PCIe V%d: PHY V%d: Initializing 10nm QMP phy - 100MHz\n", |
| 36 | dev->rev, dev->phy_rev); |
| 37 | break; |
| 38 | default: |
| 39 | EP_PCIE_ERR(dev, |
| 40 | "PCIe V%d: Unexpected phy version %d is caught!\n", |
| 41 | dev->rev, dev->phy_rev); |
| 42 | } |
| 43 | |
| 44 | if (dev->phy_init_len && dev->phy_init) { |
| 45 | int i; |
| 46 | struct ep_pcie_phy_info_t *phy_init; |
| 47 | |
| 48 | EP_PCIE_DBG(dev, |
| 49 | "PCIe V%d: PHY V%d: process the sequence specified by DT.\n", |
| 50 | dev->rev, dev->phy_rev); |
| 51 | |
| 52 | i = dev->phy_init_len; |
| 53 | phy_init = dev->phy_init; |
| 54 | while (i--) { |
| 55 | ep_pcie_write_reg(dev->phy, |
| 56 | phy_init->offset, |
| 57 | phy_init->val); |
| 58 | if (phy_init->delay) |
| 59 | usleep_range(phy_init->delay, |
| 60 | phy_init->delay + 1); |
| 61 | phy_init++; |
| 62 | } |
| 63 | return; |
| 64 | } |
| 65 | |
| 66 | ep_pcie_write_reg(dev->phy, PCIE_PHY_SW_RESET, 0x01); |
| 67 | ep_pcie_write_reg(dev->phy, PCIE_PHY_POWER_DOWN_CONTROL, 0x01); |
| 68 | |
| 69 | /* Common block settings */ |
| 70 | ep_pcie_write_reg(dev->phy, QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18); |
| 71 | ep_pcie_write_reg(dev->phy, QSERDES_COM_CLK_ENABLE1, 0x00); |
| 72 | ep_pcie_write_reg(dev->phy, QSERDES_COM_BG_TRIM, 0x0F); |
| 73 | ep_pcie_write_reg(dev->phy, QSERDES_COM_LOCK_CMP_EN, 0x01); |
| 74 | ep_pcie_write_reg(dev->phy, QSERDES_COM_VCO_TUNE_MAP, 0x00); |
| 75 | ep_pcie_write_reg(dev->phy, QSERDES_COM_VCO_TUNE_TIMER1, 0xFF); |
| 76 | ep_pcie_write_reg(dev->phy, QSERDES_COM_VCO_TUNE_TIMER2, 0x1F); |
| 77 | ep_pcie_write_reg(dev->phy, QSERDES_COM_CMN_CONFIG, 0x06); |
| 78 | ep_pcie_write_reg(dev->phy, QSERDES_COM_PLL_IVCO, 0x0F); |
| 79 | ep_pcie_write_reg(dev->phy, QSERDES_COM_HSCLK_SEL, 0x00); |
| 80 | ep_pcie_write_reg(dev->phy, QSERDES_COM_SVS_MODE_CLK_SEL, 0x01); |
| 81 | ep_pcie_write_reg(dev->phy, QSERDES_COM_CORE_CLK_EN, 0x20); |
| 82 | ep_pcie_write_reg(dev->phy, QSERDES_COM_CORECLK_DIV, 0x0A); |
| 83 | ep_pcie_write_reg(dev->phy, QSERDES_COM_RESETSM_CNTRL, 0x20); |
| 84 | ep_pcie_write_reg(dev->phy, QSERDES_COM_BG_TIMER, 0x01); |
| 85 | |
| 86 | /* PLL Config Settings */ |
| 87 | ep_pcie_write_reg(dev->phy, QSERDES_COM_SYSCLK_EN_SEL, 0x00); |
| 88 | ep_pcie_write_reg(dev->phy, QSERDES_COM_DEC_START_MODE0, 0x19); |
| 89 | ep_pcie_write_reg(dev->phy, QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00); |
| 90 | ep_pcie_write_reg(dev->phy, QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00); |
| 91 | ep_pcie_write_reg(dev->phy, QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00); |
| 92 | ep_pcie_write_reg(dev->phy, QSERDES_COM_LOCK_CMP3_MODE0, 0x00); |
| 93 | ep_pcie_write_reg(dev->phy, QSERDES_COM_LOCK_CMP2_MODE0, 0x02); |
| 94 | ep_pcie_write_reg(dev->phy, QSERDES_COM_LOCK_CMP1_MODE0, 0x7F); |
| 95 | ep_pcie_write_reg(dev->phy, QSERDES_COM_CLK_SELECT, 0x30); |
| 96 | ep_pcie_write_reg(dev->phy, QSERDES_COM_SYS_CLK_CTRL, 0x06); |
| 97 | ep_pcie_write_reg(dev->phy, QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1E); |
| 98 | ep_pcie_write_reg(dev->phy, QSERDES_COM_CP_CTRL_MODE0, 0x3F); |
| 99 | ep_pcie_write_reg(dev->phy, QSERDES_COM_PLL_RCTRL_MODE0, 0x1A); |
| 100 | ep_pcie_write_reg(dev->phy, QSERDES_COM_PLL_CCTRL_MODE0, 0x00); |
| 101 | ep_pcie_write_reg(dev->phy, QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x03); |
| 102 | ep_pcie_write_reg(dev->phy, QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0xFF); |
| 103 | |
| 104 | /* TX settings */ |
| 105 | ep_pcie_write_reg(dev->phy, QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, |
| 106 | 0x45); |
| 107 | ep_pcie_write_reg(dev->phy, QSERDES_TX_LANE_MODE, 0x06); |
| 108 | ep_pcie_write_reg(dev->phy, QSERDES_TX_RES_CODE_LANE_OFFSET, 0x02); |
| 109 | ep_pcie_write_reg(dev->phy, QSERDES_TX_RCV_DETECT_LVL_2, 0x12); |
| 110 | |
| 111 | /* RX settings */ |
| 112 | ep_pcie_write_reg(dev->phy, QSERDES_RX_SIGDET_ENABLES, 0x1C); |
| 113 | ep_pcie_write_reg(dev->phy, QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14); |
| 114 | ep_pcie_write_reg(dev->phy, QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x01); |
| 115 | ep_pcie_write_reg(dev->phy, QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x00); |
| 116 | ep_pcie_write_reg(dev->phy, QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xDB); |
| 117 | ep_pcie_write_reg(dev->phy, QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, |
| 118 | 0x4B); |
| 119 | ep_pcie_write_reg(dev->phy, QSERDES_RX_UCDR_SO_GAIN, 0x04); |
| 120 | ep_pcie_write_reg(dev->phy, QSERDES_RX_UCDR_SO_GAIN_HALF, 0x04); |
| 121 | |
| 122 | /* EP_REF_CLK settings */ |
| 123 | ep_pcie_write_reg(dev->phy, QSERDES_COM_CLK_EP_DIV, 0x19); |
| 124 | ep_pcie_write_reg(dev->phy, PCIE_PHY_ENDPOINT_REFCLK_DRIVE, 0x00); |
| 125 | |
| 126 | /* PCIE L1SS settings */ |
| 127 | ep_pcie_write_reg(dev->phy, PCIE_PHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40); |
| 128 | ep_pcie_write_reg(dev->phy, PCIE_PHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, |
| 129 | 0x00); |
| 130 | ep_pcie_write_reg(dev->phy, PCIE_PHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, |
| 131 | 0x40); |
| 132 | ep_pcie_write_reg(dev->phy, PCIE_PHY_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, |
| 133 | 0x00); |
| 134 | ep_pcie_write_reg(dev->phy, PCIE_PHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40); |
| 135 | ep_pcie_write_reg(dev->phy, PCIE_PHY_PLL_LOCK_CHK_DLY_TIME, 0x73); |
| 136 | |
| 137 | /* PCS settings */ |
| 138 | ep_pcie_write_reg(dev->phy, PCIE_PHY_SIGDET_CNTRL, 0x07); |
| 139 | ep_pcie_write_reg(dev->phy, PCIE_PHY_RX_SIGDET_LVL, 0x99); |
| 140 | ep_pcie_write_reg(dev->phy, PCIE_PHY_TXDEEMPH_M6DB_V0, 0x15); |
| 141 | ep_pcie_write_reg(dev->phy, PCIE_PHY_TXDEEMPH_M3P5DB_V0, 0x0E); |
| 142 | |
| 143 | ep_pcie_write_reg(dev->phy, PCIE_PHY_SW_RESET, 0x00); |
| 144 | ep_pcie_write_reg(dev->phy, PCIE_PHY_START_CONTROL, 0x03); |
| 145 | } |
| 146 | |
| 147 | bool ep_pcie_phy_is_ready(struct ep_pcie_dev_t *dev) |
| 148 | { |
| 149 | u32 offset; |
| 150 | |
| 151 | if (dev->phy_status_reg) |
| 152 | offset = dev->phy_status_reg; |
| 153 | else |
| 154 | offset = PCIE_PHY_PCS_STATUS; |
| 155 | |
| 156 | if (readl_relaxed(dev->phy + offset) & BIT(6)) |
| 157 | return false; |
| 158 | else |
| 159 | return true; |
| 160 | } |