Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 1 | /* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | * |
| 12 | */ |
| 13 | |
| 14 | #include <linux/module.h> |
| 15 | #include <linux/interrupt.h> |
| 16 | #include <linux/spinlock.h> |
| 17 | #include <linux/delay.h> |
| 18 | #include <linux/io.h> |
| 19 | #include <linux/dma-mapping.h> |
| 20 | #include <linux/slab.h> |
| 21 | #include <linux/iopoll.h> |
| 22 | #include <linux/interrupt.h> |
| 23 | #include <linux/of_device.h> |
| 24 | |
| 25 | #include "dsi_v2.h" |
| 26 | #include "dsi_io_v2.h" |
| 27 | #include "dsi_host_v2.h" |
| 28 | #include "mdss_debug.h" |
| 29 | #include "mdp3.h" |
| 30 | |
| 31 | #define DSI_POLL_SLEEP_US 1000 |
| 32 | #define DSI_POLL_TIMEOUT_US 16000 |
| 33 | #define DSI_ESC_CLK_RATE 19200000 |
| 34 | #define DSI_DMA_CMD_TIMEOUT_MS 200 |
| 35 | #define VSYNC_PERIOD 17 |
| 36 | #define DSI_MAX_PKT_SIZE 10 |
| 37 | #define DSI_SHORT_PKT_DATA_SIZE 2 |
| 38 | #define DSI_MAX_BYTES_TO_READ 16 |
| 39 | |
| 40 | struct dsi_host_v2_private { |
| 41 | unsigned char *dsi_base; |
| 42 | size_t dsi_reg_size; |
| 43 | struct device dis_dev; |
| 44 | int clk_count; |
| 45 | int dsi_on; |
| 46 | |
| 47 | void (*debug_enable_clk)(int on); |
| 48 | }; |
| 49 | |
| 50 | static struct dsi_host_v2_private *dsi_host_private; |
| 51 | static int msm_dsi_clk_ctrl(struct mdss_panel_data *pdata, int enable); |
| 52 | |
| 53 | int msm_dsi_init(void) |
| 54 | { |
| 55 | if (!dsi_host_private) { |
| 56 | dsi_host_private = kzalloc(sizeof(struct dsi_host_v2_private), |
| 57 | GFP_KERNEL); |
| 58 | if (!dsi_host_private) |
| 59 | return -ENOMEM; |
| 60 | |
| 61 | } |
| 62 | |
| 63 | return 0; |
| 64 | } |
| 65 | |
| 66 | void msm_dsi_deinit(void) |
| 67 | { |
| 68 | kfree(dsi_host_private); |
| 69 | dsi_host_private = NULL; |
| 70 | } |
| 71 | |
| 72 | void msm_dsi_ack_err_status(unsigned char *ctrl_base) |
| 73 | { |
| 74 | u32 status; |
| 75 | |
| 76 | status = MIPI_INP(ctrl_base + DSI_ACK_ERR_STATUS); |
| 77 | |
| 78 | if (status) { |
| 79 | MIPI_OUTP(ctrl_base + DSI_ACK_ERR_STATUS, status); |
| 80 | |
| 81 | /* Writing of an extra 0 needed to clear error bits */ |
| 82 | MIPI_OUTP(ctrl_base + DSI_ACK_ERR_STATUS, 0); |
| 83 | pr_err("%s: status=%x\n", __func__, status); |
| 84 | } |
| 85 | } |
| 86 | |
| 87 | void msm_dsi_timeout_status(unsigned char *ctrl_base) |
| 88 | { |
| 89 | u32 status; |
| 90 | |
| 91 | status = MIPI_INP(ctrl_base + DSI_TIMEOUT_STATUS); |
| 92 | if (status & 0x0111) { |
| 93 | MIPI_OUTP(ctrl_base + DSI_TIMEOUT_STATUS, status); |
| 94 | pr_err("%s: status=%x\n", __func__, status); |
| 95 | } |
| 96 | } |
| 97 | |
| 98 | void msm_dsi_dln0_phy_err(unsigned char *ctrl_base) |
| 99 | { |
| 100 | u32 status; |
| 101 | |
| 102 | status = MIPI_INP(ctrl_base + DSI_DLN0_PHY_ERR); |
| 103 | |
| 104 | if (status & 0x011111) { |
| 105 | MIPI_OUTP(ctrl_base + DSI_DLN0_PHY_ERR, status); |
| 106 | pr_err("%s: status=%x\n", __func__, status); |
| 107 | } |
| 108 | } |
| 109 | |
| 110 | void msm_dsi_fifo_status(unsigned char *ctrl_base) |
| 111 | { |
| 112 | u32 status; |
| 113 | |
| 114 | status = MIPI_INP(ctrl_base + DSI_FIFO_STATUS); |
| 115 | |
| 116 | if (status & 0x44444489) { |
| 117 | MIPI_OUTP(ctrl_base + DSI_FIFO_STATUS, status); |
| 118 | pr_err("%s: status=%x\n", __func__, status); |
| 119 | } |
| 120 | } |
| 121 | |
| 122 | void msm_dsi_status(unsigned char *ctrl_base) |
| 123 | { |
| 124 | u32 status; |
| 125 | |
| 126 | status = MIPI_INP(ctrl_base + DSI_STATUS); |
| 127 | |
| 128 | if (status & 0x80000000) { |
| 129 | MIPI_OUTP(ctrl_base + DSI_STATUS, status); |
| 130 | pr_err("%s: status=%x\n", __func__, status); |
| 131 | } |
| 132 | } |
| 133 | |
| 134 | void msm_dsi_error(unsigned char *ctrl_base) |
| 135 | { |
| 136 | msm_dsi_ack_err_status(ctrl_base); |
| 137 | msm_dsi_timeout_status(ctrl_base); |
| 138 | msm_dsi_fifo_status(ctrl_base); |
| 139 | msm_dsi_status(ctrl_base); |
| 140 | msm_dsi_dln0_phy_err(ctrl_base); |
| 141 | } |
| 142 | |
| 143 | static void msm_dsi_set_irq_mask(struct mdss_dsi_ctrl_pdata *ctrl, u32 mask) |
| 144 | { |
| 145 | u32 intr_ctrl; |
| 146 | |
| 147 | intr_ctrl = MIPI_INP(dsi_host_private->dsi_base + DSI_INT_CTRL); |
| 148 | intr_ctrl |= mask; |
| 149 | MIPI_OUTP(dsi_host_private->dsi_base + DSI_INT_CTRL, intr_ctrl); |
| 150 | } |
| 151 | |
| 152 | static void msm_dsi_clear_irq_mask(struct mdss_dsi_ctrl_pdata *ctrl, u32 mask) |
| 153 | { |
| 154 | u32 intr_ctrl; |
| 155 | |
| 156 | intr_ctrl = MIPI_INP(dsi_host_private->dsi_base + DSI_INT_CTRL); |
| 157 | intr_ctrl &= ~mask; |
| 158 | MIPI_OUTP(dsi_host_private->dsi_base + DSI_INT_CTRL, intr_ctrl); |
| 159 | } |
| 160 | |
| 161 | static void msm_dsi_set_irq(struct mdss_dsi_ctrl_pdata *ctrl, u32 mask) |
| 162 | { |
| 163 | unsigned long flags; |
| 164 | |
| 165 | spin_lock_irqsave(&ctrl->irq_lock, flags); |
| 166 | if (ctrl->dsi_irq_mask & mask) { |
| 167 | spin_unlock_irqrestore(&ctrl->irq_lock, flags); |
| 168 | return; |
| 169 | } |
| 170 | if (ctrl->dsi_irq_mask == 0) { |
| 171 | ctrl->mdss_util->enable_irq(ctrl->dsi_hw); |
| 172 | pr_debug("%s: IRQ Enable, mask=%x term=%x\n", __func__, |
| 173 | (int)ctrl->dsi_irq_mask, (int)mask); |
| 174 | } |
| 175 | |
| 176 | msm_dsi_set_irq_mask(ctrl, mask); |
| 177 | ctrl->dsi_irq_mask |= mask; |
| 178 | spin_unlock_irqrestore(&ctrl->irq_lock, flags); |
| 179 | } |
| 180 | |
| 181 | static void msm_dsi_clear_irq(struct mdss_dsi_ctrl_pdata *ctrl, u32 mask) |
| 182 | { |
| 183 | unsigned long flags; |
| 184 | |
| 185 | spin_lock_irqsave(&ctrl->irq_lock, flags); |
| 186 | if (!(ctrl->dsi_irq_mask & mask)) { |
| 187 | spin_unlock_irqrestore(&ctrl->irq_lock, flags); |
| 188 | return; |
| 189 | } |
| 190 | ctrl->dsi_irq_mask &= ~mask; |
| 191 | if (ctrl->dsi_irq_mask == 0) { |
| 192 | ctrl->mdss_util->disable_irq(ctrl->dsi_hw); |
| 193 | pr_debug("%s: IRQ Disable, mask=%x term=%x\n", __func__, |
| 194 | (int)ctrl->dsi_irq_mask, (int)mask); |
| 195 | } |
| 196 | msm_dsi_clear_irq_mask(ctrl, mask); |
| 197 | spin_unlock_irqrestore(&ctrl->irq_lock, flags); |
| 198 | } |
| 199 | |
| 200 | irqreturn_t msm_dsi_isr_handler(int irq, void *ptr) |
| 201 | { |
| 202 | u32 isr; |
| 203 | |
| 204 | struct mdss_dsi_ctrl_pdata *ctrl = |
| 205 | (struct mdss_dsi_ctrl_pdata *)ptr; |
| 206 | |
| 207 | spin_lock(&ctrl->mdp_lock); |
| 208 | |
| 209 | if (ctrl->dsi_irq_mask == 0) { |
| 210 | spin_unlock(&ctrl->mdp_lock); |
| 211 | return IRQ_HANDLED; |
| 212 | } |
| 213 | |
| 214 | isr = MIPI_INP(dsi_host_private->dsi_base + DSI_INT_CTRL); |
| 215 | MIPI_OUTP(dsi_host_private->dsi_base + DSI_INT_CTRL, isr); |
| 216 | |
| 217 | pr_debug("%s: isr=%x", __func__, isr); |
| 218 | |
| 219 | if (isr & DSI_INTR_ERROR) { |
| 220 | pr_err("%s: isr=%x %x", __func__, isr, (int)DSI_INTR_ERROR); |
| 221 | msm_dsi_error(dsi_host_private->dsi_base); |
| 222 | } |
| 223 | |
| 224 | if (isr & DSI_INTR_VIDEO_DONE) |
| 225 | complete(&ctrl->video_comp); |
| 226 | |
| 227 | if (isr & DSI_INTR_CMD_DMA_DONE) |
| 228 | complete(&ctrl->dma_comp); |
| 229 | |
| 230 | if (isr & DSI_INTR_BTA_DONE) |
| 231 | complete(&ctrl->bta_comp); |
| 232 | |
| 233 | if (isr & DSI_INTR_CMD_MDP_DONE) |
| 234 | complete(&ctrl->mdp_comp); |
| 235 | |
| 236 | spin_unlock(&ctrl->mdp_lock); |
| 237 | |
| 238 | return IRQ_HANDLED; |
| 239 | } |
| 240 | |
| 241 | int msm_dsi_irq_init(struct device *dev, int irq_no, |
| 242 | struct mdss_dsi_ctrl_pdata *ctrl) |
| 243 | { |
| 244 | int ret; |
| 245 | u32 isr; |
| 246 | struct mdss_hw *dsi_hw; |
| 247 | |
| 248 | msm_dsi_ahb_ctrl(1); |
| 249 | isr = MIPI_INP(dsi_host_private->dsi_base + DSI_INT_CTRL); |
| 250 | isr &= ~DSI_INTR_ALL_MASK; |
| 251 | MIPI_OUTP(dsi_host_private->dsi_base + DSI_INT_CTRL, isr); |
| 252 | msm_dsi_ahb_ctrl(0); |
| 253 | |
| 254 | ret = devm_request_irq(dev, irq_no, msm_dsi_isr_handler, |
| 255 | IRQF_DISABLED, "DSI", ctrl); |
| 256 | if (ret) { |
| 257 | pr_err("msm_dsi_irq_init request_irq() failed!\n"); |
| 258 | return ret; |
| 259 | } |
| 260 | |
| 261 | dsi_hw = kzalloc(sizeof(struct mdss_hw), GFP_KERNEL); |
| 262 | if (!dsi_hw) |
| 263 | return -ENOMEM; |
| 264 | |
| 265 | ctrl->dsi_hw = dsi_hw; |
| 266 | |
| 267 | dsi_hw->irq_info = kzalloc(sizeof(struct irq_info), GFP_KERNEL); |
| 268 | if (!dsi_hw->irq_info) { |
| 269 | kfree(dsi_hw); |
| 270 | pr_err("no mem to save irq info: kzalloc fail\n"); |
| 271 | return -ENOMEM; |
| 272 | } |
| 273 | |
| 274 | dsi_hw->hw_ndx = MDSS_HW_DSI0; |
| 275 | dsi_hw->irq_info->irq = irq_no; |
| 276 | dsi_hw->irq_info->irq_mask = 0; |
| 277 | dsi_hw->irq_info->irq_ena = false; |
| 278 | dsi_hw->irq_info->irq_buzy = false; |
| 279 | |
| 280 | ctrl->mdss_util->register_irq(ctrl->dsi_hw); |
| 281 | ctrl->mdss_util->disable_irq(ctrl->dsi_hw); |
| 282 | |
| 283 | return 0; |
| 284 | } |
| 285 | |
| 286 | static void msm_dsi_get_cmd_engine(struct mdss_dsi_ctrl_pdata *ctrl) |
| 287 | { |
| 288 | unsigned char *ctrl_base = dsi_host_private->dsi_base; |
| 289 | u32 dsi_ctrl; |
| 290 | |
| 291 | if (ctrl->panel_mode == DSI_VIDEO_MODE) { |
| 292 | dsi_ctrl = MIPI_INP(ctrl_base + DSI_CTRL); |
| 293 | MIPI_OUTP(ctrl_base + DSI_CTRL, dsi_ctrl | 0x04); |
| 294 | } |
| 295 | } |
| 296 | |
| 297 | static void msm_dsi_release_cmd_engine(struct mdss_dsi_ctrl_pdata *ctrl) |
| 298 | { |
| 299 | unsigned char *ctrl_base = dsi_host_private->dsi_base; |
| 300 | u32 dsi_ctrl; |
| 301 | |
| 302 | if (ctrl->panel_mode == DSI_VIDEO_MODE) { |
| 303 | dsi_ctrl = MIPI_INP(ctrl_base + DSI_CTRL); |
| 304 | dsi_ctrl &= ~0x04; |
| 305 | MIPI_OUTP(ctrl_base + DSI_CTRL, dsi_ctrl); |
| 306 | } |
| 307 | } |
| 308 | |
| 309 | static int msm_dsi_wait4mdp_done(struct mdss_dsi_ctrl_pdata *ctrl) |
| 310 | { |
| 311 | int rc; |
| 312 | unsigned long flag; |
| 313 | |
| 314 | spin_lock_irqsave(&ctrl->mdp_lock, flag); |
| 315 | reinit_completion(&ctrl->mdp_comp); |
| 316 | msm_dsi_set_irq(ctrl, DSI_INTR_CMD_MDP_DONE_MASK); |
| 317 | spin_unlock_irqrestore(&ctrl->mdp_lock, flag); |
| 318 | |
| 319 | rc = wait_for_completion_timeout(&ctrl->mdp_comp, |
| 320 | msecs_to_jiffies(VSYNC_PERIOD * 4)); |
| 321 | |
| 322 | if (rc == 0) { |
| 323 | pr_err("DSI wait 4 mdp done time out\n"); |
| 324 | rc = -ETIME; |
| 325 | } else if (!IS_ERR_VALUE(rc)) { |
| 326 | rc = 0; |
| 327 | } |
| 328 | |
| 329 | msm_dsi_clear_irq(ctrl, DSI_INTR_CMD_MDP_DONE_MASK); |
| 330 | |
| 331 | return rc; |
| 332 | } |
| 333 | |
| 334 | void msm_dsi_cmd_mdp_busy(struct mdss_dsi_ctrl_pdata *ctrl) |
| 335 | { |
| 336 | int rc; |
| 337 | u32 dsi_status; |
| 338 | unsigned char *ctrl_base = dsi_host_private->dsi_base; |
| 339 | |
| 340 | if (ctrl->panel_mode == DSI_VIDEO_MODE) |
| 341 | return; |
| 342 | |
| 343 | dsi_status = MIPI_INP(ctrl_base + DSI_STATUS); |
| 344 | if (dsi_status & 0x04) { |
| 345 | pr_debug("dsi command engine is busy\n"); |
| 346 | rc = msm_dsi_wait4mdp_done(ctrl); |
| 347 | if (rc) |
| 348 | pr_err("Timed out waiting for mdp done"); |
| 349 | } |
| 350 | } |
| 351 | |
| 352 | static int msm_dsi_wait4video_done(struct mdss_dsi_ctrl_pdata *ctrl) |
| 353 | { |
| 354 | int rc; |
| 355 | unsigned long flag; |
| 356 | |
| 357 | spin_lock_irqsave(&ctrl->mdp_lock, flag); |
| 358 | reinit_completion(&ctrl->video_comp); |
| 359 | msm_dsi_set_irq(ctrl, DSI_INTR_VIDEO_DONE_MASK); |
| 360 | spin_unlock_irqrestore(&ctrl->mdp_lock, flag); |
| 361 | |
| 362 | rc = wait_for_completion_timeout(&ctrl->video_comp, |
| 363 | msecs_to_jiffies(VSYNC_PERIOD * 4)); |
| 364 | |
| 365 | if (rc == 0) { |
| 366 | pr_err("DSI wait 4 video done time out\n"); |
| 367 | rc = -ETIME; |
| 368 | } else if (!IS_ERR_VALUE(rc)) { |
| 369 | rc = 0; |
| 370 | } |
| 371 | |
| 372 | msm_dsi_clear_irq(ctrl, DSI_INTR_VIDEO_DONE_MASK); |
| 373 | |
| 374 | return rc; |
| 375 | } |
| 376 | |
| 377 | static int msm_dsi_wait4video_eng_busy(struct mdss_dsi_ctrl_pdata *ctrl) |
| 378 | { |
| 379 | int rc = 0; |
| 380 | u32 dsi_status; |
| 381 | unsigned char *ctrl_base = dsi_host_private->dsi_base; |
| 382 | |
| 383 | if (ctrl->panel_mode == DSI_CMD_MODE) |
| 384 | return rc; |
| 385 | |
| 386 | dsi_status = MIPI_INP(ctrl_base + DSI_STATUS); |
| 387 | if (dsi_status & 0x08) { |
| 388 | pr_debug("dsi command in video mode wait for active region\n"); |
| 389 | rc = msm_dsi_wait4video_done(ctrl); |
| 390 | /* delay 4-5 ms to skip BLLP */ |
| 391 | if (!rc) |
| 392 | usleep_range(4000, 5000); |
| 393 | } |
| 394 | return rc; |
| 395 | } |
| 396 | |
| 397 | void msm_dsi_host_init(struct mdss_panel_data *pdata) |
| 398 | { |
| 399 | u32 dsi_ctrl, data; |
| 400 | unsigned char *ctrl_base = dsi_host_private->dsi_base; |
| 401 | struct mdss_dsi_ctrl_pdata *ctrl_pdata = NULL; |
| 402 | struct mipi_panel_info *pinfo; |
| 403 | |
| 404 | pr_debug("msm_dsi_host_init\n"); |
| 405 | |
| 406 | ctrl_pdata = container_of(pdata, struct mdss_dsi_ctrl_pdata, |
| 407 | panel_data); |
| 408 | pinfo = &pdata->panel_info.mipi; |
| 409 | |
| 410 | |
| 411 | if (pinfo->mode == DSI_VIDEO_MODE) { |
| 412 | data = 0; |
| 413 | if (pinfo->pulse_mode_hsa_he) |
| 414 | data |= BIT(28); |
| 415 | if (pinfo->hfp_power_stop) |
| 416 | data |= BIT(24); |
| 417 | if (pinfo->hbp_power_stop) |
| 418 | data |= BIT(20); |
| 419 | if (pinfo->hsa_power_stop) |
| 420 | data |= BIT(16); |
| 421 | if (pinfo->eof_bllp_power_stop) |
| 422 | data |= BIT(15); |
| 423 | if (pinfo->bllp_power_stop) |
| 424 | data |= BIT(12); |
| 425 | data |= ((pinfo->traffic_mode & 0x03) << 8); |
| 426 | data |= ((pinfo->dst_format & 0x03) << 4); /* 2 bits */ |
| 427 | data |= (pinfo->vc & 0x03); |
| 428 | MIPI_OUTP(ctrl_base + DSI_VIDEO_MODE_CTRL, data); |
| 429 | |
| 430 | data = 0; |
| 431 | data |= ((pinfo->rgb_swap & 0x07) << 12); |
| 432 | if (pinfo->b_sel) |
| 433 | data |= BIT(8); |
| 434 | if (pinfo->g_sel) |
| 435 | data |= BIT(4); |
| 436 | if (pinfo->r_sel) |
| 437 | data |= BIT(0); |
| 438 | MIPI_OUTP(ctrl_base + DSI_VIDEO_MODE_DATA_CTRL, data); |
| 439 | } else if (pinfo->mode == DSI_CMD_MODE) { |
| 440 | data = 0; |
| 441 | data |= ((pinfo->interleave_max & 0x0f) << 20); |
| 442 | data |= ((pinfo->rgb_swap & 0x07) << 16); |
| 443 | if (pinfo->b_sel) |
| 444 | data |= BIT(12); |
| 445 | if (pinfo->g_sel) |
| 446 | data |= BIT(8); |
| 447 | if (pinfo->r_sel) |
| 448 | data |= BIT(4); |
| 449 | data |= (pinfo->dst_format & 0x0f); /* 4 bits */ |
| 450 | MIPI_OUTP(ctrl_base + DSI_COMMAND_MODE_MDP_CTRL, data); |
| 451 | |
| 452 | /* DSI_COMMAND_MODE_MDP_DCS_CMD_CTRL */ |
| 453 | data = pinfo->wr_mem_continue & 0x0ff; |
| 454 | data <<= 8; |
| 455 | data |= (pinfo->wr_mem_start & 0x0ff); |
| 456 | if (pinfo->insert_dcs_cmd) |
| 457 | data |= BIT(16); |
| 458 | MIPI_OUTP(ctrl_base + DSI_COMMAND_MODE_MDP_DCS_CMD_CTRL, |
| 459 | data); |
| 460 | } else |
| 461 | pr_err("%s: Unknown DSI mode=%d\n", __func__, pinfo->mode); |
| 462 | |
| 463 | dsi_ctrl = BIT(8) | BIT(2); /* clock enable & cmd mode */ |
| 464 | |
| 465 | if (pinfo->crc_check) |
| 466 | dsi_ctrl |= BIT(24); |
| 467 | if (pinfo->ecc_check) |
| 468 | dsi_ctrl |= BIT(20); |
| 469 | if (pinfo->data_lane3) |
| 470 | dsi_ctrl |= BIT(7); |
| 471 | if (pinfo->data_lane2) |
| 472 | dsi_ctrl |= BIT(6); |
| 473 | if (pinfo->data_lane1) |
| 474 | dsi_ctrl |= BIT(5); |
| 475 | if (pinfo->data_lane0) |
| 476 | dsi_ctrl |= BIT(4); |
| 477 | |
| 478 | /* from frame buffer, low power mode */ |
| 479 | /* DSI_COMMAND_MODE_DMA_CTRL */ |
| 480 | MIPI_OUTP(ctrl_base + DSI_COMMAND_MODE_DMA_CTRL, 0x14000000); |
| 481 | |
| 482 | data = 0; |
| 483 | if (pinfo->te_sel) |
| 484 | data |= BIT(31); |
| 485 | data |= pinfo->mdp_trigger << 4;/* cmd mdp trigger */ |
| 486 | data |= pinfo->dma_trigger; /* cmd dma trigger */ |
| 487 | data |= (pinfo->stream & 0x01) << 8; |
| 488 | MIPI_OUTP(ctrl_base + DSI_TRIG_CTRL, data); |
| 489 | |
| 490 | /* DSI_LAN_SWAP_CTRL */ |
| 491 | MIPI_OUTP(ctrl_base + DSI_LANE_SWAP_CTRL, ctrl_pdata->dlane_swap); |
| 492 | |
| 493 | /* clock out ctrl */ |
| 494 | data = pinfo->t_clk_post & 0x3f; /* 6 bits */ |
| 495 | data <<= 8; |
| 496 | data |= pinfo->t_clk_pre & 0x3f; /* 6 bits */ |
| 497 | /* DSI_CLKOUT_TIMING_CTRL */ |
| 498 | MIPI_OUTP(ctrl_base + DSI_CLKOUT_TIMING_CTRL, data); |
| 499 | |
| 500 | data = 0; |
| 501 | if (pinfo->rx_eot_ignore) |
| 502 | data |= BIT(4); |
| 503 | if (pinfo->tx_eot_append) |
| 504 | data |= BIT(0); |
| 505 | MIPI_OUTP(ctrl_base + DSI_EOT_PACKET_CTRL, data); |
| 506 | |
| 507 | |
| 508 | /* allow only ack-err-status to generate interrupt */ |
| 509 | /* DSI_ERR_INT_MASK0 */ |
| 510 | MIPI_OUTP(ctrl_base + DSI_ERR_INT_MASK0, 0x13ff3fe0); |
| 511 | |
| 512 | /* turn esc, byte, dsi, pclk, sclk, hclk on */ |
| 513 | MIPI_OUTP(ctrl_base + DSI_CLK_CTRL, 0x23f); |
| 514 | |
| 515 | dsi_ctrl |= BIT(0); /* enable dsi */ |
| 516 | MIPI_OUTP(ctrl_base + DSI_CTRL, dsi_ctrl); |
| 517 | |
| 518 | wmb(); /* ensure write is finished before progressing */ |
| 519 | } |
| 520 | |
| 521 | void dsi_set_tx_power_mode(int mode) |
| 522 | { |
| 523 | u32 data; |
| 524 | unsigned char *ctrl_base = dsi_host_private->dsi_base; |
| 525 | |
| 526 | data = MIPI_INP(ctrl_base + DSI_COMMAND_MODE_DMA_CTRL); |
| 527 | |
| 528 | if (mode == 0) |
| 529 | data &= ~BIT(26); |
| 530 | else |
| 531 | data |= BIT(26); |
| 532 | |
| 533 | MIPI_OUTP(ctrl_base + DSI_COMMAND_MODE_DMA_CTRL, data); |
| 534 | } |
| 535 | |
| 536 | void msm_dsi_sw_reset(void) |
| 537 | { |
| 538 | u32 dsi_ctrl; |
| 539 | unsigned char *ctrl_base = dsi_host_private->dsi_base; |
| 540 | |
| 541 | pr_debug("msm_dsi_sw_reset\n"); |
| 542 | |
| 543 | dsi_ctrl = MIPI_INP(ctrl_base + DSI_CTRL); |
| 544 | dsi_ctrl &= ~0x01; |
| 545 | MIPI_OUTP(ctrl_base + DSI_CTRL, dsi_ctrl); |
| 546 | wmb(); /* ensure write is finished before progressing */ |
| 547 | |
| 548 | /* turn esc, byte, dsi, pclk, sclk, hclk on */ |
| 549 | MIPI_OUTP(ctrl_base + DSI_CLK_CTRL, 0x23f); |
| 550 | wmb(); /* ensure write is finished before progressing */ |
| 551 | |
| 552 | MIPI_OUTP(ctrl_base + DSI_SOFT_RESET, 0x01); |
| 553 | wmb(); /* ensure write is finished before progressing */ |
| 554 | MIPI_OUTP(ctrl_base + DSI_SOFT_RESET, 0x00); |
| 555 | wmb(); /* ensure write is finished before progressing */ |
| 556 | } |
| 557 | |
| 558 | void msm_dsi_controller_cfg(int enable) |
| 559 | { |
| 560 | u32 dsi_ctrl, status; |
| 561 | unsigned char *ctrl_base = dsi_host_private->dsi_base; |
| 562 | |
| 563 | pr_debug("msm_dsi_controller_cfg\n"); |
| 564 | |
| 565 | /* Check for CMD_MODE_DMA_BUSY */ |
| 566 | if (readl_poll_timeout((ctrl_base + DSI_STATUS), |
| 567 | status, |
| 568 | ((status & 0x02) == 0), |
| 569 | DSI_POLL_SLEEP_US, DSI_POLL_TIMEOUT_US)) { |
| 570 | pr_err("%s: DSI status=%x failed\n", __func__, status); |
| 571 | pr_err("%s: Doing sw reset\n", __func__); |
| 572 | msm_dsi_sw_reset(); |
| 573 | } |
| 574 | |
| 575 | /* Check for x_HS_FIFO_EMPTY */ |
| 576 | if (readl_poll_timeout((ctrl_base + DSI_FIFO_STATUS), |
| 577 | status, |
| 578 | ((status & 0x11111000) == 0x11111000), |
| 579 | DSI_POLL_SLEEP_US, DSI_POLL_TIMEOUT_US)) |
| 580 | pr_err("%s: FIFO status=%x failed\n", __func__, status); |
| 581 | |
| 582 | /* Check for VIDEO_MODE_ENGINE_BUSY */ |
| 583 | if (readl_poll_timeout((ctrl_base + DSI_STATUS), |
| 584 | status, |
| 585 | ((status & 0x08) == 0), |
| 586 | DSI_POLL_SLEEP_US, DSI_POLL_TIMEOUT_US)) { |
| 587 | pr_err("%s: DSI status=%x\n", __func__, status); |
| 588 | pr_err("%s: Doing sw reset\n", __func__); |
| 589 | msm_dsi_sw_reset(); |
| 590 | } |
| 591 | |
| 592 | dsi_ctrl = MIPI_INP(ctrl_base + DSI_CTRL); |
| 593 | if (enable) |
| 594 | dsi_ctrl |= 0x01; |
| 595 | else |
| 596 | dsi_ctrl &= ~0x01; |
| 597 | |
| 598 | MIPI_OUTP(ctrl_base + DSI_CTRL, dsi_ctrl); |
| 599 | wmb(); /* ensure write is finished before progressing */ |
| 600 | } |
| 601 | |
| 602 | void msm_dsi_op_mode_config(int mode, struct mdss_panel_data *pdata) |
| 603 | { |
| 604 | u32 dsi_ctrl; |
| 605 | unsigned char *ctrl_base = dsi_host_private->dsi_base; |
| 606 | |
| 607 | pr_debug("msm_dsi_op_mode_config\n"); |
| 608 | |
| 609 | dsi_ctrl = MIPI_INP(ctrl_base + DSI_CTRL); |
| 610 | |
| 611 | if (dsi_ctrl & DSI_VIDEO_MODE_EN) |
| 612 | dsi_ctrl &= ~(DSI_CMD_MODE_EN|DSI_EN); |
| 613 | else |
| 614 | dsi_ctrl &= ~(DSI_CMD_MODE_EN|DSI_VIDEO_MODE_EN|DSI_EN); |
| 615 | |
| 616 | if (mode == DSI_VIDEO_MODE) { |
| 617 | dsi_ctrl |= (DSI_VIDEO_MODE_EN|DSI_EN); |
| 618 | } else { |
| 619 | dsi_ctrl |= (DSI_CMD_MODE_EN|DSI_EN); |
| 620 | /* For Video mode panel, keep Video and Cmd mode ON */ |
| 621 | if (pdata->panel_info.type == MIPI_VIDEO_PANEL) |
| 622 | dsi_ctrl |= DSI_VIDEO_MODE_EN; |
| 623 | } |
| 624 | |
| 625 | pr_debug("%s: dsi_ctrl=%x\n", __func__, dsi_ctrl); |
| 626 | |
| 627 | MIPI_OUTP(ctrl_base + DSI_CTRL, dsi_ctrl); |
| 628 | wmb(); /* ensure write is finished before progressing */ |
| 629 | } |
| 630 | |
| 631 | int msm_dsi_cmd_dma_tx(struct mdss_dsi_ctrl_pdata *ctrl, |
| 632 | struct dsi_buf *tp) |
| 633 | { |
| 634 | int len, rc; |
| 635 | unsigned long size, addr; |
| 636 | unsigned char *ctrl_base = dsi_host_private->dsi_base; |
| 637 | unsigned long flag; |
| 638 | |
| 639 | len = ALIGN(tp->len, 4); |
| 640 | size = ALIGN(tp->len, SZ_4K); |
| 641 | |
| 642 | tp->dmap = dma_map_single(&dsi_host_private->dis_dev, tp->data, size, |
| 643 | DMA_TO_DEVICE); |
| 644 | if (dma_mapping_error(&dsi_host_private->dis_dev, tp->dmap)) { |
| 645 | pr_err("%s: dmap mapp failed\n", __func__); |
| 646 | return -ENOMEM; |
| 647 | } |
| 648 | |
| 649 | addr = tp->dmap; |
| 650 | |
| 651 | msm_dsi_get_cmd_engine(ctrl); |
| 652 | |
| 653 | spin_lock_irqsave(&ctrl->mdp_lock, flag); |
| 654 | reinit_completion(&ctrl->dma_comp); |
| 655 | msm_dsi_set_irq(ctrl, DSI_INTR_CMD_DMA_DONE_MASK); |
| 656 | spin_unlock_irqrestore(&ctrl->mdp_lock, flag); |
| 657 | |
| 658 | MIPI_OUTP(ctrl_base + DSI_DMA_CMD_OFFSET, addr); |
| 659 | MIPI_OUTP(ctrl_base + DSI_DMA_CMD_LENGTH, len); |
| 660 | wmb(); /* ensure write is finished before progressing */ |
| 661 | |
| 662 | MIPI_OUTP(ctrl_base + DSI_CMD_MODE_DMA_SW_TRIGGER, 0x01); |
| 663 | wmb(); /* ensure write is finished before progressing */ |
| 664 | |
| 665 | rc = wait_for_completion_timeout(&ctrl->dma_comp, |
| 666 | msecs_to_jiffies(DSI_DMA_CMD_TIMEOUT_MS)); |
| 667 | if (rc == 0) { |
| 668 | pr_err("DSI command transaction time out\n"); |
| 669 | rc = -ETIME; |
| 670 | } else if (!IS_ERR_VALUE(rc)) { |
| 671 | rc = 0; |
| 672 | } |
| 673 | |
| 674 | dma_unmap_single(&dsi_host_private->dis_dev, tp->dmap, size, |
| 675 | DMA_TO_DEVICE); |
| 676 | tp->dmap = 0; |
| 677 | |
| 678 | msm_dsi_clear_irq(ctrl, DSI_INTR_CMD_DMA_DONE_MASK); |
| 679 | |
| 680 | msm_dsi_release_cmd_engine(ctrl); |
| 681 | |
| 682 | return rc; |
| 683 | } |
| 684 | |
| 685 | int msm_dsi_cmd_dma_rx(struct mdss_dsi_ctrl_pdata *ctrl, |
| 686 | struct dsi_buf *rp, int rlen) |
| 687 | { |
| 688 | u32 *lp, data; |
| 689 | int i, off, cnt; |
| 690 | unsigned char *ctrl_base = dsi_host_private->dsi_base; |
| 691 | |
| 692 | lp = (u32 *)rp->data; |
| 693 | cnt = rlen; |
| 694 | cnt += 3; |
| 695 | cnt >>= 2; |
| 696 | |
| 697 | if (cnt > 4) |
| 698 | cnt = 4; /* 4 x 32 bits registers only */ |
| 699 | |
| 700 | off = DSI_RDBK_DATA0; |
| 701 | off += ((cnt - 1) * 4); |
| 702 | |
| 703 | for (i = 0; i < cnt; i++) { |
| 704 | data = (u32)MIPI_INP(ctrl_base + off); |
| 705 | *lp++ = ntohl(data); /* to network byte order */ |
| 706 | pr_debug("%s: data = 0x%x and ntohl(data) = 0x%x\n", |
| 707 | __func__, data, ntohl(data)); |
| 708 | off -= 4; |
| 709 | rp->len += sizeof(*lp); |
| 710 | } |
| 711 | |
| 712 | return rlen; |
| 713 | } |
| 714 | |
| 715 | static int msm_dsi_cmds_tx(struct mdss_dsi_ctrl_pdata *ctrl, |
| 716 | struct dsi_cmd_desc *cmds, int cnt) |
| 717 | { |
| 718 | struct dsi_buf *tp; |
| 719 | struct dsi_cmd_desc *cm; |
| 720 | struct dsi_ctrl_hdr *dchdr; |
| 721 | int len; |
| 722 | int rc = 0; |
| 723 | |
| 724 | tp = &ctrl->tx_buf; |
| 725 | mdss_dsi_buf_init(tp); |
| 726 | cm = cmds; |
| 727 | len = 0; |
| 728 | while (cnt--) { |
| 729 | dchdr = &cm->dchdr; |
| 730 | mdss_dsi_buf_reserve(tp, len); |
| 731 | len = mdss_dsi_cmd_dma_add(tp, cm); |
| 732 | if (!len) { |
| 733 | pr_err("%s: failed to add cmd = 0x%x\n", |
| 734 | __func__, cm->payload[0]); |
| 735 | rc = -EINVAL; |
| 736 | goto dsi_cmds_tx_err; |
| 737 | } |
| 738 | |
| 739 | if (dchdr->last) { |
| 740 | tp->data = tp->start; /* begin of buf */ |
| 741 | rc = msm_dsi_wait4video_eng_busy(ctrl); |
| 742 | if (rc) { |
| 743 | pr_err("%s: wait4video_eng failed\n", __func__); |
| 744 | goto dsi_cmds_tx_err; |
| 745 | |
| 746 | } |
| 747 | |
| 748 | rc = msm_dsi_cmd_dma_tx(ctrl, tp); |
| 749 | if (IS_ERR_VALUE(len)) { |
| 750 | pr_err("%s: failed to call cmd_dma_tx for cmd = 0x%x\n", |
| 751 | __func__, cmds->payload[0]); |
| 752 | goto dsi_cmds_tx_err; |
| 753 | } |
| 754 | |
| 755 | if (dchdr->wait) |
| 756 | usleep_range(dchdr->wait * 1000, |
| 757 | dchdr->wait * 1000); |
| 758 | |
| 759 | mdss_dsi_buf_init(tp); |
| 760 | len = 0; |
| 761 | } |
| 762 | cm++; |
| 763 | } |
| 764 | |
| 765 | dsi_cmds_tx_err: |
| 766 | return rc; |
| 767 | } |
| 768 | |
| 769 | static int msm_dsi_parse_rx_response(struct dsi_buf *rp) |
| 770 | { |
| 771 | int rc = 0; |
| 772 | unsigned char cmd; |
| 773 | |
| 774 | cmd = rp->data[0]; |
| 775 | switch (cmd) { |
| 776 | case DTYPE_ACK_ERR_RESP: |
| 777 | pr_debug("%s: rx ACK_ERR_PACLAGE\n", __func__); |
| 778 | rc = -EINVAL; |
| 779 | break; |
| 780 | case DTYPE_GEN_READ1_RESP: |
| 781 | case DTYPE_DCS_READ1_RESP: |
| 782 | mdss_dsi_short_read1_resp(rp); |
| 783 | break; |
| 784 | case DTYPE_GEN_READ2_RESP: |
| 785 | case DTYPE_DCS_READ2_RESP: |
| 786 | mdss_dsi_short_read2_resp(rp); |
| 787 | break; |
| 788 | case DTYPE_GEN_LREAD_RESP: |
| 789 | case DTYPE_DCS_LREAD_RESP: |
| 790 | mdss_dsi_long_read_resp(rp); |
| 791 | break; |
| 792 | default: |
| 793 | rc = -EINVAL; |
| 794 | pr_warn("%s: Unknown cmd received\n", __func__); |
| 795 | break; |
| 796 | } |
| 797 | |
| 798 | return rc; |
| 799 | } |
| 800 | |
| 801 | /* MIPI_DSI_MRPS, Maximum Return Packet Size */ |
| 802 | static char max_pktsize[2] = {0x00, 0x00}; /* LSB tx first, 10 bytes */ |
| 803 | |
| 804 | static struct dsi_cmd_desc pkt_size_cmd = { |
| 805 | {DTYPE_MAX_PKTSIZE, 1, 0, 0, 0, sizeof(max_pktsize)}, |
| 806 | max_pktsize, |
| 807 | }; |
| 808 | |
| 809 | static int msm_dsi_set_max_packet_size(struct mdss_dsi_ctrl_pdata *ctrl, |
| 810 | int size) |
| 811 | { |
| 812 | struct dsi_buf *tp; |
| 813 | int rc; |
| 814 | |
| 815 | tp = &ctrl->tx_buf; |
| 816 | mdss_dsi_buf_init(tp); |
| 817 | max_pktsize[0] = size; |
| 818 | |
| 819 | rc = mdss_dsi_cmd_dma_add(tp, &pkt_size_cmd); |
| 820 | if (!rc) { |
| 821 | pr_err("%s: failed to add max_pkt_size\n", __func__); |
| 822 | return -EINVAL; |
| 823 | } |
| 824 | |
| 825 | rc = msm_dsi_wait4video_eng_busy(ctrl); |
| 826 | if (rc) { |
| 827 | pr_err("%s: failed to wait4video_eng\n", __func__); |
| 828 | return rc; |
| 829 | } |
| 830 | |
| 831 | rc = msm_dsi_cmd_dma_tx(ctrl, tp); |
| 832 | if (IS_ERR_VALUE(rc)) { |
| 833 | pr_err("%s: failed to tx max_pkt_size\n", __func__); |
| 834 | return rc; |
| 835 | } |
| 836 | pr_debug("%s: max_pkt_size=%d sent\n", __func__, size); |
| 837 | return rc; |
| 838 | } |
| 839 | |
| 840 | /* read data length is less than or equal to 10 bytes*/ |
| 841 | static int msm_dsi_cmds_rx_1(struct mdss_dsi_ctrl_pdata *ctrl, |
| 842 | struct dsi_cmd_desc *cmds, int rlen) |
| 843 | { |
| 844 | int rc; |
| 845 | struct dsi_buf *tp, *rp; |
| 846 | |
| 847 | tp = &ctrl->tx_buf; |
| 848 | rp = &ctrl->rx_buf; |
| 849 | mdss_dsi_buf_init(rp); |
| 850 | mdss_dsi_buf_init(tp); |
| 851 | |
| 852 | rc = mdss_dsi_cmd_dma_add(tp, cmds); |
| 853 | if (!rc) { |
| 854 | pr_err("%s: dsi_cmd_dma_add failed\n", __func__); |
| 855 | rc = -EINVAL; |
| 856 | goto dsi_cmds_rx_1_error; |
| 857 | } |
| 858 | |
| 859 | rc = msm_dsi_wait4video_eng_busy(ctrl); |
| 860 | if (rc) { |
| 861 | pr_err("%s: wait4video_eng failed\n", __func__); |
| 862 | goto dsi_cmds_rx_1_error; |
| 863 | } |
| 864 | |
| 865 | rc = msm_dsi_cmd_dma_tx(ctrl, tp); |
| 866 | if (IS_ERR_VALUE(rc)) { |
| 867 | pr_err("%s: msm_dsi_cmd_dma_tx failed\n", __func__); |
| 868 | goto dsi_cmds_rx_1_error; |
| 869 | } |
| 870 | |
| 871 | if (rlen <= DSI_SHORT_PKT_DATA_SIZE) { |
| 872 | msm_dsi_cmd_dma_rx(ctrl, rp, rlen); |
| 873 | } else { |
| 874 | msm_dsi_cmd_dma_rx(ctrl, rp, rlen + DSI_HOST_HDR_SIZE); |
| 875 | rp->len = rlen + DSI_HOST_HDR_SIZE; |
| 876 | } |
| 877 | rc = msm_dsi_parse_rx_response(rp); |
| 878 | |
| 879 | dsi_cmds_rx_1_error: |
| 880 | if (rc) |
| 881 | rp->len = 0; |
| 882 | |
| 883 | return rc; |
| 884 | } |
| 885 | |
| 886 | /* read data length is more than 10 bytes, which requires multiple DSI read*/ |
| 887 | static int msm_dsi_cmds_rx_2(struct mdss_dsi_ctrl_pdata *ctrl, |
| 888 | struct dsi_cmd_desc *cmds, int rlen) |
| 889 | { |
| 890 | int rc; |
| 891 | struct dsi_buf *tp, *rp; |
| 892 | int pkt_size, data_bytes, total; |
| 893 | |
| 894 | tp = &ctrl->tx_buf; |
| 895 | rp = &ctrl->rx_buf; |
| 896 | mdss_dsi_buf_init(rp); |
| 897 | pkt_size = DSI_MAX_PKT_SIZE; |
| 898 | data_bytes = MDSS_DSI_LEN; |
| 899 | total = 0; |
| 900 | |
| 901 | while (true) { |
| 902 | rc = msm_dsi_set_max_packet_size(ctrl, pkt_size); |
| 903 | if (rc) |
| 904 | break; |
| 905 | |
| 906 | mdss_dsi_buf_init(tp); |
| 907 | rc = mdss_dsi_cmd_dma_add(tp, cmds); |
| 908 | if (!rc) { |
| 909 | pr_err("%s: dsi_cmd_dma_add failed\n", __func__); |
| 910 | rc = -EINVAL; |
| 911 | break; |
| 912 | } |
| 913 | rc = msm_dsi_wait4video_eng_busy(ctrl); |
| 914 | if (rc) { |
| 915 | pr_err("%s: wait4video_eng failed\n", __func__); |
| 916 | break; |
| 917 | } |
| 918 | |
| 919 | rc = msm_dsi_cmd_dma_tx(ctrl, tp); |
| 920 | if (IS_ERR_VALUE(rc)) { |
| 921 | pr_err("%s: msm_dsi_cmd_dma_tx failed\n", __func__); |
| 922 | break; |
| 923 | } |
| 924 | |
| 925 | msm_dsi_cmd_dma_rx(ctrl, rp, DSI_MAX_BYTES_TO_READ); |
| 926 | |
| 927 | rp->data += DSI_MAX_BYTES_TO_READ - DSI_HOST_HDR_SIZE; |
| 928 | total += data_bytes; |
| 929 | if (total >= rlen) |
| 930 | break; |
| 931 | |
| 932 | data_bytes = DSI_MAX_BYTES_TO_READ - DSI_HOST_HDR_SIZE; |
| 933 | pkt_size += data_bytes; |
| 934 | } |
| 935 | |
| 936 | if (!rc) { |
| 937 | rp->data = rp->start; |
| 938 | rp->len = rlen + DSI_HOST_HDR_SIZE; |
| 939 | rc = msm_dsi_parse_rx_response(rp); |
| 940 | } |
| 941 | |
| 942 | if (rc) |
| 943 | rp->len = 0; |
| 944 | |
| 945 | return rc; |
| 946 | } |
| 947 | |
| 948 | int msm_dsi_cmds_rx(struct mdss_dsi_ctrl_pdata *ctrl, |
| 949 | struct dsi_cmd_desc *cmds, int rlen) |
| 950 | { |
| 951 | int rc; |
| 952 | |
| 953 | if (rlen <= DSI_MAX_PKT_SIZE) |
| 954 | rc = msm_dsi_cmds_rx_1(ctrl, cmds, rlen); |
| 955 | else |
| 956 | rc = msm_dsi_cmds_rx_2(ctrl, cmds, rlen); |
| 957 | |
| 958 | return rc; |
| 959 | } |
| 960 | |
| 961 | void msm_dsi_cmdlist_tx(struct mdss_dsi_ctrl_pdata *ctrl, |
| 962 | struct dcs_cmd_req *req) |
| 963 | { |
| 964 | int ret; |
| 965 | |
| 966 | ret = msm_dsi_cmds_tx(ctrl, req->cmds, req->cmds_cnt); |
| 967 | |
| 968 | if (req->cb) |
| 969 | req->cb(ret); |
| 970 | } |
| 971 | |
| 972 | void msm_dsi_cmdlist_rx(struct mdss_dsi_ctrl_pdata *ctrl, |
| 973 | struct dcs_cmd_req *req) |
| 974 | { |
| 975 | struct dsi_buf *rp; |
| 976 | int len = 0; |
| 977 | |
| 978 | if (req->rbuf) { |
| 979 | rp = &ctrl->rx_buf; |
| 980 | len = msm_dsi_cmds_rx(ctrl, req->cmds, req->rlen); |
| 981 | memcpy(req->rbuf, rp->data, rp->len); |
| 982 | } else { |
| 983 | pr_err("%s: No rx buffer provided\n", __func__); |
| 984 | } |
| 985 | |
| 986 | if (req->cb) |
| 987 | req->cb(len); |
| 988 | } |
| 989 | int msm_dsi_cmdlist_commit(struct mdss_dsi_ctrl_pdata *ctrl, int from_mdp) |
| 990 | { |
| 991 | struct dcs_cmd_req *req; |
| 992 | int dsi_on; |
| 993 | int ret = -EINVAL; |
| 994 | |
| 995 | mutex_lock(&ctrl->mutex); |
| 996 | dsi_on = dsi_host_private->dsi_on; |
| 997 | mutex_unlock(&ctrl->mutex); |
| 998 | if (!dsi_on) { |
| 999 | pr_err("try to send DSI commands while dsi is off\n"); |
| 1000 | return ret; |
| 1001 | } |
| 1002 | |
| 1003 | if (from_mdp) /* from mdp kickoff */ |
| 1004 | mutex_lock(&ctrl->cmd_mutex); |
| 1005 | req = mdss_dsi_cmdlist_get(ctrl, from_mdp); |
| 1006 | |
| 1007 | if (!req) { |
| 1008 | mutex_unlock(&ctrl->cmd_mutex); |
| 1009 | return ret; |
| 1010 | } |
| 1011 | /* |
| 1012 | * mdss interrupt is generated in mdp core clock domain |
| 1013 | * mdp clock need to be enabled to receive dsi interrupt |
| 1014 | * also, axi bus bandwidth need since dsi controller will |
| 1015 | * fetch dcs commands from axi bus |
| 1016 | */ |
| 1017 | mdp3_res_update(1, 1, MDP3_CLIENT_DMA_P); |
| 1018 | msm_dsi_clk_ctrl(&ctrl->panel_data, 1); |
| 1019 | |
| 1020 | if (0 == (req->flags & CMD_REQ_LP_MODE)) |
| 1021 | dsi_set_tx_power_mode(0); |
| 1022 | |
| 1023 | if (req->flags & CMD_REQ_RX) |
| 1024 | msm_dsi_cmdlist_rx(ctrl, req); |
| 1025 | else |
| 1026 | msm_dsi_cmdlist_tx(ctrl, req); |
| 1027 | |
| 1028 | if (0 == (req->flags & CMD_REQ_LP_MODE)) |
| 1029 | dsi_set_tx_power_mode(1); |
| 1030 | |
| 1031 | msm_dsi_clk_ctrl(&ctrl->panel_data, 0); |
| 1032 | mdp3_res_update(0, 1, MDP3_CLIENT_DMA_P); |
| 1033 | |
| 1034 | if (from_mdp) /* from mdp kickoff */ |
| 1035 | mutex_unlock(&ctrl->cmd_mutex); |
| 1036 | return 0; |
| 1037 | } |
| 1038 | |
| 1039 | static int msm_dsi_cal_clk_rate(struct mdss_panel_data *pdata, |
| 1040 | u64 *bitclk_rate, |
| 1041 | u32 *dsiclk_rate, |
| 1042 | u32 *byteclk_rate, |
| 1043 | u32 *pclk_rate) |
| 1044 | { |
| 1045 | struct mdss_panel_info *pinfo; |
| 1046 | struct mipi_panel_info *mipi; |
| 1047 | u32 hbp, hfp, vbp, vfp, hspw, vspw, width, height; |
| 1048 | int lanes; |
| 1049 | u64 clk_rate; |
| 1050 | |
| 1051 | pinfo = &pdata->panel_info; |
| 1052 | mipi = &pdata->panel_info.mipi; |
| 1053 | |
| 1054 | hbp = pdata->panel_info.lcdc.h_back_porch; |
| 1055 | hfp = pdata->panel_info.lcdc.h_front_porch; |
| 1056 | vbp = pdata->panel_info.lcdc.v_back_porch; |
| 1057 | vfp = pdata->panel_info.lcdc.v_front_porch; |
| 1058 | hspw = pdata->panel_info.lcdc.h_pulse_width; |
| 1059 | vspw = pdata->panel_info.lcdc.v_pulse_width; |
| 1060 | width = pdata->panel_info.xres; |
| 1061 | height = pdata->panel_info.yres; |
| 1062 | |
| 1063 | lanes = 0; |
| 1064 | if (mipi->data_lane0) |
| 1065 | lanes++; |
| 1066 | if (mipi->data_lane1) |
| 1067 | lanes++; |
| 1068 | if (mipi->data_lane2) |
| 1069 | lanes++; |
| 1070 | if (mipi->data_lane3) |
| 1071 | lanes++; |
| 1072 | if (lanes == 0) |
| 1073 | return -EINVAL; |
| 1074 | |
| 1075 | *bitclk_rate = (width + hbp + hfp + hspw) * (height + vbp + vfp + vspw); |
| 1076 | *bitclk_rate *= mipi->frame_rate; |
| 1077 | *bitclk_rate *= pdata->panel_info.bpp; |
| 1078 | do_div(*bitclk_rate, lanes); |
| 1079 | clk_rate = *bitclk_rate; |
| 1080 | |
| 1081 | do_div(clk_rate, 8U); |
| 1082 | *byteclk_rate = (u32) clk_rate; |
| 1083 | *dsiclk_rate = *byteclk_rate * lanes; |
| 1084 | *pclk_rate = *byteclk_rate * lanes * 8 / pdata->panel_info.bpp; |
| 1085 | |
| 1086 | pr_debug("dsiclk_rate=%u, byteclk=%u, pck_=%u\n", |
| 1087 | *dsiclk_rate, *byteclk_rate, *pclk_rate); |
| 1088 | return 0; |
| 1089 | } |
| 1090 | |
| 1091 | static int msm_dsi_on(struct mdss_panel_data *pdata) |
| 1092 | { |
| 1093 | int ret = 0, i; |
| 1094 | u64 clk_rate; |
| 1095 | struct mdss_panel_info *pinfo; |
| 1096 | struct mipi_panel_info *mipi; |
| 1097 | u32 hbp, hfp, vbp, vfp, hspw, vspw, width, height; |
| 1098 | u32 ystride, bpp, data; |
| 1099 | u32 dummy_xres, dummy_yres; |
| 1100 | u64 bitclk_rate = 0 |
| 1101 | u32 byteclk_rate = 0, pclk_rate = 0, dsiclk_rate = 0; |
| 1102 | unsigned char *ctrl_base = dsi_host_private->dsi_base; |
| 1103 | struct mdss_dsi_ctrl_pdata *ctrl_pdata = NULL; |
| 1104 | |
| 1105 | pr_debug("msm_dsi_on\n"); |
| 1106 | |
| 1107 | pinfo = &pdata->panel_info; |
| 1108 | |
| 1109 | ctrl_pdata = container_of(pdata, struct mdss_dsi_ctrl_pdata, |
| 1110 | panel_data); |
| 1111 | |
| 1112 | mutex_lock(&ctrl_pdata->mutex); |
| 1113 | |
| 1114 | |
| 1115 | if (!pdata->panel_info.dynamic_switch_pending) { |
| 1116 | for (i = 0; !ret && (i < DSI_MAX_PM); i++) { |
| 1117 | ret = msm_dss_enable_vreg( |
| 1118 | ctrl_pdata->power_data[i].vreg_config, |
| 1119 | ctrl_pdata->power_data[i].num_vreg, 1); |
| 1120 | if (ret) { |
| 1121 | pr_err("%s: failed to enable vregs for %s\n", |
| 1122 | __func__, __mdss_dsi_pm_name(i)); |
| 1123 | goto error_vreg; |
| 1124 | } |
| 1125 | } |
| 1126 | } |
| 1127 | |
| 1128 | msm_dsi_ahb_ctrl(1); |
| 1129 | msm_dsi_phy_sw_reset(dsi_host_private->dsi_base); |
| 1130 | msm_dsi_phy_init(dsi_host_private->dsi_base, pdata); |
| 1131 | |
| 1132 | msm_dsi_cal_clk_rate(pdata, &bitclk_rate, &dsiclk_rate, |
| 1133 | &byteclk_rate, &pclk_rate); |
| 1134 | msm_dsi_clk_set_rate(DSI_ESC_CLK_RATE, dsiclk_rate, |
| 1135 | byteclk_rate, pclk_rate); |
| 1136 | msm_dsi_prepare_clocks(); |
| 1137 | msm_dsi_clk_enable(); |
| 1138 | |
| 1139 | clk_rate = pdata->panel_info.clk_rate; |
| 1140 | clk_rate = min(clk_rate, pdata->panel_info.clk_max); |
| 1141 | |
| 1142 | hbp = pdata->panel_info.lcdc.h_back_porch; |
| 1143 | hfp = pdata->panel_info.lcdc.h_front_porch; |
| 1144 | vbp = pdata->panel_info.lcdc.v_back_porch; |
| 1145 | vfp = pdata->panel_info.lcdc.v_front_porch; |
| 1146 | hspw = pdata->panel_info.lcdc.h_pulse_width; |
| 1147 | vspw = pdata->panel_info.lcdc.v_pulse_width; |
| 1148 | width = pdata->panel_info.xres; |
| 1149 | height = pdata->panel_info.yres; |
| 1150 | |
| 1151 | mipi = &pdata->panel_info.mipi; |
| 1152 | if (pdata->panel_info.type == MIPI_VIDEO_PANEL) { |
| 1153 | dummy_xres = pdata->panel_info.lcdc.xres_pad; |
| 1154 | dummy_yres = pdata->panel_info.lcdc.yres_pad; |
| 1155 | |
| 1156 | MIPI_OUTP(ctrl_base + DSI_VIDEO_MODE_ACTIVE_H, |
| 1157 | ((hspw + hbp + width + dummy_xres) << 16 | |
| 1158 | (hspw + hbp))); |
| 1159 | MIPI_OUTP(ctrl_base + DSI_VIDEO_MODE_ACTIVE_V, |
| 1160 | ((vspw + vbp + height + dummy_yres) << 16 | |
| 1161 | (vspw + vbp))); |
| 1162 | MIPI_OUTP(ctrl_base + DSI_VIDEO_MODE_TOTAL, |
| 1163 | (vspw + vbp + height + dummy_yres + |
| 1164 | vfp - 1) << 16 | (hspw + hbp + |
| 1165 | width + dummy_xres + hfp - 1)); |
| 1166 | |
| 1167 | MIPI_OUTP(ctrl_base + DSI_VIDEO_MODE_HSYNC, (hspw << 16)); |
| 1168 | MIPI_OUTP(ctrl_base + DSI_VIDEO_MODE_VSYNC, 0); |
| 1169 | MIPI_OUTP(ctrl_base + DSI_VIDEO_MODE_VSYNC_VPOS, |
| 1170 | (vspw << 16)); |
| 1171 | |
| 1172 | } else { /* command mode */ |
| 1173 | if (mipi->dst_format == DSI_CMD_DST_FORMAT_RGB888) |
| 1174 | bpp = 3; |
| 1175 | else if (mipi->dst_format == DSI_CMD_DST_FORMAT_RGB666) |
| 1176 | bpp = 3; |
| 1177 | else if (mipi->dst_format == DSI_CMD_DST_FORMAT_RGB565) |
| 1178 | bpp = 2; |
| 1179 | else |
| 1180 | bpp = 3; /* Default format set to RGB888 */ |
| 1181 | |
| 1182 | ystride = width * bpp + 1; |
| 1183 | |
| 1184 | data = (ystride << 16) | (mipi->vc << 8) | DTYPE_DCS_LWRITE; |
| 1185 | MIPI_OUTP(ctrl_base + DSI_COMMAND_MODE_MDP_STREAM0_CTRL, |
| 1186 | data); |
| 1187 | MIPI_OUTP(ctrl_base + DSI_COMMAND_MODE_MDP_STREAM1_CTRL, |
| 1188 | data); |
| 1189 | |
| 1190 | data = height << 16 | width; |
| 1191 | MIPI_OUTP(ctrl_base + DSI_COMMAND_MODE_MDP_STREAM1_TOTAL, |
| 1192 | data); |
| 1193 | MIPI_OUTP(ctrl_base + DSI_COMMAND_MODE_MDP_STREAM0_TOTAL, |
| 1194 | data); |
| 1195 | } |
| 1196 | |
| 1197 | msm_dsi_sw_reset(); |
| 1198 | msm_dsi_host_init(pdata); |
| 1199 | |
| 1200 | if (mipi->force_clk_lane_hs) { |
| 1201 | u32 tmp; |
| 1202 | |
| 1203 | tmp = MIPI_INP(ctrl_base + DSI_LANE_CTRL); |
| 1204 | tmp |= (1<<28); |
| 1205 | MIPI_OUTP(ctrl_base + DSI_LANE_CTRL, tmp); |
| 1206 | wmb(); /* ensure write is finished before progressing */ |
| 1207 | } |
| 1208 | |
| 1209 | msm_dsi_op_mode_config(mipi->mode, pdata); |
| 1210 | |
| 1211 | msm_dsi_set_irq(ctrl_pdata, DSI_INTR_ERROR_MASK); |
| 1212 | dsi_host_private->clk_count = 1; |
| 1213 | dsi_host_private->dsi_on = 1; |
| 1214 | |
| 1215 | error_vreg: |
| 1216 | if (ret) { |
| 1217 | for (; i >= 0; i--) |
| 1218 | msm_dss_enable_vreg( |
| 1219 | ctrl_pdata->power_data[i].vreg_config, |
| 1220 | ctrl_pdata->power_data[i].num_vreg, 0); |
| 1221 | } |
| 1222 | |
| 1223 | mutex_unlock(&ctrl_pdata->mutex); |
| 1224 | return ret; |
| 1225 | } |
| 1226 | |
| 1227 | static int msm_dsi_off(struct mdss_panel_data *pdata) |
| 1228 | { |
| 1229 | int ret = 0, i; |
| 1230 | struct mdss_dsi_ctrl_pdata *ctrl_pdata = NULL; |
| 1231 | |
| 1232 | if (pdata == NULL) { |
| 1233 | pr_err("%s: Invalid input data\n", __func__); |
| 1234 | ret = -EINVAL; |
| 1235 | return ret; |
| 1236 | } |
| 1237 | |
| 1238 | ctrl_pdata = container_of(pdata, struct mdss_dsi_ctrl_pdata, |
| 1239 | panel_data); |
| 1240 | |
| 1241 | pr_debug("msm_dsi_off\n"); |
| 1242 | mutex_lock(&ctrl_pdata->mutex); |
| 1243 | msm_dsi_clear_irq(ctrl_pdata, ctrl_pdata->dsi_irq_mask); |
| 1244 | msm_dsi_controller_cfg(0); |
| 1245 | msm_dsi_clk_set_rate(DSI_ESC_CLK_RATE, 0, 0, 0); |
| 1246 | msm_dsi_clk_disable(); |
| 1247 | msm_dsi_unprepare_clocks(); |
| 1248 | msm_dsi_phy_off(dsi_host_private->dsi_base); |
| 1249 | msm_dsi_ahb_ctrl(0); |
| 1250 | |
| 1251 | if (!pdata->panel_info.dynamic_switch_pending) { |
| 1252 | for (i = DSI_MAX_PM - 1; i >= 0; i--) { |
| 1253 | ret = msm_dss_enable_vreg( |
| 1254 | ctrl_pdata->power_data[i].vreg_config, |
| 1255 | ctrl_pdata->power_data[i].num_vreg, 0); |
| 1256 | if (ret) |
| 1257 | pr_err("%s: failed to disable vregs for %s\n", |
| 1258 | __func__, __mdss_dsi_pm_name(i)); |
| 1259 | } |
| 1260 | } |
| 1261 | dsi_host_private->clk_count = 0; |
| 1262 | dsi_host_private->dsi_on = 0; |
| 1263 | |
| 1264 | mutex_unlock(&ctrl_pdata->mutex); |
| 1265 | |
| 1266 | return ret; |
| 1267 | } |
| 1268 | |
| 1269 | static int msm_dsi_cont_on(struct mdss_panel_data *pdata) |
| 1270 | { |
| 1271 | struct mdss_panel_info *pinfo; |
| 1272 | int ret = 0, i; |
| 1273 | struct mdss_dsi_ctrl_pdata *ctrl_pdata = NULL; |
| 1274 | |
| 1275 | if (pdata == NULL) { |
| 1276 | pr_err("%s: Invalid input data\n", __func__); |
| 1277 | ret = -EINVAL; |
| 1278 | return ret; |
| 1279 | } |
| 1280 | |
| 1281 | |
| 1282 | pr_debug("%s:\n", __func__); |
| 1283 | |
| 1284 | ctrl_pdata = container_of(pdata, struct mdss_dsi_ctrl_pdata, |
| 1285 | panel_data); |
| 1286 | |
| 1287 | pinfo = &pdata->panel_info; |
| 1288 | mutex_lock(&ctrl_pdata->mutex); |
| 1289 | for (i = 0; !ret && (i < DSI_MAX_PM); i++) { |
| 1290 | ret = msm_dss_enable_vreg( |
| 1291 | ctrl_pdata->power_data[i].vreg_config, |
| 1292 | ctrl_pdata->power_data[i].num_vreg, 1); |
| 1293 | if (ret) { |
| 1294 | pr_err("%s: failed to enable vregs for %s\n", |
| 1295 | __func__, __mdss_dsi_pm_name(i)); |
| 1296 | goto error_vreg; |
| 1297 | } |
| 1298 | } |
| 1299 | pinfo->panel_power_state = MDSS_PANEL_POWER_ON; |
| 1300 | ret = mdss_dsi_panel_reset(pdata, 1); |
| 1301 | if (ret) { |
| 1302 | pr_err("%s: Panel reset failed\n", __func__); |
| 1303 | mutex_unlock(&ctrl_pdata->mutex); |
| 1304 | return ret; |
| 1305 | } |
| 1306 | |
| 1307 | msm_dsi_ahb_ctrl(1); |
| 1308 | msm_dsi_prepare_clocks(); |
| 1309 | msm_dsi_clk_enable(); |
| 1310 | msm_dsi_set_irq(ctrl_pdata, DSI_INTR_ERROR_MASK); |
| 1311 | dsi_host_private->clk_count = 1; |
| 1312 | dsi_host_private->dsi_on = 1; |
| 1313 | |
| 1314 | error_vreg: |
| 1315 | if (ret) { |
| 1316 | for (; i >= 0; i--) |
| 1317 | msm_dss_enable_vreg( |
| 1318 | ctrl_pdata->power_data[i].vreg_config, |
| 1319 | ctrl_pdata->power_data[i].num_vreg, 0); |
| 1320 | } |
| 1321 | |
| 1322 | mutex_unlock(&ctrl_pdata->mutex); |
| 1323 | return ret; |
| 1324 | } |
| 1325 | |
| 1326 | static int msm_dsi_read_status(struct mdss_dsi_ctrl_pdata *ctrl) |
| 1327 | { |
| 1328 | struct dcs_cmd_req cmdreq; |
| 1329 | |
| 1330 | memset(&cmdreq, 0, sizeof(cmdreq)); |
| 1331 | cmdreq.cmds = ctrl->status_cmds.cmds; |
| 1332 | cmdreq.cmds_cnt = ctrl->status_cmds.cmd_cnt; |
| 1333 | cmdreq.flags = CMD_REQ_COMMIT | CMD_REQ_RX; |
| 1334 | cmdreq.rlen = 1; |
| 1335 | cmdreq.cb = NULL; |
| 1336 | cmdreq.rbuf = ctrl->status_buf.data; |
| 1337 | |
| 1338 | return mdss_dsi_cmdlist_put(ctrl, &cmdreq); |
| 1339 | } |
| 1340 | |
| 1341 | |
| 1342 | /** |
| 1343 | * msm_dsi_reg_status_check() - Check dsi panel status through reg read |
| 1344 | * @ctrl_pdata: pointer to the dsi controller structure |
| 1345 | * |
| 1346 | * This function can be used to check the panel status through reading the |
| 1347 | * status register from the panel. |
| 1348 | * |
| 1349 | * Return: positive value if the panel is in good state, negative value or |
| 1350 | * zero otherwise. |
| 1351 | */ |
| 1352 | int msm_dsi_reg_status_check(struct mdss_dsi_ctrl_pdata *ctrl_pdata) |
| 1353 | { |
| 1354 | int ret = 0; |
| 1355 | |
| 1356 | if (ctrl_pdata == NULL) { |
| 1357 | pr_err("%s: Invalid input data\n", __func__); |
| 1358 | return 0; |
| 1359 | } |
| 1360 | |
| 1361 | pr_debug("%s: Checking Register status\n", __func__); |
| 1362 | |
| 1363 | msm_dsi_clk_ctrl(&ctrl_pdata->panel_data, 1); |
| 1364 | |
| 1365 | if (ctrl_pdata->status_cmds.link_state == DSI_HS_MODE) |
| 1366 | dsi_set_tx_power_mode(0); |
| 1367 | |
| 1368 | ret = msm_dsi_read_status(ctrl_pdata); |
| 1369 | |
| 1370 | if (ctrl_pdata->status_cmds.link_state == DSI_HS_MODE) |
| 1371 | dsi_set_tx_power_mode(1); |
| 1372 | |
| 1373 | if (ret == 0) { |
| 1374 | if (!mdss_dsi_cmp_panel_reg(ctrl_pdata->status_buf, |
| 1375 | ctrl_pdata->status_value, 0)) { |
| 1376 | pr_err("%s: Read back value from panel is incorrect\n", |
| 1377 | __func__); |
| 1378 | ret = -EINVAL; |
| 1379 | } else { |
| 1380 | ret = 1; |
| 1381 | } |
| 1382 | } else { |
| 1383 | pr_err("%s: Read status register returned error\n", __func__); |
| 1384 | } |
| 1385 | |
| 1386 | msm_dsi_clk_ctrl(&ctrl_pdata->panel_data, 0); |
| 1387 | pr_debug("%s: Read register done with ret: %d\n", __func__, ret); |
| 1388 | |
| 1389 | return ret; |
| 1390 | } |
| 1391 | |
| 1392 | /** |
| 1393 | * msm_dsi_bta_status_check() - Check dsi panel status through bta check |
| 1394 | * @ctrl_pdata: pointer to the dsi controller structure |
| 1395 | * |
| 1396 | * This function can be used to check status of the panel using bta check |
| 1397 | * for the panel. |
| 1398 | * |
| 1399 | * Return: positive value if the panel is in good state, negative value or |
| 1400 | * zero otherwise. |
| 1401 | */ |
| 1402 | static int msm_dsi_bta_status_check(struct mdss_dsi_ctrl_pdata *ctrl_pdata) |
| 1403 | { |
| 1404 | int ret = 0; |
| 1405 | |
| 1406 | if (ctrl_pdata == NULL) { |
| 1407 | pr_err("%s: Invalid input data\n", __func__); |
| 1408 | return 0; |
| 1409 | } |
| 1410 | |
| 1411 | mutex_lock(&ctrl_pdata->cmd_mutex); |
| 1412 | msm_dsi_clk_ctrl(&ctrl_pdata->panel_data, 1); |
| 1413 | msm_dsi_cmd_mdp_busy(ctrl_pdata); |
| 1414 | msm_dsi_set_irq(ctrl_pdata, DSI_INTR_BTA_DONE_MASK); |
| 1415 | reinit_completion(&ctrl_pdata->bta_comp); |
| 1416 | |
| 1417 | /* BTA trigger */ |
| 1418 | MIPI_OUTP(dsi_host_private->dsi_base + DSI_CMD_MODE_BTA_SW_TRIGGER, |
| 1419 | 0x01); |
| 1420 | wmb(); /* ensure write is finished before progressing */ |
| 1421 | ret = wait_for_completion_killable_timeout(&ctrl_pdata->bta_comp, |
| 1422 | HZ/10); |
| 1423 | msm_dsi_clear_irq(ctrl_pdata, DSI_INTR_BTA_DONE_MASK); |
| 1424 | msm_dsi_clk_ctrl(&ctrl_pdata->panel_data, 0); |
| 1425 | mutex_unlock(&ctrl_pdata->cmd_mutex); |
| 1426 | |
| 1427 | if (ret <= 0) |
| 1428 | pr_err("%s: DSI BTA error: %i\n", __func__, __LINE__); |
| 1429 | |
| 1430 | pr_debug("%s: BTA done with ret: %d\n", __func__, ret); |
| 1431 | return ret; |
| 1432 | } |
| 1433 | |
| 1434 | static void msm_dsi_debug_enable_clock(int on) |
| 1435 | { |
| 1436 | if (dsi_host_private->debug_enable_clk) |
| 1437 | dsi_host_private->debug_enable_clk(on); |
| 1438 | |
| 1439 | if (on) |
| 1440 | msm_dsi_ahb_ctrl(1); |
| 1441 | else |
| 1442 | msm_dsi_ahb_ctrl(0); |
| 1443 | } |
| 1444 | |
| 1445 | static int msm_dsi_debug_init(void) |
| 1446 | { |
| 1447 | int rc; |
| 1448 | |
| 1449 | if (!mdss_res) |
| 1450 | return 0; |
| 1451 | |
| 1452 | dsi_host_private->debug_enable_clk = |
| 1453 | mdss_res->debug_inf.debug_enable_clock; |
| 1454 | |
| 1455 | mdss_res->debug_inf.debug_enable_clock = msm_dsi_debug_enable_clock; |
| 1456 | |
| 1457 | |
| 1458 | rc = mdss_debug_register_base("dsi0", |
| 1459 | dsi_host_private->dsi_base, |
| 1460 | dsi_host_private->dsi_reg_size, |
| 1461 | NULL); |
| 1462 | |
| 1463 | return rc; |
| 1464 | } |
| 1465 | |
| 1466 | static int dsi_get_panel_cfg(char *panel_cfg) |
| 1467 | { |
| 1468 | int rc; |
| 1469 | struct mdss_panel_cfg *pan_cfg = NULL; |
| 1470 | |
| 1471 | if (!panel_cfg) |
| 1472 | return MDSS_PANEL_INTF_INVALID; |
| 1473 | |
| 1474 | pan_cfg = mdp3_panel_intf_type(MDSS_PANEL_INTF_DSI); |
| 1475 | if (IS_ERR(pan_cfg)) { |
| 1476 | panel_cfg[0] = 0; |
| 1477 | return PTR_ERR(pan_cfg); |
| 1478 | } else if (!pan_cfg) { |
| 1479 | panel_cfg[0] = 0; |
| 1480 | return 0; |
| 1481 | } |
| 1482 | |
| 1483 | pr_debug("%s:%d: cfg:[%s]\n", __func__, __LINE__, |
| 1484 | pan_cfg->arg_cfg); |
| 1485 | rc = strlcpy(panel_cfg, pan_cfg->arg_cfg, |
| 1486 | MDSS_MAX_PANEL_LEN); |
| 1487 | return rc; |
| 1488 | } |
| 1489 | |
| 1490 | static struct device_node *dsi_pref_prim_panel( |
| 1491 | struct platform_device *pdev) |
| 1492 | { |
| 1493 | struct device_node *dsi_pan_node = NULL; |
| 1494 | |
| 1495 | pr_debug("%s:%d: Select primary panel from dt\n", |
| 1496 | __func__, __LINE__); |
| 1497 | dsi_pan_node = of_parse_phandle(pdev->dev.of_node, |
| 1498 | "qcom,dsi-pref-prim-pan", 0); |
| 1499 | if (!dsi_pan_node) |
| 1500 | pr_err("%s:can't find panel phandle\n", __func__); |
| 1501 | |
| 1502 | return dsi_pan_node; |
| 1503 | } |
| 1504 | |
| 1505 | /** |
| 1506 | * dsi_find_panel_of_node(): find device node of dsi panel |
| 1507 | * @pdev: platform_device of the dsi ctrl node |
| 1508 | * @panel_cfg: string containing intf specific config data |
| 1509 | * |
| 1510 | * Function finds the panel device node using the interface |
| 1511 | * specific configuration data. This configuration data is |
| 1512 | * could be derived from the result of bootloader's GCDB |
| 1513 | * panel detection mechanism. If such config data doesn't |
| 1514 | * exist then this panel returns the default panel configured |
| 1515 | * in the device tree. |
| 1516 | * |
| 1517 | * returns pointer to panel node on success, NULL on error. |
| 1518 | */ |
| 1519 | static struct device_node *dsi_find_panel_of_node( |
| 1520 | struct platform_device *pdev, char *panel_cfg) |
| 1521 | { |
| 1522 | int l; |
| 1523 | char *panel_name; |
| 1524 | struct device_node *dsi_pan_node = NULL, *mdss_node = NULL; |
| 1525 | |
| 1526 | if (!panel_cfg) |
| 1527 | return NULL; |
| 1528 | |
| 1529 | l = strlen(panel_cfg); |
| 1530 | if (!l) { |
| 1531 | /* no panel cfg chg, parse dt */ |
| 1532 | pr_debug("%s:%d: no cmd line cfg present\n", |
| 1533 | __func__, __LINE__); |
| 1534 | dsi_pan_node = dsi_pref_prim_panel(pdev); |
| 1535 | } else { |
| 1536 | if (panel_cfg[0] != '0') { |
| 1537 | pr_err("%s:%d:ctrl id=[%d] not supported\n", |
| 1538 | __func__, __LINE__, panel_cfg[0]); |
| 1539 | return NULL; |
| 1540 | } |
| 1541 | /* |
| 1542 | * skip first two chars '<dsi_ctrl_id>' and |
| 1543 | * ':' to get to the panel name |
| 1544 | */ |
| 1545 | panel_name = panel_cfg + 2; |
| 1546 | pr_debug("%s:%d:%s:%s\n", __func__, __LINE__, |
| 1547 | panel_cfg, panel_name); |
| 1548 | |
| 1549 | mdss_node = of_parse_phandle(pdev->dev.of_node, |
| 1550 | "qcom,mdss-mdp", 0); |
| 1551 | |
| 1552 | if (!mdss_node) { |
| 1553 | pr_err("%s: %d: mdss_node null\n", |
| 1554 | __func__, __LINE__); |
| 1555 | return NULL; |
| 1556 | } |
| 1557 | dsi_pan_node = of_find_node_by_name(mdss_node, |
| 1558 | panel_name); |
| 1559 | if (!dsi_pan_node) { |
| 1560 | pr_err("%s: invalid pan node\n", |
| 1561 | __func__); |
| 1562 | dsi_pan_node = dsi_pref_prim_panel(pdev); |
| 1563 | } |
| 1564 | } |
| 1565 | return dsi_pan_node; |
| 1566 | } |
| 1567 | |
| 1568 | static int msm_dsi_clk_ctrl(struct mdss_panel_data *pdata, int enable) |
| 1569 | { |
| 1570 | u32 bitclk_rate = 0, byteclk_rate = 0, pclk_rate = 0, dsiclk_rate = 0; |
| 1571 | struct mdss_dsi_ctrl_pdata *ctrl_pdata = NULL; |
| 1572 | |
| 1573 | pr_debug("%s:\n", __func__); |
| 1574 | |
| 1575 | ctrl_pdata = container_of(pdata, struct mdss_dsi_ctrl_pdata, |
| 1576 | panel_data); |
| 1577 | |
| 1578 | mutex_lock(&ctrl_pdata->mutex); |
| 1579 | |
| 1580 | if (enable) { |
| 1581 | dsi_host_private->clk_count++; |
| 1582 | if (dsi_host_private->clk_count == 1) { |
| 1583 | msm_dsi_ahb_ctrl(1); |
| 1584 | msm_dsi_cal_clk_rate(pdata, &bitclk_rate, &dsiclk_rate, |
| 1585 | &byteclk_rate, &pclk_rate); |
| 1586 | msm_dsi_clk_set_rate(DSI_ESC_CLK_RATE, dsiclk_rate, |
| 1587 | byteclk_rate, pclk_rate); |
| 1588 | msm_dsi_prepare_clocks(); |
| 1589 | msm_dsi_clk_enable(); |
| 1590 | } |
| 1591 | } else { |
| 1592 | dsi_host_private->clk_count--; |
| 1593 | if (dsi_host_private->clk_count == 0) { |
| 1594 | msm_dsi_clear_irq(ctrl_pdata, ctrl_pdata->dsi_irq_mask); |
| 1595 | msm_dsi_clk_set_rate(DSI_ESC_CLK_RATE, 0, 0, 0); |
| 1596 | msm_dsi_clk_disable(); |
| 1597 | msm_dsi_unprepare_clocks(); |
| 1598 | msm_dsi_ahb_ctrl(0); |
| 1599 | } |
| 1600 | } |
| 1601 | mutex_unlock(&ctrl_pdata->mutex); |
| 1602 | return 0; |
| 1603 | } |
| 1604 | |
| 1605 | void msm_dsi_ctrl_init(struct mdss_dsi_ctrl_pdata *ctrl) |
| 1606 | { |
| 1607 | init_completion(&ctrl->dma_comp); |
| 1608 | init_completion(&ctrl->mdp_comp); |
| 1609 | init_completion(&ctrl->bta_comp); |
| 1610 | init_completion(&ctrl->video_comp); |
| 1611 | spin_lock_init(&ctrl->irq_lock); |
| 1612 | spin_lock_init(&ctrl->mdp_lock); |
| 1613 | mutex_init(&ctrl->mutex); |
| 1614 | mutex_init(&ctrl->cmd_mutex); |
| 1615 | complete(&ctrl->mdp_comp); |
| 1616 | dsi_buf_alloc(&ctrl->tx_buf, SZ_4K); |
| 1617 | dsi_buf_alloc(&ctrl->rx_buf, SZ_4K); |
| 1618 | dsi_buf_alloc(&ctrl->status_buf, SZ_4K); |
| 1619 | ctrl->cmdlist_commit = msm_dsi_cmdlist_commit; |
| 1620 | ctrl->panel_mode = ctrl->panel_data.panel_info.mipi.mode; |
| 1621 | |
| 1622 | if (ctrl->status_mode == ESD_REG) |
| 1623 | ctrl->check_status = msm_dsi_reg_status_check; |
| 1624 | else if (ctrl->status_mode == ESD_BTA) |
| 1625 | ctrl->check_status = msm_dsi_bta_status_check; |
| 1626 | |
| 1627 | if (ctrl->status_mode == ESD_MAX) { |
| 1628 | pr_err("%s: Using default BTA for ESD check\n", __func__); |
| 1629 | ctrl->check_status = msm_dsi_bta_status_check; |
| 1630 | } |
| 1631 | } |
| 1632 | |
| 1633 | static void msm_dsi_parse_lane_swap(struct device_node *np, char *dlane_swap) |
| 1634 | { |
| 1635 | const char *data; |
| 1636 | |
| 1637 | *dlane_swap = DSI_LANE_MAP_0123; |
| 1638 | data = of_get_property(np, "qcom,lane-map", NULL); |
| 1639 | if (data) { |
| 1640 | if (!strcmp(data, "lane_map_3012")) |
| 1641 | *dlane_swap = DSI_LANE_MAP_3012; |
| 1642 | else if (!strcmp(data, "lane_map_2301")) |
| 1643 | *dlane_swap = DSI_LANE_MAP_2301; |
| 1644 | else if (!strcmp(data, "lane_map_1230")) |
| 1645 | *dlane_swap = DSI_LANE_MAP_1230; |
| 1646 | else if (!strcmp(data, "lane_map_0321")) |
| 1647 | *dlane_swap = DSI_LANE_MAP_0321; |
| 1648 | else if (!strcmp(data, "lane_map_1032")) |
| 1649 | *dlane_swap = DSI_LANE_MAP_1032; |
| 1650 | else if (!strcmp(data, "lane_map_2103")) |
| 1651 | *dlane_swap = DSI_LANE_MAP_2103; |
| 1652 | else if (!strcmp(data, "lane_map_3210")) |
| 1653 | *dlane_swap = DSI_LANE_MAP_3210; |
| 1654 | } |
| 1655 | } |
| 1656 | |
| 1657 | static int msm_dsi_probe(struct platform_device *pdev) |
| 1658 | { |
| 1659 | struct dsi_interface intf; |
| 1660 | char panel_cfg[MDSS_MAX_PANEL_LEN]; |
| 1661 | struct mdss_dsi_ctrl_pdata *ctrl_pdata = NULL; |
| 1662 | int rc = 0; |
| 1663 | struct device_node *dsi_pan_node = NULL; |
| 1664 | bool cmd_cfg_cont_splash = false; |
| 1665 | struct resource *mdss_dsi_mres; |
| 1666 | int i; |
| 1667 | |
| 1668 | pr_debug("%s\n", __func__); |
| 1669 | |
| 1670 | rc = msm_dsi_init(); |
| 1671 | if (rc) |
| 1672 | return rc; |
| 1673 | |
| 1674 | if (!pdev->dev.of_node) { |
| 1675 | pr_err("%s: Device node is not accessible\n", __func__); |
| 1676 | rc = -ENODEV; |
| 1677 | goto error_no_mem; |
| 1678 | } |
| 1679 | pdev->id = 0; |
| 1680 | |
| 1681 | ctrl_pdata = platform_get_drvdata(pdev); |
| 1682 | if (!ctrl_pdata) { |
| 1683 | ctrl_pdata = devm_kzalloc(&pdev->dev, |
| 1684 | sizeof(struct mdss_dsi_ctrl_pdata), GFP_KERNEL); |
| 1685 | if (!ctrl_pdata) { |
| 1686 | rc = -ENOMEM; |
| 1687 | goto error_no_mem; |
| 1688 | } |
| 1689 | platform_set_drvdata(pdev, ctrl_pdata); |
| 1690 | } |
| 1691 | |
| 1692 | ctrl_pdata->mdss_util = mdss_get_util_intf(); |
| 1693 | if (mdp3_res->mdss_util == NULL) { |
| 1694 | pr_err("Failed to get mdss utility functions\n"); |
| 1695 | return -ENODEV; |
| 1696 | } |
| 1697 | |
| 1698 | mdss_dsi_mres = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 1699 | if (!mdss_dsi_mres) { |
| 1700 | pr_err("%s:%d unable to get the MDSS reg resources", |
| 1701 | __func__, __LINE__); |
| 1702 | rc = -ENOMEM; |
| 1703 | goto error_io_resource; |
| 1704 | } else { |
| 1705 | dsi_host_private->dsi_reg_size = resource_size(mdss_dsi_mres); |
| 1706 | dsi_host_private->dsi_base = ioremap(mdss_dsi_mres->start, |
| 1707 | dsi_host_private->dsi_reg_size); |
| 1708 | if (!dsi_host_private->dsi_base) { |
| 1709 | pr_err("%s:%d unable to remap dsi resources", |
| 1710 | __func__, __LINE__); |
| 1711 | rc = -ENOMEM; |
| 1712 | goto error_io_resource; |
| 1713 | } |
| 1714 | } |
| 1715 | |
| 1716 | mdss_dsi_mres = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
| 1717 | if (!mdss_dsi_mres || mdss_dsi_mres->start == 0) { |
| 1718 | pr_err("%s:%d unable to get the MDSS irq resources", |
| 1719 | __func__, __LINE__); |
| 1720 | rc = -ENODEV; |
| 1721 | goto error_irq_resource; |
| 1722 | } |
| 1723 | |
| 1724 | rc = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev); |
| 1725 | if (rc) { |
| 1726 | dev_err(&pdev->dev, "%s: failed to add child nodes, rc=%d\n", |
| 1727 | __func__, rc); |
| 1728 | goto error_platform_pop; |
| 1729 | } |
| 1730 | |
| 1731 | /* DSI panels can be different between controllers */ |
| 1732 | rc = dsi_get_panel_cfg(panel_cfg); |
| 1733 | if (!rc) |
| 1734 | /* dsi panel cfg not present */ |
| 1735 | pr_warn("%s:%d:dsi specific cfg not present\n", |
| 1736 | __func__, __LINE__); |
| 1737 | |
| 1738 | /* find panel device node */ |
| 1739 | dsi_pan_node = dsi_find_panel_of_node(pdev, panel_cfg); |
| 1740 | if (!dsi_pan_node) { |
| 1741 | pr_err("%s: can't find panel node %s\n", __func__, |
| 1742 | panel_cfg); |
| 1743 | goto error_pan_node; |
| 1744 | } |
| 1745 | |
| 1746 | cmd_cfg_cont_splash = mdp3_panel_get_boot_cfg() ? true : false; |
| 1747 | |
| 1748 | rc = mdss_dsi_panel_init(dsi_pan_node, ctrl_pdata, cmd_cfg_cont_splash); |
| 1749 | if (rc) { |
| 1750 | pr_err("%s: dsi panel init failed\n", __func__); |
| 1751 | goto error_pan_node; |
| 1752 | } |
| 1753 | |
| 1754 | rc = dsi_ctrl_config_init(pdev, ctrl_pdata); |
| 1755 | if (rc) { |
| 1756 | dev_err(&pdev->dev, "%s: failed to parse mdss dtsi rc=%d\n", |
| 1757 | __func__, rc); |
| 1758 | goto error_pan_node; |
| 1759 | } |
| 1760 | |
| 1761 | msm_dsi_parse_lane_swap(pdev->dev.of_node, &(ctrl_pdata->dlane_swap)); |
| 1762 | |
| 1763 | for (i = 0; i < DSI_MAX_PM; i++) { |
| 1764 | rc = msm_dsi_io_init(pdev, &(ctrl_pdata->power_data[i])); |
| 1765 | if (rc) { |
| 1766 | dev_err(&pdev->dev, "%s: failed to init IO for %s\n", |
| 1767 | __func__, __mdss_dsi_pm_name(i)); |
| 1768 | goto error_io_init; |
| 1769 | } |
| 1770 | } |
| 1771 | |
| 1772 | pr_debug("%s: Dsi Ctrl->0 initialized\n", __func__); |
| 1773 | |
| 1774 | dsi_host_private->dis_dev = pdev->dev; |
| 1775 | intf.on = msm_dsi_on; |
| 1776 | intf.off = msm_dsi_off; |
| 1777 | intf.cont_on = msm_dsi_cont_on; |
| 1778 | intf.clk_ctrl = msm_dsi_clk_ctrl; |
| 1779 | intf.op_mode_config = msm_dsi_op_mode_config; |
| 1780 | intf.index = 0; |
| 1781 | intf.private = NULL; |
| 1782 | dsi_register_interface(&intf); |
| 1783 | |
| 1784 | msm_dsi_debug_init(); |
| 1785 | |
| 1786 | msm_dsi_ctrl_init(ctrl_pdata); |
| 1787 | |
| 1788 | rc = msm_dsi_irq_init(&pdev->dev, mdss_dsi_mres->start, |
| 1789 | ctrl_pdata); |
| 1790 | if (rc) { |
| 1791 | dev_err(&pdev->dev, "%s: failed to init irq, rc=%d\n", |
| 1792 | __func__, rc); |
| 1793 | goto error_irq_init; |
| 1794 | } |
| 1795 | |
| 1796 | rc = dsi_panel_device_register_v2(pdev, ctrl_pdata); |
| 1797 | if (rc) { |
| 1798 | pr_err("%s: dsi panel dev reg failed\n", __func__); |
| 1799 | goto error_device_register; |
| 1800 | } |
| 1801 | pr_debug("%s success\n", __func__); |
| 1802 | return 0; |
| 1803 | error_device_register: |
| 1804 | kfree(ctrl_pdata->dsi_hw->irq_info); |
| 1805 | kfree(ctrl_pdata->dsi_hw); |
| 1806 | error_irq_init: |
| 1807 | for (i = DSI_MAX_PM - 1; i >= 0; i--) |
| 1808 | msm_dsi_io_deinit(pdev, &(ctrl_pdata->power_data[i])); |
| 1809 | error_io_init: |
| 1810 | dsi_ctrl_config_deinit(pdev, ctrl_pdata); |
| 1811 | error_pan_node: |
| 1812 | of_node_put(dsi_pan_node); |
| 1813 | error_platform_pop: |
| 1814 | msm_dsi_clear_irq(ctrl_pdata, ctrl_pdata->dsi_irq_mask); |
| 1815 | error_irq_resource: |
| 1816 | if (dsi_host_private->dsi_base) { |
| 1817 | iounmap(dsi_host_private->dsi_base); |
| 1818 | dsi_host_private->dsi_base = NULL; |
| 1819 | } |
| 1820 | error_io_resource: |
| 1821 | devm_kfree(&pdev->dev, ctrl_pdata); |
| 1822 | error_no_mem: |
| 1823 | msm_dsi_deinit(); |
| 1824 | |
| 1825 | return rc; |
| 1826 | } |
| 1827 | |
| 1828 | static int msm_dsi_remove(struct platform_device *pdev) |
| 1829 | { |
| 1830 | int i; |
| 1831 | struct mdss_dsi_ctrl_pdata *ctrl_pdata = platform_get_drvdata(pdev); |
| 1832 | |
| 1833 | if (!ctrl_pdata) { |
| 1834 | pr_err("%s: no driver data\n", __func__); |
| 1835 | return -ENODEV; |
| 1836 | } |
| 1837 | |
| 1838 | msm_dsi_clear_irq(ctrl_pdata, ctrl_pdata->dsi_irq_mask); |
| 1839 | for (i = DSI_MAX_PM - 1; i >= 0; i--) |
| 1840 | msm_dsi_io_deinit(pdev, &(ctrl_pdata->power_data[i])); |
| 1841 | dsi_ctrl_config_deinit(pdev, ctrl_pdata); |
| 1842 | iounmap(dsi_host_private->dsi_base); |
| 1843 | dsi_host_private->dsi_base = NULL; |
| 1844 | msm_dsi_deinit(); |
| 1845 | devm_kfree(&pdev->dev, ctrl_pdata); |
| 1846 | |
| 1847 | return 0; |
| 1848 | } |
| 1849 | |
| 1850 | static const struct of_device_id msm_dsi_v2_dt_match[] = { |
| 1851 | {.compatible = "qcom,msm-dsi-v2"}, |
| 1852 | {} |
| 1853 | }; |
| 1854 | MODULE_DEVICE_TABLE(of, msm_dsi_v2_dt_match); |
| 1855 | |
| 1856 | static struct platform_driver msm_dsi_v2_driver = { |
| 1857 | .probe = msm_dsi_probe, |
| 1858 | .remove = msm_dsi_remove, |
| 1859 | .shutdown = NULL, |
| 1860 | .driver = { |
| 1861 | .name = "qcom,dsi-panel-v2", |
| 1862 | .of_match_table = msm_dsi_v2_dt_match, |
| 1863 | }, |
| 1864 | }; |
| 1865 | |
| 1866 | static int msm_dsi_v2_register_driver(void) |
| 1867 | { |
| 1868 | return platform_driver_register(&msm_dsi_v2_driver); |
| 1869 | } |
| 1870 | |
| 1871 | static int __init msm_dsi_v2_driver_init(void) |
| 1872 | { |
| 1873 | int ret; |
| 1874 | |
| 1875 | ret = msm_dsi_v2_register_driver(); |
| 1876 | if (ret) { |
| 1877 | pr_err("msm_dsi_v2_register_driver() failed!\n"); |
| 1878 | return ret; |
| 1879 | } |
| 1880 | |
| 1881 | return ret; |
| 1882 | } |
| 1883 | module_init(msm_dsi_v2_driver_init); |
| 1884 | |
| 1885 | static void __exit msm_dsi_v2_driver_cleanup(void) |
| 1886 | { |
| 1887 | platform_driver_unregister(&msm_dsi_v2_driver); |
| 1888 | } |
| 1889 | module_exit(msm_dsi_v2_driver_cleanup); |