Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 1 | /* Copyright (c) 2010-2016, 2018, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | #include <linux/io.h> |
| 14 | #include <linux/types.h> |
| 15 | #include <linux/delay.h> |
| 16 | #include <linux/slab.h> |
| 17 | #include <linux/stat.h> |
| 18 | #include <soc/qcom/scm.h> |
| 19 | #include <linux/hdcp_qseecom.h> |
| 20 | #include "mdss_hdmi_hdcp.h" |
| 21 | #include "video/msm_hdmi_hdcp_mgr.h" |
| 22 | |
| 23 | #define HDCP_STATE_NAME (hdcp_state_name(hdcp_ctrl->hdcp_state)) |
| 24 | |
| 25 | /* HDCP Keys state based on HDMI_HDCP_LINK0_STATUS:KEYS_STATE */ |
| 26 | #define HDCP_KEYS_STATE_NO_KEYS 0 |
| 27 | #define HDCP_KEYS_STATE_NOT_CHECKED 1 |
| 28 | #define HDCP_KEYS_STATE_CHECKING 2 |
| 29 | #define HDCP_KEYS_STATE_VALID 3 |
| 30 | #define HDCP_KEYS_STATE_AKSV_NOT_VALID 4 |
| 31 | #define HDCP_KEYS_STATE_CHKSUM_MISMATCH 5 |
| 32 | #define HDCP_KEYS_STATE_PROD_AKSV 6 |
| 33 | #define HDCP_KEYS_STATE_RESERVED 7 |
| 34 | |
| 35 | #define TZ_HDCP_CMD_ID 0x00004401 |
| 36 | #define HDCP_REG_ENABLE 0x01 |
| 37 | #define HDCP_REG_DISABLE 0x00 |
| 38 | |
| 39 | #define HDCP_INT_CLR (BIT(1) | BIT(5) | BIT(7) | BIT(9) | BIT(13)) |
| 40 | |
| 41 | struct hdmi_hdcp_reg_data { |
| 42 | u32 reg_id; |
| 43 | u32 off; |
| 44 | char *name; |
| 45 | u32 reg_val; |
| 46 | }; |
| 47 | |
| 48 | struct hdmi_hdcp_ctrl { |
| 49 | u32 auth_retries; |
| 50 | u32 tp_msgid; |
| 51 | u32 tz_hdcp; |
| 52 | enum hdmi_hdcp_state hdcp_state; |
| 53 | struct HDCP_V2V1_MSG_TOPOLOGY cached_tp; |
| 54 | struct HDCP_V2V1_MSG_TOPOLOGY current_tp; |
| 55 | struct delayed_work hdcp_auth_work; |
| 56 | struct work_struct hdcp_int_work; |
| 57 | struct completion r0_checked; |
| 58 | struct hdmi_hdcp_init_data init_data; |
| 59 | struct hdmi_hdcp_ops *ops; |
| 60 | bool hdmi_tx_ver_4; |
| 61 | }; |
| 62 | |
| 63 | const char *hdcp_state_name(enum hdmi_hdcp_state hdcp_state) |
| 64 | { |
| 65 | switch (hdcp_state) { |
| 66 | case HDCP_STATE_INACTIVE: return "HDCP_STATE_INACTIVE"; |
| 67 | case HDCP_STATE_AUTHENTICATING: return "HDCP_STATE_AUTHENTICATING"; |
| 68 | case HDCP_STATE_AUTHENTICATED: return "HDCP_STATE_AUTHENTICATED"; |
| 69 | case HDCP_STATE_AUTH_FAIL: return "HDCP_STATE_AUTH_FAIL"; |
| 70 | default: return "???"; |
| 71 | } |
| 72 | } /* hdcp_state_name */ |
| 73 | |
| 74 | static int hdmi_hdcp_count_one(u8 *array, u8 len) |
| 75 | { |
| 76 | int i, j, count = 0; |
| 77 | |
| 78 | for (i = 0; i < len; i++) |
| 79 | for (j = 0; j < 8; j++) |
| 80 | count += (((array[i] >> j) & 0x1) ? 1 : 0); |
| 81 | return count; |
| 82 | } /* hdmi_hdcp_count_one */ |
| 83 | |
| 84 | static void reset_hdcp_ddc_failures(struct hdmi_hdcp_ctrl *hdcp_ctrl) |
| 85 | { |
| 86 | int hdcp_ddc_ctrl1_reg; |
| 87 | int hdcp_ddc_status; |
| 88 | int failure; |
| 89 | int nack0; |
| 90 | struct dss_io_data *io; |
| 91 | |
| 92 | if (!hdcp_ctrl || !hdcp_ctrl->init_data.core_io) { |
| 93 | DEV_ERR("%s: invalid input\n", __func__); |
| 94 | return; |
| 95 | } |
| 96 | |
| 97 | io = hdcp_ctrl->init_data.core_io; |
| 98 | |
| 99 | /* Check for any DDC transfer failures */ |
| 100 | hdcp_ddc_status = DSS_REG_R(io, HDMI_HDCP_DDC_STATUS); |
| 101 | failure = (hdcp_ddc_status >> 16) & 0x1; |
| 102 | nack0 = (hdcp_ddc_status >> 14) & 0x1; |
| 103 | DEV_DBG("%s: %s: On Entry: HDCP_DDC_STATUS=0x%x, FAIL=%d, NACK0=%d\n", |
| 104 | __func__, HDCP_STATE_NAME, hdcp_ddc_status, failure, nack0); |
| 105 | |
| 106 | if (failure == 0x1) { |
| 107 | /* |
| 108 | * Indicates that the last HDCP HW DDC transfer failed. |
| 109 | * This occurs when a transfer is attempted with HDCP DDC |
| 110 | * disabled (HDCP_DDC_DISABLE=1) or the number of retries |
| 111 | * matches HDCP_DDC_RETRY_CNT. |
| 112 | * Failure occurred, let's clear it. |
| 113 | */ |
| 114 | DEV_DBG("%s: %s: DDC failure detected.HDCP_DDC_STATUS=0x%08x\n", |
| 115 | __func__, HDCP_STATE_NAME, hdcp_ddc_status); |
| 116 | |
| 117 | /* First, Disable DDC */ |
| 118 | DSS_REG_W(io, HDMI_HDCP_DDC_CTRL_0, BIT(0)); |
| 119 | |
| 120 | /* ACK the Failure to Clear it */ |
| 121 | hdcp_ddc_ctrl1_reg = DSS_REG_R(io, HDMI_HDCP_DDC_CTRL_1); |
| 122 | DSS_REG_W(io, HDMI_HDCP_DDC_CTRL_1, |
| 123 | hdcp_ddc_ctrl1_reg | BIT(0)); |
| 124 | |
| 125 | /* Check if the FAILURE got Cleared */ |
| 126 | hdcp_ddc_status = DSS_REG_R(io, HDMI_HDCP_DDC_STATUS); |
| 127 | hdcp_ddc_status = (hdcp_ddc_status >> 16) & BIT(0); |
| 128 | if (hdcp_ddc_status == 0x0) |
| 129 | DEV_DBG("%s: %s: HDCP DDC Failure cleared\n", __func__, |
| 130 | HDCP_STATE_NAME); |
| 131 | else |
| 132 | DEV_WARN("%s: %s: Unable to clear HDCP DDC Failure", |
| 133 | __func__, HDCP_STATE_NAME); |
| 134 | |
| 135 | /* Re-Enable HDCP DDC */ |
| 136 | DSS_REG_W(io, HDMI_HDCP_DDC_CTRL_0, 0); |
| 137 | } |
| 138 | |
| 139 | if (nack0 == 0x1) { |
| 140 | DEV_DBG("%s: %s: Before: HDMI_DDC_SW_STATUS=0x%08x\n", __func__, |
| 141 | HDCP_STATE_NAME, DSS_REG_R(io, HDMI_DDC_SW_STATUS)); |
| 142 | /* Reset HDMI DDC software status */ |
| 143 | DSS_REG_W_ND(io, HDMI_DDC_CTRL, |
| 144 | DSS_REG_R(io, HDMI_DDC_CTRL) | BIT(3)); |
| 145 | msleep(20); |
| 146 | DSS_REG_W_ND(io, HDMI_DDC_CTRL, |
| 147 | DSS_REG_R(io, HDMI_DDC_CTRL) & ~(BIT(3))); |
| 148 | |
| 149 | /* Reset HDMI DDC Controller */ |
| 150 | DSS_REG_W_ND(io, HDMI_DDC_CTRL, |
| 151 | DSS_REG_R(io, HDMI_DDC_CTRL) | BIT(1)); |
| 152 | msleep(20); |
| 153 | DSS_REG_W_ND(io, HDMI_DDC_CTRL, |
| 154 | DSS_REG_R(io, HDMI_DDC_CTRL) & ~BIT(1)); |
| 155 | DEV_DBG("%s: %s: After: HDMI_DDC_SW_STATUS=0x%08x\n", __func__, |
| 156 | HDCP_STATE_NAME, DSS_REG_R(io, HDMI_DDC_SW_STATUS)); |
| 157 | } |
| 158 | |
| 159 | hdcp_ddc_status = DSS_REG_R(io, HDMI_HDCP_DDC_STATUS); |
| 160 | |
| 161 | failure = (hdcp_ddc_status >> 16) & BIT(0); |
| 162 | nack0 = (hdcp_ddc_status >> 14) & BIT(0); |
| 163 | DEV_DBG("%s: %s: On Exit: HDCP_DDC_STATUS=0x%x, FAIL=%d, NACK0=%d\n", |
| 164 | __func__, HDCP_STATE_NAME, hdcp_ddc_status, failure, nack0); |
| 165 | } /* reset_hdcp_ddc_failures */ |
| 166 | |
| 167 | static void hdmi_hdcp_hw_ddc_clean(struct hdmi_hdcp_ctrl *hdcp_ctrl) |
| 168 | { |
| 169 | struct dss_io_data *io = NULL; |
| 170 | u32 hdcp_ddc_status, ddc_hw_status; |
| 171 | u32 ddc_xfer_done, ddc_xfer_req; |
| 172 | u32 ddc_hw_req, ddc_hw_not_idle; |
| 173 | bool ddc_hw_not_ready, xfer_not_done, hw_not_done; |
| 174 | u32 timeout_count; |
| 175 | |
| 176 | if (!hdcp_ctrl || !hdcp_ctrl->init_data.core_io) { |
| 177 | DEV_ERR("%s: invalid input\n", __func__); |
| 178 | return; |
| 179 | } |
| 180 | |
| 181 | io = hdcp_ctrl->init_data.core_io; |
| 182 | if (!io->base) { |
| 183 | DEV_ERR("%s: core io not inititalized\n", __func__); |
| 184 | return; |
| 185 | } |
| 186 | |
| 187 | /* Wait to be clean on DDC HW engine */ |
| 188 | timeout_count = 100; |
| 189 | do { |
| 190 | hdcp_ddc_status = DSS_REG_R(io, HDMI_HDCP_DDC_STATUS); |
| 191 | ddc_xfer_req = hdcp_ddc_status & BIT(4); |
| 192 | ddc_xfer_done = hdcp_ddc_status & BIT(10); |
| 193 | |
| 194 | ddc_hw_status = DSS_REG_R(io, HDMI_DDC_HW_STATUS); |
| 195 | ddc_hw_req = ddc_hw_status & BIT(16); |
| 196 | ddc_hw_not_idle = ddc_hw_status & (BIT(0) | BIT(1)); |
| 197 | |
| 198 | /* ddc transfer was requested but not completed */ |
| 199 | xfer_not_done = ddc_xfer_req && !ddc_xfer_done; |
| 200 | |
| 201 | /* ddc status is not idle or a hw request pending */ |
| 202 | hw_not_done = ddc_hw_not_idle || ddc_hw_req; |
| 203 | |
| 204 | ddc_hw_not_ready = xfer_not_done || hw_not_done; |
| 205 | |
| 206 | DEV_DBG("%s: %s: timeout count(%d): ddc hw%sready\n", |
| 207 | __func__, HDCP_STATE_NAME, timeout_count, |
| 208 | ddc_hw_not_ready ? " not " : " "); |
| 209 | DEV_DBG("hdcp_ddc_status[0x%x], ddc_hw_status[0x%x]\n", |
| 210 | hdcp_ddc_status, ddc_hw_status); |
| 211 | if (ddc_hw_not_ready) |
| 212 | msleep(20); |
| 213 | } while (ddc_hw_not_ready && --timeout_count); |
| 214 | } /* hdmi_hdcp_hw_ddc_clean */ |
| 215 | |
| 216 | static int hdcp_scm_call(struct scm_hdcp_req *req, u32 *resp) |
| 217 | { |
| 218 | int ret = 0; |
| 219 | |
| 220 | if (!is_scm_armv8()) { |
| 221 | ret = scm_call(SCM_SVC_HDCP, SCM_CMD_HDCP, (void *) req, |
| 222 | SCM_HDCP_MAX_REG * sizeof(struct scm_hdcp_req), |
| 223 | &resp, sizeof(*resp)); |
| 224 | } else { |
| 225 | struct scm_desc desc; |
| 226 | |
| 227 | desc.args[0] = req[0].addr; |
| 228 | desc.args[1] = req[0].val; |
| 229 | desc.args[2] = req[1].addr; |
| 230 | desc.args[3] = req[1].val; |
| 231 | desc.args[4] = req[2].addr; |
| 232 | desc.args[5] = req[2].val; |
| 233 | desc.args[6] = req[3].addr; |
| 234 | desc.args[7] = req[3].val; |
| 235 | desc.args[8] = req[4].addr; |
| 236 | desc.args[9] = req[4].val; |
| 237 | desc.arginfo = SCM_ARGS(10); |
| 238 | |
| 239 | ret = scm_call2(SCM_SIP_FNID(SCM_SVC_HDCP, SCM_CMD_HDCP), |
| 240 | &desc); |
| 241 | *resp = desc.ret[0]; |
| 242 | if (ret) |
| 243 | return ret; |
| 244 | } |
| 245 | |
| 246 | return ret; |
| 247 | } |
| 248 | |
| 249 | static int hdmi_hdcp_load_keys(void *input) |
| 250 | { |
| 251 | int rc = 0; |
| 252 | bool use_sw_keys = false; |
| 253 | u32 reg_val; |
| 254 | u32 ksv_lsb_addr, ksv_msb_addr; |
| 255 | u32 aksv_lsb, aksv_msb; |
| 256 | u8 aksv[5]; |
| 257 | struct dss_io_data *io; |
| 258 | struct dss_io_data *qfprom_io; |
| 259 | struct hdmi_hdcp_ctrl *hdcp_ctrl = input; |
| 260 | |
| 261 | if (!hdcp_ctrl || !hdcp_ctrl->init_data.core_io || |
| 262 | !hdcp_ctrl->init_data.qfprom_io) { |
| 263 | DEV_ERR("%s: invalid input\n", __func__); |
| 264 | rc = -EINVAL; |
| 265 | goto end; |
| 266 | } |
| 267 | |
| 268 | if ((hdcp_ctrl->hdcp_state != HDCP_STATE_INACTIVE) && |
| 269 | (hdcp_ctrl->hdcp_state != HDCP_STATE_AUTH_FAIL)) { |
| 270 | DEV_ERR("%s: %s: invalid state. returning\n", __func__, |
| 271 | HDCP_STATE_NAME); |
| 272 | rc = -EINVAL; |
| 273 | goto end; |
| 274 | } |
| 275 | |
| 276 | io = hdcp_ctrl->init_data.core_io; |
| 277 | qfprom_io = hdcp_ctrl->init_data.qfprom_io; |
| 278 | |
| 279 | /* On compatible hardware, use SW keys */ |
| 280 | reg_val = DSS_REG_R(qfprom_io, SEC_CTRL_HW_VERSION); |
| 281 | if (reg_val >= HDCP_SEL_MIN_SEC_VERSION) { |
| 282 | reg_val = DSS_REG_R(qfprom_io, |
| 283 | QFPROM_RAW_FEAT_CONFIG_ROW0_MSB + |
| 284 | QFPROM_RAW_VERSION_4); |
| 285 | |
| 286 | if (!(reg_val & BIT(23))) |
| 287 | use_sw_keys = true; |
| 288 | } |
| 289 | |
| 290 | if (use_sw_keys) { |
| 291 | if (hdcp1_set_keys(&aksv_msb, &aksv_lsb)) { |
| 292 | pr_err("%s: setting hdcp SW keys failed\n", __func__); |
| 293 | rc = -EINVAL; |
| 294 | goto end; |
| 295 | } |
| 296 | } else { |
| 297 | /* Fetch aksv from QFPROM, this info should be public. */ |
| 298 | ksv_lsb_addr = HDCP_KSV_LSB; |
| 299 | ksv_msb_addr = HDCP_KSV_MSB; |
| 300 | |
| 301 | if (hdcp_ctrl->hdmi_tx_ver_4) { |
| 302 | ksv_lsb_addr += HDCP_KSV_VERSION_4_OFFSET; |
| 303 | ksv_msb_addr += HDCP_KSV_VERSION_4_OFFSET; |
| 304 | } |
| 305 | |
| 306 | aksv_lsb = DSS_REG_R(qfprom_io, ksv_lsb_addr); |
| 307 | aksv_msb = DSS_REG_R(qfprom_io, ksv_msb_addr); |
| 308 | } |
| 309 | |
| 310 | DEV_DBG("%s: %s: AKSV=%02x%08x\n", __func__, HDCP_STATE_NAME, |
| 311 | aksv_msb, aksv_lsb); |
| 312 | |
| 313 | aksv[0] = aksv_lsb & 0xFF; |
| 314 | aksv[1] = (aksv_lsb >> 8) & 0xFF; |
| 315 | aksv[2] = (aksv_lsb >> 16) & 0xFF; |
| 316 | aksv[3] = (aksv_lsb >> 24) & 0xFF; |
| 317 | aksv[4] = aksv_msb & 0xFF; |
| 318 | |
| 319 | /* check there are 20 ones in AKSV */ |
| 320 | if (hdmi_hdcp_count_one(aksv, 5) != 20) { |
| 321 | DEV_ERR("%s: AKSV bit count failed\n", __func__); |
| 322 | rc = -EINVAL; |
| 323 | goto end; |
| 324 | } |
| 325 | |
| 326 | DSS_REG_W(io, HDMI_HDCP_SW_LOWER_AKSV, aksv_lsb); |
| 327 | DSS_REG_W(io, HDMI_HDCP_SW_UPPER_AKSV, aksv_msb); |
| 328 | |
| 329 | /* Setup seed values for random number An */ |
| 330 | DSS_REG_W(io, HDMI_HDCP_ENTROPY_CTRL0, 0xB1FFB0FF); |
| 331 | DSS_REG_W(io, HDMI_HDCP_ENTROPY_CTRL1, 0xF00DFACE); |
| 332 | |
| 333 | /* Disable the RngCipher state */ |
| 334 | DSS_REG_W(io, HDMI_HDCP_DEBUG_CTRL, |
| 335 | DSS_REG_R(io, HDMI_HDCP_DEBUG_CTRL) & ~(BIT(2))); |
| 336 | |
| 337 | /* make sure hw is programmed */ |
| 338 | wmb(); |
| 339 | |
| 340 | DSS_REG_W(io, HDMI_HDCP_CTRL, BIT(0)); |
| 341 | |
| 342 | hdcp_ctrl->hdcp_state = HDCP_STATE_AUTHENTICATING; |
| 343 | end: |
| 344 | return rc; |
| 345 | } |
| 346 | |
| 347 | static int hdmi_hdcp_authentication_part1(struct hdmi_hdcp_ctrl *hdcp_ctrl) |
| 348 | { |
| 349 | int rc; |
| 350 | u32 link0_aksv_0, link0_aksv_1; |
| 351 | u32 link0_bksv_0, link0_bksv_1; |
| 352 | u32 link0_an_0, link0_an_1; |
| 353 | u32 timeout_count; |
| 354 | bool is_match; |
| 355 | struct dss_io_data *io; |
| 356 | struct dss_io_data *hdcp_io; |
| 357 | u8 aksv[5], *bksv = NULL; |
| 358 | u8 an[8]; |
| 359 | u8 bcaps = 0; |
| 360 | struct hdmi_tx_ddc_data ddc_data; |
| 361 | u32 link0_status = 0, an_ready, keys_state; |
| 362 | u8 buf[0xFF]; |
| 363 | |
| 364 | struct scm_hdcp_req scm_buf[SCM_HDCP_MAX_REG]; |
| 365 | u32 phy_addr; |
| 366 | u32 ret = 0; |
| 367 | u32 resp = 0; |
| 368 | |
| 369 | if (!hdcp_ctrl || !hdcp_ctrl->init_data.core_io || |
| 370 | !hdcp_ctrl->init_data.qfprom_io) { |
| 371 | DEV_ERR("%s: invalid input\n", __func__); |
| 372 | rc = -EINVAL; |
| 373 | goto error; |
| 374 | } |
| 375 | |
| 376 | phy_addr = hdcp_ctrl->init_data.phy_addr; |
| 377 | bksv = hdcp_ctrl->current_tp.bksv; |
| 378 | io = hdcp_ctrl->init_data.core_io; |
| 379 | hdcp_io = hdcp_ctrl->init_data.hdcp_io; |
| 380 | |
| 381 | if (hdcp_ctrl->hdcp_state != HDCP_STATE_AUTHENTICATING) { |
| 382 | DEV_ERR("%s: %s: invalid state. returning\n", __func__, |
| 383 | HDCP_STATE_NAME); |
| 384 | rc = -EINVAL; |
| 385 | goto error; |
| 386 | } |
| 387 | |
| 388 | /* Clear any DDC failures from previous tries */ |
| 389 | reset_hdcp_ddc_failures(hdcp_ctrl); |
| 390 | |
| 391 | /* |
| 392 | * Read BCAPS |
| 393 | * We need to first try to read an HDCP register on the sink to see if |
| 394 | * the sink is ready for HDCP authentication |
| 395 | */ |
| 396 | memset(&ddc_data, 0, sizeof(ddc_data)); |
| 397 | ddc_data.dev_addr = 0x74; |
| 398 | ddc_data.offset = 0x40; |
| 399 | ddc_data.data_buf = &bcaps; |
| 400 | ddc_data.data_len = 1; |
| 401 | ddc_data.request_len = 1; |
| 402 | ddc_data.retry = 5; |
| 403 | ddc_data.what = "Bcaps"; |
| 404 | |
| 405 | hdcp_ctrl->init_data.ddc_ctrl->ddc_data = ddc_data; |
| 406 | |
| 407 | rc = hdmi_ddc_read(hdcp_ctrl->init_data.ddc_ctrl); |
| 408 | if (rc) { |
| 409 | DEV_ERR("%s: %s: BCAPS read failed\n", __func__, |
| 410 | HDCP_STATE_NAME); |
| 411 | goto error; |
| 412 | } |
| 413 | DEV_DBG("%s: %s: BCAPS=%02x\n", __func__, HDCP_STATE_NAME, bcaps); |
| 414 | |
| 415 | /* receiver (0), repeater (1) */ |
| 416 | hdcp_ctrl->current_tp.ds_type = |
| 417 | (bcaps & BIT(6)) >> 6 ? DS_REPEATER : DS_RECEIVER; |
| 418 | |
| 419 | /* Write BCAPS to the hardware */ |
| 420 | if (hdcp_ctrl->tz_hdcp) { |
| 421 | memset(scm_buf, 0x00, sizeof(scm_buf)); |
| 422 | |
| 423 | scm_buf[0].addr = phy_addr + HDMI_HDCP_RCVPORT_DATA12; |
| 424 | scm_buf[0].val = bcaps; |
| 425 | |
| 426 | ret = hdcp_scm_call(scm_buf, &resp); |
| 427 | if (ret || resp) { |
| 428 | DEV_ERR("%s: error: scm_call ret = %d, resp = %d\n", |
| 429 | __func__, ret, resp); |
| 430 | rc = -EINVAL; |
| 431 | goto error; |
| 432 | } |
| 433 | } else if (hdcp_ctrl->hdmi_tx_ver_4) { |
| 434 | DSS_REG_W(hdcp_io, HDCP_SEC_TZ_HV_HLOS_HDCP_RCVPORT_DATA12, |
| 435 | bcaps); |
| 436 | } else { |
| 437 | DSS_REG_W(io, HDMI_HDCP_RCVPORT_DATA12, bcaps); |
| 438 | } |
| 439 | |
| 440 | /* Wait for HDCP keys to be checked and validated */ |
| 441 | timeout_count = 100; |
| 442 | keys_state = (link0_status >> 28) & 0x7; |
| 443 | while ((keys_state != HDCP_KEYS_STATE_VALID) && |
| 444 | --timeout_count) { |
| 445 | link0_status = DSS_REG_R(io, HDMI_HDCP_LINK0_STATUS); |
| 446 | keys_state = (link0_status >> 28) & 0x7; |
| 447 | DEV_DBG("%s: %s: Keys not ready(%d). s=%d\n, l0=%0x08x", |
| 448 | __func__, HDCP_STATE_NAME, timeout_count, |
| 449 | keys_state, link0_status); |
| 450 | msleep(20); |
| 451 | } |
| 452 | |
| 453 | if (!timeout_count) { |
| 454 | DEV_ERR("%s: %s: Invalid Keys State: %d\n", __func__, |
| 455 | HDCP_STATE_NAME, keys_state); |
| 456 | rc = -EINVAL; |
| 457 | goto error; |
| 458 | } |
| 459 | |
| 460 | /* |
| 461 | * 1.1_Features turned off by default. |
| 462 | * No need to write AInfo since 1.1_Features is disabled. |
| 463 | */ |
| 464 | DSS_REG_W(io, HDMI_HDCP_RCVPORT_DATA4, 0); |
| 465 | |
| 466 | /* Wait for An0 and An1 bit to be ready */ |
| 467 | timeout_count = 100; |
| 468 | do { |
| 469 | link0_status = DSS_REG_R(io, HDMI_HDCP_LINK0_STATUS); |
| 470 | an_ready = (link0_status & BIT(8)) && (link0_status & BIT(9)); |
| 471 | if (!an_ready) { |
| 472 | DEV_DBG("%s: %s: An not ready(%d). l0_status=0x%08x\n", |
| 473 | __func__, HDCP_STATE_NAME, timeout_count, |
| 474 | link0_status); |
| 475 | msleep(20); |
| 476 | } |
| 477 | } while (!an_ready && --timeout_count); |
| 478 | |
| 479 | if (!timeout_count) { |
| 480 | rc = -ETIMEDOUT; |
| 481 | DEV_ERR("%s: %s: timedout, An0=%ld, An1=%ld\n", __func__, |
| 482 | HDCP_STATE_NAME, (link0_status & BIT(8)) >> 8, |
| 483 | (link0_status & BIT(9)) >> 9); |
| 484 | goto error; |
| 485 | } |
| 486 | |
| 487 | /* As per hardware recommendations, wait before reading An */ |
| 488 | msleep(20); |
| 489 | |
| 490 | /* Read An0 and An1 */ |
| 491 | link0_an_0 = DSS_REG_R(io, HDMI_HDCP_RCVPORT_DATA5); |
| 492 | link0_an_1 = DSS_REG_R(io, HDMI_HDCP_RCVPORT_DATA6); |
| 493 | |
| 494 | /* Read AKSV */ |
| 495 | link0_aksv_0 = DSS_REG_R(io, HDMI_HDCP_RCVPORT_DATA3); |
| 496 | link0_aksv_1 = DSS_REG_R(io, HDMI_HDCP_RCVPORT_DATA4); |
| 497 | |
| 498 | /* Copy An and AKSV to byte arrays for transmission */ |
| 499 | aksv[0] = link0_aksv_0 & 0xFF; |
| 500 | aksv[1] = (link0_aksv_0 >> 8) & 0xFF; |
| 501 | aksv[2] = (link0_aksv_0 >> 16) & 0xFF; |
| 502 | aksv[3] = (link0_aksv_0 >> 24) & 0xFF; |
| 503 | aksv[4] = link0_aksv_1 & 0xFF; |
| 504 | |
| 505 | an[0] = link0_an_0 & 0xFF; |
| 506 | an[1] = (link0_an_0 >> 8) & 0xFF; |
| 507 | an[2] = (link0_an_0 >> 16) & 0xFF; |
| 508 | an[3] = (link0_an_0 >> 24) & 0xFF; |
| 509 | an[4] = link0_an_1 & 0xFF; |
| 510 | an[5] = (link0_an_1 >> 8) & 0xFF; |
| 511 | an[6] = (link0_an_1 >> 16) & 0xFF; |
| 512 | an[7] = (link0_an_1 >> 24) & 0xFF; |
| 513 | |
| 514 | /* Write An to offset 0x18 */ |
| 515 | memset(&ddc_data, 0, sizeof(ddc_data)); |
| 516 | ddc_data.dev_addr = 0x74; |
| 517 | ddc_data.offset = 0x18; |
| 518 | ddc_data.data_buf = an; |
| 519 | ddc_data.data_len = 8; |
| 520 | ddc_data.what = "An"; |
| 521 | hdcp_ctrl->init_data.ddc_ctrl->ddc_data = ddc_data; |
| 522 | |
| 523 | rc = hdmi_ddc_write(hdcp_ctrl->init_data.ddc_ctrl); |
| 524 | if (rc) { |
| 525 | DEV_ERR("%s: %s: An write failed\n", __func__, HDCP_STATE_NAME); |
| 526 | goto error; |
| 527 | } |
| 528 | |
| 529 | /* Write AKSV to offset 0x10 */ |
| 530 | memset(&ddc_data, 0, sizeof(ddc_data)); |
| 531 | ddc_data.dev_addr = 0x74; |
| 532 | ddc_data.offset = 0x10; |
| 533 | ddc_data.data_buf = aksv; |
| 534 | ddc_data.data_len = 5; |
| 535 | ddc_data.what = "Aksv"; |
| 536 | hdcp_ctrl->init_data.ddc_ctrl->ddc_data = ddc_data; |
| 537 | |
| 538 | rc = hdmi_ddc_write(hdcp_ctrl->init_data.ddc_ctrl); |
| 539 | if (rc) { |
| 540 | DEV_ERR("%s: %s: AKSV write failed\n", __func__, |
| 541 | HDCP_STATE_NAME); |
| 542 | goto error; |
| 543 | } |
| 544 | DEV_DBG("%s: %s: Link0-AKSV=%02x%08x\n", __func__, |
| 545 | HDCP_STATE_NAME, link0_aksv_1 & 0xFF, link0_aksv_0); |
| 546 | |
| 547 | /* Read BKSV at offset 0x00 */ |
| 548 | memset(&ddc_data, 0, sizeof(ddc_data)); |
| 549 | ddc_data.dev_addr = 0x74; |
| 550 | ddc_data.offset = 0x00; |
| 551 | ddc_data.data_buf = bksv; |
| 552 | ddc_data.data_len = 5; |
| 553 | ddc_data.request_len = 5; |
| 554 | ddc_data.retry = 5; |
| 555 | ddc_data.what = "Bksv"; |
| 556 | |
| 557 | hdcp_ctrl->init_data.ddc_ctrl->ddc_data = ddc_data; |
| 558 | |
| 559 | rc = hdmi_ddc_read(hdcp_ctrl->init_data.ddc_ctrl); |
| 560 | if (rc) { |
| 561 | DEV_ERR("%s: %s: BKSV read failed\n", __func__, |
| 562 | HDCP_STATE_NAME); |
| 563 | goto error; |
| 564 | } |
| 565 | |
| 566 | /* check there are 20 ones in BKSV */ |
| 567 | if (hdmi_hdcp_count_one(bksv, 5) != 20) { |
| 568 | DEV_ERR("%s: %s: BKSV doesn't have 20 1's and 20 0's\n", |
| 569 | __func__, HDCP_STATE_NAME); |
| 570 | DEV_ERR("%s: %s: BKSV chk fail. BKSV=%02x%02x%02x%02x%02x\n", |
| 571 | __func__, HDCP_STATE_NAME, bksv[4], bksv[3], bksv[2], |
| 572 | bksv[1], bksv[0]); |
| 573 | rc = -EINVAL; |
| 574 | goto error; |
| 575 | } |
| 576 | |
| 577 | link0_bksv_0 = bksv[3]; |
| 578 | link0_bksv_0 = (link0_bksv_0 << 8) | bksv[2]; |
| 579 | link0_bksv_0 = (link0_bksv_0 << 8) | bksv[1]; |
| 580 | link0_bksv_0 = (link0_bksv_0 << 8) | bksv[0]; |
| 581 | link0_bksv_1 = bksv[4]; |
| 582 | DEV_DBG("%s: %s: BKSV=%02x%08x\n", __func__, HDCP_STATE_NAME, |
| 583 | link0_bksv_1, link0_bksv_0); |
| 584 | |
| 585 | if (hdcp_ctrl->tz_hdcp) { |
| 586 | memset(scm_buf, 0x00, sizeof(scm_buf)); |
| 587 | |
| 588 | scm_buf[0].addr = phy_addr + HDMI_HDCP_RCVPORT_DATA0; |
| 589 | scm_buf[0].val = link0_bksv_0; |
| 590 | scm_buf[1].addr = phy_addr + HDMI_HDCP_RCVPORT_DATA1; |
| 591 | scm_buf[1].val = link0_bksv_1; |
| 592 | |
| 593 | ret = hdcp_scm_call(scm_buf, &resp); |
| 594 | |
| 595 | if (ret || resp) { |
| 596 | DEV_ERR("%s: error: scm_call ret = %d, resp = %d\n", |
| 597 | __func__, ret, resp); |
| 598 | rc = -EINVAL; |
| 599 | goto error; |
| 600 | } |
| 601 | } else if (hdcp_ctrl->hdmi_tx_ver_4) { |
| 602 | DSS_REG_W(hdcp_io, HDCP_SEC_TZ_HV_HLOS_HDCP_RCVPORT_DATA0, |
| 603 | link0_bksv_0); |
| 604 | DSS_REG_W(hdcp_io, HDCP_SEC_TZ_HV_HLOS_HDCP_RCVPORT_DATA1, |
| 605 | link0_bksv_1); |
| 606 | } else { |
| 607 | DSS_REG_W(io, HDMI_HDCP_RCVPORT_DATA0, link0_bksv_0); |
| 608 | DSS_REG_W(io, HDMI_HDCP_RCVPORT_DATA1, link0_bksv_1); |
| 609 | } |
| 610 | |
| 611 | /* Enable HDCP interrupts and ack/clear any stale interrupts */ |
| 612 | DSS_REG_W(io, HDMI_HDCP_INT_CTRL, 0xE6); |
| 613 | |
| 614 | /* |
| 615 | * HDCP Compliace Test case 1A-01: |
| 616 | * Wait here at least 100ms before reading R0' |
| 617 | */ |
| 618 | msleep(125); |
| 619 | |
| 620 | /* Read R0' at offset 0x08 */ |
| 621 | memset(buf, 0, sizeof(buf)); |
| 622 | memset(&ddc_data, 0, sizeof(ddc_data)); |
| 623 | ddc_data.dev_addr = 0x74; |
| 624 | ddc_data.offset = 0x08; |
| 625 | ddc_data.data_buf = buf; |
| 626 | ddc_data.data_len = 2; |
| 627 | ddc_data.request_len = 2; |
| 628 | ddc_data.retry = 5; |
| 629 | ddc_data.what = "R0'"; |
| 630 | |
| 631 | hdcp_ctrl->init_data.ddc_ctrl->ddc_data = ddc_data; |
| 632 | |
| 633 | rc = hdmi_ddc_read(hdcp_ctrl->init_data.ddc_ctrl); |
| 634 | if (rc) { |
| 635 | DEV_ERR("%s: %s: R0' read failed\n", __func__, HDCP_STATE_NAME); |
| 636 | goto error; |
| 637 | } |
| 638 | DEV_DBG("%s: %s: R0'=%02x%02x\n", __func__, HDCP_STATE_NAME, |
| 639 | buf[1], buf[0]); |
| 640 | |
| 641 | /* Write R0' to HDCP registers and check to see if it is a match */ |
| 642 | reinit_completion(&hdcp_ctrl->r0_checked); |
| 643 | DSS_REG_W(io, HDMI_HDCP_RCVPORT_DATA2_0, (((u32)buf[1]) << 8) | buf[0]); |
| 644 | timeout_count = wait_for_completion_timeout( |
| 645 | &hdcp_ctrl->r0_checked, HZ*2); |
| 646 | link0_status = DSS_REG_R(io, HDMI_HDCP_LINK0_STATUS); |
| 647 | is_match = link0_status & BIT(12); |
| 648 | if (!is_match) { |
| 649 | DEV_DBG("%s: %s: Link0_Status=0x%08x\n", __func__, |
| 650 | HDCP_STATE_NAME, link0_status); |
| 651 | if (!timeout_count) { |
| 652 | DEV_ERR("%s: %s: Timeout. No R0 mtch. R0'=%02x%02x\n", |
| 653 | __func__, HDCP_STATE_NAME, buf[1], buf[0]); |
| 654 | rc = -ETIMEDOUT; |
| 655 | goto error; |
| 656 | } else { |
| 657 | DEV_ERR("%s: %s: R0 mismatch. R0'=%02x%02x\n", __func__, |
| 658 | HDCP_STATE_NAME, buf[1], buf[0]); |
| 659 | rc = -EINVAL; |
| 660 | goto error; |
| 661 | } |
| 662 | } else { |
| 663 | DEV_DBG("%s: %s: R0 matches\n", __func__, HDCP_STATE_NAME); |
| 664 | } |
| 665 | |
| 666 | error: |
| 667 | if (rc) { |
| 668 | DEV_ERR("%s: %s: Authentication Part I failed\n", __func__, |
| 669 | hdcp_ctrl ? HDCP_STATE_NAME : "???"); |
| 670 | } else { |
| 671 | /* Enable HDCP Encryption */ |
| 672 | DSS_REG_W(io, HDMI_HDCP_CTRL, BIT(0) | BIT(8)); |
| 673 | DEV_INFO("%s: %s: Authentication Part I successful\n", |
| 674 | __func__, HDCP_STATE_NAME); |
| 675 | } |
| 676 | return rc; |
| 677 | } /* hdmi_hdcp_authentication_part1 */ |
| 678 | |
Sachin Bhayare | 3d3767e | 2018-01-02 21:10:57 +0530 | [diff] [blame] | 679 | static int read_write_v_h(struct hdmi_hdcp_ctrl *hdcp_ctrl, |
| 680 | struct hdmi_tx_ddc_data ddc_data, |
| 681 | struct dss_io_data *io, int off, char *name, |
| 682 | u32 reg, bool wr) |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 683 | { |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 684 | int rc = 0; |
| 685 | |
| 686 | do { |
| 687 | ddc_data.offset = off; |
Sachin Bhayare | 3d3767e | 2018-01-02 21:10:57 +0530 | [diff] [blame] | 688 | memset(ddc_data.what, 0, 20); |
| 689 | snprintf(ddc_data.what, 20, name); |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 690 | hdcp_ctrl->init_data.ddc_ctrl->ddc_data = ddc_data; |
| 691 | rc = hdmi_ddc_read(hdcp_ctrl->init_data.ddc_ctrl); |
| 692 | if (rc) { |
| 693 | DEV_ERR("%s: %s: Read %s failed\n", __func__, |
Sachin Bhayare | 3d3767e | 2018-01-02 21:10:57 +0530 | [diff] [blame] | 694 | HDCP_STATE_NAME, ddc_data.what); |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 695 | return rc; |
| 696 | } |
| 697 | DEV_DBG("%s: %s: %s: buf[0]=%x, [1]=%x,[2]=%x, [3]=%x\n", |
Sachin Bhayare | 3d3767e | 2018-01-02 21:10:57 +0530 | [diff] [blame] | 698 | __func__, HDCP_STATE_NAME, ddc_data.what, |
| 699 | ddc_data.data_buf[0], ddc_data.data_buf[1], |
| 700 | ddc_data.data_buf[2], ddc_data.data_buf[3]); |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 701 | if (wr) { |
| 702 | DSS_REG_W((io), (reg), |
Sachin Bhayare | 3d3767e | 2018-01-02 21:10:57 +0530 | [diff] [blame] | 703 | (ddc_data.data_buf[3] << 24 | |
| 704 | ddc_data.data_buf[2] << 16 | |
| 705 | ddc_data.data_buf[1] << 8 | |
| 706 | ddc_data.data_buf[0])); |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 707 | } |
| 708 | } while (0); |
| 709 | return rc; |
| 710 | } |
| 711 | |
| 712 | static int hdmi_hdcp_transfer_v_h(struct hdmi_hdcp_ctrl *hdcp_ctrl) |
| 713 | { |
| 714 | char what[20]; |
| 715 | int rc = 0; |
| 716 | u8 buf[4]; |
| 717 | struct hdmi_tx_ddc_data ddc_data; |
| 718 | struct dss_io_data *io; |
| 719 | |
| 720 | struct scm_hdcp_req scm_buf[SCM_HDCP_MAX_REG]; |
| 721 | u32 phy_addr; |
| 722 | |
| 723 | struct hdmi_hdcp_reg_data reg_data[] = { |
| 724 | {HDMI_HDCP_RCVPORT_DATA7, 0x20, "V' H0"}, |
| 725 | {HDMI_HDCP_RCVPORT_DATA8, 0x24, "V' H1"}, |
| 726 | {HDMI_HDCP_RCVPORT_DATA9, 0x28, "V' H2"}, |
| 727 | {HDMI_HDCP_RCVPORT_DATA10, 0x2C, "V' H3"}, |
| 728 | {HDMI_HDCP_RCVPORT_DATA11, 0x30, "V' H4"}, |
| 729 | }; |
| 730 | u32 size = ARRAY_SIZE(reg_data)/sizeof(reg_data[0]); |
| 731 | u32 iter = 0; |
| 732 | u32 ret = 0; |
| 733 | u32 resp = 0; |
| 734 | |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 735 | memset(&ddc_data, 0, sizeof(ddc_data)); |
| 736 | ddc_data.dev_addr = 0x74; |
| 737 | ddc_data.data_buf = buf; |
| 738 | ddc_data.data_len = 4; |
| 739 | ddc_data.request_len = 4; |
| 740 | ddc_data.retry = 5; |
| 741 | ddc_data.what = what; |
| 742 | |
Sachin Bhayare | 3d3767e | 2018-01-02 21:10:57 +0530 | [diff] [blame] | 743 | if (!hdcp_ctrl || !hdcp_ctrl->init_data.core_io) { |
| 744 | DEV_ERR("%s: invalid input\n", __func__); |
| 745 | return -EINVAL; |
| 746 | } |
| 747 | |
| 748 | phy_addr = hdcp_ctrl->init_data.phy_addr; |
| 749 | |
| 750 | io = hdcp_ctrl->init_data.core_io; |
| 751 | |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 752 | if (hdcp_ctrl->tz_hdcp) { |
| 753 | memset(scm_buf, 0x00, sizeof(scm_buf)); |
| 754 | |
| 755 | for (iter = 0; iter < size && iter < SCM_HDCP_MAX_REG; iter++) { |
| 756 | struct hdmi_hdcp_reg_data *rd = reg_data + iter; |
| 757 | |
Sachin Bhayare | 3d3767e | 2018-01-02 21:10:57 +0530 | [diff] [blame] | 758 | if (read_write_v_h(hdcp_ctrl, ddc_data, io, rd->off, |
| 759 | rd->name, 0, false)) |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 760 | goto error; |
| 761 | |
| 762 | rd->reg_val = buf[3] << 24 | buf[2] << 16 | |
| 763 | buf[1] << 8 | buf[0]; |
| 764 | |
| 765 | scm_buf[iter].addr = phy_addr + reg_data[iter].reg_id; |
| 766 | scm_buf[iter].val = reg_data[iter].reg_val; |
| 767 | } |
| 768 | |
| 769 | ret = hdcp_scm_call(scm_buf, &resp); |
| 770 | if (ret || resp) { |
| 771 | DEV_ERR("%s: error: scm_call ret = %d, resp = %d\n", |
| 772 | __func__, ret, resp); |
| 773 | rc = -EINVAL; |
| 774 | goto error; |
| 775 | } |
| 776 | } else if (hdcp_ctrl->hdmi_tx_ver_4) { |
| 777 | struct dss_io_data *hdcp_io = hdcp_ctrl->init_data.hdcp_io; |
| 778 | |
| 779 | /* Read V'.HO 4 Byte at offset 0x20 */ |
Sachin Bhayare | 3d3767e | 2018-01-02 21:10:57 +0530 | [diff] [blame] | 780 | if (read_write_v_h(hdcp_ctrl, ddc_data, hdcp_io, 0x20, "V' H0", |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 781 | HDCP_SEC_TZ_HV_HLOS_HDCP_RCVPORT_DATA7, true)) |
| 782 | goto error; |
| 783 | |
| 784 | /* Read V'.H1 4 Byte at offset 0x24 */ |
Sachin Bhayare | 3d3767e | 2018-01-02 21:10:57 +0530 | [diff] [blame] | 785 | if (read_write_v_h(hdcp_ctrl, ddc_data, hdcp_io, 0x24, "V' H1", |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 786 | HDCP_SEC_TZ_HV_HLOS_HDCP_RCVPORT_DATA8, true)) |
| 787 | goto error; |
| 788 | |
| 789 | /* Read V'.H2 4 Byte at offset 0x28 */ |
Sachin Bhayare | 3d3767e | 2018-01-02 21:10:57 +0530 | [diff] [blame] | 790 | if (read_write_v_h(hdcp_ctrl, ddc_data, hdcp_io, 0x28, "V' H2", |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 791 | HDCP_SEC_TZ_HV_HLOS_HDCP_RCVPORT_DATA9, true)) |
| 792 | goto error; |
| 793 | |
| 794 | /* Read V'.H3 4 Byte at offset 0x2C */ |
Sachin Bhayare | 3d3767e | 2018-01-02 21:10:57 +0530 | [diff] [blame] | 795 | if (read_write_v_h(hdcp_ctrl, ddc_data, hdcp_io, 0x2C, "V' H3", |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 796 | HDCP_SEC_TZ_HV_HLOS_HDCP_RCVPORT_DATA10, true)) |
| 797 | goto error; |
| 798 | |
| 799 | /* Read V'.H4 4 Byte at offset 0x30 */ |
Sachin Bhayare | 3d3767e | 2018-01-02 21:10:57 +0530 | [diff] [blame] | 800 | if (read_write_v_h(hdcp_ctrl, ddc_data, hdcp_io, 0x30, "V' H4", |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 801 | HDCP_SEC_TZ_HV_HLOS_HDCP_RCVPORT_DATA11, true)) |
| 802 | goto error; |
| 803 | } else { |
| 804 | /* Read V'.HO 4 Byte at offset 0x20 */ |
Sachin Bhayare | 3d3767e | 2018-01-02 21:10:57 +0530 | [diff] [blame] | 805 | if (read_write_v_h(hdcp_ctrl, ddc_data, io, 0x20, "V' H0", |
| 806 | HDMI_HDCP_RCVPORT_DATA7, true)) |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 807 | goto error; |
| 808 | |
| 809 | /* Read V'.H1 4 Byte at offset 0x24 */ |
Sachin Bhayare | 3d3767e | 2018-01-02 21:10:57 +0530 | [diff] [blame] | 810 | if (read_write_v_h(hdcp_ctrl, ddc_data, io, 0x24, "V' H1", |
| 811 | HDMI_HDCP_RCVPORT_DATA8, true)) |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 812 | goto error; |
| 813 | |
| 814 | /* Read V'.H2 4 Byte at offset 0x28 */ |
Sachin Bhayare | 3d3767e | 2018-01-02 21:10:57 +0530 | [diff] [blame] | 815 | if (read_write_v_h(hdcp_ctrl, ddc_data, io, 0x28, "V' H2", |
| 816 | HDMI_HDCP_RCVPORT_DATA9, true)) |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 817 | goto error; |
| 818 | |
| 819 | /* Read V'.H3 4 Byte at offset 0x2C */ |
Sachin Bhayare | 3d3767e | 2018-01-02 21:10:57 +0530 | [diff] [blame] | 820 | if (read_write_v_h(hdcp_ctrl, ddc_data, io, 0x2C, "V' H3", |
| 821 | HDMI_HDCP_RCVPORT_DATA10, true)) |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 822 | goto error; |
| 823 | |
| 824 | /* Read V'.H4 4 Byte at offset 0x30 */ |
Sachin Bhayare | 3d3767e | 2018-01-02 21:10:57 +0530 | [diff] [blame] | 825 | if (read_write_v_h(hdcp_ctrl, ddc_data, io, 0x30, "V' H4", |
| 826 | HDMI_HDCP_RCVPORT_DATA11, true)) |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 827 | goto error; |
| 828 | } |
| 829 | |
| 830 | error: |
| 831 | return rc; |
| 832 | } |
| 833 | |
| 834 | static int hdmi_hdcp_authentication_part2(struct hdmi_hdcp_ctrl *hdcp_ctrl) |
| 835 | { |
| 836 | int rc, cnt, i; |
| 837 | struct hdmi_tx_ddc_data ddc_data; |
| 838 | u32 timeout_count, down_stream_devices = 0; |
| 839 | u32 repeater_cascade_depth = 0; |
| 840 | u8 buf[0xFF]; |
| 841 | u8 *ksv_fifo = NULL; |
| 842 | u8 bcaps; |
| 843 | u16 bstatus, max_devs_exceeded = 0, max_cascade_exceeded = 0; |
| 844 | u32 link0_status; |
| 845 | u32 ksv_bytes; |
| 846 | struct dss_io_data *io; |
| 847 | |
| 848 | struct scm_hdcp_req scm_buf[SCM_HDCP_MAX_REG]; |
| 849 | u32 phy_addr; |
| 850 | u32 ret = 0; |
| 851 | u32 resp = 0; |
| 852 | |
| 853 | if (!hdcp_ctrl || !hdcp_ctrl->init_data.core_io) { |
| 854 | DEV_ERR("%s: invalid input\n", __func__); |
| 855 | rc = -EINVAL; |
| 856 | goto error; |
| 857 | } |
| 858 | |
| 859 | phy_addr = hdcp_ctrl->init_data.phy_addr; |
| 860 | |
| 861 | if (hdcp_ctrl->hdcp_state != HDCP_STATE_AUTHENTICATING) { |
| 862 | DEV_DBG("%s: %s: invalid state. returning\n", __func__, |
| 863 | HDCP_STATE_NAME); |
| 864 | rc = -EINVAL; |
| 865 | goto error; |
| 866 | } |
| 867 | |
| 868 | ksv_fifo = hdcp_ctrl->current_tp.ksv_list; |
| 869 | |
| 870 | io = hdcp_ctrl->init_data.core_io; |
| 871 | |
| 872 | memset(buf, 0, sizeof(buf)); |
| 873 | memset(ksv_fifo, 0, |
| 874 | sizeof(hdcp_ctrl->current_tp.ksv_list)); |
| 875 | |
| 876 | /* |
| 877 | * Wait until READY bit is set in BCAPS, as per HDCP specifications |
| 878 | * maximum permitted time to check for READY bit is five seconds. |
| 879 | */ |
| 880 | timeout_count = 50; |
| 881 | do { |
| 882 | timeout_count--; |
| 883 | /* Read BCAPS at offset 0x40 */ |
| 884 | memset(&ddc_data, 0, sizeof(ddc_data)); |
| 885 | ddc_data.dev_addr = 0x74; |
| 886 | ddc_data.offset = 0x40; |
| 887 | ddc_data.data_buf = &bcaps; |
| 888 | ddc_data.data_len = 1; |
| 889 | ddc_data.request_len = 1; |
| 890 | ddc_data.retry = 5; |
| 891 | ddc_data.what = "Bcaps"; |
| 892 | ddc_data.retry_align = true; |
| 893 | |
| 894 | hdcp_ctrl->init_data.ddc_ctrl->ddc_data = ddc_data; |
| 895 | |
| 896 | rc = hdmi_ddc_read(hdcp_ctrl->init_data.ddc_ctrl); |
| 897 | if (rc) { |
| 898 | DEV_ERR("%s: %s: BCAPS read failed\n", __func__, |
| 899 | HDCP_STATE_NAME); |
| 900 | goto error; |
| 901 | } |
| 902 | msleep(100); |
| 903 | } while (!(bcaps & BIT(5)) && timeout_count); |
| 904 | |
| 905 | /* Read BSTATUS at offset 0x41 */ |
| 906 | memset(&ddc_data, 0, sizeof(ddc_data)); |
| 907 | ddc_data.dev_addr = 0x74; |
| 908 | ddc_data.offset = 0x41; |
| 909 | ddc_data.data_buf = buf; |
| 910 | ddc_data.data_len = 2; |
| 911 | ddc_data.request_len = 2; |
| 912 | ddc_data.retry = 5; |
| 913 | ddc_data.what = "Bstatuss"; |
| 914 | ddc_data.retry_align = true; |
| 915 | |
| 916 | hdcp_ctrl->init_data.ddc_ctrl->ddc_data = ddc_data; |
| 917 | |
| 918 | rc = hdmi_ddc_read(hdcp_ctrl->init_data.ddc_ctrl); |
| 919 | if (rc) { |
| 920 | DEV_ERR("%s: %s: BSTATUS read failed\n", __func__, |
| 921 | HDCP_STATE_NAME); |
| 922 | goto error; |
| 923 | } |
| 924 | bstatus = buf[1]; |
| 925 | bstatus = (bstatus << 8) | buf[0]; |
| 926 | |
| 927 | if (hdcp_ctrl->tz_hdcp) { |
| 928 | memset(scm_buf, 0x00, sizeof(scm_buf)); |
| 929 | |
| 930 | /* Write BSTATUS and BCAPS to HDCP registers */ |
| 931 | scm_buf[0].addr = phy_addr + HDMI_HDCP_RCVPORT_DATA12; |
| 932 | scm_buf[0].val = bcaps | (bstatus << 8); |
| 933 | |
| 934 | ret = hdcp_scm_call(scm_buf, &resp); |
| 935 | if (ret || resp) { |
| 936 | DEV_ERR("%s: error: scm_call ret = %d, resp = %d\n", |
| 937 | __func__, ret, resp); |
| 938 | rc = -EINVAL; |
| 939 | goto error; |
| 940 | } |
| 941 | } else if (hdcp_ctrl->hdmi_tx_ver_4) { |
| 942 | DSS_REG_W(hdcp_ctrl->init_data.hdcp_io, |
| 943 | HDCP_SEC_TZ_HV_HLOS_HDCP_RCVPORT_DATA12, |
| 944 | bcaps | (bstatus << 8)); |
| 945 | } else { |
| 946 | DSS_REG_W(io, HDMI_HDCP_RCVPORT_DATA12, bcaps | (bstatus << 8)); |
| 947 | } |
| 948 | |
| 949 | down_stream_devices = bstatus & 0x7F; |
| 950 | if (down_stream_devices == 0) { |
| 951 | /* |
| 952 | * If no downstream devices are attached to the repeater |
| 953 | * then part II fails. |
| 954 | * todo: The other approach would be to continue PART II. |
| 955 | */ |
| 956 | DEV_ERR("%s: %s: No downstream devices\n", __func__, |
| 957 | HDCP_STATE_NAME); |
| 958 | rc = -EINVAL; |
| 959 | goto error; |
| 960 | } |
| 961 | |
| 962 | /* Cascaded repeater depth */ |
| 963 | repeater_cascade_depth = (bstatus >> 8) & 0x7; |
| 964 | |
| 965 | /* |
| 966 | * HDCP Compliance 1B-05: |
| 967 | * Check if no. of devices connected to repeater |
| 968 | * exceed max_devices_connected from bit 7 of Bstatus. |
| 969 | */ |
| 970 | max_devs_exceeded = (bstatus & BIT(7)) >> 7; |
| 971 | if (max_devs_exceeded == 0x01) { |
| 972 | DEV_ERR("%s: %s: no. of devs connected exceeds max allowed", |
| 973 | __func__, HDCP_STATE_NAME); |
| 974 | rc = -EINVAL; |
| 975 | goto error; |
| 976 | } |
| 977 | |
| 978 | /* |
| 979 | * HDCP Compliance 1B-06: |
| 980 | * Check if no. of cascade connected to repeater |
| 981 | * exceed max_cascade_connected from bit 11 of Bstatus. |
| 982 | */ |
| 983 | max_cascade_exceeded = (bstatus & BIT(11)) >> 11; |
| 984 | if (max_cascade_exceeded == 0x01) { |
| 985 | DEV_ERR("%s: %s: no. of cascade conn exceeds max allowed", |
| 986 | __func__, HDCP_STATE_NAME); |
| 987 | rc = -EINVAL; |
| 988 | goto error; |
| 989 | } |
| 990 | |
| 991 | /* |
| 992 | * Read KSV FIFO over DDC |
| 993 | * Key Slection vector FIFO Used to pull downstream KSVs |
| 994 | * from HDCP Repeaters. |
| 995 | * All bytes (DEVICE_COUNT * 5) must be read in a single, |
| 996 | * auto incrementing access. |
| 997 | * All bytes read as 0x00 for HDCP Receivers that are not |
| 998 | * HDCP Repeaters (REPEATER == 0). |
| 999 | */ |
| 1000 | ksv_bytes = 5 * down_stream_devices; |
| 1001 | memset(&ddc_data, 0, sizeof(ddc_data)); |
| 1002 | ddc_data.dev_addr = 0x74; |
| 1003 | ddc_data.offset = 0x43; |
| 1004 | ddc_data.data_buf = ksv_fifo; |
| 1005 | ddc_data.data_len = ksv_bytes; |
| 1006 | ddc_data.request_len = ksv_bytes; |
| 1007 | ddc_data.retry = 5; |
| 1008 | ddc_data.what = "KSV FIFO"; |
| 1009 | |
| 1010 | hdcp_ctrl->init_data.ddc_ctrl->ddc_data = ddc_data; |
| 1011 | |
| 1012 | cnt = 0; |
| 1013 | do { |
| 1014 | rc = hdmi_ddc_read(hdcp_ctrl->init_data.ddc_ctrl); |
| 1015 | if (rc) { |
| 1016 | DEV_ERR("%s: %s: KSV FIFO read failed\n", __func__, |
| 1017 | HDCP_STATE_NAME); |
| 1018 | /* |
| 1019 | * HDCP Compliace Test case 1B-01: |
| 1020 | * Wait here until all the ksv bytes have been |
| 1021 | * read from the KSV FIFO register. |
| 1022 | */ |
| 1023 | msleep(25); |
| 1024 | } else { |
| 1025 | break; |
| 1026 | } |
| 1027 | cnt++; |
| 1028 | } while (cnt != 20); |
| 1029 | |
| 1030 | if (cnt == 20) |
| 1031 | goto error; |
| 1032 | |
| 1033 | rc = hdmi_hdcp_transfer_v_h(hdcp_ctrl); |
| 1034 | if (rc) |
| 1035 | goto error; |
| 1036 | |
| 1037 | /* |
| 1038 | * Write KSV FIFO to HDCP_SHA_DATA. |
| 1039 | * This is done 1 byte at time starting with the LSB. |
| 1040 | * On the very last byte write, the HDCP_SHA_DATA_DONE bit[0] |
| 1041 | */ |
| 1042 | |
| 1043 | /* First, reset SHA engine */ |
| 1044 | /* Next, enable SHA engine, SEL=DIGA_HDCP */ |
| 1045 | if (hdcp_ctrl->tz_hdcp) { |
| 1046 | memset(scm_buf, 0x00, sizeof(scm_buf)); |
| 1047 | |
| 1048 | scm_buf[0].addr = phy_addr + HDMI_HDCP_SHA_CTRL; |
| 1049 | scm_buf[0].val = HDCP_REG_ENABLE; |
| 1050 | scm_buf[1].addr = phy_addr + HDMI_HDCP_SHA_CTRL; |
| 1051 | scm_buf[1].val = HDCP_REG_DISABLE; |
| 1052 | |
| 1053 | ret = hdcp_scm_call(scm_buf, &resp); |
| 1054 | if (ret || resp) { |
| 1055 | DEV_ERR("%s: error: scm_call ret = %d, resp = %d\n", |
| 1056 | __func__, ret, resp); |
| 1057 | rc = -EINVAL; |
| 1058 | goto error; |
| 1059 | } |
| 1060 | } else if (hdcp_ctrl->hdmi_tx_ver_4) { |
| 1061 | DSS_REG_W(hdcp_ctrl->init_data.hdcp_io, |
| 1062 | HDCP_SEC_TZ_HV_HLOS_HDCP_SHA_CTRL, |
| 1063 | HDCP_REG_ENABLE); |
| 1064 | DSS_REG_W(hdcp_ctrl->init_data.hdcp_io, |
| 1065 | HDCP_SEC_TZ_HV_HLOS_HDCP_SHA_CTRL, |
| 1066 | HDCP_REG_DISABLE); |
| 1067 | } else { |
| 1068 | DSS_REG_W(io, HDMI_HDCP_SHA_CTRL, HDCP_REG_ENABLE); |
| 1069 | DSS_REG_W(io, HDMI_HDCP_SHA_CTRL, HDCP_REG_DISABLE); |
| 1070 | } |
| 1071 | |
| 1072 | for (i = 0; i < ksv_bytes - 1; i++) { |
| 1073 | /* Write KSV byte and do not set DONE bit[0] */ |
| 1074 | if (hdcp_ctrl->tz_hdcp) { |
| 1075 | memset(scm_buf, 0x00, sizeof(scm_buf)); |
| 1076 | |
| 1077 | scm_buf[0].addr = phy_addr + HDMI_HDCP_SHA_DATA; |
| 1078 | scm_buf[0].val = ksv_fifo[i] << 16; |
| 1079 | |
| 1080 | ret = hdcp_scm_call(scm_buf, &resp); |
| 1081 | if (ret || resp) { |
| 1082 | DEV_ERR("%s: scm_call ret = %d, resp = %d\n", |
| 1083 | __func__, ret, resp); |
| 1084 | rc = -EINVAL; |
| 1085 | goto error; |
| 1086 | } |
| 1087 | } else if (hdcp_ctrl->hdmi_tx_ver_4) { |
| 1088 | DSS_REG_W_ND(hdcp_ctrl->init_data.hdcp_io, |
| 1089 | HDCP_SEC_TZ_HV_HLOS_HDCP_SHA_DATA, |
| 1090 | ksv_fifo[i] << 16); |
| 1091 | } else { |
| 1092 | DSS_REG_W_ND(io, HDMI_HDCP_SHA_DATA, ksv_fifo[i] << 16); |
| 1093 | } |
| 1094 | |
| 1095 | /* |
| 1096 | * Once 64 bytes have been written, we need to poll for |
| 1097 | * HDCP_SHA_BLOCK_DONE before writing any further |
| 1098 | */ |
| 1099 | if (i && !((i + 1) % 64)) { |
| 1100 | timeout_count = 100; |
| 1101 | while (!(DSS_REG_R(io, HDMI_HDCP_SHA_STATUS) & BIT(0)) |
| 1102 | && (--timeout_count)) { |
| 1103 | DEV_DBG("%s: %s: Wrote 64 bytes KSV FIFO\n", |
| 1104 | __func__, HDCP_STATE_NAME); |
| 1105 | DEV_DBG("%s: %s: HDCP_SHA_STATUS=%08x\n", |
| 1106 | __func__, HDCP_STATE_NAME, |
| 1107 | DSS_REG_R(io, HDMI_HDCP_SHA_STATUS)); |
| 1108 | msleep(20); |
| 1109 | } |
| 1110 | if (!timeout_count) { |
| 1111 | rc = -ETIMEDOUT; |
| 1112 | DEV_ERR("%s: %s: Write KSV FIFO timedout", |
| 1113 | __func__, HDCP_STATE_NAME); |
| 1114 | goto error; |
| 1115 | } |
| 1116 | } |
| 1117 | |
| 1118 | } |
| 1119 | |
| 1120 | /* Write l to DONE bit[0] */ |
| 1121 | if (hdcp_ctrl->tz_hdcp) { |
| 1122 | memset(scm_buf, 0x00, sizeof(scm_buf)); |
| 1123 | |
| 1124 | scm_buf[0].addr = phy_addr + HDMI_HDCP_SHA_DATA; |
| 1125 | scm_buf[0].val = (ksv_fifo[ksv_bytes - 1] << 16) | 0x1; |
| 1126 | |
| 1127 | ret = hdcp_scm_call(scm_buf, &resp); |
| 1128 | if (ret || resp) { |
| 1129 | DEV_ERR("%s: error: scm_call ret = %d, resp = %d\n", |
| 1130 | __func__, ret, resp); |
| 1131 | rc = -EINVAL; |
| 1132 | goto error; |
| 1133 | } |
| 1134 | } else if (hdcp_ctrl->hdmi_tx_ver_4) { |
| 1135 | DSS_REG_W_ND(hdcp_ctrl->init_data.hdcp_io, |
| 1136 | HDCP_SEC_TZ_HV_HLOS_HDCP_SHA_DATA, |
| 1137 | (ksv_fifo[ksv_bytes - 1] << 16) | 0x1); |
| 1138 | } else { |
| 1139 | DSS_REG_W_ND(io, HDMI_HDCP_SHA_DATA, |
| 1140 | (ksv_fifo[ksv_bytes - 1] << 16) | 0x1); |
| 1141 | } |
| 1142 | |
| 1143 | /* Now wait for HDCP_SHA_COMP_DONE */ |
| 1144 | timeout_count = 100; |
| 1145 | while ((0x10 != (DSS_REG_R(io, HDMI_HDCP_SHA_STATUS) |
| 1146 | & 0xFFFFFF10)) && --timeout_count) |
| 1147 | msleep(20); |
| 1148 | if (!timeout_count) { |
| 1149 | rc = -ETIMEDOUT; |
| 1150 | DEV_ERR("%s: %s: SHA computation timedout", __func__, |
| 1151 | HDCP_STATE_NAME); |
| 1152 | goto error; |
| 1153 | } |
| 1154 | |
| 1155 | /* Wait for V_MATCHES */ |
| 1156 | timeout_count = 100; |
| 1157 | link0_status = DSS_REG_R(io, HDMI_HDCP_LINK0_STATUS); |
| 1158 | while (((link0_status & BIT(20)) != BIT(20)) && --timeout_count) { |
| 1159 | DEV_DBG("%s: %s: Waiting for V_MATCHES(%d). l0_status=0x%08x\n", |
| 1160 | __func__, HDCP_STATE_NAME, timeout_count, link0_status); |
| 1161 | msleep(20); |
| 1162 | link0_status = DSS_REG_R(io, HDMI_HDCP_LINK0_STATUS); |
| 1163 | } |
| 1164 | if (!timeout_count) { |
| 1165 | rc = -ETIMEDOUT; |
| 1166 | DEV_ERR("%s: %s: HDCP V Match timedout", __func__, |
| 1167 | HDCP_STATE_NAME); |
| 1168 | goto error; |
| 1169 | } |
| 1170 | |
| 1171 | error: |
| 1172 | if (rc) |
| 1173 | DEV_ERR("%s: %s: Authentication Part II failed\n", __func__, |
| 1174 | hdcp_ctrl ? HDCP_STATE_NAME : "???"); |
| 1175 | else |
| 1176 | DEV_INFO("%s: %s: Authentication Part II successful\n", |
| 1177 | __func__, HDCP_STATE_NAME); |
| 1178 | |
| 1179 | if (!hdcp_ctrl) { |
| 1180 | DEV_ERR("%s: hdcp_ctrl null. Topology not updated\n", |
| 1181 | __func__); |
| 1182 | return rc; |
| 1183 | } |
| 1184 | /* Update topology information */ |
| 1185 | hdcp_ctrl->current_tp.dev_count = down_stream_devices; |
| 1186 | hdcp_ctrl->current_tp.max_cascade_exceeded = max_cascade_exceeded; |
| 1187 | hdcp_ctrl->current_tp.max_dev_exceeded = max_devs_exceeded; |
| 1188 | hdcp_ctrl->current_tp.depth = repeater_cascade_depth; |
| 1189 | |
| 1190 | return rc; |
| 1191 | } /* hdmi_hdcp_authentication_part2 */ |
| 1192 | |
| 1193 | static void hdmi_hdcp_cache_topology(struct hdmi_hdcp_ctrl *hdcp_ctrl) |
| 1194 | { |
| 1195 | if (!hdcp_ctrl || !hdcp_ctrl->init_data.core_io) { |
| 1196 | DEV_ERR("%s: invalid input\n", __func__); |
| 1197 | return; |
| 1198 | } |
| 1199 | |
| 1200 | memcpy((void *)&hdcp_ctrl->cached_tp, |
| 1201 | (void *) &hdcp_ctrl->current_tp, |
| 1202 | sizeof(hdcp_ctrl->cached_tp)); |
| 1203 | } |
| 1204 | |
| 1205 | static void hdmi_hdcp_notify_topology(struct hdmi_hdcp_ctrl *hdcp_ctrl) |
| 1206 | { |
| 1207 | char a[16], b[16]; |
| 1208 | char *envp[] = { |
| 1209 | [0] = "HDCP_MGR_EVENT=MSG_READY", |
| 1210 | [1] = a, |
| 1211 | [2] = b, |
| 1212 | NULL, |
| 1213 | }; |
| 1214 | |
| 1215 | snprintf(envp[1], 16, "%d", (int)DOWN_CHECK_TOPOLOGY); |
| 1216 | snprintf(envp[2], 16, "%d", (int)HDCP_V1_TX); |
| 1217 | kobject_uevent_env(hdcp_ctrl->init_data.sysfs_kobj, KOBJ_CHANGE, envp); |
| 1218 | |
| 1219 | DEV_DBG("%s Event Sent: %s msgID = %s srcID = %s\n", __func__, |
| 1220 | envp[0], envp[1], envp[2]); |
| 1221 | } |
| 1222 | |
| 1223 | static void hdmi_hdcp_int_work(struct work_struct *work) |
| 1224 | { |
| 1225 | struct hdmi_hdcp_ctrl *hdcp_ctrl = container_of(work, |
| 1226 | struct hdmi_hdcp_ctrl, hdcp_int_work); |
| 1227 | |
| 1228 | if (!hdcp_ctrl) { |
| 1229 | DEV_ERR("%s: invalid input\n", __func__); |
| 1230 | return; |
| 1231 | } |
| 1232 | |
| 1233 | mutex_lock(hdcp_ctrl->init_data.mutex); |
| 1234 | hdcp_ctrl->hdcp_state = HDCP_STATE_AUTH_FAIL; |
| 1235 | mutex_unlock(hdcp_ctrl->init_data.mutex); |
| 1236 | |
| 1237 | if (hdcp_ctrl->init_data.notify_status) { |
| 1238 | hdcp_ctrl->init_data.notify_status( |
| 1239 | hdcp_ctrl->init_data.cb_data, |
| 1240 | hdcp_ctrl->hdcp_state); |
| 1241 | } |
| 1242 | } /* hdmi_hdcp_int_work */ |
| 1243 | |
| 1244 | static void hdmi_hdcp_auth_work(struct work_struct *work) |
| 1245 | { |
| 1246 | int rc; |
| 1247 | struct delayed_work *dw = to_delayed_work(work); |
| 1248 | struct hdmi_hdcp_ctrl *hdcp_ctrl = container_of(dw, |
| 1249 | struct hdmi_hdcp_ctrl, hdcp_auth_work); |
| 1250 | struct dss_io_data *io; |
| 1251 | |
| 1252 | if (!hdcp_ctrl) { |
| 1253 | DEV_ERR("%s: invalid input\n", __func__); |
| 1254 | return; |
| 1255 | } |
| 1256 | |
| 1257 | if (hdcp_ctrl->hdcp_state != HDCP_STATE_AUTHENTICATING) { |
| 1258 | DEV_DBG("%s: %s: invalid state. returning\n", __func__, |
| 1259 | HDCP_STATE_NAME); |
| 1260 | return; |
| 1261 | } |
| 1262 | |
| 1263 | io = hdcp_ctrl->init_data.core_io; |
| 1264 | /* Enabling Software DDC */ |
| 1265 | DSS_REG_W_ND(io, HDMI_DDC_ARBITRATION, DSS_REG_R(io, |
| 1266 | HDMI_DDC_ARBITRATION) & ~(BIT(4))); |
| 1267 | |
| 1268 | rc = hdmi_hdcp_authentication_part1(hdcp_ctrl); |
| 1269 | if (rc) { |
| 1270 | DEV_DBG("%s: %s: HDCP Auth Part I failed\n", __func__, |
| 1271 | HDCP_STATE_NAME); |
| 1272 | goto error; |
| 1273 | } |
| 1274 | |
| 1275 | if (hdcp_ctrl->current_tp.ds_type == DS_REPEATER) { |
| 1276 | rc = hdmi_hdcp_authentication_part2(hdcp_ctrl); |
| 1277 | if (rc) { |
| 1278 | DEV_DBG("%s: %s: HDCP Auth Part II failed\n", __func__, |
| 1279 | HDCP_STATE_NAME); |
| 1280 | goto error; |
| 1281 | } |
| 1282 | } else { |
| 1283 | DEV_INFO("%s: Downstream device is not a repeater\n", __func__); |
| 1284 | } |
| 1285 | /* Disabling software DDC before going into part3 to make sure |
| 1286 | * there is no Arbitration between software and hardware for DDCi |
| 1287 | */ |
| 1288 | DSS_REG_W_ND(io, HDMI_DDC_ARBITRATION, DSS_REG_R(io, |
| 1289 | HDMI_DDC_ARBITRATION) | (BIT(4))); |
| 1290 | |
| 1291 | error: |
| 1292 | /* |
| 1293 | * Ensure that the state did not change during authentication. |
| 1294 | * If it did, it means that deauthenticate/reauthenticate was |
| 1295 | * called. In that case, this function need not notify HDMI Tx |
| 1296 | * of the result |
| 1297 | */ |
| 1298 | mutex_lock(hdcp_ctrl->init_data.mutex); |
| 1299 | if (hdcp_ctrl->hdcp_state == HDCP_STATE_AUTHENTICATING) { |
| 1300 | if (rc) { |
| 1301 | hdcp_ctrl->hdcp_state = HDCP_STATE_AUTH_FAIL; |
| 1302 | } else { |
| 1303 | hdcp_ctrl->hdcp_state = HDCP_STATE_AUTHENTICATED; |
| 1304 | hdcp_ctrl->auth_retries = 0; |
| 1305 | hdmi_hdcp_cache_topology(hdcp_ctrl); |
| 1306 | hdmi_hdcp_notify_topology(hdcp_ctrl); |
| 1307 | } |
| 1308 | mutex_unlock(hdcp_ctrl->init_data.mutex); |
| 1309 | |
| 1310 | /* Notify HDMI Tx controller of the result */ |
| 1311 | DEV_DBG("%s: %s: Notifying HDMI Tx of auth result\n", |
| 1312 | __func__, HDCP_STATE_NAME); |
| 1313 | if (hdcp_ctrl->init_data.notify_status) { |
| 1314 | hdcp_ctrl->init_data.notify_status( |
| 1315 | hdcp_ctrl->init_data.cb_data, |
| 1316 | hdcp_ctrl->hdcp_state); |
| 1317 | } |
| 1318 | } else { |
| 1319 | DEV_DBG("%s: %s: HDCP state changed during authentication\n", |
| 1320 | __func__, HDCP_STATE_NAME); |
| 1321 | mutex_unlock(hdcp_ctrl->init_data.mutex); |
| 1322 | } |
| 1323 | } /* hdmi_hdcp_auth_work */ |
| 1324 | |
| 1325 | int hdmi_hdcp_authenticate(void *input) |
| 1326 | { |
| 1327 | struct hdmi_hdcp_ctrl *hdcp_ctrl = (struct hdmi_hdcp_ctrl *)input; |
| 1328 | |
| 1329 | if (!hdcp_ctrl) { |
| 1330 | DEV_ERR("%s: invalid input\n", __func__); |
| 1331 | return -EINVAL; |
| 1332 | } |
| 1333 | |
| 1334 | if (hdcp_ctrl->hdcp_state != HDCP_STATE_INACTIVE) { |
| 1335 | DEV_DBG("%s: %s: already active or activating. returning\n", |
| 1336 | __func__, HDCP_STATE_NAME); |
| 1337 | return 0; |
| 1338 | } |
| 1339 | |
| 1340 | DEV_DBG("%s: %s: Queuing work to start HDCP authentication", __func__, |
| 1341 | HDCP_STATE_NAME); |
| 1342 | |
| 1343 | if (!hdmi_hdcp_load_keys(input)) |
| 1344 | queue_delayed_work(hdcp_ctrl->init_data.workq, |
| 1345 | &hdcp_ctrl->hdcp_auth_work, HZ/2); |
| 1346 | else |
| 1347 | queue_work(hdcp_ctrl->init_data.workq, |
| 1348 | &hdcp_ctrl->hdcp_int_work); |
| 1349 | |
| 1350 | return 0; |
| 1351 | } /* hdmi_hdcp_authenticate */ |
| 1352 | |
| 1353 | int hdmi_hdcp_reauthenticate(void *input) |
| 1354 | { |
| 1355 | struct hdmi_hdcp_ctrl *hdcp_ctrl = (struct hdmi_hdcp_ctrl *)input; |
| 1356 | struct dss_io_data *io; |
| 1357 | u32 hdmi_hw_version; |
| 1358 | u32 ret = 0; |
| 1359 | |
| 1360 | if (!hdcp_ctrl || !hdcp_ctrl->init_data.core_io) { |
| 1361 | DEV_ERR("%s: invalid input\n", __func__); |
| 1362 | return -EINVAL; |
| 1363 | } |
| 1364 | |
| 1365 | io = hdcp_ctrl->init_data.core_io; |
| 1366 | |
| 1367 | if (hdcp_ctrl->hdcp_state != HDCP_STATE_AUTH_FAIL) { |
| 1368 | DEV_DBG("%s: %s: invalid state. returning\n", __func__, |
| 1369 | HDCP_STATE_NAME); |
| 1370 | return 0; |
| 1371 | } |
| 1372 | |
| 1373 | hdmi_hw_version = DSS_REG_R(io, HDMI_VERSION); |
| 1374 | if (hdmi_hw_version >= 0x30030000) { |
| 1375 | DSS_REG_W(io, HDMI_CTRL_SW_RESET, BIT(1)); |
| 1376 | DSS_REG_W(io, HDMI_CTRL_SW_RESET, 0); |
| 1377 | } |
| 1378 | |
| 1379 | /* Disable HDCP interrupts */ |
| 1380 | DSS_REG_W(io, HDMI_HDCP_INT_CTRL, 0); |
| 1381 | |
| 1382 | DSS_REG_W(io, HDMI_HDCP_RESET, BIT(0)); |
| 1383 | |
| 1384 | /* Wait to be clean on DDC HW engine */ |
| 1385 | hdmi_hdcp_hw_ddc_clean(hdcp_ctrl); |
| 1386 | |
| 1387 | /* Disable encryption and disable the HDCP block */ |
| 1388 | DSS_REG_W(io, HDMI_HDCP_CTRL, 0); |
| 1389 | |
| 1390 | if (!hdmi_hdcp_load_keys(input)) |
| 1391 | queue_delayed_work(hdcp_ctrl->init_data.workq, |
| 1392 | &hdcp_ctrl->hdcp_auth_work, HZ/2); |
| 1393 | else |
| 1394 | queue_work(hdcp_ctrl->init_data.workq, |
| 1395 | &hdcp_ctrl->hdcp_int_work); |
| 1396 | |
| 1397 | return ret; |
| 1398 | } /* hdmi_hdcp_reauthenticate */ |
| 1399 | |
| 1400 | void hdmi_hdcp_off(void *input) |
| 1401 | { |
| 1402 | struct hdmi_hdcp_ctrl *hdcp_ctrl = (struct hdmi_hdcp_ctrl *)input; |
| 1403 | struct dss_io_data *io; |
| 1404 | int rc = 0; |
| 1405 | |
| 1406 | if (!hdcp_ctrl || !hdcp_ctrl->init_data.core_io) { |
| 1407 | DEV_ERR("%s: invalid input\n", __func__); |
| 1408 | return; |
| 1409 | } |
| 1410 | |
| 1411 | io = hdcp_ctrl->init_data.core_io; |
| 1412 | |
| 1413 | if (hdcp_ctrl->hdcp_state == HDCP_STATE_INACTIVE) { |
| 1414 | DEV_DBG("%s: %s: inactive. returning\n", __func__, |
| 1415 | HDCP_STATE_NAME); |
| 1416 | return; |
| 1417 | } |
| 1418 | |
| 1419 | /* |
| 1420 | * Disable HDCP interrupts. |
| 1421 | * Also, need to set the state to inactive here so that any ongoing |
| 1422 | * reauth works will know that the HDCP session has been turned off. |
| 1423 | */ |
| 1424 | mutex_lock(hdcp_ctrl->init_data.mutex); |
| 1425 | DSS_REG_W(io, HDMI_HDCP_INT_CTRL, 0); |
| 1426 | hdcp_ctrl->hdcp_state = HDCP_STATE_INACTIVE; |
| 1427 | mutex_unlock(hdcp_ctrl->init_data.mutex); |
| 1428 | |
| 1429 | /* |
| 1430 | * Cancel any pending auth/reauth attempts. |
| 1431 | * If one is ongoing, this will wait for it to finish. |
| 1432 | * No more reauthentiaction attempts will be scheduled since we |
| 1433 | * set the currect state to inactive. |
| 1434 | */ |
| 1435 | rc = cancel_delayed_work_sync(&hdcp_ctrl->hdcp_auth_work); |
| 1436 | if (rc) |
| 1437 | DEV_DBG("%s: %s: Deleted hdcp auth work\n", __func__, |
| 1438 | HDCP_STATE_NAME); |
| 1439 | rc = cancel_work_sync(&hdcp_ctrl->hdcp_int_work); |
| 1440 | if (rc) |
| 1441 | DEV_DBG("%s: %s: Deleted hdcp int work\n", __func__, |
| 1442 | HDCP_STATE_NAME); |
| 1443 | |
| 1444 | DSS_REG_W(io, HDMI_HDCP_RESET, BIT(0)); |
| 1445 | |
| 1446 | /* Disable encryption and disable the HDCP block */ |
| 1447 | DSS_REG_W(io, HDMI_HDCP_CTRL, 0); |
| 1448 | |
| 1449 | DEV_DBG("%s: %s: HDCP: Off\n", __func__, HDCP_STATE_NAME); |
| 1450 | } /* hdmi_hdcp_off */ |
| 1451 | |
| 1452 | int hdmi_hdcp_isr(void *input) |
| 1453 | { |
| 1454 | struct hdmi_hdcp_ctrl *hdcp_ctrl = (struct hdmi_hdcp_ctrl *)input; |
| 1455 | int rc = 0; |
| 1456 | struct dss_io_data *io; |
| 1457 | u32 hdcp_int_val; |
| 1458 | |
| 1459 | if (!hdcp_ctrl || !hdcp_ctrl->init_data.core_io) { |
| 1460 | DEV_ERR("%s: invalid input\n", __func__); |
| 1461 | rc = -EINVAL; |
| 1462 | goto error; |
| 1463 | } |
| 1464 | |
| 1465 | io = hdcp_ctrl->init_data.core_io; |
| 1466 | |
| 1467 | hdcp_int_val = DSS_REG_R(io, HDMI_HDCP_INT_CTRL); |
| 1468 | |
| 1469 | /* Ignore HDCP interrupts if HDCP is disabled */ |
| 1470 | if (hdcp_ctrl->hdcp_state == HDCP_STATE_INACTIVE) { |
| 1471 | DSS_REG_W(io, HDMI_HDCP_INT_CTRL, HDCP_INT_CLR); |
| 1472 | return 0; |
| 1473 | } |
| 1474 | |
| 1475 | if (hdcp_int_val & BIT(0)) { |
| 1476 | /* AUTH_SUCCESS_INT */ |
| 1477 | DSS_REG_W(io, HDMI_HDCP_INT_CTRL, (hdcp_int_val | BIT(1))); |
| 1478 | DEV_INFO("%s: %s: AUTH_SUCCESS_INT received\n", __func__, |
| 1479 | HDCP_STATE_NAME); |
| 1480 | if (hdcp_ctrl->hdcp_state == HDCP_STATE_AUTHENTICATING) |
| 1481 | complete_all(&hdcp_ctrl->r0_checked); |
| 1482 | } |
| 1483 | |
| 1484 | if (hdcp_int_val & BIT(4)) { |
| 1485 | /* AUTH_FAIL_INT */ |
| 1486 | u32 link_status = DSS_REG_R(io, HDMI_HDCP_LINK0_STATUS); |
| 1487 | |
| 1488 | DSS_REG_W(io, HDMI_HDCP_INT_CTRL, (hdcp_int_val | BIT(5))); |
| 1489 | DEV_INFO("%s: %s: AUTH_FAIL_INT rcvd, LINK0_STATUS=0x%08x\n", |
| 1490 | __func__, HDCP_STATE_NAME, link_status); |
| 1491 | if (hdcp_ctrl->hdcp_state == HDCP_STATE_AUTHENTICATED) { |
| 1492 | /* Inform HDMI Tx of the failure */ |
| 1493 | queue_work(hdcp_ctrl->init_data.workq, |
| 1494 | &hdcp_ctrl->hdcp_int_work); |
| 1495 | /* todo: print debug log with auth fail reason */ |
| 1496 | } else if (hdcp_ctrl->hdcp_state == HDCP_STATE_AUTHENTICATING) { |
| 1497 | complete_all(&hdcp_ctrl->r0_checked); |
| 1498 | } |
| 1499 | |
| 1500 | /* Clear AUTH_FAIL_INFO as well */ |
| 1501 | DSS_REG_W(io, HDMI_HDCP_INT_CTRL, (hdcp_int_val | BIT(7))); |
| 1502 | } |
| 1503 | |
| 1504 | if (hdcp_int_val & BIT(8)) { |
| 1505 | /* DDC_XFER_REQ_INT */ |
| 1506 | DSS_REG_W(io, HDMI_HDCP_INT_CTRL, (hdcp_int_val | BIT(9))); |
| 1507 | DEV_INFO("%s: %s: DDC_XFER_REQ_INT received\n", __func__, |
| 1508 | HDCP_STATE_NAME); |
| 1509 | } |
| 1510 | |
| 1511 | if (hdcp_int_val & BIT(12)) { |
| 1512 | /* DDC_XFER_DONE_INT */ |
| 1513 | DSS_REG_W(io, HDMI_HDCP_INT_CTRL, (hdcp_int_val | BIT(13))); |
| 1514 | DEV_INFO("%s: %s: DDC_XFER_DONE received\n", __func__, |
| 1515 | HDCP_STATE_NAME); |
| 1516 | } |
| 1517 | |
| 1518 | error: |
| 1519 | return rc; |
| 1520 | } /* hdmi_hdcp_isr */ |
| 1521 | |
| 1522 | static ssize_t hdmi_hdcp_sysfs_rda_status(struct device *dev, |
| 1523 | struct device_attribute *attr, char *buf) |
| 1524 | { |
| 1525 | ssize_t ret; |
| 1526 | struct hdmi_hdcp_ctrl *hdcp_ctrl = |
| 1527 | hdmi_get_featuredata_from_sysfs_dev(dev, HDMI_TX_FEAT_HDCP); |
| 1528 | |
| 1529 | if (!hdcp_ctrl) { |
| 1530 | DEV_ERR("%s: invalid input\n", __func__); |
| 1531 | return -EINVAL; |
| 1532 | } |
| 1533 | |
| 1534 | mutex_lock(hdcp_ctrl->init_data.mutex); |
| 1535 | ret = snprintf(buf, PAGE_SIZE, "%d\n", hdcp_ctrl->hdcp_state); |
| 1536 | DEV_DBG("%s: '%d'\n", __func__, hdcp_ctrl->hdcp_state); |
| 1537 | mutex_unlock(hdcp_ctrl->init_data.mutex); |
| 1538 | |
| 1539 | return ret; |
| 1540 | } /* hdmi_hdcp_sysfs_rda_hdcp*/ |
| 1541 | |
| 1542 | static ssize_t hdmi_hdcp_sysfs_rda_tp(struct device *dev, |
| 1543 | struct device_attribute *attr, char *buf) |
| 1544 | { |
| 1545 | ssize_t ret = 0; |
| 1546 | struct hdmi_hdcp_ctrl *hdcp_ctrl = |
| 1547 | hdmi_get_featuredata_from_sysfs_dev(dev, HDMI_TX_FEAT_HDCP); |
| 1548 | |
| 1549 | if (!hdcp_ctrl) { |
| 1550 | DEV_ERR("%s: invalid input\n", __func__); |
| 1551 | return -EINVAL; |
| 1552 | } |
| 1553 | |
| 1554 | switch (hdcp_ctrl->tp_msgid) { |
| 1555 | case DOWN_CHECK_TOPOLOGY: |
| 1556 | case DOWN_REQUEST_TOPOLOGY: |
| 1557 | buf[MSG_ID_IDX] = hdcp_ctrl->tp_msgid; |
| 1558 | buf[RET_CODE_IDX] = HDCP_AUTHED; |
| 1559 | ret = HEADER_LEN; |
| 1560 | |
| 1561 | memcpy(buf + HEADER_LEN, &hdcp_ctrl->cached_tp, |
| 1562 | sizeof(struct HDCP_V2V1_MSG_TOPOLOGY)); |
| 1563 | |
| 1564 | ret += sizeof(struct HDCP_V2V1_MSG_TOPOLOGY); |
| 1565 | |
| 1566 | /* clear the flag once data is read back to user space*/ |
| 1567 | hdcp_ctrl->tp_msgid = -1; |
| 1568 | break; |
| 1569 | default: |
| 1570 | ret = -EINVAL; |
| 1571 | } |
| 1572 | |
| 1573 | return ret; |
| 1574 | } /* hdmi_hdcp_sysfs_rda_tp*/ |
| 1575 | |
| 1576 | static ssize_t hdmi_hdcp_sysfs_wta_tp(struct device *dev, |
| 1577 | struct device_attribute *attr, const char *buf, size_t count) |
| 1578 | { |
| 1579 | int msgid = 0; |
| 1580 | ssize_t ret = count; |
| 1581 | struct hdmi_hdcp_ctrl *hdcp_ctrl = |
| 1582 | hdmi_get_featuredata_from_sysfs_dev(dev, HDMI_TX_FEAT_HDCP); |
| 1583 | |
| 1584 | if (!hdcp_ctrl || !buf) { |
| 1585 | DEV_ERR("%s: invalid input\n", __func__); |
| 1586 | return -EINVAL; |
| 1587 | } |
| 1588 | |
| 1589 | msgid = buf[0]; |
| 1590 | |
| 1591 | switch (msgid) { |
| 1592 | case DOWN_CHECK_TOPOLOGY: |
| 1593 | case DOWN_REQUEST_TOPOLOGY: |
| 1594 | hdcp_ctrl->tp_msgid = msgid; |
| 1595 | break; |
| 1596 | /* more cases added here */ |
| 1597 | default: |
| 1598 | ret = -EINVAL; |
| 1599 | } |
| 1600 | |
| 1601 | return ret; |
| 1602 | } /* hdmi_tx_sysfs_wta_hpd */ |
| 1603 | |
| 1604 | static DEVICE_ATTR(status, 0444, hdmi_hdcp_sysfs_rda_status, NULL); |
| 1605 | static DEVICE_ATTR(tp, 0644, hdmi_hdcp_sysfs_rda_tp, |
| 1606 | hdmi_hdcp_sysfs_wta_tp); |
| 1607 | |
| 1608 | |
| 1609 | static struct attribute *hdmi_hdcp_fs_attrs[] = { |
| 1610 | &dev_attr_status.attr, |
| 1611 | &dev_attr_tp.attr, |
| 1612 | NULL, |
| 1613 | }; |
| 1614 | |
| 1615 | static struct attribute_group hdmi_hdcp_fs_attr_group = { |
| 1616 | .name = "hdcp", |
| 1617 | .attrs = hdmi_hdcp_fs_attrs, |
| 1618 | }; |
| 1619 | |
| 1620 | void hdmi_hdcp_deinit(void *input) |
| 1621 | { |
| 1622 | struct hdmi_hdcp_ctrl *hdcp_ctrl = (struct hdmi_hdcp_ctrl *)input; |
| 1623 | |
| 1624 | if (!hdcp_ctrl) { |
| 1625 | DEV_ERR("%s: invalid input\n", __func__); |
| 1626 | return; |
| 1627 | } |
| 1628 | |
| 1629 | sysfs_remove_group(hdcp_ctrl->init_data.sysfs_kobj, |
| 1630 | &hdmi_hdcp_fs_attr_group); |
| 1631 | |
| 1632 | kfree(hdcp_ctrl); |
| 1633 | } /* hdmi_hdcp_deinit */ |
| 1634 | |
| 1635 | void *hdmi_hdcp_init(struct hdmi_hdcp_init_data *init_data) |
| 1636 | { |
| 1637 | struct hdmi_hdcp_ctrl *hdcp_ctrl = NULL; |
| 1638 | int ret; |
| 1639 | static struct hdmi_hdcp_ops ops = { |
| 1640 | .hdmi_hdcp_isr = hdmi_hdcp_isr, |
| 1641 | .hdmi_hdcp_reauthenticate = hdmi_hdcp_reauthenticate, |
| 1642 | .hdmi_hdcp_authenticate = hdmi_hdcp_authenticate, |
| 1643 | .hdmi_hdcp_off = hdmi_hdcp_off |
| 1644 | }; |
| 1645 | |
| 1646 | if (!init_data || !init_data->core_io || !init_data->qfprom_io || |
| 1647 | !init_data->mutex || !init_data->ddc_ctrl || |
| 1648 | !init_data->notify_status || !init_data->workq || |
| 1649 | !init_data->cb_data) { |
| 1650 | DEV_ERR("%s: invalid input\n", __func__); |
| 1651 | goto error; |
| 1652 | } |
| 1653 | |
| 1654 | if (init_data->hdmi_tx_ver >= HDMI_TX_VERSION_4 |
| 1655 | && !init_data->hdcp_io) { |
| 1656 | DEV_ERR("%s: hdcp_io required for HDMI Tx Ver 4\n", __func__); |
| 1657 | goto error; |
| 1658 | } |
| 1659 | |
| 1660 | hdcp_ctrl = kzalloc(sizeof(*hdcp_ctrl), GFP_KERNEL); |
| 1661 | if (!hdcp_ctrl) { |
| 1662 | DEV_ERR("%s: Out of memory\n", __func__); |
| 1663 | goto error; |
| 1664 | } |
| 1665 | |
| 1666 | hdcp_ctrl->init_data = *init_data; |
| 1667 | hdcp_ctrl->ops = &ops; |
| 1668 | hdcp_ctrl->hdmi_tx_ver_4 = |
| 1669 | (init_data->hdmi_tx_ver >= HDMI_TX_VERSION_4); |
| 1670 | |
| 1671 | if (sysfs_create_group(init_data->sysfs_kobj, |
| 1672 | &hdmi_hdcp_fs_attr_group)) { |
| 1673 | DEV_ERR("%s: hdcp sysfs group creation failed\n", __func__); |
| 1674 | goto error; |
| 1675 | } |
| 1676 | |
| 1677 | INIT_DELAYED_WORK(&hdcp_ctrl->hdcp_auth_work, hdmi_hdcp_auth_work); |
| 1678 | INIT_WORK(&hdcp_ctrl->hdcp_int_work, hdmi_hdcp_int_work); |
| 1679 | |
| 1680 | hdcp_ctrl->hdcp_state = HDCP_STATE_INACTIVE; |
| 1681 | init_completion(&hdcp_ctrl->r0_checked); |
| 1682 | |
| 1683 | if (!hdcp_ctrl->hdmi_tx_ver_4) { |
| 1684 | ret = scm_is_call_available(SCM_SVC_HDCP, SCM_CMD_HDCP); |
| 1685 | if (ret <= 0) { |
| 1686 | DEV_ERR("%s: secure hdcp service unavailable, ret = %d", |
| 1687 | __func__, ret); |
| 1688 | } else { |
| 1689 | DEV_DBG("%s: tz_hdcp = 1\n", __func__); |
| 1690 | hdcp_ctrl->tz_hdcp = 1; |
| 1691 | } |
| 1692 | } |
| 1693 | |
| 1694 | DEV_DBG("%s: HDCP module initialized. HDCP_STATE=%s", __func__, |
| 1695 | HDCP_STATE_NAME); |
| 1696 | |
| 1697 | error: |
| 1698 | return (void *)hdcp_ctrl; |
| 1699 | } /* hdmi_hdcp_init */ |
| 1700 | |
| 1701 | struct hdmi_hdcp_ops *hdmi_hdcp_start(void *input) |
| 1702 | { |
| 1703 | return ((struct hdmi_hdcp_ctrl *)input)->ops; |
| 1704 | } |
| 1705 | |