Gitiles
Code Review Sign In
gerrit-public.fairphone.software / kernel / msm-4.9 / 070ea8e1f5c7003aa463fdc511b9f898544a2a39 / . / drivers / video / fbdev / msm / mdss_hdmi_util.h
blob: d26be9997a7cd8392b83ae2d63781d212213f041 [file] [log] [blame]
Sachin Bhayareeeb88892018-01-02 16:36:01 +0530[diff] [blame]1/* Copyright (c) 2010-2016, 2018, The Linux Foundation. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#ifndef __HDMI_UTIL_H__
14#define __HDMI_UTIL_H__
15#include <linux/mdss_io_util.h>
16#include "video/msm_hdmi_modes.h"
17
18/* HDMI_TX Registers */
19#define HDMI_CTRL (0x00000000)
20#define HDMI_TEST_PATTERN (0x00000010)
21#define HDMI_RANDOM_PATTERN (0x00000014)
22#define HDMI_PKT_BLK_CTRL (0x00000018)
23#define HDMI_STATUS (0x0000001C)
24#define HDMI_AUDIO_PKT_CTRL (0x00000020)
25#define HDMI_ACR_PKT_CTRL (0x00000024)
26#define HDMI_VBI_PKT_CTRL (0x00000028)
27#define HDMI_INFOFRAME_CTRL0 (0x0000002C)
28#define HDMI_INFOFRAME_CTRL1 (0x00000030)
29#define HDMI_GEN_PKT_CTRL (0x00000034)
30#define HDMI_ACP (0x0000003C)
31#define HDMI_GC (0x00000040)
32#define HDMI_AUDIO_PKT_CTRL2 (0x00000044)
33#define HDMI_ISRC1_0 (0x00000048)
34#define HDMI_ISRC1_1 (0x0000004C)
35#define HDMI_ISRC1_2 (0x00000050)
36#define HDMI_ISRC1_3 (0x00000054)
37#define HDMI_ISRC1_4 (0x00000058)
38#define HDMI_ISRC2_0 (0x0000005C)
39#define HDMI_ISRC2_1 (0x00000060)
40#define HDMI_ISRC2_2 (0x00000064)
41#define HDMI_ISRC2_3 (0x00000068)
42#define HDMI_AVI_INFO0 (0x0000006C)
43#define HDMI_AVI_INFO1 (0x00000070)
44#define HDMI_AVI_INFO2 (0x00000074)
45#define HDMI_AVI_INFO3 (0x00000078)
46#define HDMI_MPEG_INFO0 (0x0000007C)
47#define HDMI_MPEG_INFO1 (0x00000080)
48#define HDMI_GENERIC0_HDR (0x00000084)
49#define HDMI_GENERIC0_0 (0x00000088)
50#define HDMI_GENERIC0_1 (0x0000008C)
51#define HDMI_GENERIC0_2 (0x00000090)
52#define HDMI_GENERIC0_3 (0x00000094)
53#define HDMI_GENERIC0_4 (0x00000098)
54#define HDMI_GENERIC0_5 (0x0000009C)
55#define HDMI_GENERIC0_6 (0x000000A0)
56#define HDMI_GENERIC1_HDR (0x000000A4)
57#define HDMI_GENERIC1_0 (0x000000A8)
58#define HDMI_GENERIC1_1 (0x000000AC)
59#define HDMI_GENERIC1_2 (0x000000B0)
60#define HDMI_GENERIC1_3 (0x000000B4)
61#define HDMI_GENERIC1_4 (0x000000B8)
62#define HDMI_GENERIC1_5 (0x000000BC)
63#define HDMI_GENERIC1_6 (0x000000C0)
64#define HDMI_ACR_32_0 (0x000000C4)
65#define HDMI_ACR_32_1 (0x000000C8)
66#define HDMI_ACR_44_0 (0x000000CC)
67#define HDMI_ACR_44_1 (0x000000D0)
68#define HDMI_ACR_48_0 (0x000000D4)
69#define HDMI_ACR_48_1 (0x000000D8)
70#define HDMI_ACR_STATUS_0 (0x000000DC)
71#define HDMI_ACR_STATUS_1 (0x000000E0)
72#define HDMI_AUDIO_INFO0 (0x000000E4)
73#define HDMI_AUDIO_INFO1 (0x000000E8)
74#define HDMI_CS_60958_0 (0x000000EC)
75#define HDMI_CS_60958_1 (0x000000F0)
76#define HDMI_RAMP_CTRL0 (0x000000F8)
77#define HDMI_RAMP_CTRL1 (0x000000FC)
78#define HDMI_RAMP_CTRL2 (0x00000100)
79#define HDMI_RAMP_CTRL3 (0x00000104)
80#define HDMI_CS_60958_2 (0x00000108)
81#define HDMI_HDCP_CTRL2 (0x0000010C)
82#define HDMI_HDCP_CTRL (0x00000110)
83#define HDMI_HDCP_DEBUG_CTRL (0x00000114)
84#define HDMI_HDCP_INT_CTRL (0x00000118)
85#define HDMI_HDCP_LINK0_STATUS (0x0000011C)
86#define HDMI_HDCP_DDC_CTRL_0 (0x00000120)
87#define HDMI_HDCP_DDC_CTRL_1 (0x00000124)
88#define HDMI_HDCP_DDC_STATUS (0x00000128)
89#define HDMI_HDCP_ENTROPY_CTRL0 (0x0000012C)
90#define HDMI_HDCP_RESET (0x00000130)
91#define HDMI_HDCP_RCVPORT_DATA0 (0x00000134)
92#define HDMI_HDCP_RCVPORT_DATA1 (0x00000138)
93#define HDMI_HDCP_RCVPORT_DATA2_0 (0x0000013C)
94#define HDMI_HDCP_RCVPORT_DATA2_1 (0x00000140)
95#define HDMI_HDCP_RCVPORT_DATA3 (0x00000144)
96#define HDMI_HDCP_RCVPORT_DATA4 (0x00000148)
97#define HDMI_HDCP_RCVPORT_DATA5 (0x0000014C)
98#define HDMI_HDCP_RCVPORT_DATA6 (0x00000150)
99#define HDMI_HDCP_RCVPORT_DATA7 (0x00000154)
100#define HDMI_HDCP_RCVPORT_DATA8 (0x00000158)
101#define HDMI_HDCP_RCVPORT_DATA9 (0x0000015C)
102#define HDMI_HDCP_RCVPORT_DATA10 (0x00000160)
103#define HDMI_HDCP_RCVPORT_DATA11 (0x00000164)
104#define HDMI_HDCP_RCVPORT_DATA12 (0x00000168)
105#define HDMI_VENSPEC_INFO0 (0x0000016C)
106#define HDMI_VENSPEC_INFO1 (0x00000170)
107#define HDMI_VENSPEC_INFO2 (0x00000174)
108#define HDMI_VENSPEC_INFO3 (0x00000178)
109#define HDMI_VENSPEC_INFO4 (0x0000017C)
110#define HDMI_VENSPEC_INFO5 (0x00000180)
111#define HDMI_VENSPEC_INFO6 (0x00000184)
112#define HDMI_HDCP_DEBUG (0x00000194)
113#define HDMI_TMDS_CTRL_CHAR (0x0000019C)
114#define HDMI_TMDS_CTRL_SEL (0x000001A4)
115#define HDMI_TMDS_SYNCCHAR01 (0x000001A8)
116#define HDMI_TMDS_SYNCCHAR23 (0x000001AC)
117#define HDMI_TMDS_DEBUG (0x000001B4)
118#define HDMI_TMDS_CTL_BITS (0x000001B8)
119#define HDMI_TMDS_DCBAL_CTRL (0x000001BC)
120#define HDMI_TMDS_DCBAL_CHAR (0x000001C0)
121#define HDMI_TMDS_CTL01_GEN (0x000001C8)
122#define HDMI_TMDS_CTL23_GEN (0x000001CC)
123#define HDMI_AUDIO_CFG (0x000001D0)
124#define HDMI_DEBUG (0x00000204)
125#define HDMI_USEC_REFTIMER (0x00000208)
126#define HDMI_DDC_CTRL (0x0000020C)
127#define HDMI_DDC_ARBITRATION (0x00000210)
128#define HDMI_DDC_INT_CTRL (0x00000214)
129#define HDMI_DDC_SW_STATUS (0x00000218)
130#define HDMI_DDC_HW_STATUS (0x0000021C)
131#define HDMI_DDC_SPEED (0x00000220)
132#define HDMI_DDC_SETUP (0x00000224)
133#define HDMI_DDC_TRANS0 (0x00000228)
134#define HDMI_DDC_TRANS1 (0x0000022C)
135#define HDMI_DDC_TRANS2 (0x00000230)
136#define HDMI_DDC_TRANS3 (0x00000234)
137#define HDMI_DDC_DATA (0x00000238)
138#define HDMI_HDCP_SHA_CTRL (0x0000023C)
139#define HDMI_HDCP_SHA_STATUS (0x00000240)
140#define HDMI_HDCP_SHA_DATA (0x00000244)
141#define HDMI_HDCP_SHA_DBG_M0_0 (0x00000248)
142#define HDMI_HDCP_SHA_DBG_M0_1 (0x0000024C)
143#define HDMI_HPD_INT_STATUS (0x00000250)
144#define HDMI_HPD_INT_CTRL (0x00000254)
145#define HDMI_HPD_CTRL (0x00000258)
146#define HDMI_HDCP_ENTROPY_CTRL1 (0x0000025C)
147#define HDMI_HDCP_SW_UPPER_AN (0x00000260)
148#define HDMI_HDCP_SW_LOWER_AN (0x00000264)
149#define HDMI_CRC_CTRL (0x00000268)
150#define HDMI_VID_CRC (0x0000026C)
151#define HDMI_AUD_CRC (0x00000270)
152#define HDMI_VBI_CRC (0x00000274)
153#define HDMI_DDC_REF (0x0000027C)
154#define HDMI_HDCP_SW_UPPER_AKSV (0x00000284)
155#define HDMI_HDCP_SW_LOWER_AKSV (0x00000288)
156#define HDMI_CEC_CTRL (0x0000028C)
157#define HDMI_CEC_WR_DATA (0x00000290)
158#define HDMI_CEC_RETRANSMIT (0x00000294)
159#define HDMI_CEC_STATUS (0x00000298)
160#define HDMI_CEC_INT (0x0000029C)
161#define HDMI_CEC_ADDR (0x000002A0)
162#define HDMI_CEC_TIME (0x000002A4)
163#define HDMI_CEC_REFTIMER (0x000002A8)
164#define HDMI_CEC_RD_DATA (0x000002AC)
165#define HDMI_CEC_RD_FILTER (0x000002B0)
166#define HDMI_ACTIVE_H (0x000002B4)
167#define HDMI_ACTIVE_V (0x000002B8)
168#define HDMI_ACTIVE_V_F2 (0x000002BC)
169#define HDMI_TOTAL (0x000002C0)
170#define HDMI_V_TOTAL_F2 (0x000002C4)
171#define HDMI_FRAME_CTRL (0x000002C8)
172#define HDMI_AUD_INT (0x000002CC)
173#define HDMI_DEBUG_BUS_CTRL (0x000002D0)
174#define HDMI_PHY_CTRL (0x000002D4)
175#define HDMI_CEC_WR_RANGE (0x000002DC)
176#define HDMI_CEC_RD_RANGE (0x000002E0)
177#define HDMI_VERSION (0x000002E4)
178#define HDMI_BIST_ENABLE (0x000002F4)
179#define HDMI_TIMING_ENGINE_EN (0x000002F8)
180#define HDMI_INTF_CONFIG (0x000002FC)
181#define HDMI_HSYNC_CTL (0x00000300)
182#define HDMI_VSYNC_PERIOD_F0 (0x00000304)
183#define HDMI_VSYNC_PERIOD_F1 (0x00000308)
184#define HDMI_VSYNC_PULSE_WIDTH_F0 (0x0000030C)
185#define HDMI_VSYNC_PULSE_WIDTH_F1 (0x00000310)
186#define HDMI_DISPLAY_V_START_F0 (0x00000314)
187#define HDMI_DISPLAY_V_START_F1 (0x00000318)
188#define HDMI_DISPLAY_V_END_F0 (0x0000031C)
189#define HDMI_DISPLAY_V_END_F1 (0x00000320)
190#define HDMI_ACTIVE_V_START_F0 (0x00000324)
191#define HDMI_ACTIVE_V_START_F1 (0x00000328)
192#define HDMI_ACTIVE_V_END_F0 (0x0000032C)
193#define HDMI_ACTIVE_V_END_F1 (0x00000330)
194#define HDMI_DISPLAY_HCTL (0x00000334)
195#define HDMI_ACTIVE_HCTL (0x00000338)
196#define HDMI_HSYNC_SKEW (0x0000033C)
197#define HDMI_POLARITY_CTL (0x00000340)
198#define HDMI_TPG_MAIN_CONTROL (0x00000344)
199#define HDMI_TPG_VIDEO_CONFIG (0x00000348)
200#define HDMI_TPG_COMPONENT_LIMITS (0x0000034C)
201#define HDMI_TPG_RECTANGLE (0x00000350)
202#define HDMI_TPG_INITIAL_VALUE (0x00000354)
203#define HDMI_TPG_BLK_WHT_PATTERN_FRAMES (0x00000358)
204#define HDMI_TPG_RGB_MAPPING (0x0000035C)
205#define HDMI_CEC_COMPL_CTL (0x00000360)
206#define HDMI_CEC_RD_START_RANGE (0x00000364)
207#define HDMI_CEC_RD_TOTAL_RANGE (0x00000368)
208#define HDMI_CEC_RD_ERR_RESP_LO (0x0000036C)
209#define HDMI_CEC_WR_CHECK_CONFIG (0x00000370)
210#define HDMI_INTERNAL_TIMING_MODE (0x00000374)
211#define HDMI_CTRL_SW_RESET (0x00000378)
212#define HDMI_CTRL_AUDIO_RESET (0x0000037C)
213#define HDMI_SCRATCH (0x00000380)
214#define HDMI_CLK_CTRL (0x00000384)
215#define HDMI_CLK_ACTIVE (0x00000388)
216#define HDMI_VBI_CFG (0x0000038C)
217#define HDMI_DDC_INT_CTRL0 (0x00000430)
218#define HDMI_DDC_INT_CTRL1 (0x00000434)
219#define HDMI_DDC_INT_CTRL2 (0x00000438)
220#define HDMI_DDC_INT_CTRL3 (0x0000043C)
221#define HDMI_DDC_INT_CTRL4 (0x00000440)
222#define HDMI_DDC_INT_CTRL5 (0x00000444)
223#define HDMI_HDCP2P2_DDC_CTRL (0x0000044C)
224#define HDMI_HDCP2P2_DDC_TIMER_CTRL (0x00000450)
225#define HDMI_HDCP2P2_DDC_TIMER_CTRL2 (0x00000454)
226#define HDMI_HDCP2P2_DDC_STATUS (0x00000458)
227#define HDMI_SCRAMBLER_STATUS_DDC_CTRL (0x00000464)
228#define HDMI_SCRAMBLER_STATUS_DDC_TIMER_CTRL (0x00000468)
229#define HDMI_SCRAMBLER_STATUS_DDC_TIMER_CTRL2 (0x0000046C)
230#define HDMI_SCRAMBLER_STATUS_DDC_STATUS (0x00000470)
231#define HDMI_SCRAMBLER_STATUS_DDC_TIMER_STATUS (0x00000474)
232#define HDMI_SCRAMBLER_STATUS_DDC_TIMER_STATUS2 (0x00000478)
233#define HDMI_HW_DDC_CTRL (0x000004CC)
234#define HDMI_HDCP2P2_DDC_SW_TRIGGER (0x000004D0)
235#define HDMI_HDCP_STATUS (0x00000500)
236#define HDMI_HDCP_INT_CTRL2 (0x00000504)
237
238/* HDMI PHY Registers */
239#define HDMI_PHY_ANA_CFG0 (0x00000000)
240#define HDMI_PHY_ANA_CFG1 (0x00000004)
241#define HDMI_PHY_PD_CTRL0 (0x00000010)
242#define HDMI_PHY_PD_CTRL1 (0x00000014)
243#define HDMI_PHY_BIST_CFG0 (0x00000034)
244#define HDMI_PHY_BIST_PATN0 (0x0000003C)
245#define HDMI_PHY_BIST_PATN1 (0x00000040)
246#define HDMI_PHY_BIST_PATN2 (0x00000044)
247#define HDMI_PHY_BIST_PATN3 (0x00000048)
248
249/* QFPROM Registers for HDMI/HDCP */
250#define QFPROM_RAW_FEAT_CONFIG_ROW0_LSB (0x000000F8)
251#define QFPROM_RAW_FEAT_CONFIG_ROW0_MSB (0x000000FC)
252#define QFPROM_RAW_VERSION_4 (0x000000A8)
253#define SEC_CTRL_HW_VERSION (0x00006000)
254#define HDCP_KSV_LSB (0x000060D8)
255#define HDCP_KSV_MSB (0x000060DC)
256#define HDCP_KSV_VERSION_4_OFFSET (0x00000014)
257
258/* SEC_CTRL version that supports HDCP SEL */
259#define HDCP_SEL_MIN_SEC_VERSION (0x50010000)
260
261#define TOP_AND_BOTTOM (1 << HDMI_S3D_TOP_AND_BOTTOM)
262#define FRAME_PACKING (1 << HDMI_S3D_FRAME_PACKING)
263#define SIDE_BY_SIDE_HALF (1 << HDMI_S3D_SIDE_BY_SIDE)
264
265#define LPASS_LPAIF_RDDMA_CTL0 (0xFE152000)
266#define LPASS_LPAIF_RDDMA_PER_CNT0 (0x00000014)
267
268/* TX major version that supports scrambling */
269#define HDMI_TX_SCRAMBLER_MIN_TX_VERSION 0x04
270
271/* TX major versions */
272#define HDMI_TX_VERSION_4 4
273#define HDMI_TX_VERSION_3 3
274
275/* HDMI SCDC register offsets */
276#define HDMI_SCDC_UPDATE_0 0x10
277#define HDMI_SCDC_UPDATE_1 0x11
278#define HDMI_SCDC_TMDS_CONFIG 0x20
279#define HDMI_SCDC_SCRAMBLER_STATUS 0x21
280#define HDMI_SCDC_CONFIG_0 0x30
281#define HDMI_SCDC_STATUS_FLAGS_0 0x40
282#define HDMI_SCDC_STATUS_FLAGS_1 0x41
283#define HDMI_SCDC_ERR_DET_0_L 0x50
284#define HDMI_SCDC_ERR_DET_0_H 0x51
285#define HDMI_SCDC_ERR_DET_1_L 0x52
286#define HDMI_SCDC_ERR_DET_1_H 0x53
287#define HDMI_SCDC_ERR_DET_2_L 0x54
288#define HDMI_SCDC_ERR_DET_2_H 0x55
289#define HDMI_SCDC_ERR_DET_CHECKSUM 0x56
290
291/* HDCP secure registers directly accessible to HLOS since HDMI controller
292 * version major version 4.0
293 */
294#define HDCP_SEC_TZ_HV_HLOS_HDCP_RCVPORT_DATA0 (0x00000004)
295#define HDCP_SEC_TZ_HV_HLOS_HDCP_RCVPORT_DATA1 (0x00000008)
296#define HDCP_SEC_TZ_HV_HLOS_HDCP_RCVPORT_DATA7 (0x0000000C)
297#define HDCP_SEC_TZ_HV_HLOS_HDCP_RCVPORT_DATA8 (0x00000010)
298#define HDCP_SEC_TZ_HV_HLOS_HDCP_RCVPORT_DATA9 (0x00000014)
299#define HDCP_SEC_TZ_HV_HLOS_HDCP_RCVPORT_DATA10 (0x00000018)
300#define HDCP_SEC_TZ_HV_HLOS_HDCP_RCVPORT_DATA11 (0x0000001C)
301#define HDCP_SEC_TZ_HV_HLOS_HDCP_RCVPORT_DATA12 (0x00000020)
302#define HDCP_SEC_TZ_HV_HLOS_HDCP_SHA_CTRL (0x00000024)
303#define HDCP_SEC_TZ_HV_HLOS_HDCP_SHA_DATA (0x00000028)
304
305/*
306 * Offsets in HDMI_DDC_INT_CTRL0 register
307 *
308 * The HDMI_DDC_INT_CTRL0 register is intended for HDCP 2.2 RxStatus
309 * register manipulation. It reads like this:
310 *
311 * Bit 31: RXSTATUS_MESSAGE_SIZE_MASK (1 = generate interrupt when size > 0)
312 * Bit 30: RXSTATUS_MESSAGE_SIZE_ACK (1 = Acknowledge message size intr)
313 * Bits 29-20: RXSTATUS_MESSAGE_SIZE (Actual size of message available)
314 * Bits 19-18: RXSTATUS_READY_MASK (1 = generate interrupt when ready = 1
315 * 2 = generate interrupt when ready = 0)
316 * Bit 17: RXSTATUS_READY_ACK (1 = Acknowledge ready bit interrupt)
317 * Bit 16: RXSTATUS_READY (1 = Rxstatus ready bit read is 1)
318 * Bit 15: RXSTATUS_READY_NOT (1 = Rxstatus ready bit read is 0)
319 * Bit 14: RXSTATUS_REAUTH_REQ_MASK (1 = generate interrupt when reauth is
320 * requested by sink)
321 * Bit 13: RXSTATUS_REAUTH_REQ_ACK (1 = Acknowledge Reauth req interrupt)
322 * Bit 12: RXSTATUS_REAUTH_REQ (1 = Rxstatus reauth req bit read is 1)
323 * Bit 10: RXSTATUS_DDC_FAILED_MASK (1 = generate interrupt when DDC
324 * tranasaction fails)
325 * Bit 9: RXSTATUS_DDC_FAILED_ACK (1 = Acknowledge ddc failure interrupt)
326 * Bit 8: RXSTATUS_DDC_FAILED (1 = DDC transaction failed)
327 * Bit 6: RXSTATUS_DDC_DONE_MASK (1 = generate interrupt when DDC
328 * transaction completes)
329 * Bit 5: RXSTATUS_DDC_DONE_ACK (1 = Acknowledge ddc done interrupt)
330 * Bit 4: RXSTATUS_DDC_DONE (1 = DDC transaction is done)
331 * Bit 2: RXSTATUS_DDC_REQ_MASK (1 = generate interrupt when DDC Read
332 * request for RXstatus is made)
333 * Bit 1: RXSTATUS_DDC_REQ_ACK (1 = Acknowledge Rxstatus read interrupt)
334 * Bit 0: RXSTATUS_DDC_REQ (1 = RXStatus DDC read request is made)
335 *
336 */
337#define HDCP2P2_RXSTATUS_MESSAGE_SIZE_SHIFT 20
338#define HDCP2P2_RXSTATUS_MESSAGE_SIZE_MASK 0x3ff00000
339#define HDCP2P2_RXSTATUS_MESSAGE_SIZE_ACK_SHIFT 30
340#define HDCP2P2_RXSTATUS_MESSAGE_SIZE_INTR_SHIFT 31
341
342#define HDCP2P2_RXSTATUS_REAUTH_REQ_SHIFT 12
343#define HDCP2P2_RXSTATUS_REAUTH_REQ_MASK 1
344#define HDCP2P2_RXSTATUS_REAUTH_REQ_ACK_SHIFT 13
345#define HDCP2P2_RXSTATUS_REAUTH_REQ_INTR_SHIFT 14
346
347#define HDCP2P2_RXSTATUS_READY_SHIFT 16
348#define HDCP2P2_RXSTATUS_READY_MASK 1
349#define HDCP2P2_RXSTATUS_READY_ACK_SHIFT 17
350#define HDCP2P2_RXSTATUS_READY_INTR_SHIFT 18
351#define HDCP2P2_RXSTATUS_READY_INTR_MASK 18
352
353#define HDCP2P2_RXSTATUS_DDC_FAILED_SHIFT 8
354#define HDCP2P2_RXSTATUS_DDC_FAILED_ACKSHIFT 9
355#define HDCP2P2_RXSTATUS_DDC_FAILED_INTR_MASK 10
356#define HDCP2P2_RXSTATUS_DDC_DONE 6
357
358/*
359 * Bits 1:0 in HDMI_HW_DDC_CTRL that dictate how the HDCP 2.2 RxStatus will be
360 * read by the hardware
361 */
362#define HDCP2P2_RXSTATUS_HW_DDC_DISABLE 0
363#define HDCP2P2_RXSTATUS_HW_DDC_AUTOMATIC_LOOP 1
364#define HDCP2P2_RXSTATUS_HW_DDC_FORCE_LOOP 2
365#define HDCP2P2_RXSTATUS_HW_DDC_SW_TRIGGER 3
366
367/* default hsyncs for 4k@60 for 200ms */
368#define HDMI_DEFAULT_TIMEOUT_HSYNC 28571
369
370enum hdmi_tx_feature_type {
371 HDMI_TX_FEAT_EDID = BIT(0),
372 HDMI_TX_FEAT_HDCP = BIT(1),
373 HDMI_TX_FEAT_HDCP2P2 = BIT(2),
374 HDMI_TX_FEAT_CEC_HW = BIT(3),
375 HDMI_TX_FEAT_CEC_ABST = BIT(4),
376 HDMI_TX_FEAT_PANEL = BIT(5),
377 HDMI_TX_FEAT_MAX = HDMI_TX_FEAT_EDID | HDMI_TX_FEAT_HDCP |
378 HDMI_TX_FEAT_HDCP2P2 | HDMI_TX_FEAT_CEC_HW |
379 HDMI_TX_FEAT_CEC_ABST | HDMI_TX_FEAT_PANEL
380};
381
382enum hdmi_tx_scdc_access_type {
383 HDMI_TX_SCDC_SCRAMBLING_STATUS,
384 HDMI_TX_SCDC_SCRAMBLING_ENABLE,
385 HDMI_TX_SCDC_TMDS_BIT_CLOCK_RATIO_UPDATE,
386 HDMI_TX_SCDC_CLOCK_DET_STATUS,
387 HDMI_TX_SCDC_CH0_LOCK_STATUS,
388 HDMI_TX_SCDC_CH1_LOCK_STATUS,
389 HDMI_TX_SCDC_CH2_LOCK_STATUS,
390 HDMI_TX_SCDC_CH0_ERROR_COUNT,
391 HDMI_TX_SCDC_CH1_ERROR_COUNT,
392 HDMI_TX_SCDC_CH2_ERROR_COUNT,
393 HDMI_TX_SCDC_READ_ENABLE,
394 HDMI_TX_SCDC_MAX,
395};
396
397enum hdmi_tx_ddc_timer_type {
398 HDMI_TX_DDC_TIMER_HDCP2P2_RD_MSG,
399 HDMI_TX_DDC_TIMER_SCRAMBLER_STATUS,
400 HDMI_TX_DDC_TIMER_UPDATE_FLAGS,
401 HDMI_TX_DDC_TIMER_STATUS_FLAGS,
402 HDMI_TX_DDC_TIMER_CED,
403 HDMI_TX_DDC_TIMER_MAX,
404};
405
406struct hdmi_tx_ddc_data {
407 char *what;
408 u8 *data_buf;
409 u32 data_len;
410 u32 dev_addr;
411 u32 offset;
412 u32 request_len;
413 u32 retry_align;
414 u32 hard_timeout;
415 u32 timeout_left;
416 int retry;
417};
418
419enum hdmi_tx_hdcp2p2_rxstatus_intr_mask {
420 RXSTATUS_MESSAGE_SIZE = BIT(31),
421 RXSTATUS_READY = BIT(18),
422 RXSTATUS_REAUTH_REQ = BIT(14),
423};
424
425struct hdmi_tx_hdcp2p2_ddc_data {
426 enum hdmi_tx_hdcp2p2_rxstatus_intr_mask intr_mask;
427 u32 timeout_ms;
428 u32 timeout_hsync;
429 u32 periodic_timer_hsync;
430 u32 timeout_left;
431 u32 read_method;
432 u32 message_size;
433 bool encryption_ready;
434 bool ready;
435 bool reauth_req;
436 bool ddc_max_retries_fail;
437 bool ddc_done;
438 bool ddc_read_req;
439 bool ddc_timeout;
440 bool wait;
441 int irq_wait_count;
442 void (*link_cb)(void *data);
443 void *link_data;
444};
445
446struct hdmi_tx_ddc_ctrl {
447 atomic_t write_busy_wait_done;
448 atomic_t read_busy_wait_done;
449 atomic_t rxstatus_busy_wait_done;
450 struct dss_io_data *io;
451 struct completion ddc_sw_done;
452 struct hdmi_tx_ddc_data ddc_data;
453 struct hdmi_tx_hdcp2p2_ddc_data hdcp2p2_ddc_data;
454};
455
456
457struct hdmi_util_ds_data {
458 bool ds_registered;
459 u32 ds_max_clk;
460};
461
462static inline int hdmi_tx_get_v_total(const struct msm_hdmi_mode_timing_info *t)
463{
464 if (t) {
465 return t->active_v + t->front_porch_v + t->pulse_width_v +
466 t->back_porch_v;
467 }
468
469 return 0;
470}
471
472static inline int hdmi_tx_get_h_total(const struct msm_hdmi_mode_timing_info *t)
473{
474 if (t) {
475 return t->active_h + t->front_porch_h + t->pulse_width_h +
476 t->back_porch_h;
477 }
478
479 return 0;
480}
481
482/* video timing related utility routines */
483int hdmi_get_video_id_code(struct msm_hdmi_mode_timing_info *timing_in,
484 struct hdmi_util_ds_data *ds_data);
485int hdmi_get_supported_mode(struct msm_hdmi_mode_timing_info *info,
486 struct hdmi_util_ds_data *ds_data, u32 mode);
487ssize_t hdmi_get_video_3d_fmt_2string(u32 format, char *buf, u32 size);
488const char *msm_hdmi_mode_2string(u32 mode);
489int hdmi_set_resv_timing_info(struct msm_hdmi_mode_timing_info *mode);
490bool hdmi_is_valid_resv_timing(int mode);
491void hdmi_reset_resv_timing_info(void);
492
493/* todo: Fix this. Right now this is defined in mdss_hdmi_tx.c */
494void *hdmi_get_featuredata_from_sysfs_dev(struct device *device, u32 type);
495
496/* DDC */
497void hdmi_ddc_config(struct hdmi_tx_ddc_ctrl *ctrl);
498int hdmi_ddc_isr(struct hdmi_tx_ddc_ctrl *ctrl, u32 version);
499int hdmi_ddc_write(struct hdmi_tx_ddc_ctrl *ctrl);
500int hdmi_ddc_read_seg(struct hdmi_tx_ddc_ctrl *ctrl);
501int hdmi_ddc_read(struct hdmi_tx_ddc_ctrl *ctrl);
502int hdmi_ddc_abort_transaction(struct hdmi_tx_ddc_ctrl *ctrl);
503
504int hdmi_scdc_read(struct hdmi_tx_ddc_ctrl *ctrl, u32 data_type, u32 *val);
505int hdmi_scdc_write(struct hdmi_tx_ddc_ctrl *ctrl, u32 data_type, u32 val);
506int hdmi_setup_ddc_timers(struct hdmi_tx_ddc_ctrl *ctrl,
507 u32 type, u32 to_in_num_lines);
508void hdmi_scrambler_ddc_disable(struct hdmi_tx_ddc_ctrl *ctrl);
509void hdmi_hdcp2p2_ddc_disable(struct hdmi_tx_ddc_ctrl *ctrl);
510int hdmi_hdcp2p2_ddc_read_rxstatus(struct hdmi_tx_ddc_ctrl *ctrl);
511int hdmi_utils_get_timeout_in_hysnc(struct msm_hdmi_mode_timing_info *timing,
512 u32 timeout_ms);
513
514#endif /* __HDMI_UTIL_H__ */