Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 1 | /* Copyright (c) 2012-2015, 2017-2018, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | #include <linux/clk.h> |
| 14 | #include <linux/err.h> |
| 15 | #include <linux/io.h> |
| 16 | #include <linux/delay.h> |
| 17 | #include <linux/mdss_io_util.h> |
| 18 | |
| 19 | #define MAX_I2C_CMDS 16 |
| 20 | void dss_reg_w(struct dss_io_data *io, u32 offset, u32 value, u32 debug) |
| 21 | { |
| 22 | u32 in_val; |
| 23 | |
| 24 | if (!io || !io->base) { |
| 25 | DEV_ERR("%pS->%s: invalid input\n", |
| 26 | __builtin_return_address(0), __func__); |
| 27 | return; |
| 28 | } |
| 29 | |
| 30 | if (offset > io->len) { |
| 31 | DEV_ERR("%pS->%s: offset out of range\n", |
| 32 | __builtin_return_address(0), __func__); |
| 33 | return; |
| 34 | } |
| 35 | |
| 36 | writel_relaxed(value, io->base + offset); |
| 37 | if (debug) { |
| 38 | in_val = readl_relaxed(io->base + offset); |
| 39 | DEV_DBG("[%08x] => %08x [%08x]\n", |
| 40 | (u32)(unsigned long)(io->base + offset), |
| 41 | |
| 42 | value, in_val); |
| 43 | } |
| 44 | } /* dss_reg_w */ |
| 45 | EXPORT_SYMBOL(dss_reg_w); |
| 46 | |
| 47 | u32 dss_reg_r(struct dss_io_data *io, u32 offset, u32 debug) |
| 48 | { |
| 49 | u32 value; |
| 50 | |
| 51 | if (!io || !io->base) { |
| 52 | DEV_ERR("%pS->%s: invalid input\n", |
| 53 | __builtin_return_address(0), __func__); |
| 54 | return -EINVAL; |
| 55 | } |
| 56 | |
| 57 | if (offset > io->len) { |
| 58 | DEV_ERR("%pS->%s: offset out of range\n", |
| 59 | __builtin_return_address(0), __func__); |
| 60 | return -EINVAL; |
| 61 | } |
| 62 | |
| 63 | value = readl_relaxed(io->base + offset); |
| 64 | if (debug) |
| 65 | DEV_DBG("[%08x] <= %08x\n", |
| 66 | (u32)(unsigned long)(io->base + offset), value); |
| 67 | |
| 68 | return value; |
| 69 | } /* dss_reg_r */ |
| 70 | EXPORT_SYMBOL(dss_reg_r); |
| 71 | |
| 72 | void dss_reg_dump(void __iomem *base, u32 length, const char *prefix, |
| 73 | u32 debug) |
| 74 | { |
| 75 | if (debug) |
| 76 | print_hex_dump(KERN_INFO, prefix, DUMP_PREFIX_OFFSET, 32, 4, |
| 77 | (void *)base, length, false); |
| 78 | } /* dss_reg_dump */ |
| 79 | EXPORT_SYMBOL(dss_reg_dump); |
| 80 | |
| 81 | static struct resource *msm_dss_get_res_byname(struct platform_device *pdev, |
| 82 | unsigned int type, const char *name) |
| 83 | { |
| 84 | struct resource *res = NULL; |
| 85 | |
| 86 | res = platform_get_resource_byname(pdev, type, name); |
| 87 | if (!res) |
| 88 | DEV_ERR("%s: '%s' resource not found\n", __func__, name); |
| 89 | |
| 90 | return res; |
| 91 | } /* msm_dss_get_res_byname */ |
| 92 | EXPORT_SYMBOL(msm_dss_get_res_byname); |
| 93 | |
| 94 | int msm_dss_ioremap_byname(struct platform_device *pdev, |
| 95 | struct dss_io_data *io_data, const char *name) |
| 96 | { |
| 97 | struct resource *res = NULL; |
| 98 | |
| 99 | if (!pdev || !io_data) { |
| 100 | DEV_ERR("%pS->%s: invalid input\n", |
| 101 | __builtin_return_address(0), __func__); |
| 102 | return -EINVAL; |
| 103 | } |
| 104 | |
| 105 | res = msm_dss_get_res_byname(pdev, IORESOURCE_MEM, name); |
| 106 | if (!res) { |
| 107 | DEV_ERR("%pS->%s: '%s' msm_dss_get_res_byname failed\n", |
| 108 | __builtin_return_address(0), __func__, name); |
| 109 | return -ENODEV; |
| 110 | } |
| 111 | |
| 112 | io_data->len = (u32)resource_size(res); |
| 113 | io_data->base = ioremap(res->start, io_data->len); |
| 114 | if (!io_data->base) { |
| 115 | DEV_ERR("%pS->%s: '%s' ioremap failed\n", |
| 116 | __builtin_return_address(0), __func__, name); |
| 117 | return -EIO; |
| 118 | } |
| 119 | |
| 120 | return 0; |
| 121 | } /* msm_dss_ioremap_byname */ |
| 122 | EXPORT_SYMBOL(msm_dss_ioremap_byname); |
| 123 | |
| 124 | void msm_dss_iounmap(struct dss_io_data *io_data) |
| 125 | { |
| 126 | if (!io_data) { |
| 127 | DEV_ERR("%pS->%s: invalid input\n", |
| 128 | __builtin_return_address(0), __func__); |
| 129 | return; |
| 130 | } |
| 131 | |
| 132 | if (io_data->base) { |
| 133 | iounmap(io_data->base); |
| 134 | io_data->base = NULL; |
| 135 | } |
| 136 | io_data->len = 0; |
| 137 | } /* msm_dss_iounmap */ |
| 138 | EXPORT_SYMBOL(msm_dss_iounmap); |
| 139 | |
| 140 | int msm_dss_config_vreg(struct device *dev, struct dss_vreg *in_vreg, |
| 141 | int num_vreg, int config) |
| 142 | { |
| 143 | int i = 0, rc = 0; |
| 144 | struct dss_vreg *curr_vreg = NULL; |
| 145 | enum dss_vreg_type type; |
| 146 | |
| 147 | if (!in_vreg || !num_vreg) |
| 148 | return rc; |
| 149 | |
| 150 | if (config) { |
| 151 | for (i = 0; i < num_vreg; i++) { |
| 152 | curr_vreg = &in_vreg[i]; |
| 153 | curr_vreg->vreg = regulator_get(dev, |
| 154 | curr_vreg->vreg_name); |
| 155 | rc = PTR_RET(curr_vreg->vreg); |
| 156 | if (rc) { |
| 157 | DEV_ERR("%pS->%s: %s get failed. rc=%d\n", |
| 158 | __builtin_return_address(0), __func__, |
| 159 | curr_vreg->vreg_name, rc); |
| 160 | curr_vreg->vreg = NULL; |
| 161 | goto vreg_get_fail; |
| 162 | } |
| 163 | type = (regulator_count_voltages(curr_vreg->vreg) > 0) |
| 164 | ? DSS_REG_LDO : DSS_REG_VS; |
| 165 | if (type == DSS_REG_LDO) { |
| 166 | rc = regulator_set_voltage( |
| 167 | curr_vreg->vreg, |
| 168 | curr_vreg->min_voltage, |
| 169 | curr_vreg->max_voltage); |
| 170 | if (rc < 0) { |
| 171 | DEV_ERR("%pS->%s: %s set vltg fail\n", |
| 172 | __builtin_return_address(0), |
| 173 | __func__, |
| 174 | curr_vreg->vreg_name); |
| 175 | goto vreg_set_voltage_fail; |
| 176 | } |
| 177 | } |
| 178 | } |
| 179 | } else { |
| 180 | for (i = num_vreg-1; i >= 0; i--) { |
| 181 | curr_vreg = &in_vreg[i]; |
| 182 | if (curr_vreg->vreg) { |
| 183 | type = (regulator_count_voltages( |
| 184 | curr_vreg->vreg) > 0) |
| 185 | ? DSS_REG_LDO : DSS_REG_VS; |
| 186 | if (type == DSS_REG_LDO) { |
| 187 | regulator_set_voltage(curr_vreg->vreg, |
| 188 | 0, curr_vreg->max_voltage); |
| 189 | } |
| 190 | regulator_put(curr_vreg->vreg); |
| 191 | curr_vreg->vreg = NULL; |
| 192 | } |
| 193 | } |
| 194 | } |
| 195 | return 0; |
| 196 | |
| 197 | vreg_unconfig: |
| 198 | if (type == DSS_REG_LDO) |
Sachin Bhayare | 3d3767e | 2018-01-02 21:10:57 +0530 | [diff] [blame] | 199 | regulator_set_load(curr_vreg->vreg, 0); |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 200 | |
| 201 | vreg_set_voltage_fail: |
| 202 | regulator_put(curr_vreg->vreg); |
| 203 | curr_vreg->vreg = NULL; |
| 204 | |
| 205 | vreg_get_fail: |
| 206 | for (i--; i >= 0; i--) { |
| 207 | curr_vreg = &in_vreg[i]; |
| 208 | type = (regulator_count_voltages(curr_vreg->vreg) > 0) |
| 209 | ? DSS_REG_LDO : DSS_REG_VS; |
| 210 | goto vreg_unconfig; |
| 211 | } |
| 212 | return rc; |
| 213 | } /* msm_dss_config_vreg */ |
| 214 | EXPORT_SYMBOL(msm_dss_config_vreg); |
| 215 | |
| 216 | int msm_dss_config_vreg_opt_mode(struct dss_vreg *in_vreg, int num_vreg, |
| 217 | enum dss_vreg_mode mode) |
| 218 | { |
| 219 | int i = 0, rc = 0; |
| 220 | |
| 221 | if (mode >= DSS_REG_MODE_MAX) { |
| 222 | pr_err("%pS->%s: invalid mode %d\n", |
| 223 | __builtin_return_address(0), __func__, mode); |
| 224 | rc = -EINVAL; |
| 225 | goto error; |
| 226 | } |
| 227 | |
| 228 | for (i = 0; i < num_vreg; i++) { |
| 229 | rc = PTR_RET(in_vreg[i].vreg); |
| 230 | if (rc) { |
| 231 | DEV_ERR("%pS->%s: %s regulator error. rc=%d\n", |
| 232 | __builtin_return_address(0), __func__, |
| 233 | in_vreg[i].vreg_name, rc); |
| 234 | goto error; |
| 235 | } |
| 236 | |
| 237 | DEV_DBG("%s: Setting optimum mode %d for %s (load=%d)\n", |
| 238 | __func__, mode, in_vreg[i].vreg_name, |
| 239 | in_vreg[i].load[mode]); |
Sachin Bhayare | 3d3767e | 2018-01-02 21:10:57 +0530 | [diff] [blame] | 240 | rc = regulator_set_load(in_vreg[i].vreg, |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 241 | in_vreg[i].load[mode]); |
| 242 | if (rc < 0) { |
| 243 | DEV_ERR("%pS->%s: %s set opt mode failed. rc=%d\n", |
| 244 | __builtin_return_address(0), __func__, |
| 245 | in_vreg[i].vreg_name, rc); |
| 246 | goto error; |
| 247 | } else { |
| 248 | /* |
Sachin Bhayare | 3d3767e | 2018-01-02 21:10:57 +0530 | [diff] [blame] | 249 | * regulator_set_load can return non-zero |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 250 | * value for success. However, this API is expected |
| 251 | * to return 0 for success. |
| 252 | */ |
| 253 | rc = 0; |
| 254 | } |
| 255 | } |
| 256 | |
| 257 | error: |
| 258 | return rc; |
| 259 | } |
| 260 | EXPORT_SYMBOL(msm_dss_config_vreg_opt_mode); |
| 261 | |
| 262 | int msm_dss_enable_vreg(struct dss_vreg *in_vreg, int num_vreg, int enable) |
| 263 | { |
| 264 | int i = 0, rc = 0; |
| 265 | bool need_sleep; |
| 266 | |
| 267 | if (enable) { |
| 268 | for (i = 0; i < num_vreg; i++) { |
| 269 | rc = PTR_RET(in_vreg[i].vreg); |
| 270 | if (rc) { |
| 271 | DEV_ERR("%pS->%s: %s regulator error. rc=%d\n", |
| 272 | __builtin_return_address(0), __func__, |
| 273 | in_vreg[i].vreg_name, rc); |
| 274 | goto vreg_set_opt_mode_fail; |
| 275 | } |
| 276 | need_sleep = !regulator_is_enabled(in_vreg[i].vreg); |
| 277 | if (in_vreg[i].pre_on_sleep && need_sleep) |
| 278 | usleep_range(in_vreg[i].pre_on_sleep * 1000, |
| 279 | in_vreg[i].pre_on_sleep * 1000); |
Sachin Bhayare | 3d3767e | 2018-01-02 21:10:57 +0530 | [diff] [blame] | 280 | rc = regulator_set_load(in_vreg[i].vreg, |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 281 | in_vreg[i].load[DSS_REG_MODE_ENABLE]); |
| 282 | if (rc < 0) { |
| 283 | DEV_ERR("%pS->%s: %s set opt m fail\n", |
| 284 | __builtin_return_address(0), __func__, |
| 285 | in_vreg[i].vreg_name); |
| 286 | goto vreg_set_opt_mode_fail; |
| 287 | } |
| 288 | rc = regulator_enable(in_vreg[i].vreg); |
| 289 | if (in_vreg[i].post_on_sleep && need_sleep) |
| 290 | usleep_range(in_vreg[i].post_on_sleep * 1000, |
| 291 | in_vreg[i].post_on_sleep * 1000); |
| 292 | if (rc < 0) { |
| 293 | DEV_ERR("%pS->%s: %s enable failed\n", |
| 294 | __builtin_return_address(0), __func__, |
| 295 | in_vreg[i].vreg_name); |
| 296 | goto disable_vreg; |
| 297 | } |
| 298 | } |
| 299 | } else { |
| 300 | for (i = num_vreg-1; i >= 0; i--) { |
| 301 | if (in_vreg[i].pre_off_sleep) |
| 302 | usleep_range(in_vreg[i].pre_off_sleep * 1000, |
| 303 | in_vreg[i].pre_off_sleep * 1000); |
Sachin Bhayare | 3d3767e | 2018-01-02 21:10:57 +0530 | [diff] [blame] | 304 | regulator_set_load(in_vreg[i].vreg, |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 305 | in_vreg[i].load[DSS_REG_MODE_DISABLE]); |
| 306 | |
| 307 | if (regulator_is_enabled(in_vreg[i].vreg)) |
| 308 | regulator_disable(in_vreg[i].vreg); |
| 309 | |
| 310 | if (in_vreg[i].post_off_sleep) |
| 311 | usleep_range(in_vreg[i].post_off_sleep * 1000, |
| 312 | in_vreg[i].post_off_sleep * 1000); |
| 313 | } |
| 314 | } |
| 315 | return rc; |
| 316 | |
| 317 | disable_vreg: |
Sachin Bhayare | 3d3767e | 2018-01-02 21:10:57 +0530 | [diff] [blame] | 318 | regulator_set_load(in_vreg[i].vreg, |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 319 | in_vreg[i].load[DSS_REG_MODE_DISABLE]); |
| 320 | |
| 321 | vreg_set_opt_mode_fail: |
| 322 | for (i--; i >= 0; i--) { |
| 323 | if (in_vreg[i].pre_off_sleep) |
| 324 | usleep_range(in_vreg[i].pre_off_sleep * 1000, |
| 325 | in_vreg[i].pre_off_sleep * 1000); |
Sachin Bhayare | 3d3767e | 2018-01-02 21:10:57 +0530 | [diff] [blame] | 326 | regulator_set_load(in_vreg[i].vreg, |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 327 | in_vreg[i].load[DSS_REG_MODE_DISABLE]); |
| 328 | regulator_disable(in_vreg[i].vreg); |
| 329 | if (in_vreg[i].post_off_sleep) |
| 330 | usleep_range(in_vreg[i].post_off_sleep * 1000, |
| 331 | in_vreg[i].post_off_sleep * 1000); |
| 332 | } |
| 333 | |
| 334 | return rc; |
| 335 | } /* msm_dss_enable_vreg */ |
| 336 | EXPORT_SYMBOL(msm_dss_enable_vreg); |
| 337 | |
| 338 | int msm_dss_enable_gpio(struct dss_gpio *in_gpio, int num_gpio, int enable) |
| 339 | { |
| 340 | int i = 0, rc = 0; |
| 341 | |
| 342 | if (enable) { |
| 343 | for (i = 0; i < num_gpio; i++) { |
| 344 | DEV_DBG("%pS->%s: %s enable\n", |
| 345 | __builtin_return_address(0), __func__, |
| 346 | in_gpio[i].gpio_name); |
| 347 | |
| 348 | rc = gpio_request(in_gpio[i].gpio, |
| 349 | in_gpio[i].gpio_name); |
| 350 | if (rc < 0) { |
| 351 | DEV_ERR("%pS->%s: %s enable failed\n", |
| 352 | __builtin_return_address(0), __func__, |
| 353 | in_gpio[i].gpio_name); |
| 354 | goto disable_gpio; |
| 355 | } |
| 356 | gpio_set_value(in_gpio[i].gpio, in_gpio[i].value); |
| 357 | } |
| 358 | } else { |
| 359 | for (i = num_gpio-1; i >= 0; i--) { |
| 360 | DEV_DBG("%pS->%s: %s disable\n", |
| 361 | __builtin_return_address(0), __func__, |
| 362 | in_gpio[i].gpio_name); |
| 363 | if (in_gpio[i].gpio) |
| 364 | gpio_free(in_gpio[i].gpio); |
| 365 | } |
| 366 | } |
| 367 | return rc; |
| 368 | |
| 369 | disable_gpio: |
| 370 | for (i--; i >= 0; i--) |
| 371 | if (in_gpio[i].gpio) |
| 372 | gpio_free(in_gpio[i].gpio); |
| 373 | |
| 374 | return rc; |
| 375 | } /* msm_dss_enable_gpio */ |
| 376 | EXPORT_SYMBOL(msm_dss_enable_gpio); |
| 377 | |
| 378 | void msm_dss_put_clk(struct dss_clk *clk_arry, int num_clk) |
| 379 | { |
| 380 | int i; |
| 381 | |
| 382 | for (i = num_clk - 1; i >= 0; i--) { |
| 383 | if (clk_arry[i].clk) |
| 384 | clk_put(clk_arry[i].clk); |
| 385 | clk_arry[i].clk = NULL; |
| 386 | } |
| 387 | } /* msm_dss_put_clk */ |
| 388 | EXPORT_SYMBOL(msm_dss_put_clk); |
| 389 | |
| 390 | int msm_dss_get_clk(struct device *dev, struct dss_clk *clk_arry, int num_clk) |
| 391 | { |
| 392 | int i, rc = 0; |
| 393 | |
| 394 | for (i = 0; i < num_clk; i++) { |
| 395 | clk_arry[i].clk = clk_get(dev, clk_arry[i].clk_name); |
| 396 | rc = PTR_RET(clk_arry[i].clk); |
| 397 | if (rc) { |
| 398 | DEV_ERR("%pS->%s: '%s' get failed. rc=%d\n", |
| 399 | __builtin_return_address(0), __func__, |
| 400 | clk_arry[i].clk_name, rc); |
| 401 | goto error; |
| 402 | } |
| 403 | } |
| 404 | |
| 405 | return rc; |
| 406 | |
| 407 | error: |
| 408 | msm_dss_put_clk(clk_arry, num_clk); |
| 409 | |
| 410 | return rc; |
| 411 | } /* msm_dss_get_clk */ |
| 412 | EXPORT_SYMBOL(msm_dss_get_clk); |
| 413 | |
| 414 | int msm_dss_clk_set_rate(struct dss_clk *clk_arry, int num_clk) |
| 415 | { |
| 416 | int i, rc = 0; |
| 417 | |
| 418 | for (i = 0; i < num_clk; i++) { |
| 419 | if (clk_arry[i].clk) { |
| 420 | if (clk_arry[i].type != DSS_CLK_AHB) { |
| 421 | DEV_DBG("%pS->%s: '%s' rate %ld\n", |
| 422 | __builtin_return_address(0), __func__, |
| 423 | clk_arry[i].clk_name, |
| 424 | clk_arry[i].rate); |
| 425 | rc = clk_set_rate(clk_arry[i].clk, |
| 426 | clk_arry[i].rate); |
| 427 | if (rc) { |
| 428 | DEV_ERR("%pS->%s: %s failed. rc=%d\n", |
| 429 | __builtin_return_address(0), |
| 430 | __func__, |
| 431 | clk_arry[i].clk_name, rc); |
| 432 | break; |
| 433 | } |
| 434 | } |
| 435 | } else { |
| 436 | DEV_ERR("%pS->%s: '%s' is not available\n", |
| 437 | __builtin_return_address(0), __func__, |
| 438 | clk_arry[i].clk_name); |
| 439 | rc = -EPERM; |
| 440 | break; |
| 441 | } |
| 442 | } |
| 443 | |
| 444 | return rc; |
| 445 | } /* msm_dss_clk_set_rate */ |
| 446 | EXPORT_SYMBOL(msm_dss_clk_set_rate); |
| 447 | |
| 448 | int msm_dss_enable_clk(struct dss_clk *clk_arry, int num_clk, int enable) |
| 449 | { |
| 450 | int i, rc = 0; |
| 451 | |
| 452 | if (enable) { |
| 453 | for (i = 0; i < num_clk; i++) { |
| 454 | DEV_DBG("%pS->%s: enable '%s'\n", |
| 455 | __builtin_return_address(0), __func__, |
| 456 | clk_arry[i].clk_name); |
| 457 | if (clk_arry[i].clk) { |
| 458 | rc = clk_prepare_enable(clk_arry[i].clk); |
| 459 | if (rc) |
| 460 | DEV_ERR("%pS->%s: %s en fail. rc=%d\n", |
| 461 | __builtin_return_address(0), |
| 462 | __func__, |
| 463 | clk_arry[i].clk_name, rc); |
| 464 | } else { |
| 465 | DEV_ERR("%pS->%s: '%s' is not available\n", |
| 466 | __builtin_return_address(0), __func__, |
| 467 | clk_arry[i].clk_name); |
| 468 | rc = -EPERM; |
| 469 | } |
| 470 | |
| 471 | if (rc) { |
| 472 | msm_dss_enable_clk(&clk_arry[i], |
| 473 | i, false); |
| 474 | break; |
| 475 | } |
| 476 | } |
| 477 | } else { |
| 478 | for (i = num_clk - 1; i >= 0; i--) { |
| 479 | DEV_DBG("%pS->%s: disable '%s'\n", |
| 480 | __builtin_return_address(0), __func__, |
| 481 | clk_arry[i].clk_name); |
| 482 | |
| 483 | if (clk_arry[i].clk) |
| 484 | clk_disable_unprepare(clk_arry[i].clk); |
| 485 | else |
| 486 | DEV_ERR("%pS->%s: '%s' is not available\n", |
| 487 | __builtin_return_address(0), __func__, |
| 488 | clk_arry[i].clk_name); |
| 489 | } |
| 490 | } |
| 491 | |
| 492 | return rc; |
| 493 | } /* msm_dss_enable_clk */ |
| 494 | EXPORT_SYMBOL(msm_dss_enable_clk); |
| 495 | |
| 496 | |
| 497 | int mdss_i2c_byte_read(struct i2c_client *client, uint8_t slave_addr, |
| 498 | uint8_t reg_offset, uint8_t *read_buf) |
| 499 | { |
| 500 | struct i2c_msg msgs[2]; |
| 501 | int ret = -1; |
| 502 | |
| 503 | pr_debug("%s: reading from slave_addr=[%x] and offset=[%x]\n", |
| 504 | __func__, slave_addr, reg_offset); |
| 505 | |
| 506 | msgs[0].addr = slave_addr >> 1; |
| 507 | msgs[0].flags = 0; |
| 508 | msgs[0].buf = ®_offset; |
| 509 | msgs[0].len = 1; |
| 510 | |
| 511 | msgs[1].addr = slave_addr >> 1; |
| 512 | msgs[1].flags = I2C_M_RD; |
| 513 | msgs[1].buf = read_buf; |
| 514 | msgs[1].len = 1; |
| 515 | |
| 516 | ret = i2c_transfer(client->adapter, msgs, 2); |
| 517 | if (ret < 1) { |
| 518 | pr_err("%s: I2C READ FAILED=[%d]\n", __func__, ret); |
| 519 | return -EACCES; |
| 520 | } |
| 521 | pr_debug("%s: i2c buf is [%x]\n", __func__, *read_buf); |
| 522 | return 0; |
| 523 | } |
| 524 | EXPORT_SYMBOL(mdss_i2c_byte_read); |
| 525 | |
| 526 | int mdss_i2c_byte_write(struct i2c_client *client, uint8_t slave_addr, |
| 527 | uint8_t reg_offset, uint8_t *value) |
| 528 | { |
| 529 | struct i2c_msg msgs[1]; |
| 530 | uint8_t data[2]; |
| 531 | int status = -EACCES; |
| 532 | |
| 533 | pr_debug("%s: writing from slave_addr=[%x] and offset=[%x]\n", |
| 534 | __func__, slave_addr, reg_offset); |
| 535 | |
| 536 | data[0] = reg_offset; |
| 537 | data[1] = *value; |
| 538 | |
| 539 | msgs[0].addr = slave_addr >> 1; |
| 540 | msgs[0].flags = 0; |
| 541 | msgs[0].len = 2; |
| 542 | msgs[0].buf = data; |
| 543 | |
| 544 | status = i2c_transfer(client->adapter, msgs, 1); |
| 545 | if (status < 1) { |
| 546 | pr_err("I2C WRITE FAILED=[%d]\n", status); |
| 547 | return -EACCES; |
| 548 | } |
| 549 | pr_debug("%s: I2C write status=%x\n", __func__, status); |
| 550 | return status; |
| 551 | } |
| 552 | EXPORT_SYMBOL(mdss_i2c_byte_write); |