Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 1 | /* Copyright (c) 2012-2014, 2018, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | * |
| 12 | */ |
| 13 | |
| 14 | #include <linux/bitops.h> |
| 15 | #include <linux/delay.h> |
| 16 | #include <linux/module.h> |
| 17 | #include <linux/mutex.h> |
| 18 | #include <linux/of_address.h> |
| 19 | #include <linux/of_platform.h> |
| 20 | #include <linux/of_gpio.h> |
| 21 | #include <linux/types.h> |
| 22 | #include <linux/vmalloc.h> |
| 23 | #include <linux/input.h> |
| 24 | #include <linux/usb/msm_hsusb.h> |
| 25 | #include <linux/mhl_8334.h> |
| 26 | #include <linux/mdss_io_util.h> |
| 27 | |
| 28 | #include "mdss_fb.h" |
| 29 | #include "mdss_hdmi_tx.h" |
| 30 | #include "mdss_hdmi_edid.h" |
| 31 | #include "mdss.h" |
| 32 | #include "mdss_panel.h" |
| 33 | #include "mhl_msc.h" |
| 34 | #include "mdss_hdmi_mhl.h" |
| 35 | |
| 36 | #define MHL_DRIVER_NAME "sii8334" |
| 37 | #define COMPATIBLE_NAME "qcom,mhl-sii8334" |
| 38 | #define MAX_CURRENT 700000 |
| 39 | |
| 40 | #define pr_debug_intr(...) |
| 41 | |
| 42 | #define MSC_START_BIT_MSC_CMD (0x01 << 0) |
| 43 | #define MSC_START_BIT_VS_CMD (0x01 << 1) |
| 44 | #define MSC_START_BIT_READ_REG (0x01 << 2) |
| 45 | #define MSC_START_BIT_WRITE_REG (0x01 << 3) |
| 46 | #define MSC_START_BIT_WRITE_BURST (0x01 << 4) |
| 47 | |
| 48 | /* supported RCP key code */ |
| 49 | u16 support_rcp_key_code_tbl[] = { |
| 50 | KEY_ENTER, /* 0x00 Select */ |
| 51 | KEY_UP, /* 0x01 Up */ |
| 52 | KEY_DOWN, /* 0x02 Down */ |
| 53 | KEY_LEFT, /* 0x03 Left */ |
| 54 | KEY_RIGHT, /* 0x04 Right */ |
| 55 | KEY_UNKNOWN, /* 0x05 Right-up */ |
| 56 | KEY_UNKNOWN, /* 0x06 Right-down */ |
| 57 | KEY_UNKNOWN, /* 0x07 Left-up */ |
| 58 | KEY_UNKNOWN, /* 0x08 Left-down */ |
| 59 | KEY_MENU, /* 0x09 Root Menu */ |
| 60 | KEY_OPTION, /* 0x0A Setup Menu */ |
| 61 | KEY_UNKNOWN, /* 0x0B Contents Menu */ |
| 62 | KEY_UNKNOWN, /* 0x0C Favorite Menu */ |
| 63 | KEY_EXIT, /* 0x0D Exit */ |
| 64 | KEY_RESERVED, /* 0x0E */ |
| 65 | KEY_RESERVED, |
| 66 | KEY_RESERVED, |
| 67 | KEY_RESERVED, |
| 68 | KEY_RESERVED, |
| 69 | KEY_RESERVED, |
| 70 | KEY_RESERVED, |
| 71 | KEY_RESERVED, |
| 72 | KEY_RESERVED, |
| 73 | KEY_RESERVED, |
| 74 | KEY_RESERVED, |
| 75 | KEY_RESERVED, |
| 76 | KEY_RESERVED, |
| 77 | KEY_RESERVED, |
| 78 | KEY_RESERVED, |
| 79 | KEY_RESERVED, |
| 80 | KEY_RESERVED, |
| 81 | KEY_RESERVED, /* 0x1F */ |
| 82 | KEY_NUMERIC_0, /* 0x20 NUMERIC_0 */ |
| 83 | KEY_NUMERIC_1, /* 0x21 NUMERIC_1 */ |
| 84 | KEY_NUMERIC_2, /* 0x22 NUMERIC_2 */ |
| 85 | KEY_NUMERIC_3, /* 0x23 NUMERIC_3 */ |
| 86 | KEY_NUMERIC_4, /* 0x24 NUMERIC_4 */ |
| 87 | KEY_NUMERIC_5, /* 0x25 NUMERIC_5 */ |
| 88 | KEY_NUMERIC_6, /* 0x26 NUMERIC_6 */ |
| 89 | KEY_NUMERIC_7, /* 0x27 NUMERIC_7 */ |
| 90 | KEY_NUMERIC_8, /* 0x28 NUMERIC_8 */ |
| 91 | KEY_NUMERIC_9, /* 0x29 NUMERIC_9 */ |
| 92 | KEY_DOT, /* 0x2A Dot */ |
| 93 | KEY_ENTER, /* 0x2B Enter */ |
| 94 | KEY_ESC, /* 0x2C Clear */ |
| 95 | KEY_RESERVED, /* 0x2D */ |
| 96 | KEY_RESERVED, /* 0x2E */ |
| 97 | KEY_RESERVED, /* 0x2F */ |
| 98 | KEY_UNKNOWN, /* 0x30 Channel Up */ |
| 99 | KEY_UNKNOWN, /* 0x31 Channel Down */ |
| 100 | KEY_UNKNOWN, /* 0x32 Previous Channel */ |
| 101 | KEY_UNKNOWN, /* 0x33 Sound Select */ |
| 102 | KEY_UNKNOWN, /* 0x34 Input Select */ |
| 103 | KEY_UNKNOWN, /* 0x35 Show Information */ |
| 104 | KEY_UNKNOWN, /* 0x36 Help */ |
| 105 | KEY_UNKNOWN, /* 0x37 Page Up */ |
| 106 | KEY_UNKNOWN, /* 0x38 Page Down */ |
| 107 | KEY_RESERVED, /* 0x39 */ |
| 108 | KEY_RESERVED, |
| 109 | KEY_RESERVED, |
| 110 | KEY_RESERVED, |
| 111 | KEY_RESERVED, |
| 112 | KEY_RESERVED, |
| 113 | KEY_RESERVED, /* 0x3F */ |
| 114 | KEY_RESERVED, /* 0x40 */ |
| 115 | KEY_VOLUMEUP, /* 0x41 Volume Up */ |
| 116 | KEY_VOLUMEDOWN, /* 0x42 Volume Down */ |
| 117 | KEY_MUTE, /* 0x43 Mute */ |
| 118 | KEY_PLAY, /* 0x44 Play */ |
| 119 | KEY_STOP, /* 0x45 Stop */ |
| 120 | KEY_PAUSE, /* 0x46 Pause */ |
| 121 | KEY_UNKNOWN, /* 0x47 Record */ |
| 122 | KEY_REWIND, /* 0x48 Rewind */ |
| 123 | KEY_FASTFORWARD, /* 0x49 Fast Forward */ |
| 124 | KEY_UNKNOWN, /* 0x4A Eject */ |
| 125 | KEY_FORWARD, /* 0x4B Forward */ |
| 126 | KEY_BACK, /* 0x4C Backward */ |
| 127 | KEY_RESERVED, /* 0x4D */ |
| 128 | KEY_RESERVED, |
| 129 | KEY_RESERVED, /* 0x4F */ |
| 130 | KEY_UNKNOWN, /* 0x50 Angle */ |
| 131 | KEY_UNKNOWN, /* 0x51 Subtitle */ |
| 132 | KEY_RESERVED, /* 0x52 */ |
| 133 | KEY_RESERVED, |
| 134 | KEY_RESERVED, |
| 135 | KEY_RESERVED, |
| 136 | KEY_RESERVED, |
| 137 | KEY_RESERVED, |
| 138 | KEY_RESERVED, |
| 139 | KEY_RESERVED, |
| 140 | KEY_RESERVED, |
| 141 | KEY_RESERVED, |
| 142 | KEY_RESERVED, |
| 143 | KEY_RESERVED, |
| 144 | KEY_RESERVED, |
| 145 | KEY_RESERVED, /* 0x5F */ |
| 146 | KEY_PLAYPAUSE, /* 0x60 Play Function */ |
| 147 | KEY_PLAYPAUSE, /* 0x61 Pause_Play Function */ |
| 148 | KEY_UNKNOWN, /* 0x62 Record Function */ |
| 149 | KEY_PAUSE, /* 0x63 Pause Record Function */ |
| 150 | KEY_STOP, /* 0x64 Stop Function */ |
| 151 | KEY_MUTE, /* 0x65 Mute Function */ |
| 152 | KEY_UNKNOWN, /* 0x66 Restore Volume Function */ |
| 153 | KEY_UNKNOWN, /* 0x67 Tune Function */ |
| 154 | KEY_UNKNOWN, /* 0x68 Select Media Function */ |
| 155 | KEY_RESERVED, /* 0x69 */ |
| 156 | KEY_RESERVED, |
| 157 | KEY_RESERVED, |
| 158 | KEY_RESERVED, |
| 159 | KEY_RESERVED, |
| 160 | KEY_RESERVED, |
| 161 | KEY_RESERVED, |
| 162 | KEY_RESERVED, /* 0x70 */ |
| 163 | KEY_BLUE, /* 0x71 F1 */ |
| 164 | KEY_RED, /* 0x72 F2 */ |
| 165 | KEY_GREEN, /* 0x73 F3 */ |
| 166 | KEY_YELLOW, /* 0x74 F4 */ |
| 167 | KEY_UNKNOWN, /* 0x75 F5 */ |
| 168 | KEY_RESERVED, /* 0x76 */ |
| 169 | KEY_RESERVED, |
| 170 | KEY_RESERVED, |
| 171 | KEY_RESERVED, |
| 172 | KEY_RESERVED, |
| 173 | KEY_RESERVED, |
| 174 | KEY_RESERVED, |
| 175 | KEY_RESERVED, /* 0x7D */ |
| 176 | KEY_VENDOR, /* Vendor Specific */ |
| 177 | KEY_RESERVED, /* 0x7F */ |
| 178 | }; |
| 179 | |
| 180 | |
| 181 | uint8_t slave_addrs[MAX_PAGES] = { |
| 182 | DEV_PAGE_TPI_0, |
| 183 | DEV_PAGE_TX_L0_0, |
| 184 | DEV_PAGE_TX_L1_0, |
| 185 | DEV_PAGE_TX_2_0, |
| 186 | DEV_PAGE_TX_3_0, |
| 187 | DEV_PAGE_CBUS, |
| 188 | DEV_PAGE_DDC_EDID, |
| 189 | DEV_PAGE_DDC_SEGM, |
| 190 | }; |
| 191 | |
| 192 | static irqreturn_t mhl_tx_isr(int irq, void *dev_id); |
| 193 | static void switch_mode(struct mhl_tx_ctrl *mhl_ctrl, |
| 194 | enum mhl_st_type to_mode, bool hpd_off); |
| 195 | static void mhl_init_reg_settings(struct mhl_tx_ctrl *mhl_ctrl, |
| 196 | bool mhl_disc_en); |
| 197 | static int mhl_gpio_config(struct mhl_tx_ctrl *mhl_ctrl, int on); |
| 198 | static int mhl_vreg_config(struct mhl_tx_ctrl *mhl_ctrl, uint8_t on); |
| 199 | |
| 200 | int mhl_i2c_reg_read(struct i2c_client *client, |
| 201 | uint8_t slave_addr_index, uint8_t reg_offset) |
| 202 | { |
| 203 | int rc = -1; |
| 204 | uint8_t buffer = 0; |
| 205 | |
| 206 | rc = mdss_i2c_byte_read(client, slave_addrs[slave_addr_index], |
| 207 | reg_offset, &buffer); |
| 208 | if (rc) { |
| 209 | pr_err("%s: slave=%x, off=%x\n", |
| 210 | __func__, slave_addrs[slave_addr_index], reg_offset); |
| 211 | return rc; |
| 212 | } |
| 213 | return buffer; |
| 214 | } |
| 215 | |
| 216 | |
| 217 | int mhl_i2c_reg_write(struct i2c_client *client, |
| 218 | uint8_t slave_addr_index, uint8_t reg_offset, |
| 219 | uint8_t value) |
| 220 | { |
| 221 | return mdss_i2c_byte_write(client, slave_addrs[slave_addr_index], |
| 222 | reg_offset, &value); |
| 223 | } |
| 224 | |
| 225 | void mhl_i2c_reg_modify(struct i2c_client *client, |
| 226 | uint8_t slave_addr_index, uint8_t reg_offset, |
| 227 | uint8_t mask, uint8_t val) |
| 228 | { |
| 229 | uint8_t temp; |
| 230 | |
| 231 | temp = mhl_i2c_reg_read(client, slave_addr_index, reg_offset); |
| 232 | temp &= (~mask); |
| 233 | temp |= (mask & val); |
| 234 | mhl_i2c_reg_write(client, slave_addr_index, reg_offset, temp); |
| 235 | } |
| 236 | |
| 237 | |
| 238 | static int mhl_tx_get_dt_data(struct device *dev, |
| 239 | struct mhl_tx_platform_data *pdata) |
| 240 | { |
| 241 | int i, rc = 0; |
| 242 | struct device_node *of_node = NULL; |
| 243 | struct dss_gpio *temp_gpio = NULL; |
| 244 | struct platform_device *hdmi_pdev = NULL; |
| 245 | struct device_node *hdmi_tx_node = NULL; |
| 246 | int dt_gpio; |
| 247 | |
| 248 | i = 0; |
| 249 | |
| 250 | if (!dev || !pdata) { |
| 251 | pr_err("%s: invalid input\n", __func__); |
| 252 | return -EINVAL; |
| 253 | } |
| 254 | |
| 255 | of_node = dev->of_node; |
| 256 | if (!of_node) { |
| 257 | pr_err("%s: invalid of_node\n", __func__); |
| 258 | goto error; |
| 259 | } |
| 260 | |
| 261 | pr_debug("%s: id=%d\n", __func__, dev->id); |
| 262 | |
| 263 | /* GPIOs */ |
| 264 | temp_gpio = NULL; |
| 265 | temp_gpio = devm_kzalloc(dev, sizeof(struct dss_gpio), GFP_KERNEL); |
| 266 | pr_debug("%s: gpios allocd\n", __func__); |
| 267 | if (!(temp_gpio)) { |
| 268 | pr_err("%s: can't alloc %d gpio mem\n", __func__, i); |
| 269 | goto error; |
| 270 | } |
| 271 | /* RESET */ |
| 272 | dt_gpio = of_get_named_gpio(of_node, "mhl-rst-gpio", 0); |
| 273 | if (dt_gpio < 0) { |
| 274 | pr_err("%s: Can't get mhl-rst-gpio\n", __func__); |
| 275 | goto error; |
| 276 | } |
| 277 | |
| 278 | temp_gpio->gpio = dt_gpio; |
| 279 | snprintf(temp_gpio->gpio_name, 32, "%s", "mhl-rst-gpio"); |
| 280 | pr_debug("%s: rst gpio=[%d]\n", __func__, |
| 281 | temp_gpio->gpio); |
| 282 | pdata->gpios[MHL_TX_RESET_GPIO] = temp_gpio; |
| 283 | |
| 284 | /* PWR */ |
| 285 | temp_gpio = NULL; |
| 286 | temp_gpio = devm_kzalloc(dev, sizeof(struct dss_gpio), GFP_KERNEL); |
| 287 | pr_debug("%s: gpios allocd\n", __func__); |
| 288 | if (!(temp_gpio)) { |
| 289 | pr_err("%s: can't alloc %d gpio mem\n", __func__, i); |
| 290 | goto error; |
| 291 | } |
| 292 | dt_gpio = of_get_named_gpio(of_node, "mhl-pwr-gpio", 0); |
| 293 | if (dt_gpio < 0) { |
| 294 | pr_err("%s: Can't get mhl-pwr-gpio\n", __func__); |
| 295 | goto error; |
| 296 | } |
| 297 | |
| 298 | temp_gpio->gpio = dt_gpio; |
| 299 | snprintf(temp_gpio->gpio_name, 32, "%s", "mhl-pwr-gpio"); |
| 300 | pr_debug("%s: pmic gpio=[%d]\n", __func__, |
| 301 | temp_gpio->gpio); |
| 302 | pdata->gpios[MHL_TX_PMIC_PWR_GPIO] = temp_gpio; |
| 303 | |
| 304 | /* INTR */ |
| 305 | temp_gpio = NULL; |
| 306 | temp_gpio = devm_kzalloc(dev, sizeof(struct dss_gpio), GFP_KERNEL); |
| 307 | pr_debug("%s: gpios allocd\n", __func__); |
| 308 | if (!(temp_gpio)) { |
| 309 | pr_err("%s: can't alloc %d gpio mem\n", __func__, i); |
| 310 | goto error; |
| 311 | } |
| 312 | dt_gpio = of_get_named_gpio(of_node, "mhl-intr-gpio", 0); |
| 313 | if (dt_gpio < 0) { |
| 314 | pr_err("%s: Can't get mhl-intr-gpio\n", __func__); |
| 315 | goto error; |
| 316 | } |
| 317 | |
| 318 | temp_gpio->gpio = dt_gpio; |
| 319 | snprintf(temp_gpio->gpio_name, 32, "%s", "mhl-intr-gpio"); |
| 320 | pr_debug("%s: intr gpio=[%d]\n", __func__, |
| 321 | temp_gpio->gpio); |
| 322 | pdata->gpios[MHL_TX_INTR_GPIO] = temp_gpio; |
| 323 | |
| 324 | /* parse phandle for hdmi tx */ |
| 325 | hdmi_tx_node = of_parse_phandle(of_node, "qcom,hdmi-tx-map", 0); |
| 326 | if (!hdmi_tx_node) { |
| 327 | pr_err("%s: can't find hdmi phandle\n", __func__); |
| 328 | goto error; |
| 329 | } |
| 330 | |
| 331 | hdmi_pdev = of_find_device_by_node(hdmi_tx_node); |
| 332 | if (!hdmi_pdev) { |
| 333 | pr_err("%s: can't find the device by node\n", __func__); |
| 334 | goto error; |
| 335 | } |
| 336 | pr_debug("%s: hdmi_pdev [0X%x] to pdata->pdev\n", |
| 337 | __func__, (unsigned int)hdmi_pdev); |
| 338 | |
| 339 | pdata->hdmi_pdev = hdmi_pdev; |
| 340 | |
| 341 | return 0; |
| 342 | error: |
| 343 | pr_err("%s: ret due to err\n", __func__); |
| 344 | for (i = 0; i < MHL_TX_MAX_GPIO; i++) |
| 345 | if (pdata->gpios[i]) |
| 346 | devm_kfree(dev, pdata->gpios[i]); |
| 347 | return rc; |
| 348 | } /* mhl_tx_get_dt_data */ |
| 349 | |
| 350 | static int mhl_sii_reset_pin(struct mhl_tx_ctrl *mhl_ctrl, int on) |
| 351 | { |
| 352 | if (mhl_ctrl->pdata->gpios[MHL_TX_RESET_GPIO]) { |
| 353 | gpio_set_value( |
| 354 | mhl_ctrl->pdata->gpios[MHL_TX_RESET_GPIO]->gpio, |
| 355 | on); |
| 356 | } |
| 357 | return 0; |
| 358 | } |
| 359 | |
| 360 | |
| 361 | static int mhl_sii_wait_for_rgnd(struct mhl_tx_ctrl *mhl_ctrl) |
| 362 | { |
| 363 | int timeout; |
| 364 | |
| 365 | pr_debug("%s:%u\n", __func__, __LINE__); |
| 366 | |
| 367 | if (mhl_ctrl->mhl_mode) { |
| 368 | pr_debug("%s: already in mhl mode\n", __func__); |
| 369 | return 0; |
| 370 | } |
| 371 | |
| 372 | reinit_completion(&mhl_ctrl->rgnd_done); |
| 373 | /* |
| 374 | * after toggling reset line and enabling disc |
| 375 | * tx can take a while to generate intr |
| 376 | */ |
| 377 | timeout = wait_for_completion_timeout |
| 378 | (&mhl_ctrl->rgnd_done, HZ * 3); |
| 379 | if (!timeout) { |
| 380 | /* |
| 381 | * most likely nothing plugged in USB |
| 382 | * USB HOST connected or already in USB mode |
| 383 | */ |
| 384 | pr_warn("%s:%u timedout\n", __func__, __LINE__); |
| 385 | return -ENODEV; |
| 386 | } |
| 387 | |
| 388 | return 0; |
| 389 | } |
| 390 | |
| 391 | static int mhl_sii_config(struct mhl_tx_ctrl *mhl_ctrl, bool on) |
| 392 | { |
| 393 | int rc = 0; |
| 394 | struct i2c_client *client = NULL; |
| 395 | |
| 396 | if (!mhl_ctrl) { |
| 397 | pr_err("%s: ctrl is NULL\n", __func__); |
| 398 | return -EINVAL; |
| 399 | } |
| 400 | |
| 401 | client = mhl_ctrl->i2c_handle; |
| 402 | |
| 403 | if (on && !mhl_ctrl->irq_req_done) { |
| 404 | rc = mhl_vreg_config(mhl_ctrl, 1); |
| 405 | if (rc) { |
| 406 | pr_err("%s: vreg init failed [%d]\n", |
| 407 | __func__, rc); |
| 408 | return -ENODEV; |
| 409 | } |
| 410 | |
| 411 | rc = mhl_gpio_config(mhl_ctrl, 1); |
| 412 | if (rc) { |
| 413 | pr_err("%s: gpio init failed [%d]\n", |
| 414 | __func__, rc); |
| 415 | return -ENODEV; |
| 416 | } |
| 417 | |
| 418 | rc = request_threaded_irq(mhl_ctrl->i2c_handle->irq, NULL, |
| 419 | &mhl_tx_isr, IRQF_TRIGGER_LOW | IRQF_ONESHOT, |
| 420 | client->dev.driver->name, mhl_ctrl); |
| 421 | if (rc) { |
| 422 | pr_err("%s: request_threaded_irq failed, status: %d\n", |
| 423 | __func__, rc); |
| 424 | return -ENODEV; |
| 425 | } |
| 426 | mhl_ctrl->irq_req_done = true; |
| 427 | } else if (!on && mhl_ctrl->irq_req_done) { |
| 428 | free_irq(mhl_ctrl->i2c_handle->irq, mhl_ctrl); |
| 429 | mhl_gpio_config(mhl_ctrl, 0); |
| 430 | mhl_vreg_config(mhl_ctrl, 0); |
| 431 | mhl_ctrl->irq_req_done = false; |
| 432 | } |
| 433 | |
| 434 | return rc; |
| 435 | } |
| 436 | |
| 437 | static void mhl_sii_disc_intr_work(struct work_struct *work) |
| 438 | { |
| 439 | struct mhl_tx_ctrl *mhl_ctrl = NULL; |
| 440 | |
| 441 | mhl_ctrl = container_of(work, struct mhl_tx_ctrl, mhl_intr_work); |
| 442 | |
| 443 | mhl_sii_config(mhl_ctrl, false); |
| 444 | } |
| 445 | |
| 446 | /* USB_HANDSHAKING FUNCTIONS */ |
| 447 | static int mhl_sii_device_discovery(void *data, int id, |
| 448 | void (*usb_notify_cb)(void *, int), void *ctx) |
| 449 | { |
| 450 | int rc; |
| 451 | struct mhl_tx_ctrl *mhl_ctrl = data; |
| 452 | unsigned long flags; |
| 453 | |
| 454 | if (id) { |
| 455 | /* When MHL cable is disconnected we get a sii8334 |
| 456 | * mhl_disconnect interrupt which is handled separately. |
| 457 | */ |
| 458 | pr_debug("%s: USB ID pin high\n", __func__); |
| 459 | return id; |
| 460 | } |
| 461 | |
| 462 | if (!mhl_ctrl || !usb_notify_cb) { |
| 463 | pr_warn("%s: cb || ctrl is NULL\n", __func__); |
| 464 | /* return "USB" so caller can proceed */ |
| 465 | return -EINVAL; |
| 466 | } |
| 467 | |
| 468 | if (!mhl_ctrl->notify_usb_online) { |
| 469 | mhl_ctrl->notify_usb_online = usb_notify_cb; |
| 470 | mhl_ctrl->notify_ctx = ctx; |
| 471 | } |
| 472 | |
| 473 | flush_work(&mhl_ctrl->mhl_intr_work); |
| 474 | |
| 475 | if (!mhl_ctrl->irq_req_done) { |
| 476 | rc = mhl_sii_config(mhl_ctrl, true); |
| 477 | if (rc) { |
| 478 | pr_err("%s: Failed to config vreg/gpio\n", __func__); |
| 479 | return rc; |
| 480 | } |
| 481 | |
| 482 | /* wait for i2c interrupt line to be activated */ |
| 483 | msleep(100); |
| 484 | } |
| 485 | |
| 486 | if (!mhl_ctrl->disc_enabled) { |
| 487 | spin_lock_irqsave(&mhl_ctrl->lock, flags); |
| 488 | mhl_ctrl->tx_powered_off = false; |
| 489 | spin_unlock_irqrestore(&mhl_ctrl->lock, flags); |
| 490 | mhl_sii_reset_pin(mhl_ctrl, 0); |
| 491 | msleep(50); |
| 492 | mhl_sii_reset_pin(mhl_ctrl, 1); |
| 493 | /* chipset PR recommends waiting for at least 100 ms |
| 494 | * the chipset needs longer to come out of D3 state. |
| 495 | */ |
| 496 | msleep(100); |
| 497 | mhl_init_reg_settings(mhl_ctrl, true); |
| 498 | /* allow tx to enable dev disc after D3 state */ |
| 499 | msleep(100); |
| 500 | if (mhl_sii_wait_for_rgnd(mhl_ctrl)) { |
| 501 | pr_err("%s: discovery timeout\n", __func__); |
| 502 | |
| 503 | mhl_sii_config(mhl_ctrl, false); |
| 504 | |
| 505 | return -EAGAIN; |
| 506 | } |
| 507 | } else { |
| 508 | if (mhl_ctrl->cur_state == POWER_STATE_D3) { |
| 509 | mhl_sii_wait_for_rgnd(mhl_ctrl); |
| 510 | } else { |
| 511 | /* in MHL mode */ |
| 512 | pr_debug("%s:%u\n", __func__, __LINE__); |
| 513 | } |
| 514 | } |
| 515 | |
| 516 | rc = mhl_ctrl->mhl_mode ? 0 : 1; |
| 517 | |
| 518 | pr_debug("%s: ret result: %s\n", __func__, rc ? "usb" : " mhl"); |
| 519 | return rc; |
| 520 | } |
| 521 | |
| 522 | static int mhl_power_get_property(struct power_supply *psy, |
| 523 | enum power_supply_property psp, |
| 524 | union power_supply_propval *val) |
| 525 | { |
| 526 | struct mhl_tx_ctrl *mhl_ctrl = |
| 527 | container_of(psy, struct mhl_tx_ctrl, mhl_psy); |
| 528 | |
| 529 | switch (psp) { |
| 530 | case POWER_SUPPLY_PROP_CURRENT_MAX: |
| 531 | val->intval = mhl_ctrl->current_val; |
| 532 | break; |
| 533 | case POWER_SUPPLY_PROP_PRESENT: |
| 534 | val->intval = mhl_ctrl->vbus_active; |
| 535 | break; |
| 536 | case POWER_SUPPLY_PROP_ONLINE: |
| 537 | val->intval = mhl_ctrl->vbus_active && mhl_ctrl->mhl_mode; |
| 538 | break; |
| 539 | default: |
| 540 | return -EINVAL; |
| 541 | } |
| 542 | return 0; |
| 543 | } |
| 544 | |
| 545 | static int mhl_power_set_property(struct power_supply *psy, |
| 546 | enum power_supply_property psp, |
| 547 | const union power_supply_propval *val) |
| 548 | { |
| 549 | struct mhl_tx_ctrl *mhl_ctrl = |
| 550 | container_of(psy, struct mhl_tx_ctrl, mhl_psy); |
| 551 | |
| 552 | switch (psp) { |
| 553 | case POWER_SUPPLY_PROP_PRESENT: |
| 554 | mhl_ctrl->vbus_active = val->intval; |
| 555 | if (mhl_ctrl->vbus_active) |
| 556 | mhl_ctrl->current_val = MAX_CURRENT; |
| 557 | else |
| 558 | mhl_ctrl->current_val = 0; |
| 559 | power_supply_changed(psy); |
| 560 | break; |
| 561 | case POWER_SUPPLY_PROP_ONLINE: |
| 562 | case POWER_SUPPLY_PROP_CURRENT_MAX: |
| 563 | break; |
| 564 | default: |
| 565 | return -EINVAL; |
| 566 | } |
| 567 | |
| 568 | return 0; |
| 569 | } |
| 570 | |
| 571 | static char *mhl_pm_power_supplied_to[] = { |
| 572 | "usb", |
| 573 | }; |
| 574 | |
| 575 | static enum power_supply_property mhl_pm_power_props[] = { |
| 576 | POWER_SUPPLY_PROP_PRESENT, |
| 577 | POWER_SUPPLY_PROP_ONLINE, |
| 578 | POWER_SUPPLY_PROP_CURRENT_MAX, |
| 579 | }; |
| 580 | |
| 581 | static void cbus_reset(struct mhl_tx_ctrl *mhl_ctrl) |
| 582 | { |
| 583 | uint8_t i; |
| 584 | struct i2c_client *client = mhl_ctrl->i2c_handle; |
| 585 | |
| 586 | /* Read the chip rev ID */ |
| 587 | mhl_ctrl->chip_rev_id = MHL_SII_PAGE0_RD(0x04); |
| 588 | pr_debug("MHL: chip rev ID read=[%x]\n", mhl_ctrl->chip_rev_id); |
| 589 | |
| 590 | /* |
| 591 | * REG_SRST |
| 592 | */ |
| 593 | MHL_SII_REG_NAME_MOD(REG_SRST, BIT3, BIT3); |
| 594 | msleep(20); |
| 595 | MHL_SII_REG_NAME_MOD(REG_SRST, BIT3, 0x00); |
| 596 | /* |
| 597 | * REG_INTR1 and REG_INTR4 |
| 598 | */ |
| 599 | MHL_SII_REG_NAME_WR(REG_INTR1_MASK, BIT6); |
| 600 | MHL_SII_REG_NAME_WR(REG_INTR4_MASK, |
| 601 | BIT0 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6); |
| 602 | |
| 603 | if (mhl_ctrl->chip_rev_id < 1) |
| 604 | MHL_SII_REG_NAME_WR(REG_INTR5_MASK, BIT3 | BIT4); |
| 605 | else |
| 606 | MHL_SII_REG_NAME_WR(REG_INTR5_MASK, 0x00); |
| 607 | |
| 608 | /* Unmask CBUS1 Intrs */ |
| 609 | MHL_SII_REG_NAME_WR(REG_CBUS_INTR_ENABLE, |
| 610 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6); |
| 611 | |
| 612 | /* Unmask CBUS2 Intrs */ |
| 613 | MHL_SII_REG_NAME_WR(REG_CBUS_MSC_INT2_ENABLE, BIT2 | BIT3); |
| 614 | |
| 615 | for (i = 0; i < 4; i++) { |
| 616 | /* |
| 617 | * Enable WRITE_STAT interrupt for writes to |
| 618 | * all 4 MSC Status registers. |
| 619 | */ |
| 620 | MHL_SII_CBUS_WR((0xE0 + i), 0xFF); |
| 621 | |
| 622 | /* |
| 623 | * Enable SET_INT interrupt for writes to |
| 624 | * all 4 MSC Interrupt registers. |
| 625 | */ |
| 626 | MHL_SII_CBUS_WR((0xF0 + i), 0xFF); |
| 627 | } |
| 628 | } |
| 629 | |
| 630 | static void init_cbus_regs(struct i2c_client *client) |
| 631 | { |
| 632 | uint8_t regval; |
| 633 | |
| 634 | /* Increase DDC translation layer timer*/ |
| 635 | MHL_SII_CBUS_WR(0x0007, 0xF2); |
| 636 | /* Drive High Time */ |
| 637 | MHL_SII_CBUS_WR(0x0036, 0x0B); |
| 638 | /* Use programmed timing */ |
| 639 | MHL_SII_CBUS_WR(0x0039, 0x30); |
| 640 | /* CBUS Drive Strength */ |
| 641 | MHL_SII_CBUS_WR(0x0040, 0x03); |
| 642 | /* |
| 643 | * Write initial default settings |
| 644 | * to devcap regs: default settings |
| 645 | */ |
| 646 | MHL_SII_CBUS_WR(0x0080 | |
| 647 | DEVCAP_OFFSET_DEV_STATE, DEVCAP_VAL_DEV_STATE); |
| 648 | MHL_SII_CBUS_WR(0x0080 | |
| 649 | DEVCAP_OFFSET_MHL_VERSION, DEVCAP_VAL_MHL_VERSION); |
| 650 | MHL_SII_CBUS_WR(0x0080 | |
| 651 | DEVCAP_OFFSET_DEV_CAT, DEVCAP_VAL_DEV_CAT); |
| 652 | MHL_SII_CBUS_WR(0x0080 | |
| 653 | DEVCAP_OFFSET_ADOPTER_ID_H, DEVCAP_VAL_ADOPTER_ID_H); |
| 654 | MHL_SII_CBUS_WR(0x0080 | |
| 655 | DEVCAP_OFFSET_ADOPTER_ID_L, DEVCAP_VAL_ADOPTER_ID_L); |
| 656 | MHL_SII_CBUS_WR(0x0080 | DEVCAP_OFFSET_VID_LINK_MODE, |
| 657 | DEVCAP_VAL_VID_LINK_MODE); |
| 658 | MHL_SII_CBUS_WR(0x0080 | |
| 659 | DEVCAP_OFFSET_AUD_LINK_MODE, |
| 660 | DEVCAP_VAL_AUD_LINK_MODE); |
| 661 | MHL_SII_CBUS_WR(0x0080 | |
| 662 | DEVCAP_OFFSET_VIDEO_TYPE, DEVCAP_VAL_VIDEO_TYPE); |
| 663 | MHL_SII_CBUS_WR(0x0080 | |
| 664 | DEVCAP_OFFSET_LOG_DEV_MAP, DEVCAP_VAL_LOG_DEV_MAP); |
| 665 | MHL_SII_CBUS_WR(0x0080 | |
| 666 | DEVCAP_OFFSET_BANDWIDTH, DEVCAP_VAL_BANDWIDTH); |
| 667 | MHL_SII_CBUS_WR(0x0080 | |
| 668 | DEVCAP_OFFSET_FEATURE_FLAG, DEVCAP_VAL_FEATURE_FLAG); |
| 669 | MHL_SII_CBUS_WR(0x0080 | |
| 670 | DEVCAP_OFFSET_DEVICE_ID_H, DEVCAP_VAL_DEVICE_ID_H); |
| 671 | MHL_SII_CBUS_WR(0x0080 | |
| 672 | DEVCAP_OFFSET_DEVICE_ID_L, DEVCAP_VAL_DEVICE_ID_L); |
| 673 | MHL_SII_CBUS_WR(0x0080 | |
| 674 | DEVCAP_OFFSET_SCRATCHPAD_SIZE, |
| 675 | DEVCAP_VAL_SCRATCHPAD_SIZE); |
| 676 | MHL_SII_CBUS_WR(0x0080 | |
| 677 | DEVCAP_OFFSET_INT_STAT_SIZE, |
| 678 | DEVCAP_VAL_INT_STAT_SIZE); |
| 679 | MHL_SII_CBUS_WR(0x0080 | |
| 680 | DEVCAP_OFFSET_RESERVED, DEVCAP_VAL_RESERVED); |
| 681 | |
| 682 | /* Make bits 2,3 (initiator timeout) to 1,1 |
| 683 | * for register CBUS_LINK_CONTROL_2 |
| 684 | * REG_CBUS_LINK_CONTROL_2 |
| 685 | */ |
| 686 | regval = MHL_SII_CBUS_RD(0x0031); |
| 687 | regval = (regval | 0x0C); |
| 688 | /* REG_CBUS_LINK_CONTROL_2 */ |
| 689 | MHL_SII_CBUS_WR(0x0031, regval); |
| 690 | /* REG_MSC_TIMEOUT_LIMIT */ |
| 691 | MHL_SII_CBUS_WR(0x0022, 0x0F); |
| 692 | /* REG_CBUS_LINK_CONTROL_1 */ |
| 693 | MHL_SII_CBUS_WR(0x0030, 0x01); |
| 694 | /* disallow vendor specific commands */ |
| 695 | MHL_SII_CBUS_MOD(0x002E, BIT4, BIT4); |
| 696 | } |
| 697 | |
| 698 | /* |
| 699 | * Configure the initial reg settings |
| 700 | */ |
| 701 | static void mhl_init_reg_settings(struct mhl_tx_ctrl *mhl_ctrl, |
| 702 | bool mhl_disc_en) |
| 703 | { |
| 704 | uint8_t regval; |
| 705 | |
| 706 | /* |
| 707 | * ============================================ |
| 708 | * POWER UP |
| 709 | * ============================================ |
| 710 | */ |
| 711 | struct i2c_client *client = mhl_ctrl->i2c_handle; |
| 712 | |
| 713 | /* Power up 1.2V core */ |
| 714 | MHL_SII_PAGE1_WR(0x003D, 0x3F); |
| 715 | /* Enable Tx PLL Clock */ |
| 716 | MHL_SII_PAGE2_WR(0x0011, 0x01); |
| 717 | /* Enable Tx Clock Path and Equalizer */ |
| 718 | MHL_SII_PAGE2_WR(0x0012, 0x11); |
| 719 | /* Tx Source Termination ON */ |
| 720 | MHL_SII_REG_NAME_WR(REG_MHLTX_CTL1, 0x10); |
| 721 | /* Enable 1X MHL Clock output */ |
| 722 | MHL_SII_REG_NAME_WR(REG_MHLTX_CTL6, 0xBC); |
| 723 | /* Tx Differential Driver Config */ |
| 724 | MHL_SII_REG_NAME_WR(REG_MHLTX_CTL2, 0x3C); |
| 725 | MHL_SII_REG_NAME_WR(REG_MHLTX_CTL4, 0xC8); |
| 726 | /* PLL Bandwidth Control */ |
| 727 | MHL_SII_REG_NAME_WR(REG_MHLTX_CTL7, 0x03); |
| 728 | MHL_SII_REG_NAME_WR(REG_MHLTX_CTL8, 0x0A); |
| 729 | /* |
| 730 | * ============================================ |
| 731 | * Analog PLL Control |
| 732 | * ============================================ |
| 733 | */ |
| 734 | /* Enable Rx PLL clock */ |
| 735 | MHL_SII_REG_NAME_WR(REG_TMDS_CCTRL, 0x08); |
| 736 | MHL_SII_PAGE0_WR(0x00F8, 0x8C); |
| 737 | MHL_SII_PAGE0_WR(0x0085, 0x02); |
| 738 | MHL_SII_PAGE2_WR(0x0000, 0x00); |
| 739 | regval = MHL_SII_PAGE2_RD(0x0005); |
| 740 | regval &= ~BIT5; |
| 741 | MHL_SII_PAGE2_WR(0x0005, regval); |
| 742 | MHL_SII_PAGE2_WR(0x0013, 0x60); |
| 743 | /* PLL Cal ref sel */ |
| 744 | MHL_SII_PAGE2_WR(0x0017, 0x03); |
| 745 | /* VCO Cal */ |
| 746 | MHL_SII_PAGE2_WR(0x001A, 0x20); |
| 747 | /* Auto EQ */ |
| 748 | MHL_SII_PAGE2_WR(0x0022, 0xE0); |
| 749 | MHL_SII_PAGE2_WR(0x0023, 0xC0); |
| 750 | MHL_SII_PAGE2_WR(0x0024, 0xA0); |
| 751 | MHL_SII_PAGE2_WR(0x0025, 0x80); |
| 752 | MHL_SII_PAGE2_WR(0x0026, 0x60); |
| 753 | MHL_SII_PAGE2_WR(0x0027, 0x40); |
| 754 | MHL_SII_PAGE2_WR(0x0028, 0x20); |
| 755 | MHL_SII_PAGE2_WR(0x0029, 0x00); |
| 756 | /* Rx PLL Bandwidth 4MHz */ |
| 757 | MHL_SII_PAGE2_WR(0x0031, 0x0A); |
| 758 | /* Rx PLL Bandwidth value from I2C */ |
| 759 | MHL_SII_PAGE2_WR(0x0045, 0x06); |
| 760 | MHL_SII_PAGE2_WR(0x004B, 0x06); |
| 761 | MHL_SII_PAGE2_WR(0x004C, 0x60); |
| 762 | /* Manual zone control */ |
| 763 | MHL_SII_PAGE2_WR(0x004C, 0xE0); |
| 764 | /* PLL Mode value */ |
| 765 | MHL_SII_PAGE2_WR(0x004D, 0x00); |
| 766 | MHL_SII_PAGE0_WR(0x0008, 0x35); |
| 767 | /* |
| 768 | * Discovery Control and Status regs |
| 769 | * Setting De-glitch time to 50 ms (default) |
| 770 | * Switch Control Disabled |
| 771 | */ |
| 772 | MHL_SII_REG_NAME_WR(REG_DISC_CTRL2, 0xAD); |
| 773 | /* 1.8V CBUS VTH */ |
| 774 | MHL_SII_REG_NAME_WR(REG_DISC_CTRL5, 0x57); |
| 775 | /* RGND and single Discovery attempt */ |
| 776 | MHL_SII_REG_NAME_WR(REG_DISC_CTRL6, 0x11); |
| 777 | /* Ignore VBUS */ |
| 778 | MHL_SII_REG_NAME_WR(REG_DISC_CTRL8, 0x82); |
| 779 | |
| 780 | /* Enable CBUS Discovery */ |
| 781 | if (mhl_disc_en) { |
| 782 | MHL_SII_REG_NAME_WR(REG_DISC_CTRL9, 0x24); |
| 783 | /* Enable MHL Discovery */ |
| 784 | MHL_SII_REG_NAME_WR(REG_DISC_CTRL1, 0x27); |
| 785 | /* Pull-up resistance off for IDLE state */ |
| 786 | MHL_SII_REG_NAME_WR(REG_DISC_CTRL4, 0x8C); |
| 787 | } else { |
| 788 | MHL_SII_REG_NAME_WR(REG_DISC_CTRL9, 0x26); |
| 789 | /* Disable MHL Discovery */ |
| 790 | MHL_SII_REG_NAME_WR(REG_DISC_CTRL1, 0x26); |
| 791 | MHL_SII_REG_NAME_WR(REG_DISC_CTRL4, 0x8C); |
| 792 | } |
| 793 | |
| 794 | MHL_SII_REG_NAME_WR(REG_DISC_CTRL7, 0x20); |
| 795 | /* MHL CBUS Discovery - immediate comm. */ |
| 796 | MHL_SII_REG_NAME_WR(REG_DISC_CTRL3, 0x86); |
| 797 | |
| 798 | MHL_SII_PAGE3_WR(0x3C, 0x80); |
| 799 | |
| 800 | MHL_SII_REG_NAME_MOD(REG_INT_CTRL, |
| 801 | (BIT6 | BIT5 | BIT4), (BIT6 | BIT4)); |
| 802 | |
| 803 | /* Enable Auto Soft RESET */ |
| 804 | MHL_SII_REG_NAME_WR(REG_SRST, 0x084); |
| 805 | /* HDMI Transcode mode enable */ |
| 806 | MHL_SII_PAGE0_WR(0x000D, 0x1C); |
| 807 | |
| 808 | cbus_reset(mhl_ctrl); |
| 809 | init_cbus_regs(client); |
| 810 | } |
| 811 | |
| 812 | |
| 813 | static void switch_mode(struct mhl_tx_ctrl *mhl_ctrl, enum mhl_st_type to_mode, |
| 814 | bool hpd_off) |
| 815 | { |
| 816 | struct i2c_client *client = mhl_ctrl->i2c_handle; |
| 817 | unsigned long flags; |
| 818 | int rc; |
| 819 | struct msm_hdmi_mhl_ops *hdmi_mhl_ops = mhl_ctrl->hdmi_mhl_ops; |
| 820 | |
| 821 | pr_debug("%s: tx pwr on\n", __func__); |
| 822 | spin_lock_irqsave(&mhl_ctrl->lock, flags); |
| 823 | mhl_ctrl->tx_powered_off = false; |
| 824 | spin_unlock_irqrestore(&mhl_ctrl->lock, flags); |
| 825 | |
| 826 | switch (to_mode) { |
| 827 | case POWER_STATE_D0_NO_MHL: |
| 828 | mhl_ctrl->cur_state = to_mode; |
| 829 | mhl_init_reg_settings(mhl_ctrl, true); |
| 830 | /* REG_DISC_CTRL1 */ |
| 831 | MHL_SII_REG_NAME_MOD(REG_DISC_CTRL1, BIT1 | BIT0, BIT0); |
| 832 | |
| 833 | /* TPI_DEVICE_POWER_STATE_CTRL_REG */ |
| 834 | mhl_i2c_reg_modify(client, TX_PAGE_TPI, 0x001E, BIT1 | BIT0, |
| 835 | 0x00); |
| 836 | break; |
| 837 | case POWER_STATE_D0_MHL: |
| 838 | mhl_ctrl->cur_state = to_mode; |
| 839 | break; |
| 840 | case POWER_STATE_D3: |
| 841 | if (mhl_ctrl->cur_state == POWER_STATE_D3) { |
| 842 | pr_debug("%s: mhl tx already in low power mode\n", |
| 843 | __func__); |
| 844 | break; |
| 845 | } |
| 846 | |
| 847 | /* Force HPD to 0 when not in MHL mode. */ |
| 848 | mhl_drive_hpd(mhl_ctrl, HPD_DOWN); |
| 849 | mhl_tmds_ctrl(mhl_ctrl, TMDS_DISABLE); |
| 850 | /* |
| 851 | * Change TMDS termination to high impedance |
| 852 | * on disconnection. |
| 853 | */ |
| 854 | MHL_SII_REG_NAME_WR(REG_MHLTX_CTL1, 0xD0); |
| 855 | msleep(50); |
| 856 | if (!mhl_ctrl->disc_enabled) |
| 857 | MHL_SII_REG_NAME_MOD(REG_DISC_CTRL1, BIT1 | BIT0, 0x00); |
| 858 | if (hdmi_mhl_ops && hpd_off) { |
| 859 | rc = hdmi_mhl_ops->set_upstream_hpd( |
| 860 | mhl_ctrl->pdata->hdmi_pdev, 0); |
| 861 | pr_debug("%s: hdmi unset hpd %s\n", __func__, |
| 862 | rc ? "failed" : "passed"); |
| 863 | } |
| 864 | mhl_ctrl->cur_state = POWER_STATE_D3; |
| 865 | mhl_ctrl->mhl_mode = 0; |
| 866 | break; |
| 867 | default: |
| 868 | break; |
| 869 | } |
| 870 | } |
| 871 | |
| 872 | static bool is_mhl_powered(void *mhl_ctx) |
| 873 | { |
| 874 | struct mhl_tx_ctrl *mhl_ctrl = (struct mhl_tx_ctrl *)mhl_ctx; |
| 875 | unsigned long flags; |
| 876 | bool r = false; |
| 877 | |
| 878 | spin_lock_irqsave(&mhl_ctrl->lock, flags); |
| 879 | if (mhl_ctrl->tx_powered_off) |
| 880 | r = false; |
| 881 | else |
| 882 | r = true; |
| 883 | spin_unlock_irqrestore(&mhl_ctrl->lock, flags); |
| 884 | |
| 885 | pr_debug("%s: ret pwr state as %x\n", __func__, r); |
| 886 | return r; |
| 887 | } |
| 888 | |
| 889 | void mhl_tmds_ctrl(struct mhl_tx_ctrl *mhl_ctrl, uint8_t on) |
| 890 | { |
| 891 | struct i2c_client *client = mhl_ctrl->i2c_handle; |
| 892 | |
| 893 | if (on) { |
| 894 | MHL_SII_REG_NAME_MOD(REG_TMDS_CCTRL, BIT4, BIT4); |
| 895 | mhl_ctrl->tmds_en_state = true; |
| 896 | } else { |
| 897 | MHL_SII_REG_NAME_MOD(REG_TMDS_CCTRL, BIT4, 0x00); |
| 898 | mhl_ctrl->tmds_en_state = false; |
| 899 | } |
| 900 | } |
| 901 | |
| 902 | void mhl_drive_hpd(struct mhl_tx_ctrl *mhl_ctrl, uint8_t to_state) |
| 903 | { |
| 904 | struct i2c_client *client = mhl_ctrl->i2c_handle; |
| 905 | unsigned long flags; |
| 906 | |
| 907 | pr_debug("%s: To state=[0x%x]\n", __func__, to_state); |
| 908 | if (to_state == HPD_UP) { |
| 909 | /* |
| 910 | * Drive HPD to UP state |
| 911 | * Set HPD_OUT_OVR_EN = HPD State |
| 912 | * EDID read and Un-force HPD (from low) |
| 913 | * propagate to src let HPD float by clearing |
| 914 | * HPD OUT OVRRD EN |
| 915 | */ |
| 916 | spin_lock_irqsave(&mhl_ctrl->lock, flags); |
| 917 | mhl_ctrl->tx_powered_off = false; |
| 918 | spin_unlock_irqrestore(&mhl_ctrl->lock, flags); |
| 919 | MHL_SII_REG_NAME_MOD(REG_INT_CTRL, BIT4, 0); |
| 920 | } else { |
| 921 | /* Drive HPD to DOWN state */ |
| 922 | MHL_SII_REG_NAME_MOD(REG_INT_CTRL, (BIT4 | BIT5), BIT4); |
| 923 | } |
| 924 | } |
| 925 | |
| 926 | static void mhl_msm_connection(struct mhl_tx_ctrl *mhl_ctrl) |
| 927 | { |
| 928 | uint8_t val; |
| 929 | struct i2c_client *client = mhl_ctrl->i2c_handle; |
| 930 | |
| 931 | pr_debug("%s: cur st [0x%x]\n", __func__, |
| 932 | mhl_ctrl->cur_state); |
| 933 | |
| 934 | if (mhl_ctrl->cur_state == POWER_STATE_D0_MHL) { |
| 935 | /* Already in D0 - MHL power state */ |
| 936 | pr_err("%s: cur st not D0\n", __func__); |
| 937 | return; |
| 938 | } |
| 939 | switch_mode(mhl_ctrl, POWER_STATE_D0_MHL, true); |
| 940 | |
| 941 | MHL_SII_REG_NAME_WR(REG_MHLTX_CTL1, 0x10); |
| 942 | MHL_SII_CBUS_WR(0x07, 0xF2); |
| 943 | |
| 944 | /* |
| 945 | * Keep the discovery enabled. Need RGND interrupt |
| 946 | * Possibly chip disables discovery after MHL_EST?? |
| 947 | * Need to re-enable here |
| 948 | */ |
| 949 | val = MHL_SII_PAGE3_RD(0x10); |
| 950 | MHL_SII_PAGE3_WR(0x10, val | BIT0); |
| 951 | |
| 952 | /* |
| 953 | * indicate DCAP_RDY and DCAP_CHG |
| 954 | * to the peer only after |
| 955 | * msm conn has been established |
| 956 | */ |
| 957 | mhl_msc_send_write_stat(mhl_ctrl, |
| 958 | MHL_STATUS_REG_CONNECTED_RDY, |
| 959 | MHL_STATUS_DCAP_RDY); |
| 960 | |
| 961 | mhl_msc_send_set_int(mhl_ctrl, |
| 962 | MHL_RCHANGE_INT, |
| 963 | MHL_INT_DCAP_CHG, |
| 964 | MSC_PRIORITY_SEND); |
| 965 | |
| 966 | } |
| 967 | |
| 968 | static void mhl_msm_disconnection(struct mhl_tx_ctrl *mhl_ctrl) |
| 969 | { |
| 970 | struct i2c_client *client = mhl_ctrl->i2c_handle; |
| 971 | |
| 972 | /* disabling Tx termination */ |
| 973 | MHL_SII_REG_NAME_WR(REG_MHLTX_CTL1, 0xD0); |
| 974 | switch_mode(mhl_ctrl, POWER_STATE_D3, true); |
| 975 | mhl_msc_clear(mhl_ctrl); |
| 976 | } |
| 977 | |
| 978 | static int mhl_msm_read_rgnd_int(struct mhl_tx_ctrl *mhl_ctrl) |
| 979 | { |
| 980 | uint8_t rgnd_imp; |
| 981 | struct i2c_client *client = mhl_ctrl->i2c_handle; |
| 982 | struct msm_hdmi_mhl_ops *hdmi_mhl_ops = mhl_ctrl->hdmi_mhl_ops; |
| 983 | unsigned long flags; |
| 984 | int rc; |
| 985 | |
| 986 | spin_lock_irqsave(&mhl_ctrl->lock, flags); |
| 987 | mhl_ctrl->tx_powered_off = false; |
| 988 | spin_unlock_irqrestore(&mhl_ctrl->lock, flags); |
| 989 | |
| 990 | /* DISC STATUS REG 2 */ |
| 991 | rgnd_imp = (mhl_i2c_reg_read(client, TX_PAGE_3, 0x001C) & |
| 992 | (BIT1 | BIT0)); |
| 993 | pr_debug("imp range read=%02X\n", (int)rgnd_imp); |
| 994 | |
| 995 | if (rgnd_impi == 0x02) { |
| 996 | pr_debug("%s: mhl sink\n", __func__); |
| 997 | if (hdmi_mhl_ops) { |
| 998 | rc = hdmi_mhl_ops->set_upstream_hpd( |
| 999 | mhl_ctrl->pdata->hdmi_pdev, 1); |
| 1000 | pr_debug("%s: hdmi set hpd %s\n", __func__, |
| 1001 | rc ? "failed" : "passed"); |
| 1002 | } |
| 1003 | mhl_ctrl->mhl_mode = 1; |
| 1004 | power_supply_changed(&mhl_ctrl->mhl_psy); |
| 1005 | if (mhl_ctrl->notify_usb_online) |
| 1006 | mhl_ctrl->notify_usb_online(mhl_ctrl->notify_ctx, 1); |
| 1007 | } else { |
| 1008 | pr_debug("%s: non-mhl sink\n", __func__); |
| 1009 | mhl_ctrl->mhl_mode = 0; |
| 1010 | switch_mode(mhl_ctrl, POWER_STATE_D3, true); |
| 1011 | } |
| 1012 | complete(&mhl_ctrl->rgnd_done); |
| 1013 | return mhl_ctrl->mhl_mode ? |
| 1014 | MHL_DISCOVERY_RESULT_MHL : MHL_DISCOVERY_RESULT_USB; |
| 1015 | } |
| 1016 | |
| 1017 | static void force_usb_switch_open(struct mhl_tx_ctrl *mhl_ctrl) |
| 1018 | { |
| 1019 | struct i2c_client *client = mhl_ctrl->i2c_handle; |
| 1020 | |
| 1021 | /*disable discovery*/ |
| 1022 | MHL_SII_REG_NAME_MOD(REG_DISC_CTRL1, BIT0, 0); |
| 1023 | /* force USB ID switch to open*/ |
| 1024 | MHL_SII_REG_NAME_MOD(REG_DISC_CTRL6, BIT6, BIT6); |
| 1025 | MHL_SII_REG_NAME_WR(REG_DISC_CTRL3, 0x86); |
| 1026 | /* force HPD to 0 when not in mhl mode. */ |
| 1027 | MHL_SII_REG_NAME_MOD(REG_INT_CTRL, BIT5 | BIT4, BIT4); |
| 1028 | } |
| 1029 | |
| 1030 | static void release_usb_switch_open(struct mhl_tx_ctrl *mhl_ctrl) |
| 1031 | { |
| 1032 | struct i2c_client *client = mhl_ctrl->i2c_handle; |
| 1033 | |
| 1034 | msleep(50); |
| 1035 | MHL_SII_REG_NAME_MOD(REG_DISC_CTRL6, BIT6, 0x00); |
| 1036 | MHL_SII_REG_NAME_MOD(REG_DISC_CTRL1, BIT0, BIT0); |
| 1037 | } |
| 1038 | |
| 1039 | static void scdt_st_chg(struct i2c_client *client) |
| 1040 | { |
| 1041 | uint8_t tmds_cstat; |
| 1042 | uint8_t mhl_fifo_status; |
| 1043 | |
| 1044 | /* tmds cstat */ |
| 1045 | tmds_cstat = MHL_SII_PAGE3_RD(0x0040); |
| 1046 | pr_debug("%s: tmds cstat: 0x%02x\n", __func__, |
| 1047 | tmds_cstat); |
| 1048 | |
| 1049 | if (!(tmds_cstat & BIT1)) |
| 1050 | return; |
| 1051 | |
| 1052 | mhl_fifo_status = MHL_SII_REG_NAME_RD(REG_INTR5); |
| 1053 | pr_debug("%s: mhl fifo st: 0x%02x\n", __func__, |
| 1054 | mhl_fifo_status); |
| 1055 | if (mhl_fifo_status & 0x0C) { |
| 1056 | MHL_SII_REG_NAME_WR(REG_INTR5, 0x0C); |
| 1057 | pr_debug("%s: mhl fifo rst\n", __func__); |
| 1058 | MHL_SII_REG_NAME_WR(REG_SRST, 0x94); |
| 1059 | MHL_SII_REG_NAME_WR(REG_SRST, 0x84); |
| 1060 | } |
| 1061 | } |
| 1062 | |
| 1063 | |
| 1064 | static int dev_detect_isr(struct mhl_tx_ctrl *mhl_ctrl) |
| 1065 | { |
| 1066 | uint8_t status, reg; |
| 1067 | struct i2c_client *client = mhl_ctrl->i2c_handle; |
| 1068 | |
| 1069 | /* INTR_STATUS4 */ |
| 1070 | status = MHL_SII_REG_NAME_RD(REG_INTR4); |
| 1071 | pr_debug("%s: reg int4 st=%02X\n", __func__, status); |
| 1072 | |
| 1073 | if ((status == 0x00) && |
| 1074 | (mhl_ctrl->cur_state == POWER_STATE_D3)) { |
| 1075 | pr_warn("%s: invalid intr\n", __func__); |
| 1076 | return 0; |
| 1077 | } |
| 1078 | |
| 1079 | if (status == 0xFF) { |
| 1080 | pr_warn("%s: invalid intr 0xff\n", __func__); |
| 1081 | MHL_SII_REG_NAME_WR(REG_INTR4, status); |
| 1082 | return 0; |
| 1083 | } |
| 1084 | |
| 1085 | if ((status & BIT0) && (mhl_ctrl->chip_rev_id < 1)) { |
| 1086 | pr_debug("%s: scdt intr\n", __func__); |
| 1087 | scdt_st_chg(client); |
| 1088 | } |
| 1089 | |
| 1090 | if (status & BIT1) |
| 1091 | pr_debug("mhl: int4 bit1 set\n"); |
| 1092 | |
| 1093 | /* mhl_est interrupt */ |
| 1094 | if (status & BIT2) { |
| 1095 | pr_debug("%s: mhl_est st=%02X\n", __func__, |
| 1096 | (int) status); |
| 1097 | mhl_msm_connection(mhl_ctrl); |
| 1098 | } else if (status & BIT3) { |
| 1099 | pr_debug("%s: uUSB-a type dev detct\n", __func__); |
| 1100 | power_supply_changed(&mhl_ctrl->mhl_psy); |
| 1101 | mhl_drive_hpd(mhl_ctrl, HPD_DOWN); |
| 1102 | return 0; |
| 1103 | } |
| 1104 | |
| 1105 | if (status & BIT5) { |
| 1106 | /* clr intr - reg int4 */ |
| 1107 | pr_debug("%s: mhl discon: int4 st=%02X\n", __func__, |
| 1108 | (int)status); |
| 1109 | mhl_ctrl->mhl_det_discon = true; |
| 1110 | |
| 1111 | reg = MHL_SII_REG_NAME_RD(REG_INTR4); |
| 1112 | MHL_SII_REG_NAME_WR(REG_INTR4, reg); |
| 1113 | mhl_msm_disconnection(mhl_ctrl); |
| 1114 | power_supply_changed(&mhl_ctrl->mhl_psy); |
| 1115 | if (mhl_ctrl->notify_usb_online) |
| 1116 | mhl_ctrl->notify_usb_online(mhl_ctrl->notify_ctx, 0); |
| 1117 | |
| 1118 | queue_work(mhl_ctrl->mhl_workq, &mhl_ctrl->mhl_intr_work); |
| 1119 | |
| 1120 | return 0; |
| 1121 | } |
| 1122 | |
| 1123 | if ((mhl_ctrl->cur_state != POWER_STATE_D0_NO_MHL) && |
| 1124 | (status & BIT6)) { |
| 1125 | /* rgnd rdy Intr */ |
| 1126 | pr_debug("%s: rgnd ready intr\n", __func__); |
| 1127 | switch_mode(mhl_ctrl, POWER_STATE_D0_NO_MHL, true); |
| 1128 | mhl_msm_read_rgnd_int(mhl_ctrl); |
| 1129 | } |
| 1130 | |
| 1131 | /* Can't succeed at these in D3 */ |
| 1132 | if ((mhl_ctrl->cur_state != POWER_STATE_D3) && |
| 1133 | (status & BIT4)) { |
| 1134 | /* cbus lockout interrupt? |
| 1135 | * Hardware detection mechanism figures that |
| 1136 | * CBUS line is latched and raises this intr |
| 1137 | * where we force usb switch open and release |
| 1138 | */ |
| 1139 | pr_warn("%s: cbus locked out!\n", __func__); |
| 1140 | force_usb_switch_open(mhl_ctrl); |
| 1141 | release_usb_switch_open(mhl_ctrl); |
| 1142 | } |
| 1143 | MHL_SII_REG_NAME_WR(REG_INTR4, status); |
| 1144 | return 0; |
| 1145 | } |
| 1146 | |
| 1147 | static void mhl_misc_isr(struct mhl_tx_ctrl *mhl_ctrl) |
| 1148 | { |
| 1149 | uint8_t intr_5_stat; |
| 1150 | struct i2c_client *client = mhl_ctrl->i2c_handle; |
| 1151 | |
| 1152 | /* |
| 1153 | * Clear INT 5 |
| 1154 | * INTR5 is related to FIFO underflow/overflow reset |
| 1155 | * which is handled in 8334 by auto FIFO reset |
| 1156 | */ |
| 1157 | intr_5_stat = MHL_SII_REG_NAME_RD(REG_INTR5); |
| 1158 | MHL_SII_REG_NAME_WR(REG_INTR5, intr_5_stat); |
| 1159 | } |
| 1160 | |
| 1161 | static void mhl_tx_down(struct mhl_tx_ctrl *mhl_ctrl) |
| 1162 | { |
| 1163 | struct i2c_client *client = mhl_ctrl->i2c_handle; |
| 1164 | unsigned long flags; |
| 1165 | uint8_t reg; |
| 1166 | |
| 1167 | switch_mode(mhl_ctrl, POWER_STATE_D3, true); |
| 1168 | |
| 1169 | reg = MHL_SII_REG_NAME_RD(REG_INTR1); |
| 1170 | MHL_SII_REG_NAME_WR(REG_INTR1, reg); |
| 1171 | |
| 1172 | reg = MHL_SII_REG_NAME_RD(REG_INTR4); |
| 1173 | MHL_SII_REG_NAME_WR(REG_INTR4, reg); |
| 1174 | |
| 1175 | /* disable INTR1 and INTR4 */ |
| 1176 | MHL_SII_REG_NAME_MOD(REG_INTR1_MASK, BIT6, 0x0); |
| 1177 | MHL_SII_REG_NAME_MOD(REG_INTR4_MASK, |
| 1178 | (BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6), 0x0); |
| 1179 | |
| 1180 | MHL_SII_PAGE1_MOD(0x003D, BIT0, 0x00); |
| 1181 | spin_lock_irqsave(&mhl_ctrl->lock, flags); |
| 1182 | mhl_ctrl->tx_powered_off = true; |
| 1183 | spin_unlock_irqrestore(&mhl_ctrl->lock, flags); |
| 1184 | pr_debug("%s: disabled\n", __func__); |
| 1185 | disable_irq_nosync(client->irq); |
| 1186 | } |
| 1187 | |
| 1188 | static void mhl_hpd_stat_isr(struct mhl_tx_ctrl *mhl_ctrl) |
| 1189 | { |
| 1190 | uint8_t intr_1_stat, cbus_stat, t; |
| 1191 | unsigned long flags; |
| 1192 | struct i2c_client *client = mhl_ctrl->i2c_handle; |
| 1193 | |
| 1194 | if (!is_mhl_powered(mhl_ctrl)) |
| 1195 | return; |
| 1196 | |
| 1197 | /* INTR STATUS 1 */ |
| 1198 | intr_1_stat = MHL_SII_PAGE0_RD(0x0071); |
| 1199 | |
| 1200 | if (!intr_1_stat) |
| 1201 | return; |
| 1202 | |
| 1203 | /* Clear interrupts */ |
| 1204 | MHL_SII_PAGE0_WR(0x0071, intr_1_stat); |
| 1205 | |
| 1206 | if (BIT6 & intr_1_stat) { |
| 1207 | /* |
| 1208 | * HPD status change event is pending |
| 1209 | * Read CBUS HPD status for this info |
| 1210 | * MSC REQ ABRT REASON |
| 1211 | */ |
| 1212 | cbus_stat = MHL_SII_CBUS_RD(0x0D); |
| 1213 | pr_debug("%s: cbus_stat=[0x%02x] cur_pwr=[%u]\n", |
| 1214 | __func__, cbus_stat, mhl_ctrl->cur_state); |
| 1215 | |
| 1216 | spin_lock_irqsave(&mhl_ctrl->lock, flags); |
| 1217 | t = mhl_ctrl->dwnstream_hpd; |
| 1218 | pr_debug("%s: %u: dwnstrm_hpd=0x%02x\n", |
| 1219 | __func__, __LINE__, mhl_ctrl->dwnstream_hpd); |
| 1220 | spin_unlock_irqrestore(&mhl_ctrl->lock, flags); |
| 1221 | |
| 1222 | if (BIT6 & (cbus_stat ^ t)) { |
| 1223 | u8 status = cbus_stat & BIT6; |
| 1224 | |
| 1225 | mhl_drive_hpd(mhl_ctrl, status ? HPD_UP : HPD_DOWN); |
| 1226 | if (!status && mhl_ctrl->mhl_det_discon) { |
| 1227 | pr_debug("%s:%u: power_down\n", |
| 1228 | __func__, __LINE__); |
| 1229 | mhl_tx_down(mhl_ctrl); |
| 1230 | } |
| 1231 | spin_lock_irqsave(&mhl_ctrl->lock, flags); |
| 1232 | mhl_ctrl->dwnstream_hpd = cbus_stat; |
| 1233 | pr_debug("%s: %u: dwnstrm_hpd=0x%02x\n", |
| 1234 | __func__, __LINE__, mhl_ctrl->dwnstream_hpd); |
| 1235 | spin_unlock_irqrestore(&mhl_ctrl->lock, flags); |
| 1236 | mhl_ctrl->mhl_det_discon = false; |
| 1237 | } |
| 1238 | } |
| 1239 | } |
| 1240 | |
| 1241 | static void mhl_sii_cbus_process_errors(struct i2c_client *client, |
| 1242 | u8 int_status) |
| 1243 | { |
| 1244 | u8 abort_reason = 0; |
| 1245 | |
| 1246 | if (int_status & BIT2) { |
| 1247 | abort_reason = MHL_SII_REG_NAME_RD(REG_DDC_ABORT_REASON); |
| 1248 | pr_debug("%s: CBUS DDC Abort Reason(0x%02x)\n", |
| 1249 | __func__, abort_reason); |
| 1250 | } |
| 1251 | if (int_status & BIT5) { |
| 1252 | abort_reason = MHL_SII_REG_NAME_RD(REG_PRI_XFR_ABORT_REASON); |
| 1253 | pr_debug("%s: CBUS MSC Requestor Abort Reason(0x%02x)\n", |
| 1254 | __func__, abort_reason); |
| 1255 | MHL_SII_REG_NAME_WR(REG_PRI_XFR_ABORT_REASON, 0xFF); |
| 1256 | } |
| 1257 | if (int_status & BIT6) { |
| 1258 | abort_reason = MHL_SII_REG_NAME_RD( |
| 1259 | REG_CBUS_PRI_FWR_ABORT_REASON); |
| 1260 | pr_debug("%s: CBUS MSC Responder Abort Reason(0x%02x)\n", |
| 1261 | __func__, abort_reason); |
| 1262 | MHL_SII_REG_NAME_WR(REG_CBUS_PRI_FWR_ABORT_REASON, 0xFF); |
| 1263 | } |
| 1264 | } |
| 1265 | |
| 1266 | int mhl_send_msc_command(struct mhl_tx_ctrl *mhl_ctrl, |
| 1267 | struct msc_command_struct *req) |
| 1268 | { |
| 1269 | int timeout; |
| 1270 | u8 start_bit = 0x00; |
| 1271 | u8 *burst_data; |
| 1272 | int i; |
| 1273 | struct i2c_client *client = mhl_ctrl->i2c_handle; |
| 1274 | |
| 1275 | if (mhl_ctrl->cur_state != POWER_STATE_D0_MHL) { |
| 1276 | pr_debug("%s: power_state:%02x CBUS(0x0A):%02x\n", |
| 1277 | __func__, |
| 1278 | mhl_ctrl->cur_state, |
| 1279 | MHL_SII_REG_NAME_RD(REG_CBUS_BUS_STATUS)); |
| 1280 | return -EFAULT; |
| 1281 | } |
| 1282 | |
| 1283 | if (!req) |
| 1284 | return -EFAULT; |
| 1285 | |
| 1286 | pr_debug("%s: command=0x%02x offset=0x%02x %02x %02x", |
| 1287 | __func__, |
| 1288 | req->command, |
| 1289 | req->offset, |
| 1290 | req->payload.data[0], |
| 1291 | req->payload.data[1]); |
| 1292 | |
| 1293 | /* REG_CBUS_PRI_ADDR_CMD = REQ CBUS CMD or OFFSET */ |
| 1294 | MHL_SII_REG_NAME_WR(REG_CBUS_PRI_ADDR_CMD, req->offset); |
| 1295 | MHL_SII_REG_NAME_WR(REG_CBUS_PRI_WR_DATA_1ST, |
| 1296 | req->payload.data[0]); |
| 1297 | |
| 1298 | switch (req->command) { |
| 1299 | case MHL_SET_INT: |
| 1300 | case MHL_WRITE_STAT: |
| 1301 | start_bit = MSC_START_BIT_WRITE_REG; |
| 1302 | break; |
| 1303 | case MHL_READ_DEVCAP: |
| 1304 | start_bit = MSC_START_BIT_READ_REG; |
| 1305 | break; |
| 1306 | case MHL_GET_STATE: |
| 1307 | case MHL_GET_VENDOR_ID: |
| 1308 | case MHL_SET_HPD: |
| 1309 | case MHL_CLR_HPD: |
| 1310 | case MHL_GET_SC1_ERRORCODE: |
| 1311 | case MHL_GET_DDC_ERRORCODE: |
| 1312 | case MHL_GET_MSC_ERRORCODE: |
| 1313 | case MHL_GET_SC3_ERRORCODE: |
| 1314 | start_bit = MSC_START_BIT_MSC_CMD; |
| 1315 | MHL_SII_REG_NAME_WR(REG_CBUS_PRI_ADDR_CMD, req->command); |
| 1316 | break; |
| 1317 | case MHL_MSC_MSG: |
| 1318 | start_bit = MSC_START_BIT_VS_CMD; |
| 1319 | MHL_SII_REG_NAME_WR(REG_CBUS_PRI_WR_DATA_2ND, |
| 1320 | req->payload.data[1]); |
| 1321 | MHL_SII_REG_NAME_WR(REG_CBUS_PRI_ADDR_CMD, req->command); |
| 1322 | break; |
| 1323 | case MHL_WRITE_BURST: |
| 1324 | start_bit = MSC_START_BIT_WRITE_BURST; |
| 1325 | MHL_SII_REG_NAME_WR(REG_MSC_WRITE_BURST_LEN, req->length - 1); |
| 1326 | if (!(req->payload.burst_data)) { |
| 1327 | pr_err("%s: burst data is null!\n", __func__); |
| 1328 | goto cbus_send_fail; |
| 1329 | } |
| 1330 | burst_data = req->payload.burst_data; |
| 1331 | for (i = 0; i < req->length; i++, burst_data++) |
| 1332 | MHL_SII_REG_NAME_WR(REG_CBUS_SCRATCHPAD_0 + i, |
| 1333 | *burst_data); |
| 1334 | break; |
| 1335 | default: |
| 1336 | pr_err("%s: unknown command! (%02x)\n", |
| 1337 | __func__, req->command); |
| 1338 | goto cbus_send_fail; |
| 1339 | } |
| 1340 | |
| 1341 | reinit_completion(&mhl_ctrl->msc_cmd_done); |
| 1342 | MHL_SII_REG_NAME_WR(REG_CBUS_PRI_START, start_bit); |
| 1343 | timeout = wait_for_completion_timeout |
| 1344 | (&mhl_ctrl->msc_cmd_done, msecs_to_jiffies(T_ABORT_NEXT)); |
| 1345 | if (!timeout) { |
| 1346 | pr_err("%s: cbus_command_send timed out!\n", __func__); |
| 1347 | goto cbus_send_fail; |
| 1348 | } |
| 1349 | |
| 1350 | switch (req->command) { |
| 1351 | case MHL_READ_DEVCAP: |
| 1352 | req->retval = MHL_SII_REG_NAME_RD(REG_CBUS_PRI_RD_DATA_1ST); |
| 1353 | break; |
| 1354 | case MHL_MSC_MSG: |
| 1355 | /* check if MSC_MSG NACKed */ |
| 1356 | if (MHL_SII_REG_NAME_RD(REG_MSC_WRITE_BURST_LEN) & BIT6) |
| 1357 | return -EAGAIN; |
| 1358 | default: |
| 1359 | req->retval = 0; |
| 1360 | break; |
| 1361 | } |
| 1362 | mhl_msc_command_done(mhl_ctrl, req); |
| 1363 | pr_debug("%s: msc cmd done\n", __func__); |
| 1364 | return 0; |
| 1365 | |
| 1366 | cbus_send_fail: |
| 1367 | return -EFAULT; |
| 1368 | } |
| 1369 | |
| 1370 | /* read scratchpad */ |
| 1371 | void mhl_read_scratchpad(struct mhl_tx_ctrl *mhl_ctrl) |
| 1372 | { |
| 1373 | struct i2c_client *client = mhl_ctrl->i2c_handle; |
| 1374 | int i; |
| 1375 | |
| 1376 | for (i = 0; i < MHL_SCRATCHPAD_SIZE; i++) { |
| 1377 | mhl_ctrl->scrpd.data[i] = MHL_SII_REG_NAME_RD( |
| 1378 | REG_CBUS_SCRATCHPAD_0 + i); |
| 1379 | } |
| 1380 | } |
| 1381 | |
| 1382 | static void mhl_cbus_isr(struct mhl_tx_ctrl *mhl_ctrl) |
| 1383 | { |
| 1384 | uint8_t regval; |
| 1385 | int req_done = 0; |
| 1386 | uint8_t sub_cmd = 0x0; |
| 1387 | uint8_t cmd_data = 0x0; |
| 1388 | int msc_msg_recved = 0; |
| 1389 | int rc = -1; |
| 1390 | unsigned long flags; |
| 1391 | struct i2c_client *client = mhl_ctrl->i2c_handle; |
| 1392 | |
| 1393 | regval = MHL_SII_REG_NAME_RD(REG_CBUS_INTR_STATUS); |
| 1394 | if (regval == 0xff) |
| 1395 | return; |
| 1396 | |
| 1397 | if (regval) |
| 1398 | MHL_SII_REG_NAME_WR(REG_CBUS_INTR_STATUS, regval); |
| 1399 | |
| 1400 | pr_debug("%s: CBUS_INT = %02x\n", __func__, regval); |
| 1401 | |
| 1402 | /* MSC_MSG (RCP/RAP) */ |
| 1403 | if (regval & BIT3) { |
| 1404 | sub_cmd = MHL_SII_REG_NAME_RD(REG_CBUS_PRI_VS_CMD); |
| 1405 | cmd_data = MHL_SII_REG_NAME_RD(REG_CBUS_PRI_VS_DATA); |
| 1406 | msc_msg_recved = 1; |
| 1407 | } |
| 1408 | /* MSC_MT_ABRT/MSC_MR_ABRT/DDC_ABORT */ |
| 1409 | if (regval & (BIT6 | BIT5 | BIT2)) |
| 1410 | mhl_sii_cbus_process_errors(client, regval); |
| 1411 | |
| 1412 | /* MSC_REQ_DONE */ |
| 1413 | if (regval & BIT4) |
| 1414 | req_done = 1; |
| 1415 | |
| 1416 | /* look for interrupts on CBUS_MSC_INT2 */ |
| 1417 | regval = MHL_SII_REG_NAME_RD(REG_CBUS_MSC_INT2_STATUS); |
| 1418 | |
| 1419 | /* clear all interrupts */ |
| 1420 | if (regval) |
| 1421 | MHL_SII_REG_NAME_WR(REG_CBUS_MSC_INT2_STATUS, regval); |
| 1422 | |
| 1423 | pr_debug("%s: CBUS_MSC_INT2 = %02x\n", __func__, regval); |
| 1424 | |
| 1425 | /* received SET_INT */ |
| 1426 | if (regval & BIT2) { |
| 1427 | uint8_t intr; |
| 1428 | |
| 1429 | intr = MHL_SII_REG_NAME_RD(REG_CBUS_SET_INT_0); |
| 1430 | MHL_SII_REG_NAME_WR(REG_CBUS_SET_INT_0, intr); |
| 1431 | mhl_msc_recv_set_int(mhl_ctrl, 0, intr); |
| 1432 | if (intr & MHL_INT_DCAP_CHG) { |
| 1433 | /* No need to go to low power mode */ |
| 1434 | spin_lock_irqsave(&mhl_ctrl->lock, flags); |
| 1435 | mhl_ctrl->dwnstream_hpd = 0x00; |
| 1436 | pr_debug("%s: %u: dwnstrm_hpd=0x%02x\n", |
| 1437 | __func__, __LINE__, mhl_ctrl->dwnstream_hpd); |
| 1438 | spin_unlock_irqrestore(&mhl_ctrl->lock, flags); |
| 1439 | } |
| 1440 | |
| 1441 | pr_debug("%s: MHL_INT_0 = %02x\n", __func__, intr); |
| 1442 | intr = MHL_SII_REG_NAME_RD(REG_CBUS_SET_INT_1); |
| 1443 | MHL_SII_REG_NAME_WR(REG_CBUS_SET_INT_1, intr); |
| 1444 | mhl_msc_recv_set_int(mhl_ctrl, 1, intr); |
| 1445 | |
| 1446 | pr_debug("%s: MHL_INT_1 = %02x\n", __func__, intr); |
| 1447 | MHL_SII_REG_NAME_WR(REG_CBUS_SET_INT_2, 0xFF); |
| 1448 | MHL_SII_REG_NAME_WR(REG_CBUS_SET_INT_3, 0xFF); |
| 1449 | } |
| 1450 | |
| 1451 | /* received WRITE_STAT */ |
| 1452 | if (regval & BIT3) { |
| 1453 | uint8_t stat; |
| 1454 | |
| 1455 | stat = MHL_SII_REG_NAME_RD(REG_CBUS_WRITE_STAT_0); |
| 1456 | mhl_msc_recv_write_stat(mhl_ctrl, 0, stat); |
| 1457 | |
| 1458 | pr_debug("%s: MHL_STATUS_0 = %02x\n", __func__, stat); |
| 1459 | stat = MHL_SII_REG_NAME_RD(REG_CBUS_WRITE_STAT_1); |
| 1460 | mhl_msc_recv_write_stat(mhl_ctrl, 1, stat); |
| 1461 | pr_debug("%s: MHL_STATUS_1 = %02x\n", __func__, stat); |
| 1462 | |
| 1463 | MHL_SII_REG_NAME_WR(REG_CBUS_WRITE_STAT_0, 0xFF); |
| 1464 | MHL_SII_REG_NAME_WR(REG_CBUS_WRITE_STAT_1, 0xFF); |
| 1465 | MHL_SII_REG_NAME_WR(REG_CBUS_WRITE_STAT_2, 0xFF); |
| 1466 | MHL_SII_REG_NAME_WR(REG_CBUS_WRITE_STAT_3, 0xFF); |
| 1467 | } |
| 1468 | |
| 1469 | /* received MSC_MSG */ |
| 1470 | if (msc_msg_recved) { |
| 1471 | /*mhl msc recv msc msg*/ |
| 1472 | rc = mhl_msc_recv_msc_msg(mhl_ctrl, sub_cmd, cmd_data); |
| 1473 | if (rc) |
| 1474 | pr_err("MHL: mhl msc recv msc msg failed(%d)!\n", rc); |
| 1475 | } |
| 1476 | /* complete last command */ |
| 1477 | if (req_done) |
| 1478 | complete_all(&mhl_ctrl->msc_cmd_done); |
| 1479 | |
| 1480 | } |
| 1481 | |
| 1482 | static irqreturn_t mhl_tx_isr(int irq, void *data) |
| 1483 | { |
| 1484 | int rc; |
| 1485 | struct mhl_tx_ctrl *mhl_ctrl = (struct mhl_tx_ctrl *)data; |
| 1486 | unsigned long flags; |
| 1487 | |
| 1488 | pr_debug("%s: Getting Interrupts\n", __func__); |
| 1489 | |
| 1490 | spin_lock_irqsave(&mhl_ctrl->lock, flags); |
| 1491 | if (mhl_ctrl->tx_powered_off) { |
| 1492 | pr_warn("%s: powered off\n", __func__); |
| 1493 | spin_unlock_irqrestore(&mhl_ctrl->lock, flags); |
| 1494 | return IRQ_HANDLED; |
| 1495 | } |
| 1496 | spin_unlock_irqrestore(&mhl_ctrl->lock, flags); |
| 1497 | |
| 1498 | /* |
| 1499 | * Check RGND, MHL_EST, CBUS_LOCKOUT, SCDT |
| 1500 | * interrupts. In D3, we get only RGND |
| 1501 | */ |
| 1502 | rc = dev_detect_isr(mhl_ctrl); |
| 1503 | if (rc) |
| 1504 | pr_debug("%s: dev_detect_isr rc=[%d]\n", __func__, rc); |
| 1505 | |
| 1506 | pr_debug("%s: cur pwr state is [0x%x]\n", |
| 1507 | __func__, mhl_ctrl->cur_state); |
| 1508 | |
| 1509 | /* |
| 1510 | * If dev_detect_isr() didn't move the tx to D3 |
| 1511 | * on disconnect, continue to check other |
| 1512 | * interrupt sources. |
| 1513 | */ |
| 1514 | mhl_misc_isr(mhl_ctrl); |
| 1515 | |
| 1516 | /* |
| 1517 | * Check for any peer messages for DCAP_CHG, MSC etc |
| 1518 | * Dispatch to have the CBUS module working only |
| 1519 | * once connected. |
| 1520 | */ |
| 1521 | mhl_cbus_isr(mhl_ctrl); |
| 1522 | mhl_hpd_stat_isr(mhl_ctrl); |
| 1523 | |
| 1524 | return IRQ_HANDLED; |
| 1525 | } |
| 1526 | |
| 1527 | |
| 1528 | static int mhl_sii_reg_config(struct i2c_client *client, bool enable) |
| 1529 | { |
| 1530 | static struct regulator *reg_8941_l24; |
| 1531 | static struct regulator *reg_8941_l02; |
| 1532 | static struct regulator *reg_8941_smps3a; |
| 1533 | static struct regulator *reg_8941_vdda; |
| 1534 | int rc = -EINVAL; |
| 1535 | |
| 1536 | pr_debug("%s\n", __func__); |
| 1537 | |
| 1538 | if (!enable) { |
| 1539 | if (reg_8941_vdda) { |
| 1540 | regulator_disable(reg_8941_vdda); |
| 1541 | regulator_put(reg_8941_vdda); |
| 1542 | reg_8941_vdda = NULL; |
| 1543 | } |
| 1544 | |
| 1545 | if (reg_8941_smps3a) { |
| 1546 | regulator_disable(reg_8941_smps3a); |
| 1547 | regulator_put(reg_8941_smps3a); |
| 1548 | reg_8941_smps3a = NULL; |
| 1549 | } |
| 1550 | |
| 1551 | if (reg_8941_l02) { |
| 1552 | regulator_disable(reg_8941_l02); |
| 1553 | regulator_put(reg_8941_l02); |
| 1554 | reg_8941_l02 = NULL; |
| 1555 | } |
| 1556 | |
| 1557 | if (reg_8941_l24) { |
| 1558 | regulator_disable(reg_8941_l24); |
| 1559 | regulator_put(reg_8941_l24); |
| 1560 | reg_8941_l24 = NULL; |
| 1561 | } |
| 1562 | return 0; |
| 1563 | } |
| 1564 | |
| 1565 | if (!reg_8941_l24) { |
| 1566 | reg_8941_l24 = regulator_get(&client->dev, |
| 1567 | "avcc_18"); |
| 1568 | if (IS_ERR(reg_8941_l24)) { |
| 1569 | pr_err("could not get 8941 l24, rc = %ld\n", |
| 1570 | PTR_ERR(reg_8941_l24)); |
| 1571 | return -ENODEV; |
| 1572 | } |
| 1573 | if (enable) |
| 1574 | rc = regulator_enable(reg_8941_l24); |
| 1575 | else |
| 1576 | rc = regulator_disable(reg_8941_l24); |
| 1577 | if (rc) { |
| 1578 | pr_err("'%s' regulator config[%u] failed, rc=%d\n", |
| 1579 | "avcc_1.8V", enable, rc); |
| 1580 | goto l24_fail; |
| 1581 | } else { |
| 1582 | pr_debug("%s: vreg L24 %s\n", |
| 1583 | __func__, (enable ? "enabled" : "disabled")); |
| 1584 | } |
| 1585 | } |
| 1586 | |
| 1587 | if (!reg_8941_l02) { |
| 1588 | reg_8941_l02 = regulator_get(&client->dev, |
| 1589 | "avcc_12"); |
| 1590 | if (IS_ERR(reg_8941_l02)) { |
| 1591 | pr_err("could not get reg_8941_l02, rc = %ld\n", |
| 1592 | PTR_ERR(reg_8941_l02)); |
| 1593 | goto l24_fail; |
| 1594 | } |
| 1595 | if (enable) |
| 1596 | rc = regulator_enable(reg_8941_l02); |
| 1597 | else |
| 1598 | rc = regulator_disable(reg_8941_l02); |
| 1599 | if (rc) { |
| 1600 | pr_debug("'%s' regulator configure[%u] failed, rc=%d\n", |
| 1601 | "avcc_1.2V", enable, rc); |
| 1602 | goto l02_fail; |
| 1603 | } else { |
| 1604 | pr_debug("%s: vreg L02 %s\n", |
| 1605 | __func__, (enable ? "enabled" : "disabled")); |
| 1606 | } |
| 1607 | } |
| 1608 | |
| 1609 | if (!reg_8941_smps3a) { |
| 1610 | reg_8941_smps3a = regulator_get(&client->dev, |
| 1611 | "smps3a"); |
| 1612 | if (IS_ERR(reg_8941_smps3a)) { |
| 1613 | pr_err("could not get vreg smps3a, rc = %ld\n", |
| 1614 | PTR_ERR(reg_8941_smps3a)); |
| 1615 | goto l02_fail; |
| 1616 | } |
| 1617 | if (enable) |
| 1618 | rc = regulator_enable(reg_8941_smps3a); |
| 1619 | else |
| 1620 | rc = regulator_disable(reg_8941_smps3a); |
| 1621 | if (rc) { |
| 1622 | pr_err("'%s' regulator config[%u] failed, rc=%d\n", |
| 1623 | "SMPS3A", enable, rc); |
| 1624 | goto smps3a_fail; |
| 1625 | } else { |
| 1626 | pr_debug("%s: vreg SMPS3A %s\n", |
| 1627 | __func__, (enable ? "enabled" : "disabled")); |
| 1628 | } |
| 1629 | } |
| 1630 | |
| 1631 | if (!reg_8941_vdda) { |
| 1632 | reg_8941_vdda = regulator_get(&client->dev, |
| 1633 | "vdda"); |
| 1634 | if (IS_ERR(reg_8941_vdda)) { |
| 1635 | pr_err("could not get vreg vdda, rc = %ld\n", |
| 1636 | PTR_ERR(reg_8941_vdda)); |
| 1637 | goto smps3a_fail; |
| 1638 | } |
| 1639 | if (enable) |
| 1640 | rc = regulator_enable(reg_8941_vdda); |
| 1641 | else |
| 1642 | rc = regulator_disable(reg_8941_vdda); |
| 1643 | if (rc) { |
| 1644 | pr_err("'%s' regulator config[%u] failed, rc=%d\n", |
| 1645 | "VDDA", enable, rc); |
| 1646 | goto vdda_fail; |
| 1647 | } else { |
| 1648 | pr_debug("%s: vreg VDDA %s\n", |
| 1649 | __func__, (enable ? "enabled" : "disabled")); |
| 1650 | } |
| 1651 | } |
| 1652 | |
| 1653 | return rc; |
| 1654 | |
| 1655 | vdda_fail: |
| 1656 | regulator_disable(reg_8941_vdda); |
| 1657 | regulator_put(reg_8941_vdda); |
| 1658 | smps3a_fail: |
| 1659 | regulator_disable(reg_8941_smps3a); |
| 1660 | regulator_put(reg_8941_smps3a); |
| 1661 | l02_fail: |
| 1662 | regulator_disable(reg_8941_l02); |
| 1663 | regulator_put(reg_8941_l02); |
| 1664 | l24_fail: |
| 1665 | regulator_disable(reg_8941_l24); |
| 1666 | regulator_put(reg_8941_l24); |
| 1667 | |
| 1668 | return -EINVAL; |
| 1669 | } |
| 1670 | |
| 1671 | |
| 1672 | static int mhl_vreg_config(struct mhl_tx_ctrl *mhl_ctrl, uint8_t on) |
| 1673 | { |
| 1674 | int ret; |
| 1675 | struct i2c_client *client = mhl_ctrl->i2c_handle; |
| 1676 | int pwr_gpio = mhl_ctrl->pdata->gpios[MHL_TX_PMIC_PWR_GPIO]->gpio; |
| 1677 | |
| 1678 | pr_debug("%s\n", __func__); |
| 1679 | if (on) { |
| 1680 | ret = gpio_request(pwr_gpio, |
| 1681 | mhl_ctrl->pdata->gpios[MHL_TX_PMIC_PWR_GPIO]->gpio_name); |
| 1682 | if (ret < 0) { |
| 1683 | pr_err("%s: mhl pwr gpio req failed: %d\n", |
| 1684 | __func__, ret); |
| 1685 | return ret; |
| 1686 | } |
| 1687 | ret = gpio_direction_output(pwr_gpio, 1); |
| 1688 | if (ret < 0) { |
| 1689 | pr_err("%s: set gpio MHL_PWR_EN dircn failed: %d\n", |
| 1690 | __func__, ret); |
| 1691 | goto vreg_config_failed; |
| 1692 | } |
| 1693 | |
| 1694 | ret = mhl_sii_reg_config(client, true); |
| 1695 | if (ret) { |
| 1696 | pr_err("%s: regulator enable failed\n", __func__); |
| 1697 | goto vreg_config_failed; |
| 1698 | } |
| 1699 | pr_debug("%s: mhl sii power on successful\n", __func__); |
| 1700 | } else { |
| 1701 | pr_warn("%s: turning off pwr controls\n", __func__); |
| 1702 | mhl_sii_reg_config(client, false); |
| 1703 | gpio_free(pwr_gpio); |
| 1704 | } |
| 1705 | pr_debug("%s: successful\n", __func__); |
| 1706 | return 0; |
| 1707 | vreg_config_failed: |
| 1708 | gpio_free(pwr_gpio); |
| 1709 | return -EINVAL; |
| 1710 | } |
| 1711 | |
| 1712 | /* |
| 1713 | * Request for GPIO allocations |
| 1714 | * Set appropriate GPIO directions |
| 1715 | */ |
| 1716 | static int mhl_gpio_config(struct mhl_tx_ctrl *mhl_ctrl, int on) |
| 1717 | { |
| 1718 | int ret; |
| 1719 | struct dss_gpio *temp_reset_gpio, *temp_intr_gpio; |
| 1720 | |
| 1721 | /* caused too many line spills */ |
| 1722 | temp_reset_gpio = mhl_ctrl->pdata->gpios[MHL_TX_RESET_GPIO]; |
| 1723 | temp_intr_gpio = mhl_ctrl->pdata->gpios[MHL_TX_INTR_GPIO]; |
| 1724 | |
| 1725 | if (on) { |
| 1726 | if (gpio_is_valid(temp_reset_gpio->gpio)) { |
| 1727 | ret = gpio_request(temp_reset_gpio->gpio, |
| 1728 | temp_reset_gpio->gpio_name); |
| 1729 | if (ret < 0) { |
| 1730 | pr_err("%s:rst_gpio=[%d] req failed:%d\n", |
| 1731 | __func__, temp_reset_gpio->gpio, ret); |
| 1732 | return -EBUSY; |
| 1733 | } |
| 1734 | ret = gpio_direction_output(temp_reset_gpio->gpio, 0); |
| 1735 | if (ret < 0) { |
| 1736 | pr_err("%s: set dirn rst failed: %d\n", |
| 1737 | __func__, ret); |
| 1738 | return -EBUSY; |
| 1739 | } |
| 1740 | } |
| 1741 | if (gpio_is_valid(temp_intr_gpio->gpio)) { |
| 1742 | ret = gpio_request(temp_intr_gpio->gpio, |
| 1743 | temp_intr_gpio->gpio_name); |
| 1744 | if (ret < 0) { |
| 1745 | pr_err("%s: intr_gpio req failed: %d\n", |
| 1746 | __func__, ret); |
| 1747 | return -EBUSY; |
| 1748 | } |
| 1749 | ret = gpio_direction_input(temp_intr_gpio->gpio); |
| 1750 | if (ret < 0) { |
| 1751 | pr_err("%s: set dirn intr failed: %d\n", |
| 1752 | __func__, ret); |
| 1753 | return -EBUSY; |
| 1754 | } |
| 1755 | mhl_ctrl->i2c_handle->irq = gpio_to_irq( |
| 1756 | temp_intr_gpio->gpio); |
| 1757 | pr_debug("%s: gpio_to_irq=%d\n", |
| 1758 | __func__, mhl_ctrl->i2c_handle->irq); |
| 1759 | } |
| 1760 | } else { |
| 1761 | pr_warn("%s: freeing gpios\n", __func__); |
| 1762 | gpio_free(temp_intr_gpio->gpio); |
| 1763 | gpio_free(temp_reset_gpio->gpio); |
| 1764 | } |
| 1765 | pr_debug("%s: successful\n", __func__); |
| 1766 | return 0; |
| 1767 | } |
| 1768 | |
| 1769 | static int mhl_i2c_probe(struct i2c_client *client, |
| 1770 | const struct i2c_device_id *id) |
| 1771 | { |
| 1772 | int rc = 0; |
| 1773 | struct mhl_tx_platform_data *pdata = NULL; |
| 1774 | struct mhl_tx_ctrl *mhl_ctrl; |
| 1775 | struct usb_ext_notification *mhl_info = NULL; |
| 1776 | struct msm_hdmi_mhl_ops *hdmi_mhl_ops = NULL; |
| 1777 | |
| 1778 | mhl_ctrl = devm_kzalloc(&client->dev, sizeof(*mhl_ctrl), GFP_KERNEL); |
| 1779 | if (!mhl_ctrl) { |
| 1780 | rc = -ENOMEM; |
| 1781 | goto failed_no_mem; |
| 1782 | } |
| 1783 | |
| 1784 | if (client->dev.of_node) { |
| 1785 | pdata = devm_kzalloc(&client->dev, |
| 1786 | sizeof(struct mhl_tx_platform_data), GFP_KERNEL); |
| 1787 | if (!pdata) { |
| 1788 | rc = -ENOMEM; |
| 1789 | goto failed_no_mem; |
| 1790 | } |
| 1791 | |
| 1792 | rc = mhl_tx_get_dt_data(&client->dev, pdata); |
| 1793 | if (rc) { |
| 1794 | pr_err("%s: FAILED: parsing device tree data; rc=%d\n", |
| 1795 | __func__, rc); |
| 1796 | goto failed_dt_data; |
| 1797 | } |
| 1798 | mhl_ctrl->i2c_handle = client; |
| 1799 | mhl_ctrl->pdata = pdata; |
| 1800 | i2c_set_clientdata(client, mhl_ctrl); |
| 1801 | } |
| 1802 | |
| 1803 | /* |
| 1804 | * Other initializations |
| 1805 | * such tx specific |
| 1806 | */ |
| 1807 | mhl_ctrl->disc_enabled = false; |
| 1808 | INIT_WORK(&mhl_ctrl->mhl_msc_send_work, mhl_msc_send_work); |
| 1809 | mhl_ctrl->cur_state = POWER_STATE_D0_MHL; |
| 1810 | INIT_LIST_HEAD(&mhl_ctrl->list_cmd); |
| 1811 | init_completion(&mhl_ctrl->msc_cmd_done); |
| 1812 | spin_lock_init(&mhl_ctrl->lock); |
| 1813 | mhl_ctrl->msc_send_workqueue = create_singlethread_workqueue |
| 1814 | ("mhl_msc_cmd_queue"); |
| 1815 | mhl_ctrl->mhl_workq = create_singlethread_workqueue("mhl_workq"); |
| 1816 | |
| 1817 | INIT_WORK(&mhl_ctrl->mhl_intr_work, mhl_sii_disc_intr_work); |
| 1818 | |
| 1819 | mhl_ctrl->input = input_allocate_device(); |
| 1820 | if (mhl_ctrl->input) { |
| 1821 | int i; |
| 1822 | struct input_dev *input = mhl_ctrl->input; |
| 1823 | |
| 1824 | mhl_ctrl->rcp_key_code_tbl = vmalloc( |
| 1825 | sizeof(support_rcp_key_code_tbl)); |
| 1826 | if (!mhl_ctrl->rcp_key_code_tbl) |
| 1827 | return -ENOMEM; |
| 1828 | |
| 1829 | mhl_ctrl->rcp_key_code_tbl_len = sizeof( |
| 1830 | support_rcp_key_code_tbl); |
| 1831 | memcpy(mhl_ctrl->rcp_key_code_tbl, |
| 1832 | &support_rcp_key_code_tbl[0], |
| 1833 | mhl_ctrl->rcp_key_code_tbl_len); |
| 1834 | |
| 1835 | input->phys = "cbus/input0"; |
| 1836 | input->id.bustype = BUS_VIRTUAL; |
| 1837 | input->id.vendor = 0x1095; |
| 1838 | input->id.product = 0x8334; |
| 1839 | input->id.version = 0xA; |
| 1840 | |
| 1841 | input->name = "mhl-rcp"; |
| 1842 | |
| 1843 | input->keycode = support_rcp_key_code_tbl; |
| 1844 | input->keycodesize = sizeof(u16); |
| 1845 | input->keycodemax = ARRAY_SIZE(support_rcp_key_code_tbl); |
| 1846 | |
| 1847 | input->evbit[0] = EV_KEY; |
| 1848 | for (i = 0; i < ARRAY_SIZE(support_rcp_key_code_tbl); i++) { |
| 1849 | if (support_rcp_key_code_tbl[i] > 1) |
| 1850 | input_set_capability(input, EV_KEY, |
| 1851 | support_rcp_key_code_tbl[i]); |
| 1852 | } |
| 1853 | |
| 1854 | if (input_register_device(input) < 0) { |
| 1855 | pr_warn("%s: failed to register input device\n", |
| 1856 | __func__); |
| 1857 | input_free_device(input); |
| 1858 | mhl_ctrl->input = NULL; |
| 1859 | } |
| 1860 | } |
| 1861 | |
| 1862 | mhl_ctrl->dwnstream_hpd = 0; |
| 1863 | mhl_ctrl->tx_powered_off = false; |
| 1864 | |
| 1865 | |
| 1866 | init_completion(&mhl_ctrl->rgnd_done); |
| 1867 | |
| 1868 | |
| 1869 | mhl_ctrl->mhl_psy.name = "ext-vbus"; |
| 1870 | mhl_ctrl->mhl_psy.type = POWER_SUPPLY_TYPE_USB_DCP; |
| 1871 | mhl_ctrl->mhl_psy.supplied_to = mhl_pm_power_supplied_to; |
| 1872 | mhl_ctrl->mhl_psy.num_supplicants = ARRAY_SIZE( |
| 1873 | mhl_pm_power_supplied_to); |
| 1874 | mhl_ctrl->mhl_psy.properties = mhl_pm_power_props; |
| 1875 | mhl_ctrl->mhl_psy.num_properties = ARRAY_SIZE(mhl_pm_power_props); |
| 1876 | mhl_ctrl->mhl_psy.get_property = mhl_power_get_property; |
| 1877 | mhl_ctrl->mhl_psy.set_property = mhl_power_set_property; |
| 1878 | |
| 1879 | rc = power_supply_register(&client->dev, &mhl_ctrl->mhl_psy); |
| 1880 | if (rc < 0) { |
| 1881 | dev_err(&client->dev, "%s:power_supply_register ext_vbus_psy failed\n", |
| 1882 | __func__); |
| 1883 | goto failed_probe; |
| 1884 | } |
| 1885 | |
| 1886 | hdmi_mhl_ops = devm_kzalloc(&client->dev, |
| 1887 | sizeof(struct msm_hdmi_mhl_ops), |
| 1888 | GFP_KERNEL); |
| 1889 | if (!hdmi_mhl_ops) { |
| 1890 | pr_err("%s: alloc hdmi mhl ops failed\n", __func__); |
| 1891 | rc = -ENOMEM; |
| 1892 | goto failed_probe_pwr; |
| 1893 | } |
| 1894 | |
| 1895 | pr_debug("%s: i2c client addr is [%x]\n", __func__, client->addr); |
| 1896 | if (mhl_ctrl->pdata->hdmi_pdev) { |
| 1897 | rc = msm_hdmi_register_mhl(mhl_ctrl->pdata->hdmi_pdev, |
| 1898 | hdmi_mhl_ops, mhl_ctrl); |
| 1899 | if (rc) { |
| 1900 | pr_err("%s: register with hdmi failed\n", __func__); |
| 1901 | rc = -EPROBE_DEFER; |
| 1902 | goto failed_probe_pwr; |
| 1903 | } |
| 1904 | } |
| 1905 | |
| 1906 | if (!hdmi_mhl_ops || !hdmi_mhl_ops->tmds_enabled || |
| 1907 | !hdmi_mhl_ops->set_mhl_max_pclk) { |
| 1908 | pr_err("%s: func ptr is NULL\n", __func__); |
| 1909 | rc = -EINVAL; |
| 1910 | goto failed_probe_pwr; |
| 1911 | } |
| 1912 | mhl_ctrl->hdmi_mhl_ops = hdmi_mhl_ops; |
| 1913 | |
| 1914 | rc = hdmi_mhl_ops->set_mhl_max_pclk( |
| 1915 | mhl_ctrl->pdata->hdmi_pdev, MAX_MHL_PCLK); |
| 1916 | if (rc) { |
| 1917 | pr_err("%s: can't set max mhl pclk\n", __func__); |
| 1918 | goto failed_probe_pwr; |
| 1919 | } |
| 1920 | |
| 1921 | mhl_info = devm_kzalloc(&client->dev, sizeof(*mhl_info), GFP_KERNEL); |
| 1922 | if (!mhl_info) { |
| 1923 | rc = -ENOMEM; |
| 1924 | goto failed_probe_pwr; |
| 1925 | } |
| 1926 | |
| 1927 | mhl_info->ctxt = mhl_ctrl; |
| 1928 | mhl_info->notify = mhl_sii_device_discovery; |
| 1929 | if (msm_register_usb_ext_notification(mhl_info)) { |
| 1930 | pr_err("%s: register for usb notifcn failed\n", __func__); |
| 1931 | rc = -EPROBE_DEFER; |
| 1932 | goto failed_probe_pwr; |
| 1933 | } |
| 1934 | mhl_ctrl->mhl_info = mhl_info; |
| 1935 | mhl_register_msc(mhl_ctrl); |
| 1936 | return 0; |
| 1937 | |
| 1938 | failed_probe_pwr: |
| 1939 | power_supply_unregister(&mhl_ctrl->mhl_psy); |
| 1940 | failed_probe: |
| 1941 | mhl_sii_config(mhl_ctrl, false); |
| 1942 | /* do not deep-free */ |
| 1943 | if (mhl_info) |
| 1944 | devm_kfree(&client->dev, mhl_info); |
| 1945 | failed_dt_data: |
| 1946 | if (pdata) |
| 1947 | devm_kfree(&client->dev, pdata); |
| 1948 | failed_no_mem: |
| 1949 | if (mhl_ctrl) |
| 1950 | devm_kfree(&client->dev, mhl_ctrl); |
| 1951 | mhl_info = NULL; |
| 1952 | pdata = NULL; |
| 1953 | mhl_ctrl = NULL; |
| 1954 | pr_err("%s: PROBE FAILED, rc=%d\n", __func__, rc); |
| 1955 | return rc; |
| 1956 | } |
| 1957 | |
| 1958 | |
| 1959 | static int mhl_i2c_remove(struct i2c_client *client) |
| 1960 | { |
| 1961 | struct mhl_tx_ctrl *mhl_ctrl = i2c_get_clientdata(client); |
| 1962 | |
| 1963 | if (!mhl_ctrl) { |
| 1964 | pr_warn("%s: i2c get client data failed\n", __func__); |
| 1965 | return -EINVAL; |
| 1966 | } |
| 1967 | |
| 1968 | mhl_sii_config(mhl_ctrl, false); |
| 1969 | |
| 1970 | destroy_workqueue(mhl_ctrl->mhl_workq); |
| 1971 | |
| 1972 | if (mhl_ctrl->mhl_info) |
| 1973 | devm_kfree(&client->dev, mhl_ctrl->mhl_info); |
| 1974 | if (mhl_ctrl->pdata) |
| 1975 | devm_kfree(&client->dev, mhl_ctrl->pdata); |
| 1976 | devm_kfree(&client->dev, mhl_ctrl); |
| 1977 | return 0; |
| 1978 | } |
| 1979 | |
| 1980 | static struct i2c_device_id mhl_sii_i2c_id[] = { |
| 1981 | { MHL_DRIVER_NAME, 0 }, |
| 1982 | { } |
| 1983 | }; |
| 1984 | |
| 1985 | |
| 1986 | MODULE_DEVICE_TABLE(i2c, mhl_sii_i2c_id); |
| 1987 | |
| 1988 | #if defined(CONFIG_PM) || defined(CONFIG_PM_SLEEP) |
| 1989 | static int mhl_i2c_suspend_sub(struct i2c_client *client) |
| 1990 | { |
| 1991 | struct mhl_tx_ctrl *mhl_ctrl = i2c_get_clientdata(client); |
| 1992 | |
| 1993 | pr_debug("%s\n", __func__); |
| 1994 | |
| 1995 | if (!mhl_ctrl) { |
| 1996 | pr_err("%s: invalid ctrl data\n", __func__); |
| 1997 | return 0; |
| 1998 | } |
| 1999 | |
| 2000 | if (mhl_ctrl->mhl_mode) { |
| 2001 | mhl_ctrl->mhl_mode = 0; |
| 2002 | |
| 2003 | power_supply_changed(&mhl_ctrl->mhl_psy); |
| 2004 | if (mhl_ctrl->notify_usb_online) |
| 2005 | mhl_ctrl->notify_usb_online(mhl_ctrl->notify_ctx, 0); |
| 2006 | |
| 2007 | mhl_sii_config(mhl_ctrl, false); |
| 2008 | } |
| 2009 | |
| 2010 | return 0; |
| 2011 | } |
| 2012 | |
| 2013 | static int mhl_i2c_resume_sub(struct i2c_client *client) |
| 2014 | { |
| 2015 | pr_debug("%s\n", __func__); |
| 2016 | |
| 2017 | return 0; |
| 2018 | } |
| 2019 | #endif /* defined(CONFIG_PM) || defined(CONFIG_PM_SLEEP) */ |
| 2020 | |
| 2021 | #if defined(CONFIG_PM) && !defined(CONFIG_PM_SLEEP) |
| 2022 | static int mhl_i2c_suspend(struct i2c_client *client, pm_message_t state) |
| 2023 | { |
| 2024 | if (!client) |
| 2025 | return -ENODEV; |
| 2026 | pr_debug("%s: mhl suspend\n", __func__); |
| 2027 | return mhl_i2c_suspend_sub(client); |
| 2028 | } |
| 2029 | |
| 2030 | static int mhl_i2c_resume(struct i2c_client *client) |
| 2031 | { |
| 2032 | if (!client) |
| 2033 | return -ENODEV; |
| 2034 | pr_debug("%s: mhl resume\n", __func__); |
| 2035 | return mhl_i2c_resume_sub(client); |
| 2036 | } |
| 2037 | #else |
| 2038 | #define mhl_i2c_suspend NULL |
| 2039 | #define mhl_i2c_resume NULL |
| 2040 | #endif /* defined(CONFIG_PM) && !defined(CONFIG_PM_SLEEP) */ |
| 2041 | |
| 2042 | #ifdef CONFIG_PM_SLEEP |
| 2043 | static int mhl_i2c_pm_suspend(struct device *dev) |
| 2044 | { |
| 2045 | struct i2c_client *client = |
| 2046 | container_of(dev, struct i2c_client, dev); |
| 2047 | |
| 2048 | if (!client) |
| 2049 | return -ENODEV; |
| 2050 | pr_debug("%s: mhl pm suspend\n", __func__); |
| 2051 | return mhl_i2c_suspend_sub(client); |
| 2052 | |
| 2053 | } |
| 2054 | |
| 2055 | static int mhl_i2c_pm_resume(struct device *dev) |
| 2056 | { |
| 2057 | struct i2c_client *client = |
| 2058 | container_of(dev, struct i2c_client, dev); |
| 2059 | |
| 2060 | if (!client) |
| 2061 | return -ENODEV; |
| 2062 | pr_debug("%s: mhl pm resume\n", __func__); |
| 2063 | return mhl_i2c_resume_sub(client); |
| 2064 | } |
| 2065 | |
| 2066 | static const struct dev_pm_ops mhl_i2c_pm_ops = { |
| 2067 | SET_SYSTEM_SLEEP_PM_OPS(mhl_i2c_pm_suspend, mhl_i2c_pm_resume) |
| 2068 | }; |
| 2069 | #endif /* CONFIG_PM_SLEEP */ |
| 2070 | |
| 2071 | const struct of_device_id mhl_match_table[] = { |
| 2072 | {.compatible = COMPATIBLE_NAME,}, |
| 2073 | { }, |
| 2074 | }; |
| 2075 | |
| 2076 | static struct i2c_driver mhl_sii_i2c_driver = { |
| 2077 | .driver = { |
| 2078 | .name = MHL_DRIVER_NAME, |
| 2079 | .owner = THIS_MODULE, |
| 2080 | .of_match_table = mhl_match_table, |
| 2081 | #ifdef CONFIG_PM_SLEEP |
| 2082 | .pm = &mhl_i2c_pm_ops, |
| 2083 | #endif /* CONFIG_PM_SLEEP */ |
| 2084 | }, |
| 2085 | .probe = mhl_i2c_probe, |
| 2086 | .remove = mhl_i2c_remove, |
| 2087 | #if defined(CONFIG_PM) && !defined(CONFIG_PM_SLEEP) |
| 2088 | .suspend = mhl_i2c_suspend, |
| 2089 | .resume = mhl_i2c_resume, |
| 2090 | #endif /* defined(CONFIG_PM) && !defined(CONFIG_PM_SLEEP) */ |
| 2091 | .id_table = mhl_sii_i2c_id, |
| 2092 | }; |
| 2093 | |
| 2094 | module_i2c_driver(mhl_sii_i2c_driver); |
| 2095 | |
| 2096 | MODULE_LICENSE("GPL v2"); |
| 2097 | MODULE_DESCRIPTION("MHL SII 8334 TX Driver"); |