Soren Brinkmann | 812283c | 2014-10-02 09:13:35 -0700 | [diff] [blame] | 1 | Binding for Xilinx Clocking Wizard IP Core |
| 2 | |
| 3 | This binding uses the common clock binding[1]. Details about the devices can be |
| 4 | found in the product guide[2]. |
| 5 | |
| 6 | [1] Documentation/devicetree/bindings/clock/clock-bindings.txt |
| 7 | [2] Clocking Wizard Product Guide |
| 8 | http://www.xilinx.com/support/documentation/ip_documentation/clk_wiz/v5_1/pg065-clk-wiz.pdf |
| 9 | |
| 10 | Required properties: |
| 11 | - compatible: Must be 'xlnx,clocking-wizard' |
| 12 | - reg: Base and size of the cores register space |
| 13 | - clocks: Handle to input clock |
| 14 | - clock-names: Tuple containing 'clk_in1' and 's_axi_aclk' |
| 15 | - clock-output-names: Names for the output clocks |
| 16 | |
| 17 | Optional properties: |
| 18 | - speed-grade: Speed grade of the device (valid values are 1..3) |
| 19 | |
| 20 | Example: |
| 21 | clock-generator@40040000 { |
| 22 | reg = <0x40040000 0x1000>; |
| 23 | compatible = "xlnx,clocking-wizard"; |
| 24 | speed-grade = <1>; |
| 25 | clock-names = "clk_in1", "s_axi_aclk"; |
| 26 | clocks = <&clkc 15>, <&clkc 15>; |
| 27 | clock-output-names = "clk_out0", "clk_out1", "clk_out2", |
| 28 | "clk_out3", "clk_out4", "clk_out5", |
| 29 | "clk_out6", "clk_out7"; |
| 30 | }; |