Catalin Marinas | 8ad68bb | 2005-10-31 14:25:02 +0000 | [diff] [blame] | 1 | /* |
| 2 | * linux/arch/arm/mach-realview/core.c |
| 3 | * |
| 4 | * Copyright (C) 1999 - 2003 ARM Limited |
| 5 | * Copyright (C) 2000 Deep Blue Solutions Ltd |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; either version 2 of the License, or |
| 10 | * (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 20 | */ |
Catalin Marinas | 8ad68bb | 2005-10-31 14:25:02 +0000 | [diff] [blame] | 21 | #include <linux/init.h> |
Russell King | 1be7228 | 2005-10-31 16:57:06 +0000 | [diff] [blame] | 22 | #include <linux/platform_device.h> |
Catalin Marinas | 8ad68bb | 2005-10-31 14:25:02 +0000 | [diff] [blame] | 23 | #include <linux/dma-mapping.h> |
| 24 | #include <linux/sysdev.h> |
| 25 | #include <linux/interrupt.h> |
Russell King | a62c80e | 2006-01-07 13:52:45 +0000 | [diff] [blame] | 26 | #include <linux/amba/bus.h> |
| 27 | #include <linux/amba/clcd.h> |
Russell King | fced80c | 2008-09-06 12:10:45 +0100 | [diff] [blame] | 28 | #include <linux/io.h> |
Steve Glendinning | c5142e8 | 2009-01-20 13:23:30 +0000 | [diff] [blame] | 29 | #include <linux/smsc911x.h> |
Catalin Marinas | 6be62ba | 2009-02-12 15:59:21 +0100 | [diff] [blame] | 30 | #include <linux/ata_platform.h> |
Linus Walleij | 6ef297f | 2009-09-22 14:29:36 +0100 | [diff] [blame] | 31 | #include <linux/amba/mmci.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 32 | #include <linux/gfp.h> |
Jean-Christop PLAGNIOL-VILLARD | 6d803ba | 2010-11-17 10:04:33 +0100 | [diff] [blame] | 33 | #include <linux/clkdev.h> |
Marc Zyngier | b8b87ae | 2011-05-18 10:51:49 +0100 | [diff] [blame] | 34 | #include <linux/mtd/physmap.h> |
Catalin Marinas | 8ad68bb | 2005-10-31 14:25:02 +0000 | [diff] [blame] | 35 | |
| 36 | #include <asm/system.h> |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 37 | #include <mach/hardware.h> |
Catalin Marinas | 8ad68bb | 2005-10-31 14:25:02 +0000 | [diff] [blame] | 38 | #include <asm/irq.h> |
| 39 | #include <asm/leds.h> |
Colin Tuckley | 68c3d93 | 2008-11-10 14:10:11 +0000 | [diff] [blame] | 40 | #include <asm/mach-types.h> |
Catalin Marinas | 8ad68bb | 2005-10-31 14:25:02 +0000 | [diff] [blame] | 41 | #include <asm/hardware/arm_timer.h> |
Russell King | c5a0adb | 2010-01-16 20:16:10 +0000 | [diff] [blame] | 42 | #include <asm/hardware/icst.h> |
Catalin Marinas | 8ad68bb | 2005-10-31 14:25:02 +0000 | [diff] [blame] | 43 | |
| 44 | #include <asm/mach/arch.h> |
Catalin Marinas | 8ad68bb | 2005-10-31 14:25:02 +0000 | [diff] [blame] | 45 | #include <asm/mach/irq.h> |
Catalin Marinas | 8ad68bb | 2005-10-31 14:25:02 +0000 | [diff] [blame] | 46 | #include <asm/mach/map.h> |
Catalin Marinas | 8ad68bb | 2005-10-31 14:25:02 +0000 | [diff] [blame] | 47 | |
| 48 | #include <asm/hardware/gic.h> |
| 49 | |
Catalin Marinas | ee8c957 | 2009-05-30 14:00:17 +0100 | [diff] [blame] | 50 | #include <mach/platform.h> |
| 51 | #include <mach/irqs.h> |
Rob Herring | 8a9618f | 2010-10-06 16:18:08 +0100 | [diff] [blame] | 52 | #include <asm/hardware/timer-sp.h> |
Catalin Marinas | ee8c957 | 2009-05-30 14:00:17 +0100 | [diff] [blame] | 53 | |
Russell King | 3cb5ee4 | 2011-01-18 20:13:20 +0000 | [diff] [blame] | 54 | #include <plat/clcd.h> |
Russell King | 1da0c89 | 2010-12-15 21:56:47 +0000 | [diff] [blame] | 55 | #include <plat/sched_clock.h> |
| 56 | |
Catalin Marinas | 8ad68bb | 2005-10-31 14:25:02 +0000 | [diff] [blame] | 57 | #include "core.h" |
Catalin Marinas | 8ad68bb | 2005-10-31 14:25:02 +0000 | [diff] [blame] | 58 | |
Catalin Marinas | 8ad68bb | 2005-10-31 14:25:02 +0000 | [diff] [blame] | 59 | #define REALVIEW_FLASHCTRL (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_FLASH_OFFSET) |
| 60 | |
Marc Zyngier | 667f390 | 2011-05-18 10:51:55 +0100 | [diff] [blame] | 61 | static void realview_flash_set_vpp(struct platform_device *pdev, int on) |
Catalin Marinas | 8ad68bb | 2005-10-31 14:25:02 +0000 | [diff] [blame] | 62 | { |
| 63 | u32 val; |
| 64 | |
| 65 | val = __raw_readl(REALVIEW_FLASHCTRL); |
| 66 | if (on) |
| 67 | val |= REALVIEW_FLASHPROG_FLVPPEN; |
| 68 | else |
| 69 | val &= ~REALVIEW_FLASHPROG_FLVPPEN; |
| 70 | __raw_writel(val, REALVIEW_FLASHCTRL); |
| 71 | } |
| 72 | |
Marc Zyngier | b8b87ae | 2011-05-18 10:51:49 +0100 | [diff] [blame] | 73 | static struct physmap_flash_data realview_flash_data = { |
Catalin Marinas | 8ad68bb | 2005-10-31 14:25:02 +0000 | [diff] [blame] | 74 | .width = 4, |
Catalin Marinas | 8ad68bb | 2005-10-31 14:25:02 +0000 | [diff] [blame] | 75 | .set_vpp = realview_flash_set_vpp, |
| 76 | }; |
| 77 | |
Catalin Marinas | 8ad68bb | 2005-10-31 14:25:02 +0000 | [diff] [blame] | 78 | struct platform_device realview_flash_device = { |
Marc Zyngier | b8b87ae | 2011-05-18 10:51:49 +0100 | [diff] [blame] | 79 | .name = "physmap-flash", |
Catalin Marinas | 8ad68bb | 2005-10-31 14:25:02 +0000 | [diff] [blame] | 80 | .id = 0, |
| 81 | .dev = { |
| 82 | .platform_data = &realview_flash_data, |
| 83 | }, |
Catalin Marinas | 8ad68bb | 2005-10-31 14:25:02 +0000 | [diff] [blame] | 84 | }; |
| 85 | |
Catalin Marinas | a44ddfd | 2008-04-18 22:43:10 +0100 | [diff] [blame] | 86 | int realview_flash_register(struct resource *res, u32 num) |
| 87 | { |
| 88 | realview_flash_device.resource = res; |
| 89 | realview_flash_device.num_resources = num; |
| 90 | return platform_device_register(&realview_flash_device); |
| 91 | } |
| 92 | |
Steve Glendinning | c5142e8 | 2009-01-20 13:23:30 +0000 | [diff] [blame] | 93 | static struct smsc911x_platform_config smsc911x_config = { |
| 94 | .flags = SMSC911X_USE_32BIT, |
| 95 | .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH, |
| 96 | .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, |
| 97 | .phy_interface = PHY_INTERFACE_MODE_MII, |
Catalin Marinas | 0a5b2f6 | 2008-12-01 14:54:59 +0000 | [diff] [blame] | 98 | }; |
| 99 | |
Catalin Marinas | 0a38133 | 2008-12-01 14:54:58 +0000 | [diff] [blame] | 100 | static struct platform_device realview_eth_device = { |
Steve Glendinning | c5142e8 | 2009-01-20 13:23:30 +0000 | [diff] [blame] | 101 | .name = "smsc911x", |
Catalin Marinas | 0a38133 | 2008-12-01 14:54:58 +0000 | [diff] [blame] | 102 | .id = 0, |
| 103 | .num_resources = 2, |
| 104 | }; |
| 105 | |
| 106 | int realview_eth_register(const char *name, struct resource *res) |
| 107 | { |
| 108 | if (name) |
| 109 | realview_eth_device.name = name; |
| 110 | realview_eth_device.resource = res; |
Steve Glendinning | c5142e8 | 2009-01-20 13:23:30 +0000 | [diff] [blame] | 111 | if (strcmp(realview_eth_device.name, "smsc911x") == 0) |
| 112 | realview_eth_device.dev.platform_data = &smsc911x_config; |
Catalin Marinas | 0a38133 | 2008-12-01 14:54:58 +0000 | [diff] [blame] | 113 | |
| 114 | return platform_device_register(&realview_eth_device); |
| 115 | } |
| 116 | |
Catalin Marinas | 7db2171 | 2009-02-12 16:00:21 +0100 | [diff] [blame] | 117 | struct platform_device realview_usb_device = { |
| 118 | .name = "isp1760", |
| 119 | .num_resources = 2, |
| 120 | }; |
| 121 | |
| 122 | int realview_usb_register(struct resource *res) |
| 123 | { |
| 124 | realview_usb_device.resource = res; |
| 125 | return platform_device_register(&realview_usb_device); |
| 126 | } |
| 127 | |
Catalin Marinas | 6be62ba | 2009-02-12 15:59:21 +0100 | [diff] [blame] | 128 | static struct pata_platform_info pata_platform_data = { |
| 129 | .ioport_shift = 1, |
| 130 | }; |
| 131 | |
| 132 | static struct resource pata_resources[] = { |
| 133 | [0] = { |
| 134 | .start = REALVIEW_CF_BASE, |
| 135 | .end = REALVIEW_CF_BASE + 0xff, |
| 136 | .flags = IORESOURCE_MEM, |
| 137 | }, |
| 138 | [1] = { |
| 139 | .start = REALVIEW_CF_BASE + 0x100, |
| 140 | .end = REALVIEW_CF_BASE + SZ_4K - 1, |
| 141 | .flags = IORESOURCE_MEM, |
| 142 | }, |
| 143 | }; |
| 144 | |
| 145 | struct platform_device realview_cf_device = { |
| 146 | .name = "pata_platform", |
| 147 | .id = -1, |
| 148 | .num_resources = ARRAY_SIZE(pata_resources), |
| 149 | .resource = pata_resources, |
| 150 | .dev = { |
| 151 | .platform_data = &pata_platform_data, |
| 152 | }, |
| 153 | }; |
| 154 | |
Russell King | 6b65cd7 | 2006-12-10 21:21:32 +0100 | [diff] [blame] | 155 | static struct resource realview_i2c_resource = { |
| 156 | .start = REALVIEW_I2C_BASE, |
| 157 | .end = REALVIEW_I2C_BASE + SZ_4K - 1, |
| 158 | .flags = IORESOURCE_MEM, |
| 159 | }; |
| 160 | |
| 161 | struct platform_device realview_i2c_device = { |
| 162 | .name = "versatile-i2c", |
Catalin Marinas | 533ad5e | 2009-02-12 15:58:20 +0100 | [diff] [blame] | 163 | .id = 0, |
Russell King | 6b65cd7 | 2006-12-10 21:21:32 +0100 | [diff] [blame] | 164 | .num_resources = 1, |
| 165 | .resource = &realview_i2c_resource, |
| 166 | }; |
| 167 | |
Catalin Marinas | 533ad5e | 2009-02-12 15:58:20 +0100 | [diff] [blame] | 168 | static struct i2c_board_info realview_i2c_board_info[] = { |
| 169 | { |
Russell King | 64e8be6 | 2009-07-18 15:51:55 +0100 | [diff] [blame] | 170 | I2C_BOARD_INFO("ds1338", 0xd0 >> 1), |
Catalin Marinas | 533ad5e | 2009-02-12 15:58:20 +0100 | [diff] [blame] | 171 | }, |
| 172 | }; |
| 173 | |
| 174 | static int __init realview_i2c_init(void) |
| 175 | { |
| 176 | return i2c_register_board_info(0, realview_i2c_board_info, |
| 177 | ARRAY_SIZE(realview_i2c_board_info)); |
| 178 | } |
| 179 | arch_initcall(realview_i2c_init); |
| 180 | |
Catalin Marinas | 8ad68bb | 2005-10-31 14:25:02 +0000 | [diff] [blame] | 181 | #define REALVIEW_SYSMCI (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_MCI_OFFSET) |
| 182 | |
Russell King | 98b0979 | 2009-07-09 15:17:41 +0100 | [diff] [blame] | 183 | /* |
| 184 | * This is only used if GPIOLIB support is disabled |
| 185 | */ |
Catalin Marinas | 8ad68bb | 2005-10-31 14:25:02 +0000 | [diff] [blame] | 186 | static unsigned int realview_mmc_status(struct device *dev) |
| 187 | { |
| 188 | struct amba_device *adev = container_of(dev, struct amba_device, dev); |
| 189 | u32 mask; |
| 190 | |
Linus Walleij | 48f1d5a | 2010-07-02 10:24:03 +0100 | [diff] [blame] | 191 | if (machine_is_realview_pb1176()) { |
| 192 | static bool inserted = false; |
| 193 | |
| 194 | /* |
| 195 | * The PB1176 does not have the status register, |
| 196 | * assume it is inserted at startup, then invert |
| 197 | * for each call so card insertion/removal will |
| 198 | * be detected anyway. This will not be called if |
| 199 | * GPIO on PL061 is active, which is the proper |
| 200 | * way to do this on the PB1176. |
| 201 | */ |
| 202 | inserted = !inserted; |
| 203 | return inserted ? 0 : 1; |
| 204 | } |
| 205 | |
Catalin Marinas | 8ad68bb | 2005-10-31 14:25:02 +0000 | [diff] [blame] | 206 | if (adev->res.start == REALVIEW_MMCI0_BASE) |
| 207 | mask = 1; |
| 208 | else |
| 209 | mask = 2; |
| 210 | |
Russell King | 74bc809 | 2010-07-29 15:58:59 +0100 | [diff] [blame] | 211 | return readl(REALVIEW_SYSMCI) & mask; |
Catalin Marinas | 8ad68bb | 2005-10-31 14:25:02 +0000 | [diff] [blame] | 212 | } |
| 213 | |
Linus Walleij | 6ef297f | 2009-09-22 14:29:36 +0100 | [diff] [blame] | 214 | struct mmci_platform_data realview_mmc0_plat_data = { |
Catalin Marinas | 8ad68bb | 2005-10-31 14:25:02 +0000 | [diff] [blame] | 215 | .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, |
| 216 | .status = realview_mmc_status, |
Russell King | 98b0979 | 2009-07-09 15:17:41 +0100 | [diff] [blame] | 217 | .gpio_wp = 17, |
| 218 | .gpio_cd = 16, |
Rabin Vincent | 2971944 | 2010-08-09 12:54:43 +0100 | [diff] [blame] | 219 | .cd_invert = true, |
Catalin Marinas | 8ad68bb | 2005-10-31 14:25:02 +0000 | [diff] [blame] | 220 | }; |
| 221 | |
Linus Walleij | 6ef297f | 2009-09-22 14:29:36 +0100 | [diff] [blame] | 222 | struct mmci_platform_data realview_mmc1_plat_data = { |
Catalin Marinas | 8ad68bb | 2005-10-31 14:25:02 +0000 | [diff] [blame] | 223 | .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, |
| 224 | .status = realview_mmc_status, |
Russell King | 98b0979 | 2009-07-09 15:17:41 +0100 | [diff] [blame] | 225 | .gpio_wp = 19, |
| 226 | .gpio_cd = 18, |
Rabin Vincent | 2971944 | 2010-08-09 12:54:43 +0100 | [diff] [blame] | 227 | .cd_invert = true, |
Catalin Marinas | 8ad68bb | 2005-10-31 14:25:02 +0000 | [diff] [blame] | 228 | }; |
| 229 | |
| 230 | /* |
| 231 | * Clock handling |
| 232 | */ |
Russell King | 39c0cb0 | 2010-01-16 16:27:28 +0000 | [diff] [blame] | 233 | static const struct icst_params realview_oscvco_params = { |
Russell King | 64fceb1 | 2010-01-16 17:28:44 +0000 | [diff] [blame] | 234 | .ref = 24000000, |
Russell King | 4de2edb | 2010-01-16 18:08:47 +0000 | [diff] [blame] | 235 | .vco_max = ICST307_VCO_MAX, |
Russell King | e73a46a | 2010-01-16 19:49:39 +0000 | [diff] [blame] | 236 | .vco_min = ICST307_VCO_MIN, |
Catalin Marinas | 8ad68bb | 2005-10-31 14:25:02 +0000 | [diff] [blame] | 237 | .vd_min = 4 + 8, |
| 238 | .vd_max = 511 + 8, |
| 239 | .rd_min = 1 + 2, |
| 240 | .rd_max = 127 + 2, |
Russell King | 232eaf7 | 2010-01-16 19:46:19 +0000 | [diff] [blame] | 241 | .s2div = icst307_s2div, |
| 242 | .idx2s = icst307_idx2s, |
Catalin Marinas | 8ad68bb | 2005-10-31 14:25:02 +0000 | [diff] [blame] | 243 | }; |
| 244 | |
Russell King | 39c0cb0 | 2010-01-16 16:27:28 +0000 | [diff] [blame] | 245 | static void realview_oscvco_set(struct clk *clk, struct icst_vco vco) |
Catalin Marinas | 8ad68bb | 2005-10-31 14:25:02 +0000 | [diff] [blame] | 246 | { |
| 247 | void __iomem *sys_lock = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LOCK_OFFSET; |
Catalin Marinas | 8ad68bb | 2005-10-31 14:25:02 +0000 | [diff] [blame] | 248 | u32 val; |
| 249 | |
Russell King | d1914c7 | 2010-01-14 20:09:34 +0000 | [diff] [blame] | 250 | val = readl(clk->vcoreg) & ~0x7ffff; |
Catalin Marinas | 8ad68bb | 2005-10-31 14:25:02 +0000 | [diff] [blame] | 251 | val |= vco.v | (vco.r << 9) | (vco.s << 16); |
| 252 | |
| 253 | writel(0xa05f, sys_lock); |
Russell King | d1914c7 | 2010-01-14 20:09:34 +0000 | [diff] [blame] | 254 | writel(val, clk->vcoreg); |
Catalin Marinas | 8ad68bb | 2005-10-31 14:25:02 +0000 | [diff] [blame] | 255 | writel(0, sys_lock); |
| 256 | } |
| 257 | |
Russell King | 9bf5b2e | 2010-03-01 16:18:39 +0000 | [diff] [blame] | 258 | static const struct clk_ops oscvco_clk_ops = { |
| 259 | .round = icst_clk_round, |
| 260 | .set = icst_clk_set, |
| 261 | .setvco = realview_oscvco_set, |
| 262 | }; |
| 263 | |
Russell King | cf30fb4 | 2008-11-08 20:05:55 +0000 | [diff] [blame] | 264 | static struct clk oscvco_clk = { |
Russell King | 9bf5b2e | 2010-03-01 16:18:39 +0000 | [diff] [blame] | 265 | .ops = &oscvco_clk_ops, |
Catalin Marinas | 8ad68bb | 2005-10-31 14:25:02 +0000 | [diff] [blame] | 266 | .params = &realview_oscvco_params, |
Catalin Marinas | 8ad68bb | 2005-10-31 14:25:02 +0000 | [diff] [blame] | 267 | }; |
| 268 | |
| 269 | /* |
Russell King | cf30fb4 | 2008-11-08 20:05:55 +0000 | [diff] [blame] | 270 | * These are fixed clocks. |
| 271 | */ |
| 272 | static struct clk ref24_clk = { |
| 273 | .rate = 24000000, |
| 274 | }; |
| 275 | |
Russell King | 7ff550d | 2011-05-12 13:31:48 +0100 | [diff] [blame] | 276 | static struct clk sp804_clk = { |
| 277 | .rate = 1000000, |
| 278 | }; |
| 279 | |
Russell King | 3126c7b | 2010-07-15 11:01:17 +0100 | [diff] [blame] | 280 | static struct clk dummy_apb_pclk; |
| 281 | |
Russell King | cf30fb4 | 2008-11-08 20:05:55 +0000 | [diff] [blame] | 282 | static struct clk_lookup lookups[] = { |
Russell King | 3126c7b | 2010-07-15 11:01:17 +0100 | [diff] [blame] | 283 | { /* Bus clock */ |
| 284 | .con_id = "apb_pclk", |
| 285 | .clk = &dummy_apb_pclk, |
| 286 | }, { /* UART0 */ |
Linus Walleij | 4321532 | 2009-09-21 12:30:32 +0100 | [diff] [blame] | 287 | .dev_id = "dev:uart0", |
Russell King | cf30fb4 | 2008-11-08 20:05:55 +0000 | [diff] [blame] | 288 | .clk = &ref24_clk, |
| 289 | }, { /* UART1 */ |
Linus Walleij | 4321532 | 2009-09-21 12:30:32 +0100 | [diff] [blame] | 290 | .dev_id = "dev:uart1", |
Russell King | cf30fb4 | 2008-11-08 20:05:55 +0000 | [diff] [blame] | 291 | .clk = &ref24_clk, |
| 292 | }, { /* UART2 */ |
Linus Walleij | 4321532 | 2009-09-21 12:30:32 +0100 | [diff] [blame] | 293 | .dev_id = "dev:uart2", |
Russell King | cf30fb4 | 2008-11-08 20:05:55 +0000 | [diff] [blame] | 294 | .clk = &ref24_clk, |
| 295 | }, { /* UART3 */ |
Linus Walleij | 4321532 | 2009-09-21 12:30:32 +0100 | [diff] [blame] | 296 | .dev_id = "fpga:uart3", |
Russell King | cf30fb4 | 2008-11-08 20:05:55 +0000 | [diff] [blame] | 297 | .clk = &ref24_clk, |
Linus Walleij | 48f1d5a | 2010-07-02 10:24:03 +0100 | [diff] [blame] | 298 | }, { /* UART3 is on the dev chip in PB1176 */ |
| 299 | .dev_id = "dev:uart3", |
| 300 | .clk = &ref24_clk, |
| 301 | }, { /* UART4 only exists in PB1176 */ |
| 302 | .dev_id = "fpga:uart4", |
| 303 | .clk = &ref24_clk, |
Russell King | cf30fb4 | 2008-11-08 20:05:55 +0000 | [diff] [blame] | 304 | }, { /* KMI0 */ |
Linus Walleij | 4321532 | 2009-09-21 12:30:32 +0100 | [diff] [blame] | 305 | .dev_id = "fpga:kmi0", |
Russell King | cf30fb4 | 2008-11-08 20:05:55 +0000 | [diff] [blame] | 306 | .clk = &ref24_clk, |
| 307 | }, { /* KMI1 */ |
Linus Walleij | 4321532 | 2009-09-21 12:30:32 +0100 | [diff] [blame] | 308 | .dev_id = "fpga:kmi1", |
Russell King | cf30fb4 | 2008-11-08 20:05:55 +0000 | [diff] [blame] | 309 | .clk = &ref24_clk, |
| 310 | }, { /* MMC0 */ |
Linus Walleij | 4321532 | 2009-09-21 12:30:32 +0100 | [diff] [blame] | 311 | .dev_id = "fpga:mmc0", |
Russell King | cf30fb4 | 2008-11-08 20:05:55 +0000 | [diff] [blame] | 312 | .clk = &ref24_clk, |
Linus Walleij | 48f1d5a | 2010-07-02 10:24:03 +0100 | [diff] [blame] | 313 | }, { /* CLCD is in the PB1176 and EB DevChip */ |
Linus Walleij | 4321532 | 2009-09-21 12:30:32 +0100 | [diff] [blame] | 314 | .dev_id = "dev:clcd", |
Russell King | cf30fb4 | 2008-11-08 20:05:55 +0000 | [diff] [blame] | 315 | .clk = &oscvco_clk, |
| 316 | }, { /* PB:CLCD */ |
Linus Walleij | 4321532 | 2009-09-21 12:30:32 +0100 | [diff] [blame] | 317 | .dev_id = "issp:clcd", |
Russell King | cf30fb4 | 2008-11-08 20:05:55 +0000 | [diff] [blame] | 318 | .clk = &oscvco_clk, |
Linus Walleij | d6ada86 | 2010-07-14 23:58:38 +0100 | [diff] [blame] | 319 | }, { /* SSP */ |
| 320 | .dev_id = "dev:ssp0", |
| 321 | .clk = &ref24_clk, |
Russell King | 7ff550d | 2011-05-12 13:31:48 +0100 | [diff] [blame] | 322 | }, { /* SP804 timers */ |
| 323 | .dev_id = "sp804", |
| 324 | .clk = &sp804_clk, |
| 325 | }, |
Russell King | cf30fb4 | 2008-11-08 20:05:55 +0000 | [diff] [blame] | 326 | }; |
| 327 | |
Russell King | 631e55f | 2011-01-11 13:05:01 +0000 | [diff] [blame] | 328 | void __init realview_init_early(void) |
Russell King | cf30fb4 | 2008-11-08 20:05:55 +0000 | [diff] [blame] | 329 | { |
Russell King | 631e55f | 2011-01-11 13:05:01 +0000 | [diff] [blame] | 330 | void __iomem *sys = __io_address(REALVIEW_SYS_BASE); |
| 331 | |
Russell King | d1914c7 | 2010-01-14 20:09:34 +0000 | [diff] [blame] | 332 | if (machine_is_realview_pb1176()) |
Russell King | 631e55f | 2011-01-11 13:05:01 +0000 | [diff] [blame] | 333 | oscvco_clk.vcoreg = sys + REALVIEW_SYS_OSC0_OFFSET; |
Russell King | d1914c7 | 2010-01-14 20:09:34 +0000 | [diff] [blame] | 334 | else |
Russell King | 631e55f | 2011-01-11 13:05:01 +0000 | [diff] [blame] | 335 | oscvco_clk.vcoreg = sys + REALVIEW_SYS_OSC4_OFFSET; |
Russell King | d1914c7 | 2010-01-14 20:09:34 +0000 | [diff] [blame] | 336 | |
Russell King | 0a0300d | 2010-01-12 12:28:00 +0000 | [diff] [blame] | 337 | clkdev_add_table(lookups, ARRAY_SIZE(lookups)); |
Russell King | d1914c7 | 2010-01-14 20:09:34 +0000 | [diff] [blame] | 338 | |
Russell King | 631e55f | 2011-01-11 13:05:01 +0000 | [diff] [blame] | 339 | versatile_sched_clock_init(sys + REALVIEW_SYS_24MHz_OFFSET, 24000000); |
Russell King | cf30fb4 | 2008-11-08 20:05:55 +0000 | [diff] [blame] | 340 | } |
Russell King | cf30fb4 | 2008-11-08 20:05:55 +0000 | [diff] [blame] | 341 | |
| 342 | /* |
Catalin Marinas | 8ad68bb | 2005-10-31 14:25:02 +0000 | [diff] [blame] | 343 | * CLCD support. |
| 344 | */ |
Catalin Marinas | 8ad68bb | 2005-10-31 14:25:02 +0000 | [diff] [blame] | 345 | #define SYS_CLCD_NLCDIOON (1 << 2) |
| 346 | #define SYS_CLCD_VDDPOSSWITCH (1 << 3) |
| 347 | #define SYS_CLCD_PWR3V5SWITCH (1 << 4) |
| 348 | #define SYS_CLCD_ID_MASK (0x1f << 8) |
| 349 | #define SYS_CLCD_ID_SANYO_3_8 (0x00 << 8) |
| 350 | #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8) |
| 351 | #define SYS_CLCD_ID_EPSON_2_2 (0x02 << 8) |
| 352 | #define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8) |
| 353 | #define SYS_CLCD_ID_VGA (0x1f << 8) |
| 354 | |
Catalin Marinas | 8ad68bb | 2005-10-31 14:25:02 +0000 | [diff] [blame] | 355 | /* |
| 356 | * Disable all display connectors on the interface module. |
| 357 | */ |
| 358 | static void realview_clcd_disable(struct clcd_fb *fb) |
| 359 | { |
| 360 | void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET; |
| 361 | u32 val; |
| 362 | |
| 363 | val = readl(sys_clcd); |
| 364 | val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH; |
| 365 | writel(val, sys_clcd); |
| 366 | } |
| 367 | |
| 368 | /* |
| 369 | * Enable the relevant connector on the interface module. |
| 370 | */ |
| 371 | static void realview_clcd_enable(struct clcd_fb *fb) |
| 372 | { |
| 373 | void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET; |
| 374 | u32 val; |
| 375 | |
Catalin Marinas | 9e7714d | 2006-03-16 14:10:20 +0000 | [diff] [blame] | 376 | /* |
| 377 | * Enable the PSUs |
| 378 | */ |
Catalin Marinas | 8ad68bb | 2005-10-31 14:25:02 +0000 | [diff] [blame] | 379 | val = readl(sys_clcd); |
Catalin Marinas | 8ad68bb | 2005-10-31 14:25:02 +0000 | [diff] [blame] | 380 | val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH; |
| 381 | writel(val, sys_clcd); |
| 382 | } |
| 383 | |
Russell King | 3cb5ee4 | 2011-01-18 20:13:20 +0000 | [diff] [blame] | 384 | /* |
| 385 | * Detect which LCD panel is connected, and return the appropriate |
| 386 | * clcd_panel structure. Note: we do not have any information on |
| 387 | * the required timings for the 8.4in panel, so we presently assume |
| 388 | * VGA timings. |
| 389 | */ |
Catalin Marinas | 8ad68bb | 2005-10-31 14:25:02 +0000 | [diff] [blame] | 390 | static int realview_clcd_setup(struct clcd_fb *fb) |
| 391 | { |
Russell King | 3cb5ee4 | 2011-01-18 20:13:20 +0000 | [diff] [blame] | 392 | void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET; |
| 393 | const char *panel_name, *vga_panel_name; |
Colin Tuckley | c34a102 | 2008-11-10 14:10:12 +0000 | [diff] [blame] | 394 | unsigned long framesize; |
Russell King | 3cb5ee4 | 2011-01-18 20:13:20 +0000 | [diff] [blame] | 395 | u32 val; |
Catalin Marinas | 8ad68bb | 2005-10-31 14:25:02 +0000 | [diff] [blame] | 396 | |
Russell King | 3cb5ee4 | 2011-01-18 20:13:20 +0000 | [diff] [blame] | 397 | if (machine_is_realview_eb()) { |
Colin Tuckley | c34a102 | 2008-11-10 14:10:12 +0000 | [diff] [blame] | 398 | /* VGA, 16bpp */ |
| 399 | framesize = 640 * 480 * 2; |
Russell King | 3cb5ee4 | 2011-01-18 20:13:20 +0000 | [diff] [blame] | 400 | vga_panel_name = "VGA"; |
| 401 | } else { |
Colin Tuckley | c34a102 | 2008-11-10 14:10:12 +0000 | [diff] [blame] | 402 | /* XVGA, 16bpp */ |
| 403 | framesize = 1024 * 768 * 2; |
Russell King | 3cb5ee4 | 2011-01-18 20:13:20 +0000 | [diff] [blame] | 404 | vga_panel_name = "XVGA"; |
Catalin Marinas | 8ad68bb | 2005-10-31 14:25:02 +0000 | [diff] [blame] | 405 | } |
| 406 | |
Russell King | 3cb5ee4 | 2011-01-18 20:13:20 +0000 | [diff] [blame] | 407 | val = readl(sys_clcd) & SYS_CLCD_ID_MASK; |
| 408 | if (val == SYS_CLCD_ID_SANYO_3_8) |
| 409 | panel_name = "Sanyo TM38QV67A02A"; |
| 410 | else if (val == SYS_CLCD_ID_SANYO_2_5) |
| 411 | panel_name = "Sanyo QVGA Portrait"; |
| 412 | else if (val == SYS_CLCD_ID_EPSON_2_2) |
| 413 | panel_name = "Epson L2F50113T00"; |
| 414 | else if (val == SYS_CLCD_ID_VGA) |
| 415 | panel_name = vga_panel_name; |
| 416 | else { |
| 417 | pr_err("CLCD: unknown LCD panel ID 0x%08x, using VGA\n", val); |
| 418 | panel_name = vga_panel_name; |
| 419 | } |
Catalin Marinas | 8ad68bb | 2005-10-31 14:25:02 +0000 | [diff] [blame] | 420 | |
Russell King | 3cb5ee4 | 2011-01-18 20:13:20 +0000 | [diff] [blame] | 421 | fb->panel = versatile_clcd_get_panel(panel_name); |
| 422 | if (!fb->panel) |
| 423 | return -EINVAL; |
Catalin Marinas | 8ad68bb | 2005-10-31 14:25:02 +0000 | [diff] [blame] | 424 | |
Russell King | 3cb5ee4 | 2011-01-18 20:13:20 +0000 | [diff] [blame] | 425 | return versatile_clcd_setup_dma(fb, framesize); |
Catalin Marinas | 8ad68bb | 2005-10-31 14:25:02 +0000 | [diff] [blame] | 426 | } |
| 427 | |
| 428 | struct clcd_board clcd_plat_data = { |
| 429 | .name = "RealView", |
Russell King | 3cb5ee4 | 2011-01-18 20:13:20 +0000 | [diff] [blame] | 430 | .caps = CLCD_CAP_ALL, |
Catalin Marinas | 8ad68bb | 2005-10-31 14:25:02 +0000 | [diff] [blame] | 431 | .check = clcdfb_check, |
| 432 | .decode = clcdfb_decode, |
| 433 | .disable = realview_clcd_disable, |
| 434 | .enable = realview_clcd_enable, |
| 435 | .setup = realview_clcd_setup, |
Russell King | 3cb5ee4 | 2011-01-18 20:13:20 +0000 | [diff] [blame] | 436 | .mmap = versatile_clcd_mmap_dma, |
| 437 | .remove = versatile_clcd_remove_dma, |
Catalin Marinas | 8ad68bb | 2005-10-31 14:25:02 +0000 | [diff] [blame] | 438 | }; |
| 439 | |
| 440 | #ifdef CONFIG_LEDS |
| 441 | #define VA_LEDS_BASE (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LED_OFFSET) |
| 442 | |
| 443 | void realview_leds_event(led_event_t ledevt) |
| 444 | { |
| 445 | unsigned long flags; |
| 446 | u32 val; |
Catalin Marinas | da055eb | 2009-05-30 13:56:16 +0100 | [diff] [blame] | 447 | u32 led = 1 << smp_processor_id(); |
Catalin Marinas | 8ad68bb | 2005-10-31 14:25:02 +0000 | [diff] [blame] | 448 | |
| 449 | local_irq_save(flags); |
| 450 | val = readl(VA_LEDS_BASE); |
| 451 | |
| 452 | switch (ledevt) { |
| 453 | case led_idle_start: |
Catalin Marinas | da055eb | 2009-05-30 13:56:16 +0100 | [diff] [blame] | 454 | val = val & ~led; |
Catalin Marinas | 8ad68bb | 2005-10-31 14:25:02 +0000 | [diff] [blame] | 455 | break; |
| 456 | |
| 457 | case led_idle_end: |
Catalin Marinas | da055eb | 2009-05-30 13:56:16 +0100 | [diff] [blame] | 458 | val = val | led; |
Catalin Marinas | 8ad68bb | 2005-10-31 14:25:02 +0000 | [diff] [blame] | 459 | break; |
| 460 | |
| 461 | case led_timer: |
Catalin Marinas | da055eb | 2009-05-30 13:56:16 +0100 | [diff] [blame] | 462 | val = val ^ REALVIEW_SYS_LED7; |
Catalin Marinas | 8ad68bb | 2005-10-31 14:25:02 +0000 | [diff] [blame] | 463 | break; |
| 464 | |
| 465 | case led_halted: |
| 466 | val = 0; |
| 467 | break; |
| 468 | |
| 469 | default: |
| 470 | break; |
| 471 | } |
| 472 | |
| 473 | writel(val, VA_LEDS_BASE); |
| 474 | local_irq_restore(flags); |
| 475 | } |
| 476 | #endif /* CONFIG_LEDS */ |
| 477 | |
| 478 | /* |
| 479 | * Where is the timer (VA)? |
| 480 | */ |
Catalin Marinas | 8019273 | 2008-04-18 22:43:11 +0100 | [diff] [blame] | 481 | void __iomem *timer0_va_base; |
| 482 | void __iomem *timer1_va_base; |
| 483 | void __iomem *timer2_va_base; |
| 484 | void __iomem *timer3_va_base; |
Catalin Marinas | 8ad68bb | 2005-10-31 14:25:02 +0000 | [diff] [blame] | 485 | |
| 486 | /* |
Catalin Marinas | a8655e8 | 2008-02-04 17:30:57 +0100 | [diff] [blame] | 487 | * Set up the clock source and clock events devices |
Catalin Marinas | 8ad68bb | 2005-10-31 14:25:02 +0000 | [diff] [blame] | 488 | */ |
Catalin Marinas | 8cc4c54 | 2008-02-04 17:43:02 +0100 | [diff] [blame] | 489 | void __init realview_timer_init(unsigned int timer_irq) |
Catalin Marinas | 8ad68bb | 2005-10-31 14:25:02 +0000 | [diff] [blame] | 490 | { |
| 491 | u32 val; |
| 492 | |
| 493 | /* |
| 494 | * set clock frequency: |
| 495 | * REALVIEW_REFCLK is 32KHz |
| 496 | * REALVIEW_TIMCLK is 1MHz |
| 497 | */ |
| 498 | val = readl(__io_address(REALVIEW_SCTL_BASE)); |
| 499 | writel((REALVIEW_TIMCLK << REALVIEW_TIMER1_EnSel) | |
| 500 | (REALVIEW_TIMCLK << REALVIEW_TIMER2_EnSel) | |
| 501 | (REALVIEW_TIMCLK << REALVIEW_TIMER3_EnSel) | |
| 502 | (REALVIEW_TIMCLK << REALVIEW_TIMER4_EnSel) | val, |
| 503 | __io_address(REALVIEW_SCTL_BASE)); |
| 504 | |
| 505 | /* |
| 506 | * Initialise to a known state (all timers off) |
| 507 | */ |
Catalin Marinas | 8019273 | 2008-04-18 22:43:11 +0100 | [diff] [blame] | 508 | writel(0, timer0_va_base + TIMER_CTRL); |
| 509 | writel(0, timer1_va_base + TIMER_CTRL); |
| 510 | writel(0, timer2_va_base + TIMER_CTRL); |
| 511 | writel(0, timer3_va_base + TIMER_CTRL); |
Catalin Marinas | 8ad68bb | 2005-10-31 14:25:02 +0000 | [diff] [blame] | 512 | |
Russell King | fb593cf | 2011-05-12 12:08:23 +0100 | [diff] [blame] | 513 | sp804_clocksource_init(timer3_va_base, "timer3"); |
Russell King | 57cc4f7 | 2011-05-12 15:31:13 +0100 | [diff] [blame] | 514 | sp804_clockevents_init(timer0_va_base, timer_irq, "timer0"); |
Catalin Marinas | 8ad68bb | 2005-10-31 14:25:02 +0000 | [diff] [blame] | 515 | } |
Catalin Marinas | 5b39d15 | 2009-11-04 12:19:04 +0000 | [diff] [blame] | 516 | |
| 517 | /* |
| 518 | * Setup the memory banks. |
| 519 | */ |
Russell King | 0744a3e | 2010-12-20 10:37:50 +0000 | [diff] [blame^] | 520 | void realview_fixup(struct tag *tags, char **from, struct meminfo *meminfo) |
Catalin Marinas | 5b39d15 | 2009-11-04 12:19:04 +0000 | [diff] [blame] | 521 | { |
| 522 | /* |
| 523 | * Most RealView platforms have 512MB contiguous RAM at 0x70000000. |
| 524 | * Half of this is mirrored at 0. |
| 525 | */ |
| 526 | #ifdef CONFIG_REALVIEW_HIGH_PHYS_OFFSET |
| 527 | meminfo->bank[0].start = 0x70000000; |
| 528 | meminfo->bank[0].size = SZ_512M; |
| 529 | meminfo->nr_banks = 1; |
| 530 | #else |
| 531 | meminfo->bank[0].start = 0; |
| 532 | meminfo->bank[0].size = SZ_256M; |
| 533 | meminfo->nr_banks = 1; |
| 534 | #endif |
| 535 | } |