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Catalin Marinas8ad68bb2005-10-31 14:25:02 +00001/*
2 * linux/arch/arm/mach-realview/core.c
3 *
4 * Copyright (C) 1999 - 2003 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
Catalin Marinas8ad68bb2005-10-31 14:25:02 +000021#include <linux/init.h>
Russell King1be72282005-10-31 16:57:06 +000022#include <linux/platform_device.h>
Catalin Marinas8ad68bb2005-10-31 14:25:02 +000023#include <linux/dma-mapping.h>
24#include <linux/sysdev.h>
25#include <linux/interrupt.h>
Russell Kinga62c80e2006-01-07 13:52:45 +000026#include <linux/amba/bus.h>
27#include <linux/amba/clcd.h>
Russell Kingfced80c2008-09-06 12:10:45 +010028#include <linux/io.h>
Steve Glendinningc5142e82009-01-20 13:23:30 +000029#include <linux/smsc911x.h>
Catalin Marinas6be62ba2009-02-12 15:59:21 +010030#include <linux/ata_platform.h>
Linus Walleij6ef297f2009-09-22 14:29:36 +010031#include <linux/amba/mmci.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090032#include <linux/gfp.h>
Jean-Christop PLAGNIOL-VILLARD6d803ba2010-11-17 10:04:33 +010033#include <linux/clkdev.h>
Marc Zyngierb8b87ae2011-05-18 10:51:49 +010034#include <linux/mtd/physmap.h>
Catalin Marinas8ad68bb2005-10-31 14:25:02 +000035
36#include <asm/system.h>
Russell Kinga09e64f2008-08-05 16:14:15 +010037#include <mach/hardware.h>
Catalin Marinas8ad68bb2005-10-31 14:25:02 +000038#include <asm/irq.h>
39#include <asm/leds.h>
Colin Tuckley68c3d932008-11-10 14:10:11 +000040#include <asm/mach-types.h>
Catalin Marinas8ad68bb2005-10-31 14:25:02 +000041#include <asm/hardware/arm_timer.h>
Russell Kingc5a0adb2010-01-16 20:16:10 +000042#include <asm/hardware/icst.h>
Catalin Marinas8ad68bb2005-10-31 14:25:02 +000043
44#include <asm/mach/arch.h>
Catalin Marinas8ad68bb2005-10-31 14:25:02 +000045#include <asm/mach/irq.h>
Catalin Marinas8ad68bb2005-10-31 14:25:02 +000046#include <asm/mach/map.h>
Catalin Marinas8ad68bb2005-10-31 14:25:02 +000047
48#include <asm/hardware/gic.h>
49
Catalin Marinasee8c9572009-05-30 14:00:17 +010050#include <mach/platform.h>
51#include <mach/irqs.h>
Rob Herring8a9618f2010-10-06 16:18:08 +010052#include <asm/hardware/timer-sp.h>
Catalin Marinasee8c9572009-05-30 14:00:17 +010053
Russell King3cb5ee42011-01-18 20:13:20 +000054#include <plat/clcd.h>
Russell King1da0c892010-12-15 21:56:47 +000055#include <plat/sched_clock.h>
56
Catalin Marinas8ad68bb2005-10-31 14:25:02 +000057#include "core.h"
Catalin Marinas8ad68bb2005-10-31 14:25:02 +000058
Catalin Marinas8ad68bb2005-10-31 14:25:02 +000059#define REALVIEW_FLASHCTRL (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_FLASH_OFFSET)
60
Marc Zyngier667f3902011-05-18 10:51:55 +010061static void realview_flash_set_vpp(struct platform_device *pdev, int on)
Catalin Marinas8ad68bb2005-10-31 14:25:02 +000062{
63 u32 val;
64
65 val = __raw_readl(REALVIEW_FLASHCTRL);
66 if (on)
67 val |= REALVIEW_FLASHPROG_FLVPPEN;
68 else
69 val &= ~REALVIEW_FLASHPROG_FLVPPEN;
70 __raw_writel(val, REALVIEW_FLASHCTRL);
71}
72
Marc Zyngierb8b87ae2011-05-18 10:51:49 +010073static struct physmap_flash_data realview_flash_data = {
Catalin Marinas8ad68bb2005-10-31 14:25:02 +000074 .width = 4,
Catalin Marinas8ad68bb2005-10-31 14:25:02 +000075 .set_vpp = realview_flash_set_vpp,
76};
77
Catalin Marinas8ad68bb2005-10-31 14:25:02 +000078struct platform_device realview_flash_device = {
Marc Zyngierb8b87ae2011-05-18 10:51:49 +010079 .name = "physmap-flash",
Catalin Marinas8ad68bb2005-10-31 14:25:02 +000080 .id = 0,
81 .dev = {
82 .platform_data = &realview_flash_data,
83 },
Catalin Marinas8ad68bb2005-10-31 14:25:02 +000084};
85
Catalin Marinasa44ddfd2008-04-18 22:43:10 +010086int realview_flash_register(struct resource *res, u32 num)
87{
88 realview_flash_device.resource = res;
89 realview_flash_device.num_resources = num;
90 return platform_device_register(&realview_flash_device);
91}
92
Steve Glendinningc5142e82009-01-20 13:23:30 +000093static struct smsc911x_platform_config smsc911x_config = {
94 .flags = SMSC911X_USE_32BIT,
95 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
96 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
97 .phy_interface = PHY_INTERFACE_MODE_MII,
Catalin Marinas0a5b2f62008-12-01 14:54:59 +000098};
99
Catalin Marinas0a381332008-12-01 14:54:58 +0000100static struct platform_device realview_eth_device = {
Steve Glendinningc5142e82009-01-20 13:23:30 +0000101 .name = "smsc911x",
Catalin Marinas0a381332008-12-01 14:54:58 +0000102 .id = 0,
103 .num_resources = 2,
104};
105
106int realview_eth_register(const char *name, struct resource *res)
107{
108 if (name)
109 realview_eth_device.name = name;
110 realview_eth_device.resource = res;
Steve Glendinningc5142e82009-01-20 13:23:30 +0000111 if (strcmp(realview_eth_device.name, "smsc911x") == 0)
112 realview_eth_device.dev.platform_data = &smsc911x_config;
Catalin Marinas0a381332008-12-01 14:54:58 +0000113
114 return platform_device_register(&realview_eth_device);
115}
116
Catalin Marinas7db21712009-02-12 16:00:21 +0100117struct platform_device realview_usb_device = {
118 .name = "isp1760",
119 .num_resources = 2,
120};
121
122int realview_usb_register(struct resource *res)
123{
124 realview_usb_device.resource = res;
125 return platform_device_register(&realview_usb_device);
126}
127
Catalin Marinas6be62ba2009-02-12 15:59:21 +0100128static struct pata_platform_info pata_platform_data = {
129 .ioport_shift = 1,
130};
131
132static struct resource pata_resources[] = {
133 [0] = {
134 .start = REALVIEW_CF_BASE,
135 .end = REALVIEW_CF_BASE + 0xff,
136 .flags = IORESOURCE_MEM,
137 },
138 [1] = {
139 .start = REALVIEW_CF_BASE + 0x100,
140 .end = REALVIEW_CF_BASE + SZ_4K - 1,
141 .flags = IORESOURCE_MEM,
142 },
143};
144
145struct platform_device realview_cf_device = {
146 .name = "pata_platform",
147 .id = -1,
148 .num_resources = ARRAY_SIZE(pata_resources),
149 .resource = pata_resources,
150 .dev = {
151 .platform_data = &pata_platform_data,
152 },
153};
154
Russell King6b65cd72006-12-10 21:21:32 +0100155static struct resource realview_i2c_resource = {
156 .start = REALVIEW_I2C_BASE,
157 .end = REALVIEW_I2C_BASE + SZ_4K - 1,
158 .flags = IORESOURCE_MEM,
159};
160
161struct platform_device realview_i2c_device = {
162 .name = "versatile-i2c",
Catalin Marinas533ad5e2009-02-12 15:58:20 +0100163 .id = 0,
Russell King6b65cd72006-12-10 21:21:32 +0100164 .num_resources = 1,
165 .resource = &realview_i2c_resource,
166};
167
Catalin Marinas533ad5e2009-02-12 15:58:20 +0100168static struct i2c_board_info realview_i2c_board_info[] = {
169 {
Russell King64e8be62009-07-18 15:51:55 +0100170 I2C_BOARD_INFO("ds1338", 0xd0 >> 1),
Catalin Marinas533ad5e2009-02-12 15:58:20 +0100171 },
172};
173
174static int __init realview_i2c_init(void)
175{
176 return i2c_register_board_info(0, realview_i2c_board_info,
177 ARRAY_SIZE(realview_i2c_board_info));
178}
179arch_initcall(realview_i2c_init);
180
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000181#define REALVIEW_SYSMCI (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_MCI_OFFSET)
182
Russell King98b09792009-07-09 15:17:41 +0100183/*
184 * This is only used if GPIOLIB support is disabled
185 */
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000186static unsigned int realview_mmc_status(struct device *dev)
187{
188 struct amba_device *adev = container_of(dev, struct amba_device, dev);
189 u32 mask;
190
Linus Walleij48f1d5a2010-07-02 10:24:03 +0100191 if (machine_is_realview_pb1176()) {
192 static bool inserted = false;
193
194 /*
195 * The PB1176 does not have the status register,
196 * assume it is inserted at startup, then invert
197 * for each call so card insertion/removal will
198 * be detected anyway. This will not be called if
199 * GPIO on PL061 is active, which is the proper
200 * way to do this on the PB1176.
201 */
202 inserted = !inserted;
203 return inserted ? 0 : 1;
204 }
205
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000206 if (adev->res.start == REALVIEW_MMCI0_BASE)
207 mask = 1;
208 else
209 mask = 2;
210
Russell King74bc8092010-07-29 15:58:59 +0100211 return readl(REALVIEW_SYSMCI) & mask;
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000212}
213
Linus Walleij6ef297f2009-09-22 14:29:36 +0100214struct mmci_platform_data realview_mmc0_plat_data = {
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000215 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
216 .status = realview_mmc_status,
Russell King98b09792009-07-09 15:17:41 +0100217 .gpio_wp = 17,
218 .gpio_cd = 16,
Rabin Vincent29719442010-08-09 12:54:43 +0100219 .cd_invert = true,
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000220};
221
Linus Walleij6ef297f2009-09-22 14:29:36 +0100222struct mmci_platform_data realview_mmc1_plat_data = {
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000223 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
224 .status = realview_mmc_status,
Russell King98b09792009-07-09 15:17:41 +0100225 .gpio_wp = 19,
226 .gpio_cd = 18,
Rabin Vincent29719442010-08-09 12:54:43 +0100227 .cd_invert = true,
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000228};
229
230/*
231 * Clock handling
232 */
Russell King39c0cb02010-01-16 16:27:28 +0000233static const struct icst_params realview_oscvco_params = {
Russell King64fceb12010-01-16 17:28:44 +0000234 .ref = 24000000,
Russell King4de2edb2010-01-16 18:08:47 +0000235 .vco_max = ICST307_VCO_MAX,
Russell Kinge73a46a2010-01-16 19:49:39 +0000236 .vco_min = ICST307_VCO_MIN,
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000237 .vd_min = 4 + 8,
238 .vd_max = 511 + 8,
239 .rd_min = 1 + 2,
240 .rd_max = 127 + 2,
Russell King232eaf72010-01-16 19:46:19 +0000241 .s2div = icst307_s2div,
242 .idx2s = icst307_idx2s,
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000243};
244
Russell King39c0cb02010-01-16 16:27:28 +0000245static void realview_oscvco_set(struct clk *clk, struct icst_vco vco)
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000246{
247 void __iomem *sys_lock = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LOCK_OFFSET;
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000248 u32 val;
249
Russell Kingd1914c72010-01-14 20:09:34 +0000250 val = readl(clk->vcoreg) & ~0x7ffff;
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000251 val |= vco.v | (vco.r << 9) | (vco.s << 16);
252
253 writel(0xa05f, sys_lock);
Russell Kingd1914c72010-01-14 20:09:34 +0000254 writel(val, clk->vcoreg);
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000255 writel(0, sys_lock);
256}
257
Russell King9bf5b2e2010-03-01 16:18:39 +0000258static const struct clk_ops oscvco_clk_ops = {
259 .round = icst_clk_round,
260 .set = icst_clk_set,
261 .setvco = realview_oscvco_set,
262};
263
Russell Kingcf30fb42008-11-08 20:05:55 +0000264static struct clk oscvco_clk = {
Russell King9bf5b2e2010-03-01 16:18:39 +0000265 .ops = &oscvco_clk_ops,
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000266 .params = &realview_oscvco_params,
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000267};
268
269/*
Russell Kingcf30fb42008-11-08 20:05:55 +0000270 * These are fixed clocks.
271 */
272static struct clk ref24_clk = {
273 .rate = 24000000,
274};
275
Russell King7ff550d2011-05-12 13:31:48 +0100276static struct clk sp804_clk = {
277 .rate = 1000000,
278};
279
Russell King3126c7b2010-07-15 11:01:17 +0100280static struct clk dummy_apb_pclk;
281
Russell Kingcf30fb42008-11-08 20:05:55 +0000282static struct clk_lookup lookups[] = {
Russell King3126c7b2010-07-15 11:01:17 +0100283 { /* Bus clock */
284 .con_id = "apb_pclk",
285 .clk = &dummy_apb_pclk,
286 }, { /* UART0 */
Linus Walleij43215322009-09-21 12:30:32 +0100287 .dev_id = "dev:uart0",
Russell Kingcf30fb42008-11-08 20:05:55 +0000288 .clk = &ref24_clk,
289 }, { /* UART1 */
Linus Walleij43215322009-09-21 12:30:32 +0100290 .dev_id = "dev:uart1",
Russell Kingcf30fb42008-11-08 20:05:55 +0000291 .clk = &ref24_clk,
292 }, { /* UART2 */
Linus Walleij43215322009-09-21 12:30:32 +0100293 .dev_id = "dev:uart2",
Russell Kingcf30fb42008-11-08 20:05:55 +0000294 .clk = &ref24_clk,
295 }, { /* UART3 */
Linus Walleij43215322009-09-21 12:30:32 +0100296 .dev_id = "fpga:uart3",
Russell Kingcf30fb42008-11-08 20:05:55 +0000297 .clk = &ref24_clk,
Linus Walleij48f1d5a2010-07-02 10:24:03 +0100298 }, { /* UART3 is on the dev chip in PB1176 */
299 .dev_id = "dev:uart3",
300 .clk = &ref24_clk,
301 }, { /* UART4 only exists in PB1176 */
302 .dev_id = "fpga:uart4",
303 .clk = &ref24_clk,
Russell Kingcf30fb42008-11-08 20:05:55 +0000304 }, { /* KMI0 */
Linus Walleij43215322009-09-21 12:30:32 +0100305 .dev_id = "fpga:kmi0",
Russell Kingcf30fb42008-11-08 20:05:55 +0000306 .clk = &ref24_clk,
307 }, { /* KMI1 */
Linus Walleij43215322009-09-21 12:30:32 +0100308 .dev_id = "fpga:kmi1",
Russell Kingcf30fb42008-11-08 20:05:55 +0000309 .clk = &ref24_clk,
310 }, { /* MMC0 */
Linus Walleij43215322009-09-21 12:30:32 +0100311 .dev_id = "fpga:mmc0",
Russell Kingcf30fb42008-11-08 20:05:55 +0000312 .clk = &ref24_clk,
Linus Walleij48f1d5a2010-07-02 10:24:03 +0100313 }, { /* CLCD is in the PB1176 and EB DevChip */
Linus Walleij43215322009-09-21 12:30:32 +0100314 .dev_id = "dev:clcd",
Russell Kingcf30fb42008-11-08 20:05:55 +0000315 .clk = &oscvco_clk,
316 }, { /* PB:CLCD */
Linus Walleij43215322009-09-21 12:30:32 +0100317 .dev_id = "issp:clcd",
Russell Kingcf30fb42008-11-08 20:05:55 +0000318 .clk = &oscvco_clk,
Linus Walleijd6ada862010-07-14 23:58:38 +0100319 }, { /* SSP */
320 .dev_id = "dev:ssp0",
321 .clk = &ref24_clk,
Russell King7ff550d2011-05-12 13:31:48 +0100322 }, { /* SP804 timers */
323 .dev_id = "sp804",
324 .clk = &sp804_clk,
325 },
Russell Kingcf30fb42008-11-08 20:05:55 +0000326};
327
Russell King631e55f2011-01-11 13:05:01 +0000328void __init realview_init_early(void)
Russell Kingcf30fb42008-11-08 20:05:55 +0000329{
Russell King631e55f2011-01-11 13:05:01 +0000330 void __iomem *sys = __io_address(REALVIEW_SYS_BASE);
331
Russell Kingd1914c72010-01-14 20:09:34 +0000332 if (machine_is_realview_pb1176())
Russell King631e55f2011-01-11 13:05:01 +0000333 oscvco_clk.vcoreg = sys + REALVIEW_SYS_OSC0_OFFSET;
Russell Kingd1914c72010-01-14 20:09:34 +0000334 else
Russell King631e55f2011-01-11 13:05:01 +0000335 oscvco_clk.vcoreg = sys + REALVIEW_SYS_OSC4_OFFSET;
Russell Kingd1914c72010-01-14 20:09:34 +0000336
Russell King0a0300d2010-01-12 12:28:00 +0000337 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
Russell Kingd1914c72010-01-14 20:09:34 +0000338
Russell King631e55f2011-01-11 13:05:01 +0000339 versatile_sched_clock_init(sys + REALVIEW_SYS_24MHz_OFFSET, 24000000);
Russell Kingcf30fb42008-11-08 20:05:55 +0000340}
Russell Kingcf30fb42008-11-08 20:05:55 +0000341
342/*
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000343 * CLCD support.
344 */
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000345#define SYS_CLCD_NLCDIOON (1 << 2)
346#define SYS_CLCD_VDDPOSSWITCH (1 << 3)
347#define SYS_CLCD_PWR3V5SWITCH (1 << 4)
348#define SYS_CLCD_ID_MASK (0x1f << 8)
349#define SYS_CLCD_ID_SANYO_3_8 (0x00 << 8)
350#define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
351#define SYS_CLCD_ID_EPSON_2_2 (0x02 << 8)
352#define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8)
353#define SYS_CLCD_ID_VGA (0x1f << 8)
354
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000355/*
356 * Disable all display connectors on the interface module.
357 */
358static void realview_clcd_disable(struct clcd_fb *fb)
359{
360 void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
361 u32 val;
362
363 val = readl(sys_clcd);
364 val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
365 writel(val, sys_clcd);
366}
367
368/*
369 * Enable the relevant connector on the interface module.
370 */
371static void realview_clcd_enable(struct clcd_fb *fb)
372{
373 void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
374 u32 val;
375
Catalin Marinas9e7714d2006-03-16 14:10:20 +0000376 /*
377 * Enable the PSUs
378 */
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000379 val = readl(sys_clcd);
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000380 val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
381 writel(val, sys_clcd);
382}
383
Russell King3cb5ee42011-01-18 20:13:20 +0000384/*
385 * Detect which LCD panel is connected, and return the appropriate
386 * clcd_panel structure. Note: we do not have any information on
387 * the required timings for the 8.4in panel, so we presently assume
388 * VGA timings.
389 */
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000390static int realview_clcd_setup(struct clcd_fb *fb)
391{
Russell King3cb5ee42011-01-18 20:13:20 +0000392 void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
393 const char *panel_name, *vga_panel_name;
Colin Tuckleyc34a1022008-11-10 14:10:12 +0000394 unsigned long framesize;
Russell King3cb5ee42011-01-18 20:13:20 +0000395 u32 val;
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000396
Russell King3cb5ee42011-01-18 20:13:20 +0000397 if (machine_is_realview_eb()) {
Colin Tuckleyc34a1022008-11-10 14:10:12 +0000398 /* VGA, 16bpp */
399 framesize = 640 * 480 * 2;
Russell King3cb5ee42011-01-18 20:13:20 +0000400 vga_panel_name = "VGA";
401 } else {
Colin Tuckleyc34a1022008-11-10 14:10:12 +0000402 /* XVGA, 16bpp */
403 framesize = 1024 * 768 * 2;
Russell King3cb5ee42011-01-18 20:13:20 +0000404 vga_panel_name = "XVGA";
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000405 }
406
Russell King3cb5ee42011-01-18 20:13:20 +0000407 val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
408 if (val == SYS_CLCD_ID_SANYO_3_8)
409 panel_name = "Sanyo TM38QV67A02A";
410 else if (val == SYS_CLCD_ID_SANYO_2_5)
411 panel_name = "Sanyo QVGA Portrait";
412 else if (val == SYS_CLCD_ID_EPSON_2_2)
413 panel_name = "Epson L2F50113T00";
414 else if (val == SYS_CLCD_ID_VGA)
415 panel_name = vga_panel_name;
416 else {
417 pr_err("CLCD: unknown LCD panel ID 0x%08x, using VGA\n", val);
418 panel_name = vga_panel_name;
419 }
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000420
Russell King3cb5ee42011-01-18 20:13:20 +0000421 fb->panel = versatile_clcd_get_panel(panel_name);
422 if (!fb->panel)
423 return -EINVAL;
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000424
Russell King3cb5ee42011-01-18 20:13:20 +0000425 return versatile_clcd_setup_dma(fb, framesize);
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000426}
427
428struct clcd_board clcd_plat_data = {
429 .name = "RealView",
Russell King3cb5ee42011-01-18 20:13:20 +0000430 .caps = CLCD_CAP_ALL,
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000431 .check = clcdfb_check,
432 .decode = clcdfb_decode,
433 .disable = realview_clcd_disable,
434 .enable = realview_clcd_enable,
435 .setup = realview_clcd_setup,
Russell King3cb5ee42011-01-18 20:13:20 +0000436 .mmap = versatile_clcd_mmap_dma,
437 .remove = versatile_clcd_remove_dma,
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000438};
439
440#ifdef CONFIG_LEDS
441#define VA_LEDS_BASE (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LED_OFFSET)
442
443void realview_leds_event(led_event_t ledevt)
444{
445 unsigned long flags;
446 u32 val;
Catalin Marinasda055eb2009-05-30 13:56:16 +0100447 u32 led = 1 << smp_processor_id();
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000448
449 local_irq_save(flags);
450 val = readl(VA_LEDS_BASE);
451
452 switch (ledevt) {
453 case led_idle_start:
Catalin Marinasda055eb2009-05-30 13:56:16 +0100454 val = val & ~led;
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000455 break;
456
457 case led_idle_end:
Catalin Marinasda055eb2009-05-30 13:56:16 +0100458 val = val | led;
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000459 break;
460
461 case led_timer:
Catalin Marinasda055eb2009-05-30 13:56:16 +0100462 val = val ^ REALVIEW_SYS_LED7;
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000463 break;
464
465 case led_halted:
466 val = 0;
467 break;
468
469 default:
470 break;
471 }
472
473 writel(val, VA_LEDS_BASE);
474 local_irq_restore(flags);
475}
476#endif /* CONFIG_LEDS */
477
478/*
479 * Where is the timer (VA)?
480 */
Catalin Marinas80192732008-04-18 22:43:11 +0100481void __iomem *timer0_va_base;
482void __iomem *timer1_va_base;
483void __iomem *timer2_va_base;
484void __iomem *timer3_va_base;
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000485
486/*
Catalin Marinasa8655e82008-02-04 17:30:57 +0100487 * Set up the clock source and clock events devices
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000488 */
Catalin Marinas8cc4c542008-02-04 17:43:02 +0100489void __init realview_timer_init(unsigned int timer_irq)
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000490{
491 u32 val;
492
493 /*
494 * set clock frequency:
495 * REALVIEW_REFCLK is 32KHz
496 * REALVIEW_TIMCLK is 1MHz
497 */
498 val = readl(__io_address(REALVIEW_SCTL_BASE));
499 writel((REALVIEW_TIMCLK << REALVIEW_TIMER1_EnSel) |
500 (REALVIEW_TIMCLK << REALVIEW_TIMER2_EnSel) |
501 (REALVIEW_TIMCLK << REALVIEW_TIMER3_EnSel) |
502 (REALVIEW_TIMCLK << REALVIEW_TIMER4_EnSel) | val,
503 __io_address(REALVIEW_SCTL_BASE));
504
505 /*
506 * Initialise to a known state (all timers off)
507 */
Catalin Marinas80192732008-04-18 22:43:11 +0100508 writel(0, timer0_va_base + TIMER_CTRL);
509 writel(0, timer1_va_base + TIMER_CTRL);
510 writel(0, timer2_va_base + TIMER_CTRL);
511 writel(0, timer3_va_base + TIMER_CTRL);
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000512
Russell Kingfb593cf2011-05-12 12:08:23 +0100513 sp804_clocksource_init(timer3_va_base, "timer3");
Russell King57cc4f72011-05-12 15:31:13 +0100514 sp804_clockevents_init(timer0_va_base, timer_irq, "timer0");
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000515}
Catalin Marinas5b39d152009-11-04 12:19:04 +0000516
517/*
518 * Setup the memory banks.
519 */
Russell King0744a3e2010-12-20 10:37:50 +0000520void realview_fixup(struct tag *tags, char **from, struct meminfo *meminfo)
Catalin Marinas5b39d152009-11-04 12:19:04 +0000521{
522 /*
523 * Most RealView platforms have 512MB contiguous RAM at 0x70000000.
524 * Half of this is mirrored at 0.
525 */
526#ifdef CONFIG_REALVIEW_HIGH_PHYS_OFFSET
527 meminfo->bank[0].start = 0x70000000;
528 meminfo->bank[0].size = SZ_512M;
529 meminfo->nr_banks = 1;
530#else
531 meminfo->bank[0].start = 0;
532 meminfo->bank[0].size = SZ_256M;
533 meminfo->nr_banks = 1;
534#endif
535}