| Laxman Dewangan | e9ea096 | 2013-01-08 16:27:44 +0530 | [diff] [blame] | 1 | NVIDIA Tegra20/Tegra30 high speed (DMA based) UART controller driver. |
| 2 | |
| 3 | Required properties: |
| 4 | - compatible : should be "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart". |
| 5 | - reg: Should contain UART controller registers location and length. |
| 6 | - interrupts: Should contain UART controller interrupts. |
| 7 | - nvidia,dma-request-selector : The Tegra DMA controller's phandle and |
| 8 | request selector for this UART controller. |
| Stephen Warren | d8f6479 | 2013-11-06 14:00:25 -0700 | [diff] [blame] | 9 | - clocks: Must contain one entry, for the module clock. |
| 10 | See ../clocks/clock-bindings.txt for details. |
| Stephen Warren | 0799958 | 2013-11-07 10:11:27 -0700 | [diff] [blame^] | 11 | - resets : Must contain an entry for each entry in reset-names. |
| 12 | See ../reset/reset.txt for details. |
| 13 | - reset-names : Must include the following entries: |
| 14 | - serial |
| Laxman Dewangan | e9ea096 | 2013-01-08 16:27:44 +0530 | [diff] [blame] | 15 | |
| 16 | Optional properties: |
| 17 | - nvidia,enable-modem-interrupt: Enable modem interrupts. Should be enable |
| 18 | only if all 8 lines of UART controller are pinmuxed. |
| 19 | |
| 20 | Example: |
| 21 | |
| 22 | serial@70006000 { |
| 23 | compatible = "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart"; |
| 24 | reg = <0x70006000 0x40>; |
| 25 | reg-shift = <2>; |
| 26 | interrupts = <0 36 0x04>; |
| 27 | nvidia,dma-request-selector = <&apbdma 8>; |
| 28 | nvidia,enable-modem-interrupt; |
| Stephen Warren | d8f6479 | 2013-11-06 14:00:25 -0700 | [diff] [blame] | 29 | clocks = <&tegra_car 6>; |
| Stephen Warren | 0799958 | 2013-11-07 10:11:27 -0700 | [diff] [blame^] | 30 | resets = <&tegra_car 6>; |
| 31 | reset-names = "serial"; |
| Laxman Dewangan | e9ea096 | 2013-01-08 16:27:44 +0530 | [diff] [blame] | 32 | status = "disabled"; |
| 33 | }; |