Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1 | /* |
| 2 | * DMA driver for Xilinx Video DMA Engine |
| 3 | * |
| 4 | * Copyright (C) 2010-2014 Xilinx, Inc. All rights reserved. |
| 5 | * |
| 6 | * Based on the Freescale DMA driver. |
| 7 | * |
| 8 | * Description: |
| 9 | * The AXI Video Direct Memory Access (AXI VDMA) core is a soft Xilinx IP |
| 10 | * core that provides high-bandwidth direct memory access between memory |
| 11 | * and AXI4-Stream type video target peripherals. The core provides efficient |
| 12 | * two dimensional DMA operations with independent asynchronous read (S2MM) |
| 13 | * and write (MM2S) channel operation. It can be configured to have either |
| 14 | * one channel or two channels. If configured as two channels, one is to |
| 15 | * transmit to the video device (MM2S) and another is to receive from the |
| 16 | * video device (S2MM). Initialization, status, interrupt and management |
| 17 | * registers are accessed through an AXI4-Lite slave interface. |
| 18 | * |
Kedareswara rao Appana | c0bba3a | 2016-04-07 10:59:43 +0530 | [diff] [blame] | 19 | * The AXI Direct Memory Access (AXI DMA) core is a soft Xilinx IP core that |
| 20 | * provides high-bandwidth one dimensional direct memory access between memory |
| 21 | * and AXI4-Stream target peripherals. It supports one receive and one |
| 22 | * transmit channel, both of them optional at synthesis time. |
| 23 | * |
Kedareswara rao Appana | 07b0e7d | 2016-04-07 10:59:45 +0530 | [diff] [blame^] | 24 | * The AXI CDMA, is a soft IP, which provides high-bandwidth Direct Memory |
| 25 | * Access (DMA) between a memory-mapped source address and a memory-mapped |
| 26 | * destination address. |
| 27 | * |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 28 | * This program is free software: you can redistribute it and/or modify |
| 29 | * it under the terms of the GNU General Public License as published by |
| 30 | * the Free Software Foundation, either version 2 of the License, or |
| 31 | * (at your option) any later version. |
| 32 | */ |
| 33 | |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 34 | #include <linux/bitops.h> |
| 35 | #include <linux/dmapool.h> |
Kedareswara rao Appana | 937abe8 | 2015-03-02 23:24:24 +0530 | [diff] [blame] | 36 | #include <linux/dma/xilinx_dma.h> |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 37 | #include <linux/init.h> |
| 38 | #include <linux/interrupt.h> |
| 39 | #include <linux/io.h> |
Kedareswara rao Appana | 9495f26 | 2016-02-26 19:33:54 +0530 | [diff] [blame] | 40 | #include <linux/iopoll.h> |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 41 | #include <linux/module.h> |
| 42 | #include <linux/of_address.h> |
| 43 | #include <linux/of_dma.h> |
| 44 | #include <linux/of_platform.h> |
| 45 | #include <linux/of_irq.h> |
| 46 | #include <linux/slab.h> |
| 47 | |
| 48 | #include "../dmaengine.h" |
| 49 | |
| 50 | /* Register/Descriptor Offsets */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 51 | #define XILINX_DMA_MM2S_CTRL_OFFSET 0x0000 |
| 52 | #define XILINX_DMA_S2MM_CTRL_OFFSET 0x0030 |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 53 | #define XILINX_VDMA_MM2S_DESC_OFFSET 0x0050 |
| 54 | #define XILINX_VDMA_S2MM_DESC_OFFSET 0x00a0 |
| 55 | |
| 56 | /* Control Registers */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 57 | #define XILINX_DMA_REG_DMACR 0x0000 |
| 58 | #define XILINX_DMA_DMACR_DELAY_MAX 0xff |
| 59 | #define XILINX_DMA_DMACR_DELAY_SHIFT 24 |
| 60 | #define XILINX_DMA_DMACR_FRAME_COUNT_MAX 0xff |
| 61 | #define XILINX_DMA_DMACR_FRAME_COUNT_SHIFT 16 |
| 62 | #define XILINX_DMA_DMACR_ERR_IRQ BIT(14) |
| 63 | #define XILINX_DMA_DMACR_DLY_CNT_IRQ BIT(13) |
| 64 | #define XILINX_DMA_DMACR_FRM_CNT_IRQ BIT(12) |
| 65 | #define XILINX_DMA_DMACR_MASTER_SHIFT 8 |
| 66 | #define XILINX_DMA_DMACR_FSYNCSRC_SHIFT 5 |
| 67 | #define XILINX_DMA_DMACR_FRAMECNT_EN BIT(4) |
| 68 | #define XILINX_DMA_DMACR_GENLOCK_EN BIT(3) |
| 69 | #define XILINX_DMA_DMACR_RESET BIT(2) |
| 70 | #define XILINX_DMA_DMACR_CIRC_EN BIT(1) |
| 71 | #define XILINX_DMA_DMACR_RUNSTOP BIT(0) |
| 72 | #define XILINX_DMA_DMACR_FSYNCSRC_MASK GENMASK(6, 5) |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 73 | |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 74 | #define XILINX_DMA_REG_DMASR 0x0004 |
| 75 | #define XILINX_DMA_DMASR_EOL_LATE_ERR BIT(15) |
| 76 | #define XILINX_DMA_DMASR_ERR_IRQ BIT(14) |
| 77 | #define XILINX_DMA_DMASR_DLY_CNT_IRQ BIT(13) |
| 78 | #define XILINX_DMA_DMASR_FRM_CNT_IRQ BIT(12) |
| 79 | #define XILINX_DMA_DMASR_SOF_LATE_ERR BIT(11) |
| 80 | #define XILINX_DMA_DMASR_SG_DEC_ERR BIT(10) |
| 81 | #define XILINX_DMA_DMASR_SG_SLV_ERR BIT(9) |
| 82 | #define XILINX_DMA_DMASR_EOF_EARLY_ERR BIT(8) |
| 83 | #define XILINX_DMA_DMASR_SOF_EARLY_ERR BIT(7) |
| 84 | #define XILINX_DMA_DMASR_DMA_DEC_ERR BIT(6) |
| 85 | #define XILINX_DMA_DMASR_DMA_SLAVE_ERR BIT(5) |
| 86 | #define XILINX_DMA_DMASR_DMA_INT_ERR BIT(4) |
| 87 | #define XILINX_DMA_DMASR_IDLE BIT(1) |
| 88 | #define XILINX_DMA_DMASR_HALTED BIT(0) |
| 89 | #define XILINX_DMA_DMASR_DELAY_MASK GENMASK(31, 24) |
| 90 | #define XILINX_DMA_DMASR_FRAME_COUNT_MASK GENMASK(23, 16) |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 91 | |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 92 | #define XILINX_DMA_REG_CURDESC 0x0008 |
| 93 | #define XILINX_DMA_REG_TAILDESC 0x0010 |
| 94 | #define XILINX_DMA_REG_REG_INDEX 0x0014 |
| 95 | #define XILINX_DMA_REG_FRMSTORE 0x0018 |
| 96 | #define XILINX_DMA_REG_THRESHOLD 0x001c |
| 97 | #define XILINX_DMA_REG_FRMPTR_STS 0x0024 |
| 98 | #define XILINX_DMA_REG_PARK_PTR 0x0028 |
| 99 | #define XILINX_DMA_PARK_PTR_WR_REF_SHIFT 8 |
| 100 | #define XILINX_DMA_PARK_PTR_RD_REF_SHIFT 0 |
| 101 | #define XILINX_DMA_REG_VDMA_VERSION 0x002c |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 102 | |
| 103 | /* Register Direct Mode Registers */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 104 | #define XILINX_DMA_REG_VSIZE 0x0000 |
| 105 | #define XILINX_DMA_REG_HSIZE 0x0004 |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 106 | |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 107 | #define XILINX_DMA_REG_FRMDLY_STRIDE 0x0008 |
| 108 | #define XILINX_DMA_FRMDLY_STRIDE_FRMDLY_SHIFT 24 |
| 109 | #define XILINX_DMA_FRMDLY_STRIDE_STRIDE_SHIFT 0 |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 110 | |
| 111 | #define XILINX_VDMA_REG_START_ADDRESS(n) (0x000c + 4 * (n)) |
Kedareswara rao Appana | b72db40 | 2016-04-06 10:38:08 +0530 | [diff] [blame] | 112 | #define XILINX_VDMA_REG_START_ADDRESS_64(n) (0x000c + 8 * (n)) |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 113 | |
| 114 | /* HW specific definitions */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 115 | #define XILINX_DMA_MAX_CHANS_PER_DEVICE 0x2 |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 116 | |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 117 | #define XILINX_DMA_DMAXR_ALL_IRQ_MASK \ |
| 118 | (XILINX_DMA_DMASR_FRM_CNT_IRQ | \ |
| 119 | XILINX_DMA_DMASR_DLY_CNT_IRQ | \ |
| 120 | XILINX_DMA_DMASR_ERR_IRQ) |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 121 | |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 122 | #define XILINX_DMA_DMASR_ALL_ERR_MASK \ |
| 123 | (XILINX_DMA_DMASR_EOL_LATE_ERR | \ |
| 124 | XILINX_DMA_DMASR_SOF_LATE_ERR | \ |
| 125 | XILINX_DMA_DMASR_SG_DEC_ERR | \ |
| 126 | XILINX_DMA_DMASR_SG_SLV_ERR | \ |
| 127 | XILINX_DMA_DMASR_EOF_EARLY_ERR | \ |
| 128 | XILINX_DMA_DMASR_SOF_EARLY_ERR | \ |
| 129 | XILINX_DMA_DMASR_DMA_DEC_ERR | \ |
| 130 | XILINX_DMA_DMASR_DMA_SLAVE_ERR | \ |
| 131 | XILINX_DMA_DMASR_DMA_INT_ERR) |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 132 | |
| 133 | /* |
| 134 | * Recoverable errors are DMA Internal error, SOF Early, EOF Early |
| 135 | * and SOF Late. They are only recoverable when C_FLUSH_ON_FSYNC |
| 136 | * is enabled in the h/w system. |
| 137 | */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 138 | #define XILINX_DMA_DMASR_ERR_RECOVER_MASK \ |
| 139 | (XILINX_DMA_DMASR_SOF_LATE_ERR | \ |
| 140 | XILINX_DMA_DMASR_EOF_EARLY_ERR | \ |
| 141 | XILINX_DMA_DMASR_SOF_EARLY_ERR | \ |
| 142 | XILINX_DMA_DMASR_DMA_INT_ERR) |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 143 | |
| 144 | /* Axi VDMA Flush on Fsync bits */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 145 | #define XILINX_DMA_FLUSH_S2MM 3 |
| 146 | #define XILINX_DMA_FLUSH_MM2S 2 |
| 147 | #define XILINX_DMA_FLUSH_BOTH 1 |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 148 | |
| 149 | /* Delay loop counter to prevent hardware failure */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 150 | #define XILINX_DMA_LOOP_COUNT 1000000 |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 151 | |
Kedareswara rao Appana | c0bba3a | 2016-04-07 10:59:43 +0530 | [diff] [blame] | 152 | /* AXI DMA Specific Registers/Offsets */ |
| 153 | #define XILINX_DMA_REG_SRCDSTADDR 0x18 |
| 154 | #define XILINX_DMA_REG_BTT 0x28 |
| 155 | |
| 156 | /* AXI DMA Specific Masks/Bit fields */ |
| 157 | #define XILINX_DMA_MAX_TRANS_LEN GENMASK(22, 0) |
| 158 | #define XILINX_DMA_CR_COALESCE_MAX GENMASK(23, 16) |
| 159 | #define XILINX_DMA_CR_COALESCE_SHIFT 16 |
| 160 | #define XILINX_DMA_BD_SOP BIT(27) |
| 161 | #define XILINX_DMA_BD_EOP BIT(26) |
| 162 | #define XILINX_DMA_COALESCE_MAX 255 |
| 163 | #define XILINX_DMA_NUM_APP_WORDS 5 |
| 164 | |
Kedareswara rao Appana | 07b0e7d | 2016-04-07 10:59:45 +0530 | [diff] [blame^] | 165 | /* AXI CDMA Specific Registers/Offsets */ |
| 166 | #define XILINX_CDMA_REG_SRCADDR 0x18 |
| 167 | #define XILINX_CDMA_REG_DSTADDR 0x20 |
| 168 | |
| 169 | /* AXI CDMA Specific Masks */ |
| 170 | #define XILINX_CDMA_CR_SGMODE BIT(3) |
| 171 | |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 172 | /** |
| 173 | * struct xilinx_vdma_desc_hw - Hardware Descriptor |
| 174 | * @next_desc: Next Descriptor Pointer @0x00 |
| 175 | * @pad1: Reserved @0x04 |
| 176 | * @buf_addr: Buffer address @0x08 |
Kedareswara rao Appana | b72db40 | 2016-04-06 10:38:08 +0530 | [diff] [blame] | 177 | * @buf_addr_msb: MSB of Buffer address @0x0C |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 178 | * @vsize: Vertical Size @0x10 |
| 179 | * @hsize: Horizontal Size @0x14 |
| 180 | * @stride: Number of bytes between the first |
| 181 | * pixels of each horizontal line @0x18 |
| 182 | */ |
| 183 | struct xilinx_vdma_desc_hw { |
| 184 | u32 next_desc; |
| 185 | u32 pad1; |
| 186 | u32 buf_addr; |
Kedareswara rao Appana | b72db40 | 2016-04-06 10:38:08 +0530 | [diff] [blame] | 187 | u32 buf_addr_msb; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 188 | u32 vsize; |
| 189 | u32 hsize; |
| 190 | u32 stride; |
| 191 | } __aligned(64); |
| 192 | |
| 193 | /** |
Kedareswara rao Appana | c0bba3a | 2016-04-07 10:59:43 +0530 | [diff] [blame] | 194 | * struct xilinx_axidma_desc_hw - Hardware Descriptor for AXI DMA |
| 195 | * @next_desc: Next Descriptor Pointer @0x00 |
| 196 | * @pad1: Reserved @0x04 |
| 197 | * @buf_addr: Buffer address @0x08 |
| 198 | * @pad2: Reserved @0x0C |
| 199 | * @pad3: Reserved @0x10 |
| 200 | * @pad4: Reserved @0x14 |
| 201 | * @control: Control field @0x18 |
| 202 | * @status: Status field @0x1C |
| 203 | * @app: APP Fields @0x20 - 0x30 |
| 204 | */ |
| 205 | struct xilinx_axidma_desc_hw { |
| 206 | u32 next_desc; |
| 207 | u32 pad1; |
| 208 | u32 buf_addr; |
| 209 | u32 pad2; |
| 210 | u32 pad3; |
| 211 | u32 pad4; |
| 212 | u32 control; |
| 213 | u32 status; |
| 214 | u32 app[XILINX_DMA_NUM_APP_WORDS]; |
| 215 | } __aligned(64); |
| 216 | |
| 217 | /** |
Kedareswara rao Appana | 07b0e7d | 2016-04-07 10:59:45 +0530 | [diff] [blame^] | 218 | * struct xilinx_cdma_desc_hw - Hardware Descriptor |
| 219 | * @next_desc: Next Descriptor Pointer @0x00 |
| 220 | * @pad1: Reserved @0x04 |
| 221 | * @src_addr: Source address @0x08 |
| 222 | * @pad2: Reserved @0x0C |
| 223 | * @dest_addr: Destination address @0x10 |
| 224 | * @pad3: Reserved @0x14 |
| 225 | * @control: Control field @0x18 |
| 226 | * @status: Status field @0x1C |
| 227 | */ |
| 228 | struct xilinx_cdma_desc_hw { |
| 229 | u32 next_desc; |
| 230 | u32 pad1; |
| 231 | u32 src_addr; |
| 232 | u32 pad2; |
| 233 | u32 dest_addr; |
| 234 | u32 pad3; |
| 235 | u32 control; |
| 236 | u32 status; |
| 237 | } __aligned(64); |
| 238 | |
| 239 | /** |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 240 | * struct xilinx_vdma_tx_segment - Descriptor segment |
| 241 | * @hw: Hardware descriptor |
| 242 | * @node: Node in the descriptor segments list |
| 243 | * @phys: Physical address of segment |
| 244 | */ |
| 245 | struct xilinx_vdma_tx_segment { |
| 246 | struct xilinx_vdma_desc_hw hw; |
| 247 | struct list_head node; |
| 248 | dma_addr_t phys; |
| 249 | } __aligned(64); |
| 250 | |
| 251 | /** |
Kedareswara rao Appana | c0bba3a | 2016-04-07 10:59:43 +0530 | [diff] [blame] | 252 | * struct xilinx_axidma_tx_segment - Descriptor segment |
| 253 | * @hw: Hardware descriptor |
| 254 | * @node: Node in the descriptor segments list |
| 255 | * @phys: Physical address of segment |
| 256 | */ |
| 257 | struct xilinx_axidma_tx_segment { |
| 258 | struct xilinx_axidma_desc_hw hw; |
| 259 | struct list_head node; |
| 260 | dma_addr_t phys; |
| 261 | } __aligned(64); |
| 262 | |
| 263 | /** |
Kedareswara rao Appana | 07b0e7d | 2016-04-07 10:59:45 +0530 | [diff] [blame^] | 264 | * struct xilinx_cdma_tx_segment - Descriptor segment |
| 265 | * @hw: Hardware descriptor |
| 266 | * @node: Node in the descriptor segments list |
| 267 | * @phys: Physical address of segment |
| 268 | */ |
| 269 | struct xilinx_cdma_tx_segment { |
| 270 | struct xilinx_cdma_desc_hw hw; |
| 271 | struct list_head node; |
| 272 | dma_addr_t phys; |
| 273 | } __aligned(64); |
| 274 | |
| 275 | /** |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 276 | * struct xilinx_dma_tx_descriptor - Per Transaction structure |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 277 | * @async_tx: Async transaction descriptor |
| 278 | * @segments: TX segments list |
| 279 | * @node: Node in the channel descriptors list |
| 280 | */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 281 | struct xilinx_dma_tx_descriptor { |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 282 | struct dma_async_tx_descriptor async_tx; |
| 283 | struct list_head segments; |
| 284 | struct list_head node; |
| 285 | }; |
| 286 | |
| 287 | /** |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 288 | * struct xilinx_dma_chan - Driver specific DMA channel structure |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 289 | * @xdev: Driver specific device structure |
| 290 | * @ctrl_offset: Control registers offset |
| 291 | * @desc_offset: TX descriptor registers offset |
| 292 | * @lock: Descriptor operation lock |
| 293 | * @pending_list: Descriptors waiting |
Kedareswara rao Appana | 7096f36 | 2016-02-26 19:33:51 +0530 | [diff] [blame] | 294 | * @active_list: Descriptors ready to submit |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 295 | * @done_list: Complete descriptors |
| 296 | * @common: DMA common channel |
| 297 | * @desc_pool: Descriptors pool |
| 298 | * @dev: The dma device |
| 299 | * @irq: Channel IRQ |
| 300 | * @id: Channel ID |
| 301 | * @direction: Transfer direction |
| 302 | * @num_frms: Number of frames |
| 303 | * @has_sg: Support scatter transfers |
| 304 | * @genlock: Support genlock mode |
| 305 | * @err: Channel has errors |
| 306 | * @tasklet: Cleanup work after irq |
| 307 | * @config: Device configuration info |
| 308 | * @flush_on_fsync: Flush on Frame sync |
Kedareswara rao Appana | 7096f36 | 2016-02-26 19:33:51 +0530 | [diff] [blame] | 309 | * @desc_pendingcount: Descriptor pending count |
Kedareswara rao Appana | b72db40 | 2016-04-06 10:38:08 +0530 | [diff] [blame] | 310 | * @ext_addr: Indicates 64 bit addressing is supported by dma channel |
Kedareswara rao Appana | a65cf512 | 2016-04-06 10:38:09 +0530 | [diff] [blame] | 311 | * @desc_submitcount: Descriptor h/w submitted count |
Kedareswara rao Appana | c0bba3a | 2016-04-07 10:59:43 +0530 | [diff] [blame] | 312 | * @residue: Residue for AXI DMA |
| 313 | * @seg_v: Statically allocated segments base |
| 314 | * @start_transfer: Differentiate b/w DMA IP's transfer |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 315 | */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 316 | struct xilinx_dma_chan { |
| 317 | struct xilinx_dma_device *xdev; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 318 | u32 ctrl_offset; |
| 319 | u32 desc_offset; |
| 320 | spinlock_t lock; |
| 321 | struct list_head pending_list; |
Kedareswara rao Appana | 7096f36 | 2016-02-26 19:33:51 +0530 | [diff] [blame] | 322 | struct list_head active_list; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 323 | struct list_head done_list; |
| 324 | struct dma_chan common; |
| 325 | struct dma_pool *desc_pool; |
| 326 | struct device *dev; |
| 327 | int irq; |
| 328 | int id; |
| 329 | enum dma_transfer_direction direction; |
| 330 | int num_frms; |
| 331 | bool has_sg; |
| 332 | bool genlock; |
| 333 | bool err; |
| 334 | struct tasklet_struct tasklet; |
| 335 | struct xilinx_vdma_config config; |
| 336 | bool flush_on_fsync; |
Kedareswara rao Appana | 7096f36 | 2016-02-26 19:33:51 +0530 | [diff] [blame] | 337 | u32 desc_pendingcount; |
Kedareswara rao Appana | b72db40 | 2016-04-06 10:38:08 +0530 | [diff] [blame] | 338 | bool ext_addr; |
Kedareswara rao Appana | a65cf512 | 2016-04-06 10:38:09 +0530 | [diff] [blame] | 339 | u32 desc_submitcount; |
Kedareswara rao Appana | c0bba3a | 2016-04-07 10:59:43 +0530 | [diff] [blame] | 340 | u32 residue; |
| 341 | struct xilinx_axidma_tx_segment *seg_v; |
| 342 | void (*start_transfer)(struct xilinx_dma_chan *chan); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 343 | }; |
| 344 | |
| 345 | /** |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 346 | * struct xilinx_dma_device - DMA device structure |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 347 | * @regs: I/O mapped base address |
| 348 | * @dev: Device Structure |
| 349 | * @common: DMA device structure |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 350 | * @chan: Driver specific DMA channel |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 351 | * @has_sg: Specifies whether Scatter-Gather is present or not |
| 352 | * @flush_on_fsync: Flush on frame sync |
Kedareswara rao Appana | b72db40 | 2016-04-06 10:38:08 +0530 | [diff] [blame] | 353 | * @ext_addr: Indicates 64 bit addressing is supported by dma device |
Kedareswara rao Appana | c0bba3a | 2016-04-07 10:59:43 +0530 | [diff] [blame] | 354 | * @dmatype: DMA ip type |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 355 | */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 356 | struct xilinx_dma_device { |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 357 | void __iomem *regs; |
| 358 | struct device *dev; |
| 359 | struct dma_device common; |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 360 | struct xilinx_dma_chan *chan[XILINX_DMA_MAX_CHANS_PER_DEVICE]; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 361 | bool has_sg; |
| 362 | u32 flush_on_fsync; |
Kedareswara rao Appana | b72db40 | 2016-04-06 10:38:08 +0530 | [diff] [blame] | 363 | bool ext_addr; |
Kedareswara rao Appana | c0bba3a | 2016-04-07 10:59:43 +0530 | [diff] [blame] | 364 | enum xdma_ip_type dmatype; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 365 | }; |
| 366 | |
| 367 | /* Macros */ |
| 368 | #define to_xilinx_chan(chan) \ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 369 | container_of(chan, struct xilinx_dma_chan, common) |
| 370 | #define to_dma_tx_descriptor(tx) \ |
| 371 | container_of(tx, struct xilinx_dma_tx_descriptor, async_tx) |
| 372 | #define xilinx_dma_poll_timeout(chan, reg, val, cond, delay_us, timeout_us) \ |
Kedareswara rao Appana | 9495f26 | 2016-02-26 19:33:54 +0530 | [diff] [blame] | 373 | readl_poll_timeout(chan->xdev->regs + chan->ctrl_offset + reg, val, \ |
| 374 | cond, delay_us, timeout_us) |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 375 | |
| 376 | /* IO accessors */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 377 | static inline u32 dma_read(struct xilinx_dma_chan *chan, u32 reg) |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 378 | { |
| 379 | return ioread32(chan->xdev->regs + reg); |
| 380 | } |
| 381 | |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 382 | static inline void dma_write(struct xilinx_dma_chan *chan, u32 reg, u32 value) |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 383 | { |
| 384 | iowrite32(value, chan->xdev->regs + reg); |
| 385 | } |
| 386 | |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 387 | static inline void vdma_desc_write(struct xilinx_dma_chan *chan, u32 reg, |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 388 | u32 value) |
| 389 | { |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 390 | dma_write(chan, chan->desc_offset + reg, value); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 391 | } |
| 392 | |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 393 | static inline u32 dma_ctrl_read(struct xilinx_dma_chan *chan, u32 reg) |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 394 | { |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 395 | return dma_read(chan, chan->ctrl_offset + reg); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 396 | } |
| 397 | |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 398 | static inline void dma_ctrl_write(struct xilinx_dma_chan *chan, u32 reg, |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 399 | u32 value) |
| 400 | { |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 401 | dma_write(chan, chan->ctrl_offset + reg, value); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 402 | } |
| 403 | |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 404 | static inline void dma_ctrl_clr(struct xilinx_dma_chan *chan, u32 reg, |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 405 | u32 clr) |
| 406 | { |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 407 | dma_ctrl_write(chan, reg, dma_ctrl_read(chan, reg) & ~clr); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 408 | } |
| 409 | |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 410 | static inline void dma_ctrl_set(struct xilinx_dma_chan *chan, u32 reg, |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 411 | u32 set) |
| 412 | { |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 413 | dma_ctrl_write(chan, reg, dma_ctrl_read(chan, reg) | set); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 414 | } |
| 415 | |
Kedareswara rao Appana | b72db40 | 2016-04-06 10:38:08 +0530 | [diff] [blame] | 416 | /** |
| 417 | * vdma_desc_write_64 - 64-bit descriptor write |
| 418 | * @chan: Driver specific VDMA channel |
| 419 | * @reg: Register to write |
| 420 | * @value_lsb: lower address of the descriptor. |
| 421 | * @value_msb: upper address of the descriptor. |
| 422 | * |
| 423 | * Since vdma driver is trying to write to a register offset which is not a |
| 424 | * multiple of 64 bits(ex : 0x5c), we are writing as two separate 32 bits |
| 425 | * instead of a single 64 bit register write. |
| 426 | */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 427 | static inline void vdma_desc_write_64(struct xilinx_dma_chan *chan, u32 reg, |
Kedareswara rao Appana | b72db40 | 2016-04-06 10:38:08 +0530 | [diff] [blame] | 428 | u32 value_lsb, u32 value_msb) |
| 429 | { |
| 430 | /* Write the lsb 32 bits*/ |
| 431 | writel(value_lsb, chan->xdev->regs + chan->desc_offset + reg); |
| 432 | |
| 433 | /* Write the msb 32 bits */ |
| 434 | writel(value_msb, chan->xdev->regs + chan->desc_offset + reg + 4); |
| 435 | } |
| 436 | |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 437 | /* ----------------------------------------------------------------------------- |
| 438 | * Descriptors and segments alloc and free |
| 439 | */ |
| 440 | |
| 441 | /** |
| 442 | * xilinx_vdma_alloc_tx_segment - Allocate transaction segment |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 443 | * @chan: Driver specific DMA channel |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 444 | * |
| 445 | * Return: The allocated segment on success and NULL on failure. |
| 446 | */ |
| 447 | static struct xilinx_vdma_tx_segment * |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 448 | xilinx_vdma_alloc_tx_segment(struct xilinx_dma_chan *chan) |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 449 | { |
| 450 | struct xilinx_vdma_tx_segment *segment; |
| 451 | dma_addr_t phys; |
| 452 | |
Julia Lawall | 2ba4f8a | 2016-04-29 22:09:09 +0200 | [diff] [blame] | 453 | segment = dma_pool_zalloc(chan->desc_pool, GFP_ATOMIC, &phys); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 454 | if (!segment) |
| 455 | return NULL; |
| 456 | |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 457 | segment->phys = phys; |
| 458 | |
| 459 | return segment; |
| 460 | } |
| 461 | |
| 462 | /** |
Kedareswara rao Appana | 07b0e7d | 2016-04-07 10:59:45 +0530 | [diff] [blame^] | 463 | * xilinx_cdma_alloc_tx_segment - Allocate transaction segment |
| 464 | * @chan: Driver specific DMA channel |
| 465 | * |
| 466 | * Return: The allocated segment on success and NULL on failure. |
| 467 | */ |
| 468 | static struct xilinx_cdma_tx_segment * |
| 469 | xilinx_cdma_alloc_tx_segment(struct xilinx_dma_chan *chan) |
| 470 | { |
| 471 | struct xilinx_cdma_tx_segment *segment; |
| 472 | dma_addr_t phys; |
| 473 | |
| 474 | segment = dma_pool_alloc(chan->desc_pool, GFP_ATOMIC, &phys); |
| 475 | if (!segment) |
| 476 | return NULL; |
| 477 | |
| 478 | memset(segment, 0, sizeof(*segment)); |
| 479 | segment->phys = phys; |
| 480 | |
| 481 | return segment; |
| 482 | } |
| 483 | |
| 484 | /** |
Kedareswara rao Appana | c0bba3a | 2016-04-07 10:59:43 +0530 | [diff] [blame] | 485 | * xilinx_axidma_alloc_tx_segment - Allocate transaction segment |
| 486 | * @chan: Driver specific DMA channel |
| 487 | * |
| 488 | * Return: The allocated segment on success and NULL on failure. |
| 489 | */ |
| 490 | static struct xilinx_axidma_tx_segment * |
| 491 | xilinx_axidma_alloc_tx_segment(struct xilinx_dma_chan *chan) |
| 492 | { |
| 493 | struct xilinx_axidma_tx_segment *segment; |
| 494 | dma_addr_t phys; |
| 495 | |
| 496 | segment = dma_pool_alloc(chan->desc_pool, GFP_ATOMIC, &phys); |
| 497 | if (!segment) |
| 498 | return NULL; |
| 499 | |
| 500 | memset(segment, 0, sizeof(*segment)); |
| 501 | segment->phys = phys; |
| 502 | |
| 503 | return segment; |
| 504 | } |
| 505 | |
| 506 | /** |
| 507 | * xilinx_dma_free_tx_segment - Free transaction segment |
| 508 | * @chan: Driver specific DMA channel |
| 509 | * @segment: DMA transaction segment |
| 510 | */ |
| 511 | static void xilinx_dma_free_tx_segment(struct xilinx_dma_chan *chan, |
| 512 | struct xilinx_axidma_tx_segment *segment) |
| 513 | { |
| 514 | dma_pool_free(chan->desc_pool, segment, segment->phys); |
| 515 | } |
| 516 | |
| 517 | /** |
Kedareswara rao Appana | 07b0e7d | 2016-04-07 10:59:45 +0530 | [diff] [blame^] | 518 | * xilinx_cdma_free_tx_segment - Free transaction segment |
| 519 | * @chan: Driver specific DMA channel |
| 520 | * @segment: DMA transaction segment |
| 521 | */ |
| 522 | static void xilinx_cdma_free_tx_segment(struct xilinx_dma_chan *chan, |
| 523 | struct xilinx_cdma_tx_segment *segment) |
| 524 | { |
| 525 | dma_pool_free(chan->desc_pool, segment, segment->phys); |
| 526 | } |
| 527 | |
| 528 | /** |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 529 | * xilinx_vdma_free_tx_segment - Free transaction segment |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 530 | * @chan: Driver specific DMA channel |
| 531 | * @segment: DMA transaction segment |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 532 | */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 533 | static void xilinx_vdma_free_tx_segment(struct xilinx_dma_chan *chan, |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 534 | struct xilinx_vdma_tx_segment *segment) |
| 535 | { |
| 536 | dma_pool_free(chan->desc_pool, segment, segment->phys); |
| 537 | } |
| 538 | |
| 539 | /** |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 540 | * xilinx_dma_tx_descriptor - Allocate transaction descriptor |
| 541 | * @chan: Driver specific DMA channel |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 542 | * |
| 543 | * Return: The allocated descriptor on success and NULL on failure. |
| 544 | */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 545 | static struct xilinx_dma_tx_descriptor * |
| 546 | xilinx_dma_alloc_tx_descriptor(struct xilinx_dma_chan *chan) |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 547 | { |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 548 | struct xilinx_dma_tx_descriptor *desc; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 549 | |
| 550 | desc = kzalloc(sizeof(*desc), GFP_KERNEL); |
| 551 | if (!desc) |
| 552 | return NULL; |
| 553 | |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 554 | INIT_LIST_HEAD(&desc->segments); |
| 555 | |
| 556 | return desc; |
| 557 | } |
| 558 | |
| 559 | /** |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 560 | * xilinx_dma_free_tx_descriptor - Free transaction descriptor |
| 561 | * @chan: Driver specific DMA channel |
| 562 | * @desc: DMA transaction descriptor |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 563 | */ |
| 564 | static void |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 565 | xilinx_dma_free_tx_descriptor(struct xilinx_dma_chan *chan, |
| 566 | struct xilinx_dma_tx_descriptor *desc) |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 567 | { |
| 568 | struct xilinx_vdma_tx_segment *segment, *next; |
Kedareswara rao Appana | 07b0e7d | 2016-04-07 10:59:45 +0530 | [diff] [blame^] | 569 | struct xilinx_cdma_tx_segment *cdma_segment, *cdma_next; |
Kedareswara rao Appana | c0bba3a | 2016-04-07 10:59:43 +0530 | [diff] [blame] | 570 | struct xilinx_axidma_tx_segment *axidma_segment, *axidma_next; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 571 | |
| 572 | if (!desc) |
| 573 | return; |
| 574 | |
Kedareswara rao Appana | c0bba3a | 2016-04-07 10:59:43 +0530 | [diff] [blame] | 575 | if (chan->xdev->dmatype == XDMA_TYPE_VDMA) { |
| 576 | list_for_each_entry_safe(segment, next, &desc->segments, node) { |
| 577 | list_del(&segment->node); |
| 578 | xilinx_vdma_free_tx_segment(chan, segment); |
| 579 | } |
Kedareswara rao Appana | 07b0e7d | 2016-04-07 10:59:45 +0530 | [diff] [blame^] | 580 | } else if (chan->xdev->dmatype == XDMA_TYPE_CDMA) { |
| 581 | list_for_each_entry_safe(cdma_segment, cdma_next, |
| 582 | &desc->segments, node) { |
| 583 | list_del(&cdma_segment->node); |
| 584 | xilinx_cdma_free_tx_segment(chan, cdma_segment); |
| 585 | } |
Kedareswara rao Appana | c0bba3a | 2016-04-07 10:59:43 +0530 | [diff] [blame] | 586 | } else { |
| 587 | list_for_each_entry_safe(axidma_segment, axidma_next, |
| 588 | &desc->segments, node) { |
| 589 | list_del(&axidma_segment->node); |
| 590 | xilinx_dma_free_tx_segment(chan, axidma_segment); |
| 591 | } |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 592 | } |
| 593 | |
| 594 | kfree(desc); |
| 595 | } |
| 596 | |
| 597 | /* Required functions */ |
| 598 | |
| 599 | /** |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 600 | * xilinx_dma_free_desc_list - Free descriptors list |
| 601 | * @chan: Driver specific DMA channel |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 602 | * @list: List to parse and delete the descriptor |
| 603 | */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 604 | static void xilinx_dma_free_desc_list(struct xilinx_dma_chan *chan, |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 605 | struct list_head *list) |
| 606 | { |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 607 | struct xilinx_dma_tx_descriptor *desc, *next; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 608 | |
| 609 | list_for_each_entry_safe(desc, next, list, node) { |
| 610 | list_del(&desc->node); |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 611 | xilinx_dma_free_tx_descriptor(chan, desc); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 612 | } |
| 613 | } |
| 614 | |
| 615 | /** |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 616 | * xilinx_dma_free_descriptors - Free channel descriptors |
| 617 | * @chan: Driver specific DMA channel |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 618 | */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 619 | static void xilinx_dma_free_descriptors(struct xilinx_dma_chan *chan) |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 620 | { |
| 621 | unsigned long flags; |
| 622 | |
| 623 | spin_lock_irqsave(&chan->lock, flags); |
| 624 | |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 625 | xilinx_dma_free_desc_list(chan, &chan->pending_list); |
| 626 | xilinx_dma_free_desc_list(chan, &chan->done_list); |
| 627 | xilinx_dma_free_desc_list(chan, &chan->active_list); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 628 | |
| 629 | spin_unlock_irqrestore(&chan->lock, flags); |
| 630 | } |
| 631 | |
| 632 | /** |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 633 | * xilinx_dma_free_chan_resources - Free channel resources |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 634 | * @dchan: DMA channel |
| 635 | */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 636 | static void xilinx_dma_free_chan_resources(struct dma_chan *dchan) |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 637 | { |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 638 | struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 639 | |
| 640 | dev_dbg(chan->dev, "Free all channel resources.\n"); |
| 641 | |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 642 | xilinx_dma_free_descriptors(chan); |
Kedareswara rao Appana | c0bba3a | 2016-04-07 10:59:43 +0530 | [diff] [blame] | 643 | if (chan->xdev->dmatype == XDMA_TYPE_AXIDMA) |
| 644 | xilinx_dma_free_tx_segment(chan, chan->seg_v); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 645 | dma_pool_destroy(chan->desc_pool); |
| 646 | chan->desc_pool = NULL; |
| 647 | } |
| 648 | |
| 649 | /** |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 650 | * xilinx_dma_chan_desc_cleanup - Clean channel descriptors |
| 651 | * @chan: Driver specific DMA channel |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 652 | */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 653 | static void xilinx_dma_chan_desc_cleanup(struct xilinx_dma_chan *chan) |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 654 | { |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 655 | struct xilinx_dma_tx_descriptor *desc, *next; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 656 | unsigned long flags; |
| 657 | |
| 658 | spin_lock_irqsave(&chan->lock, flags); |
| 659 | |
| 660 | list_for_each_entry_safe(desc, next, &chan->done_list, node) { |
| 661 | dma_async_tx_callback callback; |
| 662 | void *callback_param; |
| 663 | |
| 664 | /* Remove from the list of running transactions */ |
| 665 | list_del(&desc->node); |
| 666 | |
| 667 | /* Run the link descriptor callback function */ |
| 668 | callback = desc->async_tx.callback; |
| 669 | callback_param = desc->async_tx.callback_param; |
| 670 | if (callback) { |
| 671 | spin_unlock_irqrestore(&chan->lock, flags); |
| 672 | callback(callback_param); |
| 673 | spin_lock_irqsave(&chan->lock, flags); |
| 674 | } |
| 675 | |
| 676 | /* Run any dependencies, then free the descriptor */ |
| 677 | dma_run_dependencies(&desc->async_tx); |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 678 | xilinx_dma_free_tx_descriptor(chan, desc); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 679 | } |
| 680 | |
| 681 | spin_unlock_irqrestore(&chan->lock, flags); |
| 682 | } |
| 683 | |
| 684 | /** |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 685 | * xilinx_dma_do_tasklet - Schedule completion tasklet |
| 686 | * @data: Pointer to the Xilinx DMA channel structure |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 687 | */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 688 | static void xilinx_dma_do_tasklet(unsigned long data) |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 689 | { |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 690 | struct xilinx_dma_chan *chan = (struct xilinx_dma_chan *)data; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 691 | |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 692 | xilinx_dma_chan_desc_cleanup(chan); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 693 | } |
| 694 | |
| 695 | /** |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 696 | * xilinx_dma_alloc_chan_resources - Allocate channel resources |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 697 | * @dchan: DMA channel |
| 698 | * |
| 699 | * Return: '0' on success and failure value on error |
| 700 | */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 701 | static int xilinx_dma_alloc_chan_resources(struct dma_chan *dchan) |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 702 | { |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 703 | struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 704 | |
| 705 | /* Has this channel already been allocated? */ |
| 706 | if (chan->desc_pool) |
| 707 | return 0; |
| 708 | |
| 709 | /* |
| 710 | * We need the descriptor to be aligned to 64bytes |
| 711 | * for meeting Xilinx VDMA specification requirement. |
| 712 | */ |
Kedareswara rao Appana | c0bba3a | 2016-04-07 10:59:43 +0530 | [diff] [blame] | 713 | if (chan->xdev->dmatype == XDMA_TYPE_AXIDMA) { |
| 714 | chan->desc_pool = dma_pool_create("xilinx_dma_desc_pool", |
| 715 | chan->dev, |
| 716 | sizeof(struct xilinx_axidma_tx_segment), |
| 717 | __alignof__(struct xilinx_axidma_tx_segment), |
| 718 | 0); |
Kedareswara rao Appana | 07b0e7d | 2016-04-07 10:59:45 +0530 | [diff] [blame^] | 719 | } else if (chan->xdev->dmatype == XDMA_TYPE_CDMA) { |
| 720 | chan->desc_pool = dma_pool_create("xilinx_cdma_desc_pool", |
| 721 | chan->dev, |
| 722 | sizeof(struct xilinx_cdma_tx_segment), |
| 723 | __alignof__(struct xilinx_cdma_tx_segment), |
| 724 | 0); |
Kedareswara rao Appana | c0bba3a | 2016-04-07 10:59:43 +0530 | [diff] [blame] | 725 | } else { |
| 726 | chan->desc_pool = dma_pool_create("xilinx_vdma_desc_pool", |
| 727 | chan->dev, |
| 728 | sizeof(struct xilinx_vdma_tx_segment), |
| 729 | __alignof__(struct xilinx_vdma_tx_segment), |
| 730 | 0); |
| 731 | } |
| 732 | |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 733 | if (!chan->desc_pool) { |
| 734 | dev_err(chan->dev, |
| 735 | "unable to allocate channel %d descriptor pool\n", |
| 736 | chan->id); |
| 737 | return -ENOMEM; |
| 738 | } |
| 739 | |
Kedareswara rao Appana | c0bba3a | 2016-04-07 10:59:43 +0530 | [diff] [blame] | 740 | if (chan->xdev->dmatype == XDMA_TYPE_AXIDMA) |
| 741 | /* |
| 742 | * For AXI DMA case after submitting a pending_list, keep |
| 743 | * an extra segment allocated so that the "next descriptor" |
| 744 | * pointer on the tail descriptor always points to a |
| 745 | * valid descriptor, even when paused after reaching taildesc. |
| 746 | * This way, it is possible to issue additional |
| 747 | * transfers without halting and restarting the channel. |
| 748 | */ |
| 749 | chan->seg_v = xilinx_axidma_alloc_tx_segment(chan); |
| 750 | |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 751 | dma_cookie_init(dchan); |
Kedareswara rao Appana | c0bba3a | 2016-04-07 10:59:43 +0530 | [diff] [blame] | 752 | |
| 753 | if (chan->xdev->dmatype == XDMA_TYPE_AXIDMA) { |
| 754 | /* For AXI DMA resetting once channel will reset the |
| 755 | * other channel as well so enable the interrupts here. |
| 756 | */ |
| 757 | dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, |
| 758 | XILINX_DMA_DMAXR_ALL_IRQ_MASK); |
| 759 | } |
| 760 | |
Kedareswara rao Appana | 07b0e7d | 2016-04-07 10:59:45 +0530 | [diff] [blame^] | 761 | if ((chan->xdev->dmatype == XDMA_TYPE_CDMA) && chan->has_sg) |
| 762 | dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, |
| 763 | XILINX_CDMA_CR_SGMODE); |
| 764 | |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 765 | return 0; |
| 766 | } |
| 767 | |
| 768 | /** |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 769 | * xilinx_dma_tx_status - Get DMA transaction status |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 770 | * @dchan: DMA channel |
| 771 | * @cookie: Transaction identifier |
| 772 | * @txstate: Transaction state |
| 773 | * |
| 774 | * Return: DMA transaction status |
| 775 | */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 776 | static enum dma_status xilinx_dma_tx_status(struct dma_chan *dchan, |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 777 | dma_cookie_t cookie, |
| 778 | struct dma_tx_state *txstate) |
| 779 | { |
Kedareswara rao Appana | c0bba3a | 2016-04-07 10:59:43 +0530 | [diff] [blame] | 780 | struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); |
| 781 | struct xilinx_dma_tx_descriptor *desc; |
| 782 | struct xilinx_axidma_tx_segment *segment; |
| 783 | struct xilinx_axidma_desc_hw *hw; |
| 784 | enum dma_status ret; |
| 785 | unsigned long flags; |
| 786 | u32 residue = 0; |
| 787 | |
| 788 | ret = dma_cookie_status(dchan, cookie, txstate); |
| 789 | if (ret == DMA_COMPLETE || !txstate) |
| 790 | return ret; |
| 791 | |
| 792 | if (chan->xdev->dmatype == XDMA_TYPE_AXIDMA) { |
| 793 | spin_lock_irqsave(&chan->lock, flags); |
| 794 | |
| 795 | desc = list_last_entry(&chan->active_list, |
| 796 | struct xilinx_dma_tx_descriptor, node); |
| 797 | if (chan->has_sg) { |
| 798 | list_for_each_entry(segment, &desc->segments, node) { |
| 799 | hw = &segment->hw; |
| 800 | residue += (hw->control - hw->status) & |
| 801 | XILINX_DMA_MAX_TRANS_LEN; |
| 802 | } |
| 803 | } |
| 804 | spin_unlock_irqrestore(&chan->lock, flags); |
| 805 | |
| 806 | chan->residue = residue; |
| 807 | dma_set_residue(txstate, chan->residue); |
| 808 | } |
| 809 | |
| 810 | return ret; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 811 | } |
| 812 | |
| 813 | /** |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 814 | * xilinx_dma_is_running - Check if DMA channel is running |
| 815 | * @chan: Driver specific DMA channel |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 816 | * |
| 817 | * Return: '1' if running, '0' if not. |
| 818 | */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 819 | static bool xilinx_dma_is_running(struct xilinx_dma_chan *chan) |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 820 | { |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 821 | return !(dma_ctrl_read(chan, XILINX_DMA_REG_DMASR) & |
| 822 | XILINX_DMA_DMASR_HALTED) && |
| 823 | (dma_ctrl_read(chan, XILINX_DMA_REG_DMACR) & |
| 824 | XILINX_DMA_DMACR_RUNSTOP); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 825 | } |
| 826 | |
| 827 | /** |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 828 | * xilinx_dma_is_idle - Check if DMA channel is idle |
| 829 | * @chan: Driver specific DMA channel |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 830 | * |
| 831 | * Return: '1' if idle, '0' if not. |
| 832 | */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 833 | static bool xilinx_dma_is_idle(struct xilinx_dma_chan *chan) |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 834 | { |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 835 | return dma_ctrl_read(chan, XILINX_DMA_REG_DMASR) & |
| 836 | XILINX_DMA_DMASR_IDLE; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 837 | } |
| 838 | |
| 839 | /** |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 840 | * xilinx_dma_halt - Halt DMA channel |
| 841 | * @chan: Driver specific DMA channel |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 842 | */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 843 | static void xilinx_dma_halt(struct xilinx_dma_chan *chan) |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 844 | { |
Kedareswara rao Appana | 6949063 | 2016-03-03 23:02:42 +0530 | [diff] [blame] | 845 | int err; |
Kedareswara rao Appana | 9495f26 | 2016-02-26 19:33:54 +0530 | [diff] [blame] | 846 | u32 val; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 847 | |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 848 | dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR, XILINX_DMA_DMACR_RUNSTOP); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 849 | |
| 850 | /* Wait for the hardware to halt */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 851 | err = xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val, |
| 852 | (val & XILINX_DMA_DMASR_HALTED), 0, |
| 853 | XILINX_DMA_LOOP_COUNT); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 854 | |
Kedareswara rao Appana | 9495f26 | 2016-02-26 19:33:54 +0530 | [diff] [blame] | 855 | if (err) { |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 856 | dev_err(chan->dev, "Cannot stop channel %p: %x\n", |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 857 | chan, dma_ctrl_read(chan, XILINX_DMA_REG_DMASR)); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 858 | chan->err = true; |
| 859 | } |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 860 | } |
| 861 | |
| 862 | /** |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 863 | * xilinx_dma_start - Start DMA channel |
| 864 | * @chan: Driver specific DMA channel |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 865 | */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 866 | static void xilinx_dma_start(struct xilinx_dma_chan *chan) |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 867 | { |
Kedareswara rao Appana | 6949063 | 2016-03-03 23:02:42 +0530 | [diff] [blame] | 868 | int err; |
Kedareswara rao Appana | 9495f26 | 2016-02-26 19:33:54 +0530 | [diff] [blame] | 869 | u32 val; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 870 | |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 871 | dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, XILINX_DMA_DMACR_RUNSTOP); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 872 | |
| 873 | /* Wait for the hardware to start */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 874 | err = xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val, |
| 875 | !(val & XILINX_DMA_DMASR_HALTED), 0, |
| 876 | XILINX_DMA_LOOP_COUNT); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 877 | |
Kedareswara rao Appana | 9495f26 | 2016-02-26 19:33:54 +0530 | [diff] [blame] | 878 | if (err) { |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 879 | dev_err(chan->dev, "Cannot start channel %p: %x\n", |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 880 | chan, dma_ctrl_read(chan, XILINX_DMA_REG_DMASR)); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 881 | |
| 882 | chan->err = true; |
| 883 | } |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 884 | } |
| 885 | |
| 886 | /** |
| 887 | * xilinx_vdma_start_transfer - Starts VDMA transfer |
| 888 | * @chan: Driver specific channel struct pointer |
| 889 | */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 890 | static void xilinx_vdma_start_transfer(struct xilinx_dma_chan *chan) |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 891 | { |
| 892 | struct xilinx_vdma_config *config = &chan->config; |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 893 | struct xilinx_dma_tx_descriptor *desc, *tail_desc; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 894 | u32 reg; |
Kedareswara rao Appana | 7096f36 | 2016-02-26 19:33:51 +0530 | [diff] [blame] | 895 | struct xilinx_vdma_tx_segment *tail_segment; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 896 | |
Kedareswara rao Appana | 26c5e36 | 2016-02-26 19:33:52 +0530 | [diff] [blame] | 897 | /* This function was invoked with lock held */ |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 898 | if (chan->err) |
| 899 | return; |
| 900 | |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 901 | if (list_empty(&chan->pending_list)) |
Kedareswara rao Appana | 26c5e36 | 2016-02-26 19:33:52 +0530 | [diff] [blame] | 902 | return; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 903 | |
| 904 | desc = list_first_entry(&chan->pending_list, |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 905 | struct xilinx_dma_tx_descriptor, node); |
Kedareswara rao Appana | 7096f36 | 2016-02-26 19:33:51 +0530 | [diff] [blame] | 906 | tail_desc = list_last_entry(&chan->pending_list, |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 907 | struct xilinx_dma_tx_descriptor, node); |
Kedareswara rao Appana | 7096f36 | 2016-02-26 19:33:51 +0530 | [diff] [blame] | 908 | |
| 909 | tail_segment = list_last_entry(&tail_desc->segments, |
| 910 | struct xilinx_vdma_tx_segment, node); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 911 | |
| 912 | /* If it is SG mode and hardware is busy, cannot submit */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 913 | if (chan->has_sg && xilinx_dma_is_running(chan) && |
| 914 | !xilinx_dma_is_idle(chan)) { |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 915 | dev_dbg(chan->dev, "DMA controller still busy\n"); |
Kedareswara rao Appana | 26c5e36 | 2016-02-26 19:33:52 +0530 | [diff] [blame] | 916 | return; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 917 | } |
| 918 | |
| 919 | /* |
| 920 | * If hardware is idle, then all descriptors on the running lists are |
| 921 | * done, start new transfers |
| 922 | */ |
Kedareswara rao Appana | 7096f36 | 2016-02-26 19:33:51 +0530 | [diff] [blame] | 923 | if (chan->has_sg) |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 924 | dma_ctrl_write(chan, XILINX_DMA_REG_CURDESC, |
Kedareswara rao Appana | 7096f36 | 2016-02-26 19:33:51 +0530 | [diff] [blame] | 925 | desc->async_tx.phys); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 926 | |
| 927 | /* Configure the hardware using info in the config structure */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 928 | reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 929 | |
| 930 | if (config->frm_cnt_en) |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 931 | reg |= XILINX_DMA_DMACR_FRAMECNT_EN; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 932 | else |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 933 | reg &= ~XILINX_DMA_DMACR_FRAMECNT_EN; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 934 | |
Kedareswara rao Appana | e2b538a | 2016-02-26 19:33:53 +0530 | [diff] [blame] | 935 | /* Configure channel to allow number frame buffers */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 936 | dma_ctrl_write(chan, XILINX_DMA_REG_FRMSTORE, |
Kedareswara rao Appana | e2b538a | 2016-02-26 19:33:53 +0530 | [diff] [blame] | 937 | chan->desc_pendingcount); |
| 938 | |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 939 | /* |
| 940 | * With SG, start with circular mode, so that BDs can be fetched. |
| 941 | * In direct register mode, if not parking, enable circular mode |
| 942 | */ |
| 943 | if (chan->has_sg || !config->park) |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 944 | reg |= XILINX_DMA_DMACR_CIRC_EN; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 945 | |
| 946 | if (config->park) |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 947 | reg &= ~XILINX_DMA_DMACR_CIRC_EN; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 948 | |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 949 | dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 950 | |
| 951 | if (config->park && (config->park_frm >= 0) && |
| 952 | (config->park_frm < chan->num_frms)) { |
| 953 | if (chan->direction == DMA_MEM_TO_DEV) |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 954 | dma_write(chan, XILINX_DMA_REG_PARK_PTR, |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 955 | config->park_frm << |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 956 | XILINX_DMA_PARK_PTR_RD_REF_SHIFT); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 957 | else |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 958 | dma_write(chan, XILINX_DMA_REG_PARK_PTR, |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 959 | config->park_frm << |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 960 | XILINX_DMA_PARK_PTR_WR_REF_SHIFT); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 961 | } |
| 962 | |
| 963 | /* Start the hardware */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 964 | xilinx_dma_start(chan); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 965 | |
| 966 | if (chan->err) |
Kedareswara rao Appana | 26c5e36 | 2016-02-26 19:33:52 +0530 | [diff] [blame] | 967 | return; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 968 | |
| 969 | /* Start the transfer */ |
| 970 | if (chan->has_sg) { |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 971 | dma_ctrl_write(chan, XILINX_DMA_REG_TAILDESC, |
Kedareswara rao Appana | 7096f36 | 2016-02-26 19:33:51 +0530 | [diff] [blame] | 972 | tail_segment->phys); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 973 | } else { |
| 974 | struct xilinx_vdma_tx_segment *segment, *last = NULL; |
| 975 | int i = 0; |
| 976 | |
Kedareswara rao Appana | a65cf512 | 2016-04-06 10:38:09 +0530 | [diff] [blame] | 977 | if (chan->desc_submitcount < chan->num_frms) |
| 978 | i = chan->desc_submitcount; |
| 979 | |
| 980 | list_for_each_entry(segment, &desc->segments, node) { |
Kedareswara rao Appana | b72db40 | 2016-04-06 10:38:08 +0530 | [diff] [blame] | 981 | if (chan->ext_addr) |
| 982 | vdma_desc_write_64(chan, |
| 983 | XILINX_VDMA_REG_START_ADDRESS_64(i++), |
| 984 | segment->hw.buf_addr, |
| 985 | segment->hw.buf_addr_msb); |
| 986 | else |
| 987 | vdma_desc_write(chan, |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 988 | XILINX_VDMA_REG_START_ADDRESS(i++), |
| 989 | segment->hw.buf_addr); |
Kedareswara rao Appana | b72db40 | 2016-04-06 10:38:08 +0530 | [diff] [blame] | 990 | |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 991 | last = segment; |
| 992 | } |
| 993 | |
| 994 | if (!last) |
Kedareswara rao Appana | 26c5e36 | 2016-02-26 19:33:52 +0530 | [diff] [blame] | 995 | return; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 996 | |
| 997 | /* HW expects these parameters to be same for one transaction */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 998 | vdma_desc_write(chan, XILINX_DMA_REG_HSIZE, last->hw.hsize); |
| 999 | vdma_desc_write(chan, XILINX_DMA_REG_FRMDLY_STRIDE, |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1000 | last->hw.stride); |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1001 | vdma_desc_write(chan, XILINX_DMA_REG_VSIZE, last->hw.vsize); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1002 | } |
| 1003 | |
Kedareswara rao Appana | a65cf512 | 2016-04-06 10:38:09 +0530 | [diff] [blame] | 1004 | if (!chan->has_sg) { |
| 1005 | list_del(&desc->node); |
| 1006 | list_add_tail(&desc->node, &chan->active_list); |
| 1007 | chan->desc_submitcount++; |
| 1008 | chan->desc_pendingcount--; |
| 1009 | if (chan->desc_submitcount == chan->num_frms) |
| 1010 | chan->desc_submitcount = 0; |
| 1011 | } else { |
| 1012 | list_splice_tail_init(&chan->pending_list, &chan->active_list); |
| 1013 | chan->desc_pendingcount = 0; |
| 1014 | } |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1015 | } |
| 1016 | |
| 1017 | /** |
Kedareswara rao Appana | 07b0e7d | 2016-04-07 10:59:45 +0530 | [diff] [blame^] | 1018 | * xilinx_cdma_start_transfer - Starts cdma transfer |
| 1019 | * @chan: Driver specific channel struct pointer |
| 1020 | */ |
| 1021 | static void xilinx_cdma_start_transfer(struct xilinx_dma_chan *chan) |
| 1022 | { |
| 1023 | struct xilinx_dma_tx_descriptor *head_desc, *tail_desc; |
| 1024 | struct xilinx_cdma_tx_segment *tail_segment; |
| 1025 | u32 ctrl_reg = dma_read(chan, XILINX_DMA_REG_DMACR); |
| 1026 | |
| 1027 | if (chan->err) |
| 1028 | return; |
| 1029 | |
| 1030 | if (list_empty(&chan->pending_list)) |
| 1031 | return; |
| 1032 | |
| 1033 | head_desc = list_first_entry(&chan->pending_list, |
| 1034 | struct xilinx_dma_tx_descriptor, node); |
| 1035 | tail_desc = list_last_entry(&chan->pending_list, |
| 1036 | struct xilinx_dma_tx_descriptor, node); |
| 1037 | tail_segment = list_last_entry(&tail_desc->segments, |
| 1038 | struct xilinx_cdma_tx_segment, node); |
| 1039 | |
| 1040 | if (chan->desc_pendingcount <= XILINX_DMA_COALESCE_MAX) { |
| 1041 | ctrl_reg &= ~XILINX_DMA_CR_COALESCE_MAX; |
| 1042 | ctrl_reg |= chan->desc_pendingcount << |
| 1043 | XILINX_DMA_CR_COALESCE_SHIFT; |
| 1044 | dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, ctrl_reg); |
| 1045 | } |
| 1046 | |
| 1047 | if (chan->has_sg) { |
| 1048 | dma_ctrl_write(chan, XILINX_DMA_REG_CURDESC, |
| 1049 | head_desc->async_tx.phys); |
| 1050 | |
| 1051 | /* Update tail ptr register which will start the transfer */ |
| 1052 | dma_ctrl_write(chan, XILINX_DMA_REG_TAILDESC, |
| 1053 | tail_segment->phys); |
| 1054 | } else { |
| 1055 | /* In simple mode */ |
| 1056 | struct xilinx_cdma_tx_segment *segment; |
| 1057 | struct xilinx_cdma_desc_hw *hw; |
| 1058 | |
| 1059 | segment = list_first_entry(&head_desc->segments, |
| 1060 | struct xilinx_cdma_tx_segment, |
| 1061 | node); |
| 1062 | |
| 1063 | hw = &segment->hw; |
| 1064 | |
| 1065 | dma_ctrl_write(chan, XILINX_CDMA_REG_SRCADDR, hw->src_addr); |
| 1066 | dma_ctrl_write(chan, XILINX_CDMA_REG_DSTADDR, hw->dest_addr); |
| 1067 | |
| 1068 | /* Start the transfer */ |
| 1069 | dma_ctrl_write(chan, XILINX_DMA_REG_BTT, |
| 1070 | hw->control & XILINX_DMA_MAX_TRANS_LEN); |
| 1071 | } |
| 1072 | |
| 1073 | list_splice_tail_init(&chan->pending_list, &chan->active_list); |
| 1074 | chan->desc_pendingcount = 0; |
| 1075 | } |
| 1076 | |
| 1077 | /** |
Kedareswara rao Appana | c0bba3a | 2016-04-07 10:59:43 +0530 | [diff] [blame] | 1078 | * xilinx_dma_start_transfer - Starts DMA transfer |
| 1079 | * @chan: Driver specific channel struct pointer |
| 1080 | */ |
| 1081 | static void xilinx_dma_start_transfer(struct xilinx_dma_chan *chan) |
| 1082 | { |
| 1083 | struct xilinx_dma_tx_descriptor *head_desc, *tail_desc; |
| 1084 | struct xilinx_axidma_tx_segment *tail_segment, *old_head, *new_head; |
| 1085 | u32 reg; |
| 1086 | |
| 1087 | if (chan->err) |
| 1088 | return; |
| 1089 | |
| 1090 | if (list_empty(&chan->pending_list)) |
| 1091 | return; |
| 1092 | |
| 1093 | /* If it is SG mode and hardware is busy, cannot submit */ |
| 1094 | if (chan->has_sg && xilinx_dma_is_running(chan) && |
| 1095 | !xilinx_dma_is_idle(chan)) { |
| 1096 | dev_dbg(chan->dev, "DMA controller still busy\n"); |
| 1097 | return; |
| 1098 | } |
| 1099 | |
| 1100 | head_desc = list_first_entry(&chan->pending_list, |
| 1101 | struct xilinx_dma_tx_descriptor, node); |
| 1102 | tail_desc = list_last_entry(&chan->pending_list, |
| 1103 | struct xilinx_dma_tx_descriptor, node); |
| 1104 | tail_segment = list_last_entry(&tail_desc->segments, |
| 1105 | struct xilinx_axidma_tx_segment, node); |
| 1106 | |
| 1107 | old_head = list_first_entry(&head_desc->segments, |
| 1108 | struct xilinx_axidma_tx_segment, node); |
| 1109 | new_head = chan->seg_v; |
| 1110 | /* Copy Buffer Descriptor fields. */ |
| 1111 | new_head->hw = old_head->hw; |
| 1112 | |
| 1113 | /* Swap and save new reserve */ |
| 1114 | list_replace_init(&old_head->node, &new_head->node); |
| 1115 | chan->seg_v = old_head; |
| 1116 | |
| 1117 | tail_segment->hw.next_desc = chan->seg_v->phys; |
| 1118 | head_desc->async_tx.phys = new_head->phys; |
| 1119 | |
| 1120 | reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR); |
| 1121 | |
| 1122 | if (chan->desc_pendingcount <= XILINX_DMA_COALESCE_MAX) { |
| 1123 | reg &= ~XILINX_DMA_CR_COALESCE_MAX; |
| 1124 | reg |= chan->desc_pendingcount << |
| 1125 | XILINX_DMA_CR_COALESCE_SHIFT; |
| 1126 | dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg); |
| 1127 | } |
| 1128 | |
| 1129 | if (chan->has_sg) |
| 1130 | dma_ctrl_write(chan, XILINX_DMA_REG_CURDESC, |
| 1131 | head_desc->async_tx.phys); |
| 1132 | |
| 1133 | xilinx_dma_start(chan); |
| 1134 | |
| 1135 | if (chan->err) |
| 1136 | return; |
| 1137 | |
| 1138 | /* Start the transfer */ |
| 1139 | if (chan->has_sg) { |
| 1140 | dma_ctrl_write(chan, XILINX_DMA_REG_TAILDESC, |
| 1141 | tail_segment->phys); |
| 1142 | } else { |
| 1143 | struct xilinx_axidma_tx_segment *segment; |
| 1144 | struct xilinx_axidma_desc_hw *hw; |
| 1145 | |
| 1146 | segment = list_first_entry(&head_desc->segments, |
| 1147 | struct xilinx_axidma_tx_segment, |
| 1148 | node); |
| 1149 | hw = &segment->hw; |
| 1150 | |
| 1151 | dma_ctrl_write(chan, XILINX_DMA_REG_SRCDSTADDR, hw->buf_addr); |
| 1152 | |
| 1153 | /* Start the transfer */ |
| 1154 | dma_ctrl_write(chan, XILINX_DMA_REG_BTT, |
| 1155 | hw->control & XILINX_DMA_MAX_TRANS_LEN); |
| 1156 | } |
| 1157 | |
| 1158 | list_splice_tail_init(&chan->pending_list, &chan->active_list); |
| 1159 | chan->desc_pendingcount = 0; |
| 1160 | } |
| 1161 | |
| 1162 | /** |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1163 | * xilinx_dma_issue_pending - Issue pending transactions |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1164 | * @dchan: DMA channel |
| 1165 | */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1166 | static void xilinx_dma_issue_pending(struct dma_chan *dchan) |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1167 | { |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1168 | struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); |
Kedareswara rao Appana | 26c5e36 | 2016-02-26 19:33:52 +0530 | [diff] [blame] | 1169 | unsigned long flags; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1170 | |
Kedareswara rao Appana | 26c5e36 | 2016-02-26 19:33:52 +0530 | [diff] [blame] | 1171 | spin_lock_irqsave(&chan->lock, flags); |
Kedareswara rao Appana | c0bba3a | 2016-04-07 10:59:43 +0530 | [diff] [blame] | 1172 | chan->start_transfer(chan); |
Kedareswara rao Appana | 26c5e36 | 2016-02-26 19:33:52 +0530 | [diff] [blame] | 1173 | spin_unlock_irqrestore(&chan->lock, flags); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1174 | } |
| 1175 | |
| 1176 | /** |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1177 | * xilinx_dma_complete_descriptor - Mark the active descriptor as complete |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1178 | * @chan : xilinx DMA channel |
| 1179 | * |
| 1180 | * CONTEXT: hardirq |
| 1181 | */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1182 | static void xilinx_dma_complete_descriptor(struct xilinx_dma_chan *chan) |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1183 | { |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1184 | struct xilinx_dma_tx_descriptor *desc, *next; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1185 | |
Kedareswara rao Appana | 26c5e36 | 2016-02-26 19:33:52 +0530 | [diff] [blame] | 1186 | /* This function was invoked with lock held */ |
Kedareswara rao Appana | 7096f36 | 2016-02-26 19:33:51 +0530 | [diff] [blame] | 1187 | if (list_empty(&chan->active_list)) |
Kedareswara rao Appana | 26c5e36 | 2016-02-26 19:33:52 +0530 | [diff] [blame] | 1188 | return; |
Kedareswara rao Appana | 7096f36 | 2016-02-26 19:33:51 +0530 | [diff] [blame] | 1189 | |
| 1190 | list_for_each_entry_safe(desc, next, &chan->active_list, node) { |
| 1191 | list_del(&desc->node); |
| 1192 | dma_cookie_complete(&desc->async_tx); |
| 1193 | list_add_tail(&desc->node, &chan->done_list); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1194 | } |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1195 | } |
| 1196 | |
| 1197 | /** |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1198 | * xilinx_dma_reset - Reset DMA channel |
| 1199 | * @chan: Driver specific DMA channel |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1200 | * |
| 1201 | * Return: '0' on success and failure value on error |
| 1202 | */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1203 | static int xilinx_dma_reset(struct xilinx_dma_chan *chan) |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1204 | { |
Kedareswara rao Appana | 6949063 | 2016-03-03 23:02:42 +0530 | [diff] [blame] | 1205 | int err; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1206 | u32 tmp; |
| 1207 | |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1208 | dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, XILINX_DMA_DMACR_RESET); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1209 | |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1210 | /* Wait for the hardware to finish reset */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1211 | err = xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMACR, tmp, |
| 1212 | !(tmp & XILINX_DMA_DMACR_RESET), 0, |
| 1213 | XILINX_DMA_LOOP_COUNT); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1214 | |
Kedareswara rao Appana | 9495f26 | 2016-02-26 19:33:54 +0530 | [diff] [blame] | 1215 | if (err) { |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1216 | dev_err(chan->dev, "reset timeout, cr %x, sr %x\n", |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1217 | dma_ctrl_read(chan, XILINX_DMA_REG_DMACR), |
| 1218 | dma_ctrl_read(chan, XILINX_DMA_REG_DMASR)); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1219 | return -ETIMEDOUT; |
| 1220 | } |
| 1221 | |
| 1222 | chan->err = false; |
| 1223 | |
Kedareswara rao Appana | 9495f26 | 2016-02-26 19:33:54 +0530 | [diff] [blame] | 1224 | return err; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1225 | } |
| 1226 | |
| 1227 | /** |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1228 | * xilinx_dma_chan_reset - Reset DMA channel and enable interrupts |
| 1229 | * @chan: Driver specific DMA channel |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1230 | * |
| 1231 | * Return: '0' on success and failure value on error |
| 1232 | */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1233 | static int xilinx_dma_chan_reset(struct xilinx_dma_chan *chan) |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1234 | { |
| 1235 | int err; |
| 1236 | |
| 1237 | /* Reset VDMA */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1238 | err = xilinx_dma_reset(chan); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1239 | if (err) |
| 1240 | return err; |
| 1241 | |
| 1242 | /* Enable interrupts */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1243 | dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, |
| 1244 | XILINX_DMA_DMAXR_ALL_IRQ_MASK); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1245 | |
| 1246 | return 0; |
| 1247 | } |
| 1248 | |
| 1249 | /** |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1250 | * xilinx_dma_irq_handler - DMA Interrupt handler |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1251 | * @irq: IRQ number |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1252 | * @data: Pointer to the Xilinx DMA channel structure |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1253 | * |
| 1254 | * Return: IRQ_HANDLED/IRQ_NONE |
| 1255 | */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1256 | static irqreturn_t xilinx_dma_irq_handler(int irq, void *data) |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1257 | { |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1258 | struct xilinx_dma_chan *chan = data; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1259 | u32 status; |
| 1260 | |
| 1261 | /* Read the status and ack the interrupts. */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1262 | status = dma_ctrl_read(chan, XILINX_DMA_REG_DMASR); |
| 1263 | if (!(status & XILINX_DMA_DMAXR_ALL_IRQ_MASK)) |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1264 | return IRQ_NONE; |
| 1265 | |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1266 | dma_ctrl_write(chan, XILINX_DMA_REG_DMASR, |
| 1267 | status & XILINX_DMA_DMAXR_ALL_IRQ_MASK); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1268 | |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1269 | if (status & XILINX_DMA_DMASR_ERR_IRQ) { |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1270 | /* |
| 1271 | * An error occurred. If C_FLUSH_ON_FSYNC is enabled and the |
| 1272 | * error is recoverable, ignore it. Otherwise flag the error. |
| 1273 | * |
| 1274 | * Only recoverable errors can be cleared in the DMASR register, |
| 1275 | * make sure not to write to other error bits to 1. |
| 1276 | */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1277 | u32 errors = status & XILINX_DMA_DMASR_ALL_ERR_MASK; |
Kedareswara rao Appana | 48a59ed | 2016-04-06 10:44:55 +0530 | [diff] [blame] | 1278 | |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1279 | dma_ctrl_write(chan, XILINX_DMA_REG_DMASR, |
| 1280 | errors & XILINX_DMA_DMASR_ERR_RECOVER_MASK); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1281 | |
| 1282 | if (!chan->flush_on_fsync || |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1283 | (errors & ~XILINX_DMA_DMASR_ERR_RECOVER_MASK)) { |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1284 | dev_err(chan->dev, |
| 1285 | "Channel %p has errors %x, cdr %x tdr %x\n", |
| 1286 | chan, errors, |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1287 | dma_ctrl_read(chan, XILINX_DMA_REG_CURDESC), |
| 1288 | dma_ctrl_read(chan, XILINX_DMA_REG_TAILDESC)); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1289 | chan->err = true; |
| 1290 | } |
| 1291 | } |
| 1292 | |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1293 | if (status & XILINX_DMA_DMASR_DLY_CNT_IRQ) { |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1294 | /* |
| 1295 | * Device takes too long to do the transfer when user requires |
| 1296 | * responsiveness. |
| 1297 | */ |
| 1298 | dev_dbg(chan->dev, "Inter-packet latency too long\n"); |
| 1299 | } |
| 1300 | |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1301 | if (status & XILINX_DMA_DMASR_FRM_CNT_IRQ) { |
Kedareswara rao Appana | 26c5e36 | 2016-02-26 19:33:52 +0530 | [diff] [blame] | 1302 | spin_lock(&chan->lock); |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1303 | xilinx_dma_complete_descriptor(chan); |
Kedareswara rao Appana | c0bba3a | 2016-04-07 10:59:43 +0530 | [diff] [blame] | 1304 | chan->start_transfer(chan); |
Kedareswara rao Appana | 26c5e36 | 2016-02-26 19:33:52 +0530 | [diff] [blame] | 1305 | spin_unlock(&chan->lock); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1306 | } |
| 1307 | |
| 1308 | tasklet_schedule(&chan->tasklet); |
| 1309 | return IRQ_HANDLED; |
| 1310 | } |
| 1311 | |
| 1312 | /** |
Kedareswara rao Appana | 7096f36 | 2016-02-26 19:33:51 +0530 | [diff] [blame] | 1313 | * append_desc_queue - Queuing descriptor |
| 1314 | * @chan: Driver specific dma channel |
| 1315 | * @desc: dma transaction descriptor |
| 1316 | */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1317 | static void append_desc_queue(struct xilinx_dma_chan *chan, |
| 1318 | struct xilinx_dma_tx_descriptor *desc) |
Kedareswara rao Appana | 7096f36 | 2016-02-26 19:33:51 +0530 | [diff] [blame] | 1319 | { |
| 1320 | struct xilinx_vdma_tx_segment *tail_segment; |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1321 | struct xilinx_dma_tx_descriptor *tail_desc; |
Kedareswara rao Appana | c0bba3a | 2016-04-07 10:59:43 +0530 | [diff] [blame] | 1322 | struct xilinx_axidma_tx_segment *axidma_tail_segment; |
Kedareswara rao Appana | 07b0e7d | 2016-04-07 10:59:45 +0530 | [diff] [blame^] | 1323 | struct xilinx_cdma_tx_segment *cdma_tail_segment; |
Kedareswara rao Appana | 7096f36 | 2016-02-26 19:33:51 +0530 | [diff] [blame] | 1324 | |
| 1325 | if (list_empty(&chan->pending_list)) |
| 1326 | goto append; |
| 1327 | |
| 1328 | /* |
| 1329 | * Add the hardware descriptor to the chain of hardware descriptors |
| 1330 | * that already exists in memory. |
| 1331 | */ |
| 1332 | tail_desc = list_last_entry(&chan->pending_list, |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1333 | struct xilinx_dma_tx_descriptor, node); |
Kedareswara rao Appana | c0bba3a | 2016-04-07 10:59:43 +0530 | [diff] [blame] | 1334 | if (chan->xdev->dmatype == XDMA_TYPE_VDMA) { |
| 1335 | tail_segment = list_last_entry(&tail_desc->segments, |
| 1336 | struct xilinx_vdma_tx_segment, |
| 1337 | node); |
| 1338 | tail_segment->hw.next_desc = (u32)desc->async_tx.phys; |
Kedareswara rao Appana | 07b0e7d | 2016-04-07 10:59:45 +0530 | [diff] [blame^] | 1339 | } else if (chan->xdev->dmatype == XDMA_TYPE_CDMA) { |
| 1340 | cdma_tail_segment = list_last_entry(&tail_desc->segments, |
| 1341 | struct xilinx_cdma_tx_segment, |
| 1342 | node); |
| 1343 | cdma_tail_segment->hw.next_desc = (u32)desc->async_tx.phys; |
Kedareswara rao Appana | c0bba3a | 2016-04-07 10:59:43 +0530 | [diff] [blame] | 1344 | } else { |
| 1345 | axidma_tail_segment = list_last_entry(&tail_desc->segments, |
| 1346 | struct xilinx_axidma_tx_segment, |
| 1347 | node); |
| 1348 | axidma_tail_segment->hw.next_desc = (u32)desc->async_tx.phys; |
| 1349 | } |
Kedareswara rao Appana | 7096f36 | 2016-02-26 19:33:51 +0530 | [diff] [blame] | 1350 | |
| 1351 | /* |
| 1352 | * Add the software descriptor and all children to the list |
| 1353 | * of pending transactions |
| 1354 | */ |
| 1355 | append: |
| 1356 | list_add_tail(&desc->node, &chan->pending_list); |
| 1357 | chan->desc_pendingcount++; |
| 1358 | |
Kedareswara rao Appana | c0bba3a | 2016-04-07 10:59:43 +0530 | [diff] [blame] | 1359 | if (chan->has_sg && (chan->xdev->dmatype == XDMA_TYPE_VDMA) && |
Kedareswara rao Appana | a65cf512 | 2016-04-06 10:38:09 +0530 | [diff] [blame] | 1360 | unlikely(chan->desc_pendingcount > chan->num_frms)) { |
Kedareswara rao Appana | 7096f36 | 2016-02-26 19:33:51 +0530 | [diff] [blame] | 1361 | dev_dbg(chan->dev, "desc pendingcount is too high\n"); |
| 1362 | chan->desc_pendingcount = chan->num_frms; |
| 1363 | } |
| 1364 | } |
| 1365 | |
| 1366 | /** |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1367 | * xilinx_dma_tx_submit - Submit DMA transaction |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1368 | * @tx: Async transaction descriptor |
| 1369 | * |
| 1370 | * Return: cookie value on success and failure value on error |
| 1371 | */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1372 | static dma_cookie_t xilinx_dma_tx_submit(struct dma_async_tx_descriptor *tx) |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1373 | { |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1374 | struct xilinx_dma_tx_descriptor *desc = to_dma_tx_descriptor(tx); |
| 1375 | struct xilinx_dma_chan *chan = to_xilinx_chan(tx->chan); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1376 | dma_cookie_t cookie; |
| 1377 | unsigned long flags; |
| 1378 | int err; |
| 1379 | |
| 1380 | if (chan->err) { |
| 1381 | /* |
| 1382 | * If reset fails, need to hard reset the system. |
| 1383 | * Channel is no longer functional |
| 1384 | */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1385 | err = xilinx_dma_chan_reset(chan); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1386 | if (err < 0) |
| 1387 | return err; |
| 1388 | } |
| 1389 | |
| 1390 | spin_lock_irqsave(&chan->lock, flags); |
| 1391 | |
| 1392 | cookie = dma_cookie_assign(tx); |
| 1393 | |
Kedareswara rao Appana | 7096f36 | 2016-02-26 19:33:51 +0530 | [diff] [blame] | 1394 | /* Put this transaction onto the tail of the pending queue */ |
| 1395 | append_desc_queue(chan, desc); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1396 | |
| 1397 | spin_unlock_irqrestore(&chan->lock, flags); |
| 1398 | |
| 1399 | return cookie; |
| 1400 | } |
| 1401 | |
| 1402 | /** |
| 1403 | * xilinx_vdma_dma_prep_interleaved - prepare a descriptor for a |
| 1404 | * DMA_SLAVE transaction |
| 1405 | * @dchan: DMA channel |
| 1406 | * @xt: Interleaved template pointer |
| 1407 | * @flags: transfer ack flags |
| 1408 | * |
| 1409 | * Return: Async transaction descriptor on success and NULL on failure |
| 1410 | */ |
| 1411 | static struct dma_async_tx_descriptor * |
| 1412 | xilinx_vdma_dma_prep_interleaved(struct dma_chan *dchan, |
| 1413 | struct dma_interleaved_template *xt, |
| 1414 | unsigned long flags) |
| 1415 | { |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1416 | struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); |
| 1417 | struct xilinx_dma_tx_descriptor *desc; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1418 | struct xilinx_vdma_tx_segment *segment, *prev = NULL; |
| 1419 | struct xilinx_vdma_desc_hw *hw; |
| 1420 | |
| 1421 | if (!is_slave_direction(xt->dir)) |
| 1422 | return NULL; |
| 1423 | |
| 1424 | if (!xt->numf || !xt->sgl[0].size) |
| 1425 | return NULL; |
| 1426 | |
Srikanth Thokala | a5e48e2 | 2014-11-05 20:37:01 +0200 | [diff] [blame] | 1427 | if (xt->frame_size != 1) |
| 1428 | return NULL; |
| 1429 | |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1430 | /* Allocate a transaction descriptor. */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1431 | desc = xilinx_dma_alloc_tx_descriptor(chan); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1432 | if (!desc) |
| 1433 | return NULL; |
| 1434 | |
| 1435 | dma_async_tx_descriptor_init(&desc->async_tx, &chan->common); |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1436 | desc->async_tx.tx_submit = xilinx_dma_tx_submit; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1437 | async_tx_ack(&desc->async_tx); |
| 1438 | |
| 1439 | /* Allocate the link descriptor from DMA pool */ |
| 1440 | segment = xilinx_vdma_alloc_tx_segment(chan); |
| 1441 | if (!segment) |
| 1442 | goto error; |
| 1443 | |
| 1444 | /* Fill in the hardware descriptor */ |
| 1445 | hw = &segment->hw; |
| 1446 | hw->vsize = xt->numf; |
| 1447 | hw->hsize = xt->sgl[0].size; |
Srikanth Thokala | 6d80f45 | 2014-11-05 20:37:02 +0200 | [diff] [blame] | 1448 | hw->stride = (xt->sgl[0].icg + xt->sgl[0].size) << |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1449 | XILINX_DMA_FRMDLY_STRIDE_STRIDE_SHIFT; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1450 | hw->stride |= chan->config.frm_dly << |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1451 | XILINX_DMA_FRMDLY_STRIDE_FRMDLY_SHIFT; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1452 | |
Kedareswara rao Appana | b72db40 | 2016-04-06 10:38:08 +0530 | [diff] [blame] | 1453 | if (xt->dir != DMA_MEM_TO_DEV) { |
| 1454 | if (chan->ext_addr) { |
| 1455 | hw->buf_addr = lower_32_bits(xt->dst_start); |
| 1456 | hw->buf_addr_msb = upper_32_bits(xt->dst_start); |
| 1457 | } else { |
| 1458 | hw->buf_addr = xt->dst_start; |
| 1459 | } |
| 1460 | } else { |
| 1461 | if (chan->ext_addr) { |
| 1462 | hw->buf_addr = lower_32_bits(xt->src_start); |
| 1463 | hw->buf_addr_msb = upper_32_bits(xt->src_start); |
| 1464 | } else { |
| 1465 | hw->buf_addr = xt->src_start; |
| 1466 | } |
| 1467 | } |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1468 | |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1469 | /* Insert the segment into the descriptor segments list. */ |
| 1470 | list_add_tail(&segment->node, &desc->segments); |
| 1471 | |
| 1472 | prev = segment; |
| 1473 | |
| 1474 | /* Link the last hardware descriptor with the first. */ |
| 1475 | segment = list_first_entry(&desc->segments, |
| 1476 | struct xilinx_vdma_tx_segment, node); |
Kedareswara rao Appana | 7096f36 | 2016-02-26 19:33:51 +0530 | [diff] [blame] | 1477 | desc->async_tx.phys = segment->phys; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1478 | |
| 1479 | return &desc->async_tx; |
| 1480 | |
| 1481 | error: |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1482 | xilinx_dma_free_tx_descriptor(chan, desc); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1483 | return NULL; |
| 1484 | } |
| 1485 | |
| 1486 | /** |
Kedareswara rao Appana | 07b0e7d | 2016-04-07 10:59:45 +0530 | [diff] [blame^] | 1487 | * xilinx_cdma_prep_memcpy - prepare descriptors for a memcpy transaction |
| 1488 | * @dchan: DMA channel |
| 1489 | * @dma_dst: destination address |
| 1490 | * @dma_src: source address |
| 1491 | * @len: transfer length |
| 1492 | * @flags: transfer ack flags |
| 1493 | * |
| 1494 | * Return: Async transaction descriptor on success and NULL on failure |
| 1495 | */ |
| 1496 | static struct dma_async_tx_descriptor * |
| 1497 | xilinx_cdma_prep_memcpy(struct dma_chan *dchan, dma_addr_t dma_dst, |
| 1498 | dma_addr_t dma_src, size_t len, unsigned long flags) |
| 1499 | { |
| 1500 | struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); |
| 1501 | struct xilinx_dma_tx_descriptor *desc; |
| 1502 | struct xilinx_cdma_tx_segment *segment, *prev; |
| 1503 | struct xilinx_cdma_desc_hw *hw; |
| 1504 | |
| 1505 | if (!len || len > XILINX_DMA_MAX_TRANS_LEN) |
| 1506 | return NULL; |
| 1507 | |
| 1508 | desc = xilinx_dma_alloc_tx_descriptor(chan); |
| 1509 | if (!desc) |
| 1510 | return NULL; |
| 1511 | |
| 1512 | dma_async_tx_descriptor_init(&desc->async_tx, &chan->common); |
| 1513 | desc->async_tx.tx_submit = xilinx_dma_tx_submit; |
| 1514 | |
| 1515 | /* Allocate the link descriptor from DMA pool */ |
| 1516 | segment = xilinx_cdma_alloc_tx_segment(chan); |
| 1517 | if (!segment) |
| 1518 | goto error; |
| 1519 | |
| 1520 | hw = &segment->hw; |
| 1521 | hw->control = len; |
| 1522 | hw->src_addr = dma_src; |
| 1523 | hw->dest_addr = dma_dst; |
| 1524 | |
| 1525 | /* Fill the previous next descriptor with current */ |
| 1526 | prev = list_last_entry(&desc->segments, |
| 1527 | struct xilinx_cdma_tx_segment, node); |
| 1528 | prev->hw.next_desc = segment->phys; |
| 1529 | |
| 1530 | /* Insert the segment into the descriptor segments list. */ |
| 1531 | list_add_tail(&segment->node, &desc->segments); |
| 1532 | |
| 1533 | prev = segment; |
| 1534 | |
| 1535 | /* Link the last hardware descriptor with the first. */ |
| 1536 | segment = list_first_entry(&desc->segments, |
| 1537 | struct xilinx_cdma_tx_segment, node); |
| 1538 | desc->async_tx.phys = segment->phys; |
| 1539 | prev->hw.next_desc = segment->phys; |
| 1540 | |
| 1541 | return &desc->async_tx; |
| 1542 | |
| 1543 | error: |
| 1544 | xilinx_dma_free_tx_descriptor(chan, desc); |
| 1545 | return NULL; |
| 1546 | } |
| 1547 | |
| 1548 | /** |
Kedareswara rao Appana | c0bba3a | 2016-04-07 10:59:43 +0530 | [diff] [blame] | 1549 | * xilinx_dma_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction |
| 1550 | * @dchan: DMA channel |
| 1551 | * @sgl: scatterlist to transfer to/from |
| 1552 | * @sg_len: number of entries in @scatterlist |
| 1553 | * @direction: DMA direction |
| 1554 | * @flags: transfer ack flags |
| 1555 | * @context: APP words of the descriptor |
| 1556 | * |
| 1557 | * Return: Async transaction descriptor on success and NULL on failure |
| 1558 | */ |
| 1559 | static struct dma_async_tx_descriptor *xilinx_dma_prep_slave_sg( |
| 1560 | struct dma_chan *dchan, struct scatterlist *sgl, unsigned int sg_len, |
| 1561 | enum dma_transfer_direction direction, unsigned long flags, |
| 1562 | void *context) |
| 1563 | { |
| 1564 | struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); |
| 1565 | struct xilinx_dma_tx_descriptor *desc; |
| 1566 | struct xilinx_axidma_tx_segment *segment = NULL, *prev = NULL; |
| 1567 | u32 *app_w = (u32 *)context; |
| 1568 | struct scatterlist *sg; |
| 1569 | size_t copy; |
| 1570 | size_t sg_used; |
| 1571 | unsigned int i; |
| 1572 | |
| 1573 | if (!is_slave_direction(direction)) |
| 1574 | return NULL; |
| 1575 | |
| 1576 | /* Allocate a transaction descriptor. */ |
| 1577 | desc = xilinx_dma_alloc_tx_descriptor(chan); |
| 1578 | if (!desc) |
| 1579 | return NULL; |
| 1580 | |
| 1581 | dma_async_tx_descriptor_init(&desc->async_tx, &chan->common); |
| 1582 | desc->async_tx.tx_submit = xilinx_dma_tx_submit; |
| 1583 | |
| 1584 | /* Build transactions using information in the scatter gather list */ |
| 1585 | for_each_sg(sgl, sg, sg_len, i) { |
| 1586 | sg_used = 0; |
| 1587 | |
| 1588 | /* Loop until the entire scatterlist entry is used */ |
| 1589 | while (sg_used < sg_dma_len(sg)) { |
| 1590 | struct xilinx_axidma_desc_hw *hw; |
| 1591 | |
| 1592 | /* Get a free segment */ |
| 1593 | segment = xilinx_axidma_alloc_tx_segment(chan); |
| 1594 | if (!segment) |
| 1595 | goto error; |
| 1596 | |
| 1597 | /* |
| 1598 | * Calculate the maximum number of bytes to transfer, |
| 1599 | * making sure it is less than the hw limit |
| 1600 | */ |
| 1601 | copy = min_t(size_t, sg_dma_len(sg) - sg_used, |
| 1602 | XILINX_DMA_MAX_TRANS_LEN); |
| 1603 | hw = &segment->hw; |
| 1604 | |
| 1605 | /* Fill in the descriptor */ |
| 1606 | hw->buf_addr = sg_dma_address(sg) + sg_used; |
| 1607 | |
| 1608 | hw->control = copy; |
| 1609 | |
| 1610 | if (chan->direction == DMA_MEM_TO_DEV) { |
| 1611 | if (app_w) |
| 1612 | memcpy(hw->app, app_w, sizeof(u32) * |
| 1613 | XILINX_DMA_NUM_APP_WORDS); |
| 1614 | } |
| 1615 | |
| 1616 | if (prev) |
| 1617 | prev->hw.next_desc = segment->phys; |
| 1618 | |
| 1619 | prev = segment; |
| 1620 | sg_used += copy; |
| 1621 | |
| 1622 | /* |
| 1623 | * Insert the segment into the descriptor segments |
| 1624 | * list. |
| 1625 | */ |
| 1626 | list_add_tail(&segment->node, &desc->segments); |
| 1627 | } |
| 1628 | } |
| 1629 | |
| 1630 | segment = list_first_entry(&desc->segments, |
| 1631 | struct xilinx_axidma_tx_segment, node); |
| 1632 | desc->async_tx.phys = segment->phys; |
| 1633 | prev->hw.next_desc = segment->phys; |
| 1634 | |
| 1635 | /* For the last DMA_MEM_TO_DEV transfer, set EOP */ |
| 1636 | if (chan->direction == DMA_MEM_TO_DEV) { |
| 1637 | segment->hw.control |= XILINX_DMA_BD_SOP; |
| 1638 | segment = list_last_entry(&desc->segments, |
| 1639 | struct xilinx_axidma_tx_segment, |
| 1640 | node); |
| 1641 | segment->hw.control |= XILINX_DMA_BD_EOP; |
| 1642 | } |
| 1643 | |
| 1644 | return &desc->async_tx; |
| 1645 | |
| 1646 | error: |
| 1647 | xilinx_dma_free_tx_descriptor(chan, desc); |
| 1648 | return NULL; |
| 1649 | } |
| 1650 | |
| 1651 | /** |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1652 | * xilinx_dma_terminate_all - Halt the channel and free descriptors |
| 1653 | * @chan: Driver specific DMA Channel pointer |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1654 | */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1655 | static int xilinx_dma_terminate_all(struct dma_chan *dchan) |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1656 | { |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1657 | struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); |
Maxime Ripard | ba71404 | 2014-11-17 14:42:38 +0100 | [diff] [blame] | 1658 | |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1659 | /* Halt the DMA engine */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1660 | xilinx_dma_halt(chan); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1661 | |
| 1662 | /* Remove and free all of the descriptors in the lists */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1663 | xilinx_dma_free_descriptors(chan); |
Maxime Ripard | ba71404 | 2014-11-17 14:42:38 +0100 | [diff] [blame] | 1664 | |
| 1665 | return 0; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1666 | } |
| 1667 | |
| 1668 | /** |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1669 | * xilinx_dma_channel_set_config - Configure VDMA channel |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1670 | * Run-time configuration for Axi VDMA, supports: |
| 1671 | * . halt the channel |
| 1672 | * . configure interrupt coalescing and inter-packet delay threshold |
| 1673 | * . start/stop parking |
| 1674 | * . enable genlock |
| 1675 | * |
| 1676 | * @dchan: DMA channel |
| 1677 | * @cfg: VDMA device configuration pointer |
| 1678 | * |
| 1679 | * Return: '0' on success and failure value on error |
| 1680 | */ |
| 1681 | int xilinx_vdma_channel_set_config(struct dma_chan *dchan, |
| 1682 | struct xilinx_vdma_config *cfg) |
| 1683 | { |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1684 | struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1685 | u32 dmacr; |
| 1686 | |
| 1687 | if (cfg->reset) |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1688 | return xilinx_dma_chan_reset(chan); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1689 | |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1690 | dmacr = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1691 | |
| 1692 | chan->config.frm_dly = cfg->frm_dly; |
| 1693 | chan->config.park = cfg->park; |
| 1694 | |
| 1695 | /* genlock settings */ |
| 1696 | chan->config.gen_lock = cfg->gen_lock; |
| 1697 | chan->config.master = cfg->master; |
| 1698 | |
| 1699 | if (cfg->gen_lock && chan->genlock) { |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1700 | dmacr |= XILINX_DMA_DMACR_GENLOCK_EN; |
| 1701 | dmacr |= cfg->master << XILINX_DMA_DMACR_MASTER_SHIFT; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1702 | } |
| 1703 | |
| 1704 | chan->config.frm_cnt_en = cfg->frm_cnt_en; |
| 1705 | if (cfg->park) |
| 1706 | chan->config.park_frm = cfg->park_frm; |
| 1707 | else |
| 1708 | chan->config.park_frm = -1; |
| 1709 | |
| 1710 | chan->config.coalesc = cfg->coalesc; |
| 1711 | chan->config.delay = cfg->delay; |
| 1712 | |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1713 | if (cfg->coalesc <= XILINX_DMA_DMACR_FRAME_COUNT_MAX) { |
| 1714 | dmacr |= cfg->coalesc << XILINX_DMA_DMACR_FRAME_COUNT_SHIFT; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1715 | chan->config.coalesc = cfg->coalesc; |
| 1716 | } |
| 1717 | |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1718 | if (cfg->delay <= XILINX_DMA_DMACR_DELAY_MAX) { |
| 1719 | dmacr |= cfg->delay << XILINX_DMA_DMACR_DELAY_SHIFT; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1720 | chan->config.delay = cfg->delay; |
| 1721 | } |
| 1722 | |
| 1723 | /* FSync Source selection */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1724 | dmacr &= ~XILINX_DMA_DMACR_FSYNCSRC_MASK; |
| 1725 | dmacr |= cfg->ext_fsync << XILINX_DMA_DMACR_FSYNCSRC_SHIFT; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1726 | |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1727 | dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, dmacr); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1728 | |
| 1729 | return 0; |
| 1730 | } |
| 1731 | EXPORT_SYMBOL(xilinx_vdma_channel_set_config); |
| 1732 | |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1733 | /* ----------------------------------------------------------------------------- |
| 1734 | * Probe and remove |
| 1735 | */ |
| 1736 | |
| 1737 | /** |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1738 | * xilinx_dma_chan_remove - Per Channel remove function |
| 1739 | * @chan: Driver specific DMA channel |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1740 | */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1741 | static void xilinx_dma_chan_remove(struct xilinx_dma_chan *chan) |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1742 | { |
| 1743 | /* Disable all interrupts */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1744 | dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR, |
| 1745 | XILINX_DMA_DMAXR_ALL_IRQ_MASK); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1746 | |
| 1747 | if (chan->irq > 0) |
| 1748 | free_irq(chan->irq, chan); |
| 1749 | |
| 1750 | tasklet_kill(&chan->tasklet); |
| 1751 | |
| 1752 | list_del(&chan->common.device_node); |
| 1753 | } |
| 1754 | |
| 1755 | /** |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1756 | * xilinx_dma_chan_probe - Per Channel Probing |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1757 | * It get channel features from the device tree entry and |
| 1758 | * initialize special channel handling routines |
| 1759 | * |
| 1760 | * @xdev: Driver specific device structure |
| 1761 | * @node: Device node |
| 1762 | * |
| 1763 | * Return: '0' on success and failure value on error |
| 1764 | */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1765 | static int xilinx_dma_chan_probe(struct xilinx_dma_device *xdev, |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1766 | struct device_node *node) |
| 1767 | { |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1768 | struct xilinx_dma_chan *chan; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1769 | bool has_dre = false; |
| 1770 | u32 value, width; |
| 1771 | int err; |
| 1772 | |
| 1773 | /* Allocate and initialize the channel structure */ |
| 1774 | chan = devm_kzalloc(xdev->dev, sizeof(*chan), GFP_KERNEL); |
| 1775 | if (!chan) |
| 1776 | return -ENOMEM; |
| 1777 | |
| 1778 | chan->dev = xdev->dev; |
| 1779 | chan->xdev = xdev; |
| 1780 | chan->has_sg = xdev->has_sg; |
Kedareswara rao Appana | 7096f36 | 2016-02-26 19:33:51 +0530 | [diff] [blame] | 1781 | chan->desc_pendingcount = 0x0; |
Kedareswara rao Appana | b72db40 | 2016-04-06 10:38:08 +0530 | [diff] [blame] | 1782 | chan->ext_addr = xdev->ext_addr; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1783 | |
| 1784 | spin_lock_init(&chan->lock); |
| 1785 | INIT_LIST_HEAD(&chan->pending_list); |
| 1786 | INIT_LIST_HEAD(&chan->done_list); |
Kedareswara rao Appana | 7096f36 | 2016-02-26 19:33:51 +0530 | [diff] [blame] | 1787 | INIT_LIST_HEAD(&chan->active_list); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1788 | |
| 1789 | /* Retrieve the channel properties from the device tree */ |
| 1790 | has_dre = of_property_read_bool(node, "xlnx,include-dre"); |
| 1791 | |
| 1792 | chan->genlock = of_property_read_bool(node, "xlnx,genlock-mode"); |
| 1793 | |
| 1794 | err = of_property_read_u32(node, "xlnx,datawidth", &value); |
| 1795 | if (err) { |
| 1796 | dev_err(xdev->dev, "missing xlnx,datawidth property\n"); |
| 1797 | return err; |
| 1798 | } |
| 1799 | width = value >> 3; /* Convert bits to bytes */ |
| 1800 | |
| 1801 | /* If data width is greater than 8 bytes, DRE is not in hw */ |
| 1802 | if (width > 8) |
| 1803 | has_dre = false; |
| 1804 | |
| 1805 | if (!has_dre) |
| 1806 | xdev->common.copy_align = fls(width - 1); |
| 1807 | |
| 1808 | if (of_device_is_compatible(node, "xlnx,axi-vdma-mm2s-channel")) { |
| 1809 | chan->direction = DMA_MEM_TO_DEV; |
| 1810 | chan->id = 0; |
| 1811 | |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1812 | chan->ctrl_offset = XILINX_DMA_MM2S_CTRL_OFFSET; |
Kedareswara rao Appana | c0bba3a | 2016-04-07 10:59:43 +0530 | [diff] [blame] | 1813 | if (xdev->dmatype == XDMA_TYPE_VDMA) { |
| 1814 | chan->desc_offset = XILINX_VDMA_MM2S_DESC_OFFSET; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1815 | |
Kedareswara rao Appana | c0bba3a | 2016-04-07 10:59:43 +0530 | [diff] [blame] | 1816 | if (xdev->flush_on_fsync == XILINX_DMA_FLUSH_BOTH || |
| 1817 | xdev->flush_on_fsync == XILINX_DMA_FLUSH_MM2S) |
| 1818 | chan->flush_on_fsync = true; |
| 1819 | } |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1820 | } else if (of_device_is_compatible(node, |
| 1821 | "xlnx,axi-vdma-s2mm-channel")) { |
| 1822 | chan->direction = DMA_DEV_TO_MEM; |
| 1823 | chan->id = 1; |
| 1824 | |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1825 | chan->ctrl_offset = XILINX_DMA_S2MM_CTRL_OFFSET; |
Kedareswara rao Appana | c0bba3a | 2016-04-07 10:59:43 +0530 | [diff] [blame] | 1826 | if (xdev->dmatype == XDMA_TYPE_VDMA) { |
| 1827 | chan->desc_offset = XILINX_VDMA_S2MM_DESC_OFFSET; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1828 | |
Kedareswara rao Appana | c0bba3a | 2016-04-07 10:59:43 +0530 | [diff] [blame] | 1829 | if (xdev->flush_on_fsync == XILINX_DMA_FLUSH_BOTH || |
| 1830 | xdev->flush_on_fsync == XILINX_DMA_FLUSH_S2MM) |
| 1831 | chan->flush_on_fsync = true; |
| 1832 | } |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1833 | } else { |
| 1834 | dev_err(xdev->dev, "Invalid channel compatible node\n"); |
| 1835 | return -EINVAL; |
| 1836 | } |
| 1837 | |
| 1838 | /* Request the interrupt */ |
| 1839 | chan->irq = irq_of_parse_and_map(node, 0); |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1840 | err = request_irq(chan->irq, xilinx_dma_irq_handler, IRQF_SHARED, |
| 1841 | "xilinx-dma-controller", chan); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1842 | if (err) { |
| 1843 | dev_err(xdev->dev, "unable to request IRQ %d\n", chan->irq); |
| 1844 | return err; |
| 1845 | } |
| 1846 | |
Kedareswara rao Appana | c0bba3a | 2016-04-07 10:59:43 +0530 | [diff] [blame] | 1847 | if (xdev->dmatype == XDMA_TYPE_AXIDMA) |
| 1848 | chan->start_transfer = xilinx_dma_start_transfer; |
Kedareswara rao Appana | 07b0e7d | 2016-04-07 10:59:45 +0530 | [diff] [blame^] | 1849 | else if (xdev->dmatype == XDMA_TYPE_CDMA) |
| 1850 | chan->start_transfer = xilinx_cdma_start_transfer; |
Kedareswara rao Appana | c0bba3a | 2016-04-07 10:59:43 +0530 | [diff] [blame] | 1851 | else |
| 1852 | chan->start_transfer = xilinx_vdma_start_transfer; |
| 1853 | |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1854 | /* Initialize the tasklet */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1855 | tasklet_init(&chan->tasklet, xilinx_dma_do_tasklet, |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1856 | (unsigned long)chan); |
| 1857 | |
| 1858 | /* |
| 1859 | * Initialize the DMA channel and add it to the DMA engine channels |
| 1860 | * list. |
| 1861 | */ |
| 1862 | chan->common.device = &xdev->common; |
| 1863 | |
| 1864 | list_add_tail(&chan->common.device_node, &xdev->common.channels); |
| 1865 | xdev->chan[chan->id] = chan; |
| 1866 | |
| 1867 | /* Reset the channel */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1868 | err = xilinx_dma_chan_reset(chan); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1869 | if (err < 0) { |
| 1870 | dev_err(xdev->dev, "Reset channel failed\n"); |
| 1871 | return err; |
| 1872 | } |
| 1873 | |
| 1874 | return 0; |
| 1875 | } |
| 1876 | |
| 1877 | /** |
| 1878 | * of_dma_xilinx_xlate - Translation function |
| 1879 | * @dma_spec: Pointer to DMA specifier as found in the device tree |
| 1880 | * @ofdma: Pointer to DMA controller data |
| 1881 | * |
| 1882 | * Return: DMA channel pointer on success and NULL on error |
| 1883 | */ |
| 1884 | static struct dma_chan *of_dma_xilinx_xlate(struct of_phandle_args *dma_spec, |
| 1885 | struct of_dma *ofdma) |
| 1886 | { |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1887 | struct xilinx_dma_device *xdev = ofdma->of_dma_data; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1888 | int chan_id = dma_spec->args[0]; |
| 1889 | |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1890 | if (chan_id >= XILINX_DMA_MAX_CHANS_PER_DEVICE) |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1891 | return NULL; |
| 1892 | |
| 1893 | return dma_get_slave_channel(&xdev->chan[chan_id]->common); |
| 1894 | } |
| 1895 | |
Kedareswara rao Appana | c0bba3a | 2016-04-07 10:59:43 +0530 | [diff] [blame] | 1896 | static const struct of_device_id xilinx_dma_of_ids[] = { |
| 1897 | { .compatible = "xlnx,axi-dma-1.00.a", |
| 1898 | .data = (void *)XDMA_TYPE_AXIDMA }, |
Kedareswara rao Appana | 07b0e7d | 2016-04-07 10:59:45 +0530 | [diff] [blame^] | 1899 | { .compatible = "xlnx,axi-cdma-1.00.a", |
| 1900 | .data = (void *)XDMA_TYPE_CDMA }, |
Kedareswara rao Appana | c0bba3a | 2016-04-07 10:59:43 +0530 | [diff] [blame] | 1901 | { .compatible = "xlnx,axi-vdma-1.00.a", |
| 1902 | .data = (void *)XDMA_TYPE_VDMA }, |
| 1903 | {} |
| 1904 | }; |
| 1905 | MODULE_DEVICE_TABLE(of, xilinx_dma_of_ids); |
| 1906 | |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1907 | /** |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1908 | * xilinx_dma_probe - Driver probe function |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1909 | * @pdev: Pointer to the platform_device structure |
| 1910 | * |
| 1911 | * Return: '0' on success and failure value on error |
| 1912 | */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1913 | static int xilinx_dma_probe(struct platform_device *pdev) |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1914 | { |
| 1915 | struct device_node *node = pdev->dev.of_node; |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1916 | struct xilinx_dma_device *xdev; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1917 | struct device_node *child; |
| 1918 | struct resource *io; |
Kedareswara rao Appana | b72db40 | 2016-04-06 10:38:08 +0530 | [diff] [blame] | 1919 | u32 num_frames, addr_width; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1920 | int i, err; |
| 1921 | |
| 1922 | /* Allocate and initialize the DMA engine structure */ |
| 1923 | xdev = devm_kzalloc(&pdev->dev, sizeof(*xdev), GFP_KERNEL); |
| 1924 | if (!xdev) |
| 1925 | return -ENOMEM; |
| 1926 | |
| 1927 | xdev->dev = &pdev->dev; |
Kedareswara rao Appana | c0bba3a | 2016-04-07 10:59:43 +0530 | [diff] [blame] | 1928 | xdev->dmatype = (enum xdma_ip_type)of_device_get_match_data(&pdev->dev); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1929 | |
| 1930 | /* Request and map I/O memory */ |
| 1931 | io = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 1932 | xdev->regs = devm_ioremap_resource(&pdev->dev, io); |
| 1933 | if (IS_ERR(xdev->regs)) |
| 1934 | return PTR_ERR(xdev->regs); |
| 1935 | |
| 1936 | /* Retrieve the DMA engine properties from the device tree */ |
| 1937 | xdev->has_sg = of_property_read_bool(node, "xlnx,include-sg"); |
| 1938 | |
Kedareswara rao Appana | c0bba3a | 2016-04-07 10:59:43 +0530 | [diff] [blame] | 1939 | if (xdev->dmatype == XDMA_TYPE_VDMA) { |
| 1940 | err = of_property_read_u32(node, "xlnx,num-fstores", |
| 1941 | &num_frames); |
| 1942 | if (err < 0) { |
| 1943 | dev_err(xdev->dev, |
| 1944 | "missing xlnx,num-fstores property\n"); |
| 1945 | return err; |
| 1946 | } |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1947 | |
Kedareswara rao Appana | c0bba3a | 2016-04-07 10:59:43 +0530 | [diff] [blame] | 1948 | err = of_property_read_u32(node, "xlnx,flush-fsync", |
| 1949 | &xdev->flush_on_fsync); |
| 1950 | if (err < 0) |
| 1951 | dev_warn(xdev->dev, |
| 1952 | "missing xlnx,flush-fsync property\n"); |
| 1953 | } |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1954 | |
Kedareswara rao Appana | b72db40 | 2016-04-06 10:38:08 +0530 | [diff] [blame] | 1955 | err = of_property_read_u32(node, "xlnx,addrwidth", &addr_width); |
| 1956 | if (err < 0) |
| 1957 | dev_warn(xdev->dev, "missing xlnx,addrwidth property\n"); |
| 1958 | |
| 1959 | if (addr_width > 32) |
| 1960 | xdev->ext_addr = true; |
| 1961 | else |
| 1962 | xdev->ext_addr = false; |
| 1963 | |
| 1964 | /* Set the dma mask bits */ |
| 1965 | dma_set_mask(xdev->dev, DMA_BIT_MASK(addr_width)); |
| 1966 | |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1967 | /* Initialize the DMA engine */ |
| 1968 | xdev->common.dev = &pdev->dev; |
| 1969 | |
| 1970 | INIT_LIST_HEAD(&xdev->common.channels); |
Kedareswara rao Appana | 07b0e7d | 2016-04-07 10:59:45 +0530 | [diff] [blame^] | 1971 | if (!(xdev->dmatype == XDMA_TYPE_CDMA)) { |
| 1972 | dma_cap_set(DMA_SLAVE, xdev->common.cap_mask); |
| 1973 | dma_cap_set(DMA_PRIVATE, xdev->common.cap_mask); |
| 1974 | } |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1975 | |
| 1976 | xdev->common.device_alloc_chan_resources = |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1977 | xilinx_dma_alloc_chan_resources; |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1978 | xdev->common.device_free_chan_resources = |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1979 | xilinx_dma_free_chan_resources; |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 1980 | xdev->common.device_terminate_all = xilinx_dma_terminate_all; |
| 1981 | xdev->common.device_tx_status = xilinx_dma_tx_status; |
| 1982 | xdev->common.device_issue_pending = xilinx_dma_issue_pending; |
Kedareswara rao Appana | c0bba3a | 2016-04-07 10:59:43 +0530 | [diff] [blame] | 1983 | if (xdev->dmatype == XDMA_TYPE_AXIDMA) { |
| 1984 | xdev->common.device_prep_slave_sg = xilinx_dma_prep_slave_sg; |
| 1985 | /* Residue calculation is supported by only AXI DMA */ |
| 1986 | xdev->common.residue_granularity = |
| 1987 | DMA_RESIDUE_GRANULARITY_SEGMENT; |
Kedareswara rao Appana | 07b0e7d | 2016-04-07 10:59:45 +0530 | [diff] [blame^] | 1988 | } else if (xdev->dmatype == XDMA_TYPE_CDMA) { |
| 1989 | dma_cap_set(DMA_MEMCPY, xdev->common.cap_mask); |
| 1990 | xdev->common.device_prep_dma_memcpy = xilinx_cdma_prep_memcpy; |
Kedareswara rao Appana | c0bba3a | 2016-04-07 10:59:43 +0530 | [diff] [blame] | 1991 | } else { |
| 1992 | xdev->common.device_prep_interleaved_dma = |
| 1993 | xilinx_vdma_dma_prep_interleaved; |
| 1994 | } |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 1995 | |
| 1996 | platform_set_drvdata(pdev, xdev); |
| 1997 | |
| 1998 | /* Initialize the channels */ |
| 1999 | for_each_child_of_node(node, child) { |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 2000 | err = xilinx_dma_chan_probe(xdev, child); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 2001 | if (err < 0) |
| 2002 | goto error; |
| 2003 | } |
| 2004 | |
Kedareswara rao Appana | c0bba3a | 2016-04-07 10:59:43 +0530 | [diff] [blame] | 2005 | if (xdev->dmatype == XDMA_TYPE_VDMA) { |
| 2006 | for (i = 0; i < XILINX_DMA_MAX_CHANS_PER_DEVICE; i++) |
| 2007 | if (xdev->chan[i]) |
| 2008 | xdev->chan[i]->num_frms = num_frames; |
| 2009 | } |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 2010 | |
| 2011 | /* Register the DMA engine with the core */ |
| 2012 | dma_async_device_register(&xdev->common); |
| 2013 | |
| 2014 | err = of_dma_controller_register(node, of_dma_xilinx_xlate, |
| 2015 | xdev); |
| 2016 | if (err < 0) { |
| 2017 | dev_err(&pdev->dev, "Unable to register DMA to DT\n"); |
| 2018 | dma_async_device_unregister(&xdev->common); |
| 2019 | goto error; |
| 2020 | } |
| 2021 | |
| 2022 | dev_info(&pdev->dev, "Xilinx AXI VDMA Engine Driver Probed!!\n"); |
| 2023 | |
| 2024 | return 0; |
| 2025 | |
| 2026 | error: |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 2027 | for (i = 0; i < XILINX_DMA_MAX_CHANS_PER_DEVICE; i++) |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 2028 | if (xdev->chan[i]) |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 2029 | xilinx_dma_chan_remove(xdev->chan[i]); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 2030 | |
| 2031 | return err; |
| 2032 | } |
| 2033 | |
| 2034 | /** |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 2035 | * xilinx_dma_remove - Driver remove function |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 2036 | * @pdev: Pointer to the platform_device structure |
| 2037 | * |
| 2038 | * Return: Always '0' |
| 2039 | */ |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 2040 | static int xilinx_dma_remove(struct platform_device *pdev) |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 2041 | { |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 2042 | struct xilinx_dma_device *xdev = platform_get_drvdata(pdev); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 2043 | int i; |
| 2044 | |
| 2045 | of_dma_controller_free(pdev->dev.of_node); |
| 2046 | |
| 2047 | dma_async_device_unregister(&xdev->common); |
| 2048 | |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 2049 | for (i = 0; i < XILINX_DMA_MAX_CHANS_PER_DEVICE; i++) |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 2050 | if (xdev->chan[i]) |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 2051 | xilinx_dma_chan_remove(xdev->chan[i]); |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 2052 | |
| 2053 | return 0; |
| 2054 | } |
| 2055 | |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 2056 | static struct platform_driver xilinx_vdma_driver = { |
| 2057 | .driver = { |
| 2058 | .name = "xilinx-vdma", |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 2059 | .of_match_table = xilinx_dma_of_ids, |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 2060 | }, |
Kedareswara rao Appana | 42c1a2e | 2016-04-07 10:59:41 +0530 | [diff] [blame] | 2061 | .probe = xilinx_dma_probe, |
| 2062 | .remove = xilinx_dma_remove, |
Srikanth Thokala | 9cd4360 | 2014-04-23 20:23:26 +0530 | [diff] [blame] | 2063 | }; |
| 2064 | |
| 2065 | module_platform_driver(xilinx_vdma_driver); |
| 2066 | |
| 2067 | MODULE_AUTHOR("Xilinx, Inc."); |
| 2068 | MODULE_DESCRIPTION("Xilinx VDMA driver"); |
| 2069 | MODULE_LICENSE("GPL v2"); |