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Tony Lindgren1dbae812005-11-10 14:26:51 +00001/*
Uwe Zeisbergerf30c2262006-10-03 23:01:26 +02002 * linux/arch/arm/mach-omap2/irq.c
Tony Lindgren1dbae812005-11-10 14:26:51 +00003 *
4 * Interrupt handler for OMAP2 boards.
5 *
6 * Copyright (C) 2005 Nokia Corporation
7 * Author: Paul Mundt <paul.mundt@nokia.com>
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
12 */
13#include <linux/kernel.h>
Benoit Cousson52fa2122011-11-30 19:21:07 +010014#include <linux/module.h>
Tony Lindgren1dbae812005-11-10 14:26:51 +000015#include <linux/init.h>
Tony Lindgren1dbae812005-11-10 14:26:51 +000016#include <linux/interrupt.h>
Paul Walmsley2e7509e2008-10-09 17:51:28 +030017#include <linux/io.h>
Tony Lindgrenee0839c2012-02-24 10:34:35 -080018
Marc Zyngier2db14992011-09-06 09:56:17 +010019#include <asm/exception.h>
Tony Lindgren1dbae812005-11-10 14:26:51 +000020#include <asm/mach/irq.h>
Benoit Cousson52fa2122011-11-30 19:21:07 +010021#include <linux/irqdomain.h>
22#include <linux/of.h>
23#include <linux/of_address.h>
R Sricharanc4082d42012-06-05 16:31:06 +053024#include <linux/of_irq.h>
Tony Lindgren1dbae812005-11-10 14:26:51 +000025
Tony Lindgrendbc04162012-08-31 10:59:07 -070026#include "soc.h"
Tony Lindgrenee0839c2012-02-24 10:34:35 -080027#include "iomap.h"
Paul Walmsleye2ed89f2012-04-13 06:34:26 -060028#include "common.h"
Paul Walmsley2e7509e2008-10-09 17:51:28 +030029
30/* selected INTC register offsets */
31
32#define INTC_REVISION 0x0000
33#define INTC_SYSCONFIG 0x0010
34#define INTC_SYSSTATUS 0x0014
Tony Lindgren6ccc4c02008-12-10 17:36:52 -080035#define INTC_SIR 0x0040
Paul Walmsley2e7509e2008-10-09 17:51:28 +030036#define INTC_CONTROL 0x0048
Rajendra Nayak0addd612008-09-26 17:48:20 +053037#define INTC_PROTECTION 0x004C
38#define INTC_IDLE 0x0050
39#define INTC_THRESHOLD 0x0068
40#define INTC_MIR0 0x0084
Paul Walmsley2e7509e2008-10-09 17:51:28 +030041#define INTC_MIR_CLEAR0 0x0088
42#define INTC_MIR_SET0 0x008c
43#define INTC_PENDING_IRQ0 0x0098
Paul Walmsley2e7509e2008-10-09 17:51:28 +030044/* Number of IRQ state bits in each MIR register */
45#define IRQ_BITS_PER_REG 32
Tony Lindgren1dbae812005-11-10 14:26:51 +000046
Marc Zyngier2db14992011-09-06 09:56:17 +010047#define OMAP2_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE)
48#define OMAP3_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE)
49#define INTCPS_SIR_IRQ_OFFSET 0x0040 /* omap2/3 active interrupt offset */
50#define ACTIVEIRQ_MASK 0x7f /* omap2/3 active interrupt bits */
Tony Lindgren3003ce32012-09-04 17:43:29 -070051#define INTCPS_NR_MIR_REGS 3
52#define INTCPS_NR_IRQS 96
Marc Zyngier2db14992011-09-06 09:56:17 +010053
Tony Lindgren1dbae812005-11-10 14:26:51 +000054/*
55 * OMAP2 has a number of different interrupt controllers, each interrupt
56 * controller is identified as its own "bank". Register definitions are
57 * fairly consistent for each bank, but not all registers are implemented
58 * for each bank.. when in doubt, consult the TRM.
59 */
60static struct omap_irq_bank {
Russell Kinge8a91c92008-09-01 22:07:37 +010061 void __iomem *base_reg;
Tony Lindgren1dbae812005-11-10 14:26:51 +000062 unsigned int nr_irqs;
63} __attribute__ ((aligned(4))) irq_banks[] = {
64 {
65 /* MPU INTC */
Tony Lindgren1dbae812005-11-10 14:26:51 +000066 .nr_irqs = 96,
Tony Lindgren646e3ed2008-10-06 15:49:36 +030067 },
Tony Lindgren1dbae812005-11-10 14:26:51 +000068};
69
Benoit Cousson52fa2122011-11-30 19:21:07 +010070static struct irq_domain *domain;
71
Rajendra Nayak0addd612008-09-26 17:48:20 +053072/* Structure to save interrupt controller context */
73struct omap3_intc_regs {
74 u32 sysconfig;
75 u32 protection;
76 u32 idle;
77 u32 threshold;
78 u32 ilr[INTCPS_NR_IRQS];
79 u32 mir[INTCPS_NR_MIR_REGS];
80};
81
Paul Walmsley2e7509e2008-10-09 17:51:28 +030082/* INTC bank register get/set */
83
84static void intc_bank_write_reg(u32 val, struct omap_irq_bank *bank, u16 reg)
85{
Victor Kamenskyedfaf052014-04-15 20:37:46 +030086 writel_relaxed(val, bank->base_reg + reg);
Paul Walmsley2e7509e2008-10-09 17:51:28 +030087}
88
89static u32 intc_bank_read_reg(struct omap_irq_bank *bank, u16 reg)
90{
Victor Kamenskyedfaf052014-04-15 20:37:46 +030091 return readl_relaxed(bank->base_reg + reg);
Paul Walmsley2e7509e2008-10-09 17:51:28 +030092}
93
Tony Lindgren1dbae812005-11-10 14:26:51 +000094/* XXX: FIQ and additional INTC support (only MPU at the moment) */
Lennert Buytenhekdf303472010-11-29 10:39:59 +010095static void omap_ack_irq(struct irq_data *d)
Tony Lindgren1dbae812005-11-10 14:26:51 +000096{
Paul Walmsley2e7509e2008-10-09 17:51:28 +030097 intc_bank_write_reg(0x1, &irq_banks[0], INTC_CONTROL);
Tony Lindgren1dbae812005-11-10 14:26:51 +000098}
99
Lennert Buytenhekdf303472010-11-29 10:39:59 +0100100static void omap_mask_ack_irq(struct irq_data *d)
Tony Lindgren1dbae812005-11-10 14:26:51 +0000101{
Tony Lindgren667a11f2011-05-16 02:07:38 -0700102 irq_gc_mask_disable_reg(d);
Lennert Buytenhekdf303472010-11-29 10:39:59 +0100103 omap_ack_irq(d);
Tony Lindgren1dbae812005-11-10 14:26:51 +0000104}
105
Tony Lindgren1dbae812005-11-10 14:26:51 +0000106static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank)
107{
108 unsigned long tmp;
109
Paul Walmsley2e7509e2008-10-09 17:51:28 +0300110 tmp = intc_bank_read_reg(bank, INTC_REVISION) & 0xff;
Paul Walmsley7852ec02012-07-26 00:54:26 -0600111 pr_info("IRQ: Found an INTC at 0x%p (revision %ld.%ld) with %d interrupts\n",
112 bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs);
Tony Lindgren1dbae812005-11-10 14:26:51 +0000113
Paul Walmsley2e7509e2008-10-09 17:51:28 +0300114 tmp = intc_bank_read_reg(bank, INTC_SYSCONFIG);
Tony Lindgren1dbae812005-11-10 14:26:51 +0000115 tmp |= 1 << 1; /* soft reset */
Paul Walmsley2e7509e2008-10-09 17:51:28 +0300116 intc_bank_write_reg(tmp, bank, INTC_SYSCONFIG);
Tony Lindgren1dbae812005-11-10 14:26:51 +0000117
Paul Walmsley2e7509e2008-10-09 17:51:28 +0300118 while (!(intc_bank_read_reg(bank, INTC_SYSSTATUS) & 0x1))
Tony Lindgren1dbae812005-11-10 14:26:51 +0000119 /* Wait for reset to complete */;
Juha Yrjola375e12a2006-12-06 17:13:50 -0800120
121 /* Enable autoidle */
Paul Walmsley2e7509e2008-10-09 17:51:28 +0300122 intc_bank_write_reg(1 << 0, bank, INTC_SYSCONFIG);
Tony Lindgren1dbae812005-11-10 14:26:51 +0000123}
124
Jouni Hogander94434532009-02-03 15:49:04 -0800125int omap_irq_pending(void)
126{
127 int i;
128
129 for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
130 struct omap_irq_bank *bank = irq_banks + i;
131 int irq;
132
133 for (irq = 0; irq < bank->nr_irqs; irq += 32)
134 if (intc_bank_read_reg(bank, INTC_PENDING_IRQ0 +
135 ((irq >> 5) << 5)))
136 return 1;
137 }
138 return 0;
139}
140
Tony Lindgren667a11f2011-05-16 02:07:38 -0700141static __init void
142omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
143{
144 struct irq_chip_generic *gc;
145 struct irq_chip_type *ct;
146
147 gc = irq_alloc_generic_chip("INTC", 1, irq_start, base,
148 handle_level_irq);
149 ct = gc->chip_types;
150 ct->chip.irq_ack = omap_mask_ack_irq;
151 ct->chip.irq_mask = irq_gc_mask_disable_reg;
152 ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
NeilBrowne3c83c22012-04-25 13:05:24 +1000153 ct->chip.flags |= IRQCHIP_SKIP_SET_WAKE;
Tony Lindgren667a11f2011-05-16 02:07:38 -0700154
Tony Lindgren667a11f2011-05-16 02:07:38 -0700155 ct->regs.enable = INTC_MIR_CLEAR0;
156 ct->regs.disable = INTC_MIR_SET0;
157 irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
158 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
159}
160
Benoit Cousson52fa2122011-11-30 19:21:07 +0100161static void __init omap_init_irq(u32 base, int nr_irqs,
162 struct device_node *node)
Tony Lindgren1dbae812005-11-10 14:26:51 +0000163{
Marc Zyngierab65be22011-11-15 17:22:45 +0000164 void __iomem *omap_irq_base;
Thomas Gleixner4b1135a2008-10-16 15:33:18 +0200165 unsigned long nr_of_irqs = 0;
Tony Lindgren1dbae812005-11-10 14:26:51 +0000166 unsigned int nr_banks = 0;
Benoit Cousson52fa2122011-11-30 19:21:07 +0100167 int i, j, irq_base;
Tony Lindgren1dbae812005-11-10 14:26:51 +0000168
Tony Lindgren741e3a82011-05-17 03:51:26 -0700169 omap_irq_base = ioremap(base, SZ_4K);
170 if (WARN_ON(!omap_irq_base))
171 return;
172
Benoit Cousson52fa2122011-11-30 19:21:07 +0100173 irq_base = irq_alloc_descs(-1, 0, nr_irqs, 0);
174 if (irq_base < 0) {
175 pr_warn("Couldn't allocate IRQ numbers\n");
176 irq_base = 0;
177 }
178
179 domain = irq_domain_add_legacy(node, nr_irqs, irq_base, 0,
180 &irq_domain_simple_ops, NULL);
181
Tony Lindgren1dbae812005-11-10 14:26:51 +0000182 for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
183 struct omap_irq_bank *bank = irq_banks + i;
184
Tony Lindgren741e3a82011-05-17 03:51:26 -0700185 bank->nr_irqs = nr_irqs;
Hemant Pedanekar01001712011-02-16 08:31:39 -0800186
Tony Lindgren1b26fe82009-10-19 15:25:13 -0700187 /* Static mapping, never released */
188 bank->base_reg = ioremap(base, SZ_4K);
189 if (!bank->base_reg) {
Benoit Cousson52fa2122011-11-30 19:21:07 +0100190 pr_err("Could not ioremap irq bank%i\n", i);
Tony Lindgren1b26fe82009-10-19 15:25:13 -0700191 continue;
192 }
Paul Walmsley2e7509e2008-10-09 17:51:28 +0300193
Tony Lindgren1dbae812005-11-10 14:26:51 +0000194 omap_irq_bank_init_one(bank);
195
Tapani Utriainen5c30cdf2011-09-30 11:05:56 -0700196 for (j = 0; j < bank->nr_irqs; j += 32)
Benoit Cousson52fa2122011-11-30 19:21:07 +0100197 omap_alloc_gc(bank->base_reg + j, j + irq_base, 32);
Tony Lindgren667a11f2011-05-16 02:07:38 -0700198
Thomas Gleixner4b1135a2008-10-16 15:33:18 +0200199 nr_of_irqs += bank->nr_irqs;
Tony Lindgren1dbae812005-11-10 14:26:51 +0000200 nr_banks++;
201 }
202
Benoit Cousson52fa2122011-11-30 19:21:07 +0100203 pr_info("Total of %ld interrupts on %d active controller%s\n",
204 nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : "");
Tony Lindgren1dbae812005-11-10 14:26:51 +0000205}
206
Tony Lindgren741e3a82011-05-17 03:51:26 -0700207void __init omap2_init_irq(void)
208{
Benoit Cousson52fa2122011-11-30 19:21:07 +0100209 omap_init_irq(OMAP24XX_IC_BASE, 96, NULL);
Tony Lindgren741e3a82011-05-17 03:51:26 -0700210}
211
212void __init omap3_init_irq(void)
213{
Benoit Cousson52fa2122011-11-30 19:21:07 +0100214 omap_init_irq(OMAP34XX_IC_BASE, 96, NULL);
Tony Lindgren741e3a82011-05-17 03:51:26 -0700215}
216
Hemant Pedanekara9203602011-12-13 10:46:44 -0800217void __init ti81xx_init_irq(void)
Tony Lindgren741e3a82011-05-17 03:51:26 -0700218{
Benoit Cousson52fa2122011-11-30 19:21:07 +0100219 omap_init_irq(OMAP34XX_IC_BASE, 128, NULL);
Tony Lindgren741e3a82011-05-17 03:51:26 -0700220}
221
Marc Zyngier2db14992011-09-06 09:56:17 +0100222static inline void omap_intc_handle_irq(void __iomem *base_addr, struct pt_regs *regs)
223{
224 u32 irqnr;
Stefan Sørensen698b4852014-03-06 16:27:15 +0100225 int handled_irq = 0;
Marc Zyngier2db14992011-09-06 09:56:17 +0100226
227 do {
228 irqnr = readl_relaxed(base_addr + 0x98);
229 if (irqnr)
230 goto out;
231
232 irqnr = readl_relaxed(base_addr + 0xb8);
233 if (irqnr)
234 goto out;
235
236 irqnr = readl_relaxed(base_addr + 0xd8);
Markus Pargmann0bebda62013-10-17 09:18:38 +0200237#if IS_ENABLED(CONFIG_SOC_TI81XX) || IS_ENABLED(CONFIG_SOC_AM33XX)
Marc Zyngier2db14992011-09-06 09:56:17 +0100238 if (irqnr)
239 goto out;
240 irqnr = readl_relaxed(base_addr + 0xf8);
241#endif
242
243out:
244 if (!irqnr)
245 break;
246
247 irqnr = readl_relaxed(base_addr + INTCPS_SIR_IRQ_OFFSET);
248 irqnr &= ACTIVEIRQ_MASK;
249
Benoit Cousson52fa2122011-11-30 19:21:07 +0100250 if (irqnr) {
251 irqnr = irq_find_mapping(domain, irqnr);
Marc Zyngier2db14992011-09-06 09:56:17 +0100252 handle_IRQ(irqnr, regs);
Stefan Sørensen698b4852014-03-06 16:27:15 +0100253 handled_irq = 1;
Benoit Cousson52fa2122011-11-30 19:21:07 +0100254 }
Marc Zyngier2db14992011-09-06 09:56:17 +0100255 } while (irqnr);
Stefan Sørensen698b4852014-03-06 16:27:15 +0100256
257 /* If an irq is masked or deasserted while active, we will
258 * keep ending up here with no irq handled. So remove it from
259 * the INTC with an ack.*/
260 if (!handled_irq)
261 omap_ack_irq(NULL);
Marc Zyngier2db14992011-09-06 09:56:17 +0100262}
263
264asmlinkage void __exception_irq_entry omap2_intc_handle_irq(struct pt_regs *regs)
265{
266 void __iomem *base_addr = OMAP2_IRQ_BASE;
267 omap_intc_handle_irq(base_addr, regs);
268}
269
R Sricharanc4082d42012-06-05 16:31:06 +0530270int __init intc_of_init(struct device_node *node,
Benoit Cousson52fa2122011-11-30 19:21:07 +0100271 struct device_node *parent)
272{
273 struct resource res;
Venkatraman Sb56f2cb2012-06-25 15:56:39 +0530274 u32 nr_irq = 96;
Benoit Cousson52fa2122011-11-30 19:21:07 +0100275
276 if (WARN_ON(!node))
277 return -ENODEV;
278
279 if (of_address_to_resource(node, 0, &res)) {
280 WARN(1, "unable to get intc registers\n");
281 return -EINVAL;
282 }
283
Venkatraman Sb56f2cb2012-06-25 15:56:39 +0530284 if (of_property_read_u32(node, "ti,intc-size", &nr_irq))
285 pr_warn("unable to get intc-size, default to %d\n", nr_irq);
Benoit Cousson52fa2122011-11-30 19:21:07 +0100286
Venkatraman Sb56f2cb2012-06-25 15:56:39 +0530287 omap_init_irq(res.start, nr_irq, of_node_get(node));
Benoit Cousson52fa2122011-11-30 19:21:07 +0100288
289 return 0;
290}
291
R Sricharanc4082d42012-06-05 16:31:06 +0530292static struct of_device_id irq_match[] __initdata = {
293 { .compatible = "ti,omap2-intc", .data = intc_of_init, },
294 { }
295};
296
297void __init omap_intc_of_init(void)
298{
299 of_irq_init(irq_match);
300}
301
Afzal Mohammed08f30982012-05-11 00:38:49 +0530302#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX)
Felipe Balbiee23b932011-01-27 16:39:43 -0800303static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)];
304
Rajendra Nayak0addd612008-09-26 17:48:20 +0530305void omap_intc_save_context(void)
306{
307 int ind = 0, i = 0;
308 for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) {
309 struct omap_irq_bank *bank = irq_banks + ind;
310 intc_context[ind].sysconfig =
311 intc_bank_read_reg(bank, INTC_SYSCONFIG);
312 intc_context[ind].protection =
313 intc_bank_read_reg(bank, INTC_PROTECTION);
314 intc_context[ind].idle =
315 intc_bank_read_reg(bank, INTC_IDLE);
316 intc_context[ind].threshold =
317 intc_bank_read_reg(bank, INTC_THRESHOLD);
318 for (i = 0; i < INTCPS_NR_IRQS; i++)
319 intc_context[ind].ilr[i] =
Aaro Koskinen2329e7c2009-03-12 18:12:29 +0200320 intc_bank_read_reg(bank, (0x100 + 0x4*i));
Rajendra Nayak0addd612008-09-26 17:48:20 +0530321 for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
322 intc_context[ind].mir[i] =
323 intc_bank_read_reg(&irq_banks[0], INTC_MIR0 +
324 (0x20 * i));
325 }
326}
327
328void omap_intc_restore_context(void)
329{
330 int ind = 0, i = 0;
331
332 for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) {
333 struct omap_irq_bank *bank = irq_banks + ind;
334 intc_bank_write_reg(intc_context[ind].sysconfig,
335 bank, INTC_SYSCONFIG);
336 intc_bank_write_reg(intc_context[ind].sysconfig,
337 bank, INTC_SYSCONFIG);
338 intc_bank_write_reg(intc_context[ind].protection,
339 bank, INTC_PROTECTION);
340 intc_bank_write_reg(intc_context[ind].idle,
341 bank, INTC_IDLE);
342 intc_bank_write_reg(intc_context[ind].threshold,
343 bank, INTC_THRESHOLD);
344 for (i = 0; i < INTCPS_NR_IRQS; i++)
345 intc_bank_write_reg(intc_context[ind].ilr[i],
Aaro Koskinen2329e7c2009-03-12 18:12:29 +0200346 bank, (0x100 + 0x4*i));
Rajendra Nayak0addd612008-09-26 17:48:20 +0530347 for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
348 intc_bank_write_reg(intc_context[ind].mir[i],
349 &irq_banks[0], INTC_MIR0 + (0x20 * i));
350 }
351 /* MIRs are saved and restore with other PRCM registers */
352}
Tero Kristo2bbe3af2009-10-23 19:03:48 +0300353
354void omap3_intc_suspend(void)
355{
356 /* A pending interrupt would prevent OMAP from entering suspend */
Paul Walmsleya7022d62012-04-13 06:34:28 -0600357 omap_ack_irq(NULL);
Tero Kristo2bbe3af2009-10-23 19:03:48 +0300358}
Tero Kristof18cc2f2009-10-23 19:03:50 +0300359
360void omap3_intc_prepare_idle(void)
361{
Jean Pihet447b8da2010-11-17 17:52:11 +0000362 /*
363 * Disable autoidle as it can stall interrupt controller,
364 * cf. errata ID i540 for 3430 (all revisions up to 3.1.x)
365 */
Tero Kristof18cc2f2009-10-23 19:03:50 +0300366 intc_bank_write_reg(0, &irq_banks[0], INTC_SYSCONFIG);
367}
368
369void omap3_intc_resume_idle(void)
370{
371 /* Re-enable autoidle */
372 intc_bank_write_reg(1, &irq_banks[0], INTC_SYSCONFIG);
373}
Marc Zyngier2db14992011-09-06 09:56:17 +0100374
375asmlinkage void __exception_irq_entry omap3_intc_handle_irq(struct pt_regs *regs)
376{
377 void __iomem *base_addr = OMAP3_IRQ_BASE;
378 omap_intc_handle_irq(base_addr, regs);
379}
Rajendra Nayak0addd612008-09-26 17:48:20 +0530380#endif /* CONFIG_ARCH_OMAP3 */