Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2008 Keith Packard |
| 3 | * |
| 4 | * Permission to use, copy, modify, distribute, and sell this software and its |
| 5 | * documentation for any purpose is hereby granted without fee, provided that |
| 6 | * the above copyright notice appear in all copies and that both that copyright |
| 7 | * notice and this permission notice appear in supporting documentation, and |
| 8 | * that the name of the copyright holders not be used in advertising or |
| 9 | * publicity pertaining to distribution of the software without specific, |
| 10 | * written prior permission. The copyright holders make no representations |
| 11 | * about the suitability of this software for any purpose. It is provided "as |
| 12 | * is" without express or implied warranty. |
| 13 | * |
| 14 | * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, |
| 15 | * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO |
| 16 | * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR |
| 17 | * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, |
| 18 | * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER |
| 19 | * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE |
| 20 | * OF THIS SOFTWARE. |
| 21 | */ |
| 22 | |
Dave Airlie | ab2c067 | 2009-12-04 10:55:24 +1000 | [diff] [blame] | 23 | #ifndef _DRM_DP_HELPER_H_ |
| 24 | #define _DRM_DP_HELPER_H_ |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 25 | |
Jesse Barnes | 9f0e7ff | 2010-10-07 16:01:14 -0700 | [diff] [blame] | 26 | #include <linux/types.h> |
| 27 | #include <linux/i2c.h> |
Daniel Vetter | 1a644cd | 2012-10-18 15:32:40 +0200 | [diff] [blame] | 28 | #include <linux/delay.h> |
Jesse Barnes | 9f0e7ff | 2010-10-07 16:01:14 -0700 | [diff] [blame] | 29 | |
Adam Jackson | a477f4f | 2012-09-20 16:42:44 -0400 | [diff] [blame] | 30 | /* |
| 31 | * Unless otherwise noted, all values are from the DP 1.1a spec. Note that |
| 32 | * DP and DPCD versions are independent. Differences from 1.0 are not noted, |
| 33 | * 1.0 devices basically don't exist in the wild. |
| 34 | * |
| 35 | * Abbreviations, in chronological order: |
| 36 | * |
| 37 | * eDP: Embedded DisplayPort version 1 |
| 38 | * DPI: DisplayPort Interoperability Guideline v1.1a |
| 39 | * 1.2: DisplayPort 1.2 |
Dave Airlie | 3c8a092 | 2014-05-02 11:05:21 +1000 | [diff] [blame] | 40 | * MST: Multistream Transport - part of DP 1.2a |
Adam Jackson | a477f4f | 2012-09-20 16:42:44 -0400 | [diff] [blame] | 41 | * |
| 42 | * 1.2 formally includes both eDP and DPI definitions. |
| 43 | */ |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 44 | |
Simon Farnsworth | 1d002fa | 2015-02-10 18:38:08 +0000 | [diff] [blame] | 45 | #define DP_AUX_MAX_PAYLOAD_BYTES 16 |
| 46 | |
Thierry Reding | 6b27f7f | 2013-12-16 17:01:29 +0100 | [diff] [blame] | 47 | #define DP_AUX_I2C_WRITE 0x0 |
| 48 | #define DP_AUX_I2C_READ 0x1 |
| 49 | #define DP_AUX_I2C_STATUS 0x2 |
| 50 | #define DP_AUX_I2C_MOT 0x4 |
| 51 | #define DP_AUX_NATIVE_WRITE 0x8 |
| 52 | #define DP_AUX_NATIVE_READ 0x9 |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 53 | |
Thierry Reding | 6b27f7f | 2013-12-16 17:01:29 +0100 | [diff] [blame] | 54 | #define DP_AUX_NATIVE_REPLY_ACK (0x0 << 0) |
| 55 | #define DP_AUX_NATIVE_REPLY_NACK (0x1 << 0) |
| 56 | #define DP_AUX_NATIVE_REPLY_DEFER (0x2 << 0) |
| 57 | #define DP_AUX_NATIVE_REPLY_MASK (0x3 << 0) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 58 | |
Thierry Reding | 6b27f7f | 2013-12-16 17:01:29 +0100 | [diff] [blame] | 59 | #define DP_AUX_I2C_REPLY_ACK (0x0 << 2) |
| 60 | #define DP_AUX_I2C_REPLY_NACK (0x1 << 2) |
| 61 | #define DP_AUX_I2C_REPLY_DEFER (0x2 << 2) |
| 62 | #define DP_AUX_I2C_REPLY_MASK (0x3 << 2) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 63 | |
| 64 | /* AUX CH addresses */ |
Alex Deucher | 5801ead | 2009-11-24 13:32:59 -0500 | [diff] [blame] | 65 | /* DPCD */ |
| 66 | #define DP_DPCD_REV 0x000 |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 67 | |
Alex Deucher | 5801ead | 2009-11-24 13:32:59 -0500 | [diff] [blame] | 68 | #define DP_MAX_LINK_RATE 0x001 |
| 69 | |
| 70 | #define DP_MAX_LANE_COUNT 0x002 |
| 71 | # define DP_MAX_LANE_COUNT_MASK 0x1f |
Adam Jackson | a477f4f | 2012-09-20 16:42:44 -0400 | [diff] [blame] | 72 | # define DP_TPS3_SUPPORTED (1 << 6) /* 1.2 */ |
Alex Deucher | 5801ead | 2009-11-24 13:32:59 -0500 | [diff] [blame] | 73 | # define DP_ENHANCED_FRAME_CAP (1 << 7) |
| 74 | |
| 75 | #define DP_MAX_DOWNSPREAD 0x003 |
| 76 | # define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6) |
| 77 | |
| 78 | #define DP_NORP 0x004 |
| 79 | |
| 80 | #define DP_DOWNSTREAMPORT_PRESENT 0x005 |
| 81 | # define DP_DWN_STRM_PORT_PRESENT (1 << 0) |
| 82 | # define DP_DWN_STRM_PORT_TYPE_MASK 0x06 |
Jani Nikula | 3d2e423 | 2013-09-27 14:48:41 +0300 | [diff] [blame] | 83 | # define DP_DWN_STRM_PORT_TYPE_DP (0 << 1) |
| 84 | # define DP_DWN_STRM_PORT_TYPE_ANALOG (1 << 1) |
| 85 | # define DP_DWN_STRM_PORT_TYPE_TMDS (2 << 1) |
| 86 | # define DP_DWN_STRM_PORT_TYPE_OTHER (3 << 1) |
Alex Deucher | 5801ead | 2009-11-24 13:32:59 -0500 | [diff] [blame] | 87 | # define DP_FORMAT_CONVERSION (1 << 3) |
Adam Jackson | a477f4f | 2012-09-20 16:42:44 -0400 | [diff] [blame] | 88 | # define DP_DETAILED_CAP_INFO_AVAILABLE (1 << 4) /* DPI */ |
Alex Deucher | 5801ead | 2009-11-24 13:32:59 -0500 | [diff] [blame] | 89 | |
| 90 | #define DP_MAIN_LINK_CHANNEL_CODING 0x006 |
| 91 | |
Adam Jackson | de44d97 | 2012-05-14 16:05:46 -0400 | [diff] [blame] | 92 | #define DP_DOWN_STREAM_PORT_COUNT 0x007 |
Adam Jackson | e89861d | 2012-09-18 10:58:48 -0400 | [diff] [blame] | 93 | # define DP_PORT_COUNT_MASK 0x0f |
Adam Jackson | a477f4f | 2012-09-20 16:42:44 -0400 | [diff] [blame] | 94 | # define DP_MSA_TIMING_PAR_IGNORED (1 << 6) /* eDP */ |
Adam Jackson | e89861d | 2012-09-18 10:58:48 -0400 | [diff] [blame] | 95 | # define DP_OUI_SUPPORT (1 << 7) |
| 96 | |
Jani Nikula | 9474675 | 2015-02-27 13:10:38 +0200 | [diff] [blame] | 97 | #define DP_RECEIVE_PORT_0_CAP_0 0x008 |
| 98 | # define DP_LOCAL_EDID_PRESENT (1 << 1) |
| 99 | # define DP_ASSOCIATED_TO_PRECEDING_PORT (1 << 2) |
| 100 | |
| 101 | #define DP_RECEIVE_PORT_0_BUFFER_SIZE 0x009 |
| 102 | |
| 103 | #define DP_RECEIVE_PORT_1_CAP_0 0x00a |
| 104 | #define DP_RECEIVE_PORT_1_BUFFER_SIZE 0x00b |
| 105 | |
Adam Jackson | a477f4f | 2012-09-20 16:42:44 -0400 | [diff] [blame] | 106 | #define DP_I2C_SPEED_CAP 0x00c /* DPI */ |
Adam Jackson | e89861d | 2012-09-18 10:58:48 -0400 | [diff] [blame] | 107 | # define DP_I2C_SPEED_1K 0x01 |
| 108 | # define DP_I2C_SPEED_5K 0x02 |
| 109 | # define DP_I2C_SPEED_10K 0x04 |
| 110 | # define DP_I2C_SPEED_100K 0x08 |
| 111 | # define DP_I2C_SPEED_400K 0x10 |
| 112 | # define DP_I2C_SPEED_1M 0x20 |
Adam Jackson | de44d97 | 2012-05-14 16:05:46 -0400 | [diff] [blame] | 113 | |
Adam Jackson | a477f4f | 2012-09-20 16:42:44 -0400 | [diff] [blame] | 114 | #define DP_EDP_CONFIGURATION_CAP 0x00d /* XXX 1.2? */ |
Jani Nikula | 9474675 | 2015-02-27 13:10:38 +0200 | [diff] [blame] | 115 | # define DP_ALTERNATE_SCRAMBLER_RESET_CAP (1 << 0) |
| 116 | # define DP_FRAMING_CHANGE_CAP (1 << 1) |
Sonika Jindal | e045d20 | 2015-02-19 13:16:44 +0530 | [diff] [blame] | 117 | # define DP_DPCD_DISPLAY_CONTROL_CAPABLE (1 << 3) /* edp v1.2 or higher */ |
Jani Nikula | bd5da99 | 2015-02-25 14:46:51 +0200 | [diff] [blame] | 118 | |
Adam Jackson | a477f4f | 2012-09-20 16:42:44 -0400 | [diff] [blame] | 119 | #define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */ |
Alex Deucher | 428c4b5 | 2011-05-20 04:34:25 -0400 | [diff] [blame] | 120 | |
Jani Nikula | 9474675 | 2015-02-27 13:10:38 +0200 | [diff] [blame] | 121 | #define DP_ADAPTER_CAP 0x00f /* 1.2 */ |
| 122 | # define DP_FORCE_LOAD_SENSE_CAP (1 << 0) |
| 123 | # define DP_ALTERNATE_I2C_PATTERN_CAP (1 << 1) |
| 124 | |
Jani Nikula | bd5da99 | 2015-02-25 14:46:51 +0200 | [diff] [blame] | 125 | #define DP_SUPPORTED_LINK_RATES 0x010 /* eDP 1.4 */ |
| 126 | # define DP_MAX_SUPPORTED_RATES 8 /* 16-bit little-endian */ |
| 127 | |
Adam Jackson | e89861d | 2012-09-18 10:58:48 -0400 | [diff] [blame] | 128 | /* Multiple stream transport */ |
Dave Airlie | 3c8a092 | 2014-05-02 11:05:21 +1000 | [diff] [blame] | 129 | #define DP_FAUX_CAP 0x020 /* 1.2 */ |
| 130 | # define DP_FAUX_CAP_1 (1 << 0) |
| 131 | |
Adam Jackson | a477f4f | 2012-09-20 16:42:44 -0400 | [diff] [blame] | 132 | #define DP_MSTM_CAP 0x021 /* 1.2 */ |
Adam Jackson | e89861d | 2012-09-18 10:58:48 -0400 | [diff] [blame] | 133 | # define DP_MST_CAP (1 << 0) |
| 134 | |
Jani Nikula | 9474675 | 2015-02-27 13:10:38 +0200 | [diff] [blame] | 135 | #define DP_NUMBER_OF_AUDIO_ENDPOINTS 0x022 /* 1.2 */ |
| 136 | |
| 137 | /* AV_SYNC_DATA_BLOCK 1.2 */ |
| 138 | #define DP_AV_GRANULARITY 0x023 |
| 139 | # define DP_AG_FACTOR_MASK (0xf << 0) |
| 140 | # define DP_AG_FACTOR_3MS (0 << 0) |
| 141 | # define DP_AG_FACTOR_2MS (1 << 0) |
| 142 | # define DP_AG_FACTOR_1MS (2 << 0) |
| 143 | # define DP_AG_FACTOR_500US (3 << 0) |
| 144 | # define DP_AG_FACTOR_200US (4 << 0) |
| 145 | # define DP_AG_FACTOR_100US (5 << 0) |
| 146 | # define DP_AG_FACTOR_10US (6 << 0) |
| 147 | # define DP_AG_FACTOR_1US (7 << 0) |
| 148 | # define DP_VG_FACTOR_MASK (0xf << 4) |
| 149 | # define DP_VG_FACTOR_3MS (0 << 4) |
| 150 | # define DP_VG_FACTOR_2MS (1 << 4) |
| 151 | # define DP_VG_FACTOR_1MS (2 << 4) |
| 152 | # define DP_VG_FACTOR_500US (3 << 4) |
| 153 | # define DP_VG_FACTOR_200US (4 << 4) |
| 154 | # define DP_VG_FACTOR_100US (5 << 4) |
| 155 | |
| 156 | #define DP_AUD_DEC_LAT0 0x024 |
| 157 | #define DP_AUD_DEC_LAT1 0x025 |
| 158 | |
| 159 | #define DP_AUD_PP_LAT0 0x026 |
| 160 | #define DP_AUD_PP_LAT1 0x027 |
| 161 | |
| 162 | #define DP_VID_INTER_LAT 0x028 |
| 163 | |
| 164 | #define DP_VID_PROG_LAT 0x029 |
| 165 | |
| 166 | #define DP_REP_LAT 0x02a |
| 167 | |
| 168 | #define DP_AUD_DEL_INS0 0x02b |
| 169 | #define DP_AUD_DEL_INS1 0x02c |
| 170 | #define DP_AUD_DEL_INS2 0x02d |
| 171 | /* End of AV_SYNC_DATA_BLOCK */ |
| 172 | |
Jani Nikula | 6b1e3f6 | 2015-02-27 13:11:14 +0200 | [diff] [blame] | 173 | #define DP_RECEIVER_ALPM_CAP 0x02e /* eDP 1.4 */ |
| 174 | # define DP_ALPM_CAP (1 << 0) |
| 175 | |
| 176 | #define DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP 0x02f /* eDP 1.4 */ |
| 177 | # define DP_AUX_FRAME_SYNC_CAP (1 << 0) |
| 178 | |
Dave Airlie | 3c8a092 | 2014-05-02 11:05:21 +1000 | [diff] [blame] | 179 | #define DP_GUID 0x030 /* 1.2 */ |
| 180 | |
Adam Jackson | a477f4f | 2012-09-20 16:42:44 -0400 | [diff] [blame] | 181 | #define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */ |
Ben Widawsky | b73fe58 | 2011-10-04 15:16:48 -0700 | [diff] [blame] | 182 | # define DP_PSR_IS_SUPPORTED 1 |
Jani Nikula | 6b1e3f6 | 2015-02-27 13:11:14 +0200 | [diff] [blame] | 183 | # define DP_PSR2_IS_SUPPORTED 2 /* eDP 1.4 */ |
| 184 | |
Adam Jackson | a477f4f | 2012-09-20 16:42:44 -0400 | [diff] [blame] | 185 | #define DP_PSR_CAPS 0x071 /* XXX 1.2? */ |
Ben Widawsky | b73fe58 | 2011-10-04 15:16:48 -0700 | [diff] [blame] | 186 | # define DP_PSR_NO_TRAIN_ON_EXIT 1 |
| 187 | # define DP_PSR_SETUP_TIME_330 (0 << 1) |
| 188 | # define DP_PSR_SETUP_TIME_275 (1 << 1) |
| 189 | # define DP_PSR_SETUP_TIME_220 (2 << 1) |
| 190 | # define DP_PSR_SETUP_TIME_165 (3 << 1) |
| 191 | # define DP_PSR_SETUP_TIME_110 (4 << 1) |
| 192 | # define DP_PSR_SETUP_TIME_55 (5 << 1) |
| 193 | # define DP_PSR_SETUP_TIME_0 (6 << 1) |
| 194 | # define DP_PSR_SETUP_TIME_MASK (7 << 1) |
| 195 | # define DP_PSR_SETUP_TIME_SHIFT 1 |
| 196 | |
Adam Jackson | e89861d | 2012-09-18 10:58:48 -0400 | [diff] [blame] | 197 | /* |
| 198 | * 0x80-0x8f describe downstream port capabilities, but there are two layouts |
| 199 | * based on whether DP_DETAILED_CAP_INFO_AVAILABLE was set. If it was not, |
| 200 | * each port's descriptor is one byte wide. If it was set, each port's is |
| 201 | * four bytes wide, starting with the one byte from the base info. As of |
| 202 | * DP interop v1.1a only VGA defines additional detail. |
| 203 | */ |
| 204 | |
| 205 | /* offset 0 */ |
| 206 | #define DP_DOWNSTREAM_PORT_0 0x80 |
| 207 | # define DP_DS_PORT_TYPE_MASK (7 << 0) |
| 208 | # define DP_DS_PORT_TYPE_DP 0 |
| 209 | # define DP_DS_PORT_TYPE_VGA 1 |
| 210 | # define DP_DS_PORT_TYPE_DVI 2 |
| 211 | # define DP_DS_PORT_TYPE_HDMI 3 |
| 212 | # define DP_DS_PORT_TYPE_NON_EDID 4 |
| 213 | # define DP_DS_PORT_HPD (1 << 3) |
| 214 | /* offset 1 for VGA is maximum megapixels per second / 8 */ |
| 215 | /* offset 2 */ |
| 216 | # define DP_DS_VGA_MAX_BPC_MASK (3 << 0) |
| 217 | # define DP_DS_VGA_8BPC 0 |
| 218 | # define DP_DS_VGA_10BPC 1 |
| 219 | # define DP_DS_VGA_12BPC 2 |
| 220 | # define DP_DS_VGA_16BPC 3 |
| 221 | |
Alex Deucher | 5801ead | 2009-11-24 13:32:59 -0500 | [diff] [blame] | 222 | /* link configuration */ |
| 223 | #define DP_LINK_BW_SET 0x100 |
Jani Nikula | 6b1e3f6 | 2015-02-27 13:11:14 +0200 | [diff] [blame] | 224 | # define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */ |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 225 | # define DP_LINK_BW_1_62 0x06 |
| 226 | # define DP_LINK_BW_2_7 0x0a |
Adam Jackson | a477f4f | 2012-09-20 16:42:44 -0400 | [diff] [blame] | 227 | # define DP_LINK_BW_5_4 0x14 /* 1.2 */ |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 228 | |
Alex Deucher | 5801ead | 2009-11-24 13:32:59 -0500 | [diff] [blame] | 229 | #define DP_LANE_COUNT_SET 0x101 |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 230 | # define DP_LANE_COUNT_MASK 0x0f |
| 231 | # define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7) |
| 232 | |
Alex Deucher | 5801ead | 2009-11-24 13:32:59 -0500 | [diff] [blame] | 233 | #define DP_TRAINING_PATTERN_SET 0x102 |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 234 | # define DP_TRAINING_PATTERN_DISABLE 0 |
| 235 | # define DP_TRAINING_PATTERN_1 1 |
| 236 | # define DP_TRAINING_PATTERN_2 2 |
Adam Jackson | a477f4f | 2012-09-20 16:42:44 -0400 | [diff] [blame] | 237 | # define DP_TRAINING_PATTERN_3 3 /* 1.2 */ |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 238 | # define DP_TRAINING_PATTERN_MASK 0x3 |
| 239 | |
Jani Nikula | 9474675 | 2015-02-27 13:10:38 +0200 | [diff] [blame] | 240 | /* DPCD 1.1 only. For DPCD >= 1.2 see per-lane DP_LINK_QUAL_LANEn_SET */ |
| 241 | # define DP_LINK_QUAL_PATTERN_11_DISABLE (0 << 2) |
| 242 | # define DP_LINK_QUAL_PATTERN_11_D10_2 (1 << 2) |
| 243 | # define DP_LINK_QUAL_PATTERN_11_ERROR_RATE (2 << 2) |
| 244 | # define DP_LINK_QUAL_PATTERN_11_PRBS7 (3 << 2) |
| 245 | # define DP_LINK_QUAL_PATTERN_11_MASK (3 << 2) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 246 | |
| 247 | # define DP_RECOVERED_CLOCK_OUT_EN (1 << 4) |
| 248 | # define DP_LINK_SCRAMBLING_DISABLE (1 << 5) |
| 249 | |
| 250 | # define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6) |
| 251 | # define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6) |
| 252 | # define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6) |
| 253 | # define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6) |
| 254 | |
| 255 | #define DP_TRAINING_LANE0_SET 0x103 |
| 256 | #define DP_TRAINING_LANE1_SET 0x104 |
| 257 | #define DP_TRAINING_LANE2_SET 0x105 |
| 258 | #define DP_TRAINING_LANE3_SET 0x106 |
| 259 | |
| 260 | # define DP_TRAIN_VOLTAGE_SWING_MASK 0x3 |
| 261 | # define DP_TRAIN_VOLTAGE_SWING_SHIFT 0 |
| 262 | # define DP_TRAIN_MAX_SWING_REACHED (1 << 2) |
Sonika Jindal | 0504cd1 | 2014-08-08 16:23:40 +0530 | [diff] [blame] | 263 | # define DP_TRAIN_VOLTAGE_SWING_LEVEL_0 (0 << 0) |
Sonika Jindal | 0504cd1 | 2014-08-08 16:23:40 +0530 | [diff] [blame] | 264 | # define DP_TRAIN_VOLTAGE_SWING_LEVEL_1 (1 << 0) |
Sonika Jindal | 0504cd1 | 2014-08-08 16:23:40 +0530 | [diff] [blame] | 265 | # define DP_TRAIN_VOLTAGE_SWING_LEVEL_2 (2 << 0) |
Sonika Jindal | 0504cd1 | 2014-08-08 16:23:40 +0530 | [diff] [blame] | 266 | # define DP_TRAIN_VOLTAGE_SWING_LEVEL_3 (3 << 0) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 267 | |
| 268 | # define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3) |
Sonika Jindal | 0504cd1 | 2014-08-08 16:23:40 +0530 | [diff] [blame] | 269 | # define DP_TRAIN_PRE_EMPH_LEVEL_0 (0 << 3) |
Sonika Jindal | 0504cd1 | 2014-08-08 16:23:40 +0530 | [diff] [blame] | 270 | # define DP_TRAIN_PRE_EMPH_LEVEL_1 (1 << 3) |
Sonika Jindal | 0504cd1 | 2014-08-08 16:23:40 +0530 | [diff] [blame] | 271 | # define DP_TRAIN_PRE_EMPH_LEVEL_2 (2 << 3) |
Sonika Jindal | 0504cd1 | 2014-08-08 16:23:40 +0530 | [diff] [blame] | 272 | # define DP_TRAIN_PRE_EMPH_LEVEL_3 (3 << 3) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 273 | |
| 274 | # define DP_TRAIN_PRE_EMPHASIS_SHIFT 3 |
| 275 | # define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5) |
| 276 | |
| 277 | #define DP_DOWNSPREAD_CTRL 0x107 |
| 278 | # define DP_SPREAD_AMP_0_5 (1 << 4) |
Adam Jackson | a477f4f | 2012-09-20 16:42:44 -0400 | [diff] [blame] | 279 | # define DP_MSA_TIMING_PAR_IGNORE_EN (1 << 7) /* eDP */ |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 280 | |
| 281 | #define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108 |
| 282 | # define DP_SET_ANSI_8B10B (1 << 0) |
| 283 | |
Adam Jackson | a477f4f | 2012-09-20 16:42:44 -0400 | [diff] [blame] | 284 | #define DP_I2C_SPEED_CONTROL_STATUS 0x109 /* DPI */ |
Adam Jackson | e89861d | 2012-09-18 10:58:48 -0400 | [diff] [blame] | 285 | /* bitmask as for DP_I2C_SPEED_CAP */ |
| 286 | |
Adam Jackson | a477f4f | 2012-09-20 16:42:44 -0400 | [diff] [blame] | 287 | #define DP_EDP_CONFIGURATION_SET 0x10a /* XXX 1.2? */ |
Jani Nikula | 9474675 | 2015-02-27 13:10:38 +0200 | [diff] [blame] | 288 | # define DP_ALTERNATE_SCRAMBLER_RESET_ENABLE (1 << 0) |
| 289 | # define DP_FRAMING_CHANGE_ENABLE (1 << 1) |
| 290 | # define DP_PANEL_SELF_TEST_ENABLE (1 << 7) |
| 291 | |
| 292 | #define DP_LINK_QUAL_LANE0_SET 0x10b /* DPCD >= 1.2 */ |
| 293 | #define DP_LINK_QUAL_LANE1_SET 0x10c |
| 294 | #define DP_LINK_QUAL_LANE2_SET 0x10d |
| 295 | #define DP_LINK_QUAL_LANE3_SET 0x10e |
| 296 | # define DP_LINK_QUAL_PATTERN_DISABLE 0 |
| 297 | # define DP_LINK_QUAL_PATTERN_D10_2 1 |
| 298 | # define DP_LINK_QUAL_PATTERN_ERROR_RATE 2 |
| 299 | # define DP_LINK_QUAL_PATTERN_PRBS7 3 |
| 300 | # define DP_LINK_QUAL_PATTERN_80BIT_CUSTOM 4 |
| 301 | # define DP_LINK_QUAL_PATTERN_HBR2_EYE 5 |
| 302 | # define DP_LINK_QUAL_PATTERN_MASK 7 |
| 303 | |
| 304 | #define DP_TRAINING_LANE0_1_SET2 0x10f |
| 305 | #define DP_TRAINING_LANE2_3_SET2 0x110 |
| 306 | # define DP_LANE02_POST_CURSOR2_SET_MASK (3 << 0) |
| 307 | # define DP_LANE02_MAX_POST_CURSOR2_REACHED (1 << 2) |
| 308 | # define DP_LANE13_POST_CURSOR2_SET_MASK (3 << 4) |
| 309 | # define DP_LANE13_MAX_POST_CURSOR2_REACHED (1 << 6) |
Adam Jackson | e89861d | 2012-09-18 10:58:48 -0400 | [diff] [blame] | 310 | |
Adam Jackson | a477f4f | 2012-09-20 16:42:44 -0400 | [diff] [blame] | 311 | #define DP_MSTM_CTRL 0x111 /* 1.2 */ |
Adam Jackson | e89861d | 2012-09-18 10:58:48 -0400 | [diff] [blame] | 312 | # define DP_MST_EN (1 << 0) |
| 313 | # define DP_UP_REQ_EN (1 << 1) |
| 314 | # define DP_UPSTREAM_IS_SRC (1 << 2) |
| 315 | |
Jani Nikula | 9474675 | 2015-02-27 13:10:38 +0200 | [diff] [blame] | 316 | #define DP_AUDIO_DELAY0 0x112 /* 1.2 */ |
| 317 | #define DP_AUDIO_DELAY1 0x113 |
| 318 | #define DP_AUDIO_DELAY2 0x114 |
| 319 | |
Jani Nikula | bd5da99 | 2015-02-25 14:46:51 +0200 | [diff] [blame] | 320 | #define DP_LINK_RATE_SET 0x115 /* eDP 1.4 */ |
Jani Nikula | 6b1e3f6 | 2015-02-27 13:11:14 +0200 | [diff] [blame] | 321 | # define DP_LINK_RATE_SET_SHIFT 0 |
| 322 | # define DP_LINK_RATE_SET_MASK (7 << 0) |
| 323 | |
| 324 | #define DP_RECEIVER_ALPM_CONFIG 0x116 /* eDP 1.4 */ |
| 325 | # define DP_ALPM_ENABLE (1 << 0) |
| 326 | # define DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE (1 << 1) |
| 327 | |
| 328 | #define DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF 0x117 /* eDP 1.4 */ |
| 329 | # define DP_AUX_FRAME_SYNC_ENABLE (1 << 0) |
| 330 | # define DP_IRQ_HPD_ENABLE (1 << 1) |
Sonika Jindal | e045d20 | 2015-02-19 13:16:44 +0530 | [diff] [blame] | 331 | |
Jani Nikula | 9474675 | 2015-02-27 13:10:38 +0200 | [diff] [blame] | 332 | #define DP_UPSTREAM_DEVICE_DP_PWR_NEED 0x118 /* 1.2 */ |
| 333 | # define DP_PWR_NOT_NEEDED (1 << 0) |
| 334 | |
Jani Nikula | 6b1e3f6 | 2015-02-27 13:11:14 +0200 | [diff] [blame] | 335 | #define DP_AUX_FRAME_SYNC_VALUE 0x15c /* eDP 1.4 */ |
| 336 | # define DP_AUX_FRAME_SYNC_VALID (1 << 0) |
| 337 | |
Adam Jackson | a477f4f | 2012-09-20 16:42:44 -0400 | [diff] [blame] | 338 | #define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */ |
Ben Widawsky | b73fe58 | 2011-10-04 15:16:48 -0700 | [diff] [blame] | 339 | # define DP_PSR_ENABLE (1 << 0) |
| 340 | # define DP_PSR_MAIN_LINK_ACTIVE (1 << 1) |
| 341 | # define DP_PSR_CRC_VERIFICATION (1 << 2) |
| 342 | # define DP_PSR_FRAME_CAPTURE (1 << 3) |
Jani Nikula | 6b1e3f6 | 2015-02-27 13:11:14 +0200 | [diff] [blame] | 343 | # define DP_PSR_SELECTIVE_UPDATE (1 << 4) |
| 344 | # define DP_PSR_IRQ_HPD_WITH_CRC_ERRORS (1 << 5) |
Ben Widawsky | b73fe58 | 2011-10-04 15:16:48 -0700 | [diff] [blame] | 345 | |
Dave Airlie | 3c8a092 | 2014-05-02 11:05:21 +1000 | [diff] [blame] | 346 | #define DP_ADAPTER_CTRL 0x1a0 |
| 347 | # define DP_ADAPTER_CTRL_FORCE_LOAD_SENSE (1 << 0) |
| 348 | |
| 349 | #define DP_BRANCH_DEVICE_CTRL 0x1a1 |
| 350 | # define DP_BRANCH_DEVICE_IRQ_HPD (1 << 0) |
| 351 | |
| 352 | #define DP_PAYLOAD_ALLOCATE_SET 0x1c0 |
| 353 | #define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1 |
| 354 | #define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2 |
| 355 | |
Adam Jackson | e89861d | 2012-09-18 10:58:48 -0400 | [diff] [blame] | 356 | #define DP_SINK_COUNT 0x200 |
Adam Jackson | da131a4 | 2012-09-20 16:42:45 -0400 | [diff] [blame] | 357 | /* prior to 1.2 bit 7 was reserved mbz */ |
| 358 | # define DP_GET_SINK_COUNT(x) ((((x) & 0x80) >> 1) | ((x) & 0x3f)) |
Adam Jackson | e89861d | 2012-09-18 10:58:48 -0400 | [diff] [blame] | 359 | # define DP_SINK_CP_READY (1 << 6) |
| 360 | |
Jesse Barnes | a60f0e3 | 2011-10-20 15:09:17 -0700 | [diff] [blame] | 361 | #define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201 |
| 362 | # define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0) |
| 363 | # define DP_AUTOMATED_TEST_REQUEST (1 << 1) |
| 364 | # define DP_CP_IRQ (1 << 2) |
Dave Airlie | 3c8a092 | 2014-05-02 11:05:21 +1000 | [diff] [blame] | 365 | # define DP_MCCS_IRQ (1 << 3) |
| 366 | # define DP_DOWN_REP_MSG_RDY (1 << 4) /* 1.2 MST */ |
| 367 | # define DP_UP_REQ_MSG_RDY (1 << 5) /* 1.2 MST */ |
Jesse Barnes | a60f0e3 | 2011-10-20 15:09:17 -0700 | [diff] [blame] | 368 | # define DP_SINK_SPECIFIC_IRQ (1 << 6) |
| 369 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 370 | #define DP_LANE0_1_STATUS 0x202 |
| 371 | #define DP_LANE2_3_STATUS 0x203 |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 372 | # define DP_LANE_CR_DONE (1 << 0) |
| 373 | # define DP_LANE_CHANNEL_EQ_DONE (1 << 1) |
| 374 | # define DP_LANE_SYMBOL_LOCKED (1 << 2) |
| 375 | |
Alex Deucher | 5801ead | 2009-11-24 13:32:59 -0500 | [diff] [blame] | 376 | #define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \ |
| 377 | DP_LANE_CHANNEL_EQ_DONE | \ |
| 378 | DP_LANE_SYMBOL_LOCKED) |
| 379 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 380 | #define DP_LANE_ALIGN_STATUS_UPDATED 0x204 |
| 381 | |
| 382 | #define DP_INTERLANE_ALIGN_DONE (1 << 0) |
| 383 | #define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6) |
| 384 | #define DP_LINK_STATUS_UPDATED (1 << 7) |
| 385 | |
| 386 | #define DP_SINK_STATUS 0x205 |
| 387 | |
| 388 | #define DP_RECEIVE_PORT_0_STATUS (1 << 0) |
| 389 | #define DP_RECEIVE_PORT_1_STATUS (1 << 1) |
| 390 | |
| 391 | #define DP_ADJUST_REQUEST_LANE0_1 0x206 |
| 392 | #define DP_ADJUST_REQUEST_LANE2_3 0x207 |
Alex Deucher | 5801ead | 2009-11-24 13:32:59 -0500 | [diff] [blame] | 393 | # define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03 |
| 394 | # define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0 |
| 395 | # define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c |
| 396 | # define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2 |
| 397 | # define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30 |
| 398 | # define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4 |
| 399 | # define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0 |
| 400 | # define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6 |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 401 | |
Jesse Barnes | a60f0e3 | 2011-10-20 15:09:17 -0700 | [diff] [blame] | 402 | #define DP_TEST_REQUEST 0x218 |
| 403 | # define DP_TEST_LINK_TRAINING (1 << 0) |
Todd Previte | fe3c703 | 2013-10-04 12:59:03 -0700 | [diff] [blame] | 404 | # define DP_TEST_LINK_VIDEO_PATTERN (1 << 1) |
Jesse Barnes | a60f0e3 | 2011-10-20 15:09:17 -0700 | [diff] [blame] | 405 | # define DP_TEST_LINK_EDID_READ (1 << 2) |
| 406 | # define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */ |
Todd Previte | fe3c703 | 2013-10-04 12:59:03 -0700 | [diff] [blame] | 407 | # define DP_TEST_LINK_FAUX_PATTERN (1 << 4) /* DPCD >= 1.2 */ |
Jesse Barnes | a60f0e3 | 2011-10-20 15:09:17 -0700 | [diff] [blame] | 408 | |
| 409 | #define DP_TEST_LINK_RATE 0x219 |
| 410 | # define DP_LINK_RATE_162 (0x6) |
| 411 | # define DP_LINK_RATE_27 (0xa) |
| 412 | |
| 413 | #define DP_TEST_LANE_COUNT 0x220 |
| 414 | |
| 415 | #define DP_TEST_PATTERN 0x221 |
| 416 | |
Rodrigo Vivi | a25eebb | 2014-01-14 16:21:49 -0200 | [diff] [blame] | 417 | #define DP_TEST_CRC_R_CR 0x240 |
| 418 | #define DP_TEST_CRC_G_Y 0x242 |
| 419 | #define DP_TEST_CRC_B_CB 0x244 |
| 420 | |
| 421 | #define DP_TEST_SINK_MISC 0x246 |
Rodrigo Vivi | ad9dc91 | 2014-09-16 19:18:12 -0400 | [diff] [blame] | 422 | # define DP_TEST_CRC_SUPPORTED (1 << 5) |
Rodrigo Vivi | 90a2170 | 2015-07-23 16:34:58 -0700 | [diff] [blame] | 423 | # define DP_TEST_COUNT_MASK 0xf |
Rodrigo Vivi | a25eebb | 2014-01-14 16:21:49 -0200 | [diff] [blame] | 424 | |
Jesse Barnes | a60f0e3 | 2011-10-20 15:09:17 -0700 | [diff] [blame] | 425 | #define DP_TEST_RESPONSE 0x260 |
| 426 | # define DP_TEST_ACK (1 << 0) |
| 427 | # define DP_TEST_NAK (1 << 1) |
| 428 | # define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2) |
| 429 | |
Jingoo Han | 073ea2a | 2014-05-07 20:44:51 +0900 | [diff] [blame] | 430 | #define DP_TEST_EDID_CHECKSUM 0x261 |
| 431 | |
Rodrigo Vivi | a25eebb | 2014-01-14 16:21:49 -0200 | [diff] [blame] | 432 | #define DP_TEST_SINK 0x270 |
Rodrigo Vivi | ad9dc91 | 2014-09-16 19:18:12 -0400 | [diff] [blame] | 433 | # define DP_TEST_SINK_START (1 << 0) |
Rodrigo Vivi | a25eebb | 2014-01-14 16:21:49 -0200 | [diff] [blame] | 434 | |
Dave Airlie | 3c8a092 | 2014-05-02 11:05:21 +1000 | [diff] [blame] | 435 | #define DP_PAYLOAD_TABLE_UPDATE_STATUS 0x2c0 /* 1.2 MST */ |
| 436 | # define DP_PAYLOAD_TABLE_UPDATED (1 << 0) |
| 437 | # define DP_PAYLOAD_ACT_HANDLED (1 << 1) |
| 438 | |
| 439 | #define DP_VC_PAYLOAD_ID_SLOT_1 0x2c1 /* 1.2 MST */ |
| 440 | /* up to ID_SLOT_63 at 0x2ff */ |
| 441 | |
Adam Jackson | 86c3c3b | 2012-05-14 16:05:45 -0400 | [diff] [blame] | 442 | #define DP_SOURCE_OUI 0x300 |
| 443 | #define DP_SINK_OUI 0x400 |
| 444 | #define DP_BRANCH_OUI 0x500 |
| 445 | |
Alex Deucher | 1a66c95 | 2009-11-20 19:40:13 -0500 | [diff] [blame] | 446 | #define DP_SET_POWER 0x600 |
Alex Deucher | 5801ead | 2009-11-24 13:32:59 -0500 | [diff] [blame] | 447 | # define DP_SET_POWER_D0 0x1 |
| 448 | # define DP_SET_POWER_D3 0x2 |
Thierry Reding | 516c0f7 | 2013-12-09 11:47:55 +0100 | [diff] [blame] | 449 | # define DP_SET_POWER_MASK 0x3 |
Alex Deucher | 1a66c95 | 2009-11-20 19:40:13 -0500 | [diff] [blame] | 450 | |
Jani Nikula | bd5da99 | 2015-02-25 14:46:51 +0200 | [diff] [blame] | 451 | #define DP_EDP_DPCD_REV 0x700 /* eDP 1.2 */ |
Jani Nikula | 6b1e3f6 | 2015-02-27 13:11:14 +0200 | [diff] [blame] | 452 | # define DP_EDP_11 0x00 |
| 453 | # define DP_EDP_12 0x01 |
| 454 | # define DP_EDP_13 0x02 |
| 455 | # define DP_EDP_14 0x03 |
Sonika Jindal | e045d20 | 2015-02-19 13:16:44 +0530 | [diff] [blame] | 456 | |
Jani Nikula | 0e71244 | 2015-02-25 14:46:53 +0200 | [diff] [blame] | 457 | #define DP_EDP_GENERAL_CAP_1 0x701 |
| 458 | |
| 459 | #define DP_EDP_BACKLIGHT_ADJUSTMENT_CAP 0x702 |
| 460 | |
| 461 | #define DP_EDP_GENERAL_CAP_2 0x703 |
| 462 | |
Jani Nikula | 6b1e3f6 | 2015-02-27 13:11:14 +0200 | [diff] [blame] | 463 | #define DP_EDP_GENERAL_CAP_3 0x704 /* eDP 1.4 */ |
| 464 | |
Jani Nikula | 0e71244 | 2015-02-25 14:46:53 +0200 | [diff] [blame] | 465 | #define DP_EDP_DISPLAY_CONTROL_REGISTER 0x720 |
| 466 | |
| 467 | #define DP_EDP_BACKLIGHT_MODE_SET_REGISTER 0x721 |
| 468 | |
| 469 | #define DP_EDP_BACKLIGHT_BRIGHTNESS_MSB 0x722 |
| 470 | #define DP_EDP_BACKLIGHT_BRIGHTNESS_LSB 0x723 |
| 471 | |
| 472 | #define DP_EDP_PWMGEN_BIT_COUNT 0x724 |
| 473 | #define DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN 0x725 |
| 474 | #define DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX 0x726 |
| 475 | |
| 476 | #define DP_EDP_BACKLIGHT_CONTROL_STATUS 0x727 |
| 477 | |
| 478 | #define DP_EDP_BACKLIGHT_FREQ_SET 0x728 |
| 479 | |
| 480 | #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MSB 0x72a |
| 481 | #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MID 0x72b |
| 482 | #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_LSB 0x72c |
| 483 | |
| 484 | #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MSB 0x72d |
| 485 | #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MID 0x72e |
| 486 | #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB 0x72f |
| 487 | |
| 488 | #define DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET 0x732 |
| 489 | #define DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET 0x733 |
| 490 | |
Jani Nikula | 6b1e3f6 | 2015-02-27 13:11:14 +0200 | [diff] [blame] | 491 | #define DP_EDP_REGIONAL_BACKLIGHT_BASE 0x740 /* eDP 1.4 */ |
| 492 | #define DP_EDP_REGIONAL_BACKLIGHT_0 0x741 /* eDP 1.4 */ |
| 493 | |
Dave Airlie | 3c8a092 | 2014-05-02 11:05:21 +1000 | [diff] [blame] | 494 | #define DP_SIDEBAND_MSG_DOWN_REQ_BASE 0x1000 /* 1.2 MST */ |
| 495 | #define DP_SIDEBAND_MSG_UP_REP_BASE 0x1200 /* 1.2 MST */ |
| 496 | #define DP_SIDEBAND_MSG_DOWN_REP_BASE 0x1400 /* 1.2 MST */ |
| 497 | #define DP_SIDEBAND_MSG_UP_REQ_BASE 0x1600 /* 1.2 MST */ |
| 498 | |
| 499 | #define DP_SINK_COUNT_ESI 0x2002 /* 1.2 */ |
| 500 | /* 0-5 sink count */ |
| 501 | # define DP_SINK_COUNT_CP_READY (1 << 6) |
| 502 | |
| 503 | #define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 0x2003 /* 1.2 */ |
| 504 | |
| 505 | #define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI1 0x2004 /* 1.2 */ |
| 506 | |
| 507 | #define DP_LINK_SERVICE_IRQ_VECTOR_ESI0 0x2005 /* 1.2 */ |
| 508 | |
Adam Jackson | a477f4f | 2012-09-20 16:42:44 -0400 | [diff] [blame] | 509 | #define DP_PSR_ERROR_STATUS 0x2006 /* XXX 1.2? */ |
Ben Widawsky | b73fe58 | 2011-10-04 15:16:48 -0700 | [diff] [blame] | 510 | # define DP_PSR_LINK_CRC_ERROR (1 << 0) |
| 511 | # define DP_PSR_RFB_STORAGE_ERROR (1 << 1) |
Jani Nikula | 6b1e3f6 | 2015-02-27 13:11:14 +0200 | [diff] [blame] | 512 | # define DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR (1 << 2) /* eDP 1.4 */ |
Ben Widawsky | b73fe58 | 2011-10-04 15:16:48 -0700 | [diff] [blame] | 513 | |
Adam Jackson | a477f4f | 2012-09-20 16:42:44 -0400 | [diff] [blame] | 514 | #define DP_PSR_ESI 0x2007 /* XXX 1.2? */ |
Ben Widawsky | b73fe58 | 2011-10-04 15:16:48 -0700 | [diff] [blame] | 515 | # define DP_PSR_CAPS_CHANGE (1 << 0) |
| 516 | |
Adam Jackson | a477f4f | 2012-09-20 16:42:44 -0400 | [diff] [blame] | 517 | #define DP_PSR_STATUS 0x2008 /* XXX 1.2? */ |
Ben Widawsky | b73fe58 | 2011-10-04 15:16:48 -0700 | [diff] [blame] | 518 | # define DP_PSR_SINK_INACTIVE 0 |
| 519 | # define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1 |
| 520 | # define DP_PSR_SINK_ACTIVE_RFB 2 |
| 521 | # define DP_PSR_SINK_ACTIVE_SINK_SYNCED 3 |
| 522 | # define DP_PSR_SINK_ACTIVE_RESYNC 4 |
| 523 | # define DP_PSR_SINK_INTERNAL_ERROR 7 |
| 524 | # define DP_PSR_SINK_STATE_MASK 0x07 |
| 525 | |
Jani Nikula | 6b1e3f6 | 2015-02-27 13:11:14 +0200 | [diff] [blame] | 526 | #define DP_RECEIVER_ALPM_STATUS 0x200b /* eDP 1.4 */ |
| 527 | # define DP_ALPM_LOCK_TIMEOUT_ERROR (1 << 0) |
| 528 | |
Dave Airlie | 3c8a092 | 2014-05-02 11:05:21 +1000 | [diff] [blame] | 529 | /* DP 1.2 Sideband message defines */ |
| 530 | /* peer device type - DP 1.2a Table 2-92 */ |
| 531 | #define DP_PEER_DEVICE_NONE 0x0 |
| 532 | #define DP_PEER_DEVICE_SOURCE_OR_SST 0x1 |
| 533 | #define DP_PEER_DEVICE_MST_BRANCHING 0x2 |
| 534 | #define DP_PEER_DEVICE_SST_SINK 0x3 |
| 535 | #define DP_PEER_DEVICE_DP_LEGACY_CONV 0x4 |
| 536 | |
| 537 | /* DP 1.2 MST sideband request names DP 1.2a Table 2-80 */ |
| 538 | #define DP_LINK_ADDRESS 0x01 |
| 539 | #define DP_CONNECTION_STATUS_NOTIFY 0x02 |
| 540 | #define DP_ENUM_PATH_RESOURCES 0x10 |
| 541 | #define DP_ALLOCATE_PAYLOAD 0x11 |
| 542 | #define DP_QUERY_PAYLOAD 0x12 |
| 543 | #define DP_RESOURCE_STATUS_NOTIFY 0x13 |
| 544 | #define DP_CLEAR_PAYLOAD_ID_TABLE 0x14 |
| 545 | #define DP_REMOTE_DPCD_READ 0x20 |
| 546 | #define DP_REMOTE_DPCD_WRITE 0x21 |
| 547 | #define DP_REMOTE_I2C_READ 0x22 |
| 548 | #define DP_REMOTE_I2C_WRITE 0x23 |
| 549 | #define DP_POWER_UP_PHY 0x24 |
| 550 | #define DP_POWER_DOWN_PHY 0x25 |
| 551 | #define DP_SINK_EVENT_NOTIFY 0x30 |
| 552 | #define DP_QUERY_STREAM_ENC_STATUS 0x38 |
| 553 | |
| 554 | /* DP 1.2 MST sideband nak reasons - table 2.84 */ |
| 555 | #define DP_NAK_WRITE_FAILURE 0x01 |
| 556 | #define DP_NAK_INVALID_READ 0x02 |
| 557 | #define DP_NAK_CRC_FAILURE 0x03 |
| 558 | #define DP_NAK_BAD_PARAM 0x04 |
| 559 | #define DP_NAK_DEFER 0x05 |
| 560 | #define DP_NAK_LINK_FAILURE 0x06 |
| 561 | #define DP_NAK_NO_RESOURCES 0x07 |
| 562 | #define DP_NAK_DPCD_FAIL 0x08 |
| 563 | #define DP_NAK_I2C_NAK 0x09 |
| 564 | #define DP_NAK_ALLOCATE_FAIL 0x0a |
| 565 | |
Dave Airlie | ab2c067 | 2009-12-04 10:55:24 +1000 | [diff] [blame] | 566 | #define MODE_I2C_START 1 |
| 567 | #define MODE_I2C_WRITE 2 |
| 568 | #define MODE_I2C_READ 4 |
| 569 | #define MODE_I2C_STOP 8 |
| 570 | |
Daniel Vetter | 1ffdff1 | 2012-10-18 10:15:24 +0200 | [diff] [blame] | 571 | #define DP_LINK_STATUS_SIZE 6 |
Jani Nikula | 0aec288 | 2013-09-27 19:01:01 +0300 | [diff] [blame] | 572 | bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE], |
Daniel Vetter | 1ffdff1 | 2012-10-18 10:15:24 +0200 | [diff] [blame] | 573 | int lane_count); |
Jani Nikula | 0aec288 | 2013-09-27 19:01:01 +0300 | [diff] [blame] | 574 | bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE], |
Daniel Vetter | 0191627 | 2012-10-18 10:15:25 +0200 | [diff] [blame] | 575 | int lane_count); |
Jani Nikula | 0aec288 | 2013-09-27 19:01:01 +0300 | [diff] [blame] | 576 | u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE], |
Daniel Vetter | 0f037bd | 2012-10-18 10:15:27 +0200 | [diff] [blame] | 577 | int lane); |
Jani Nikula | 0aec288 | 2013-09-27 19:01:01 +0300 | [diff] [blame] | 578 | u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE], |
Daniel Vetter | 0f037bd | 2012-10-18 10:15:27 +0200 | [diff] [blame] | 579 | int lane); |
Daniel Vetter | 1ffdff1 | 2012-10-18 10:15:24 +0200 | [diff] [blame] | 580 | |
Dave Airlie | 4479046 | 2015-07-14 11:33:31 +1000 | [diff] [blame] | 581 | #define DP_BRANCH_OUI_HEADER_SIZE 0xc |
Shobhit Kumar | 52604b1 | 2013-07-11 18:44:55 -0300 | [diff] [blame] | 582 | #define DP_RECEIVER_CAP_SIZE 0xf |
| 583 | #define EDP_PSR_RECEIVER_CAP_SIZE 2 |
| 584 | |
Jani Nikula | 0aec288 | 2013-09-27 19:01:01 +0300 | [diff] [blame] | 585 | void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]); |
| 586 | void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]); |
Daniel Vetter | 1a644cd | 2012-10-18 15:32:40 +0200 | [diff] [blame] | 587 | |
Daniel Vetter | 3b5c662 | 2012-10-18 10:15:31 +0200 | [diff] [blame] | 588 | u8 drm_dp_link_rate_to_bw_code(int link_rate); |
| 589 | int drm_dp_bw_code_to_link_rate(u8 link_bw); |
| 590 | |
Shobhit Kumar | 52604b1 | 2013-07-11 18:44:55 -0300 | [diff] [blame] | 591 | struct edp_sdp_header { |
| 592 | u8 HB0; /* Secondary Data Packet ID */ |
| 593 | u8 HB1; /* Secondary Data Packet Type */ |
| 594 | u8 HB2; /* 7:5 reserved, 4:0 revision number */ |
| 595 | u8 HB3; /* 7:5 reserved, 4:0 number of valid data bytes */ |
| 596 | } __packed; |
| 597 | |
| 598 | #define EDP_SDP_HEADER_REVISION_MASK 0x1F |
| 599 | #define EDP_SDP_HEADER_VALID_PAYLOAD_BYTES 0x1F |
| 600 | |
| 601 | struct edp_vsc_psr { |
| 602 | struct edp_sdp_header sdp_header; |
| 603 | u8 DB0; /* Stereo Interface */ |
| 604 | u8 DB1; /* 0 - PSR State; 1 - Update RFB; 2 - CRC Valid */ |
| 605 | u8 DB2; /* CRC value bits 7:0 of the R or Cr component */ |
| 606 | u8 DB3; /* CRC value bits 15:8 of the R or Cr component */ |
| 607 | u8 DB4; /* CRC value bits 7:0 of the G or Y component */ |
| 608 | u8 DB5; /* CRC value bits 15:8 of the G or Y component */ |
| 609 | u8 DB6; /* CRC value bits 7:0 of the B or Cb component */ |
| 610 | u8 DB7; /* CRC value bits 15:8 of the B or Cb component */ |
| 611 | u8 DB8_31[24]; /* Reserved */ |
| 612 | } __packed; |
| 613 | |
| 614 | #define EDP_VSC_PSR_STATE_ACTIVE (1<<0) |
| 615 | #define EDP_VSC_PSR_UPDATE_RFB (1<<1) |
| 616 | #define EDP_VSC_PSR_CRC_VALUES_VALID (1<<2) |
| 617 | |
Daniel Vetter | 3b5c662 | 2012-10-18 10:15:31 +0200 | [diff] [blame] | 618 | static inline int |
Jani Nikula | 0aec288 | 2013-09-27 19:01:01 +0300 | [diff] [blame] | 619 | drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) |
Daniel Vetter | 3b5c662 | 2012-10-18 10:15:31 +0200 | [diff] [blame] | 620 | { |
| 621 | return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]); |
| 622 | } |
Daniel Vetter | 397fe15 | 2012-10-22 22:56:43 +0200 | [diff] [blame] | 623 | |
| 624 | static inline u8 |
Jani Nikula | 0aec288 | 2013-09-27 19:01:01 +0300 | [diff] [blame] | 625 | drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) |
Daniel Vetter | 397fe15 | 2012-10-22 22:56:43 +0200 | [diff] [blame] | 626 | { |
| 627 | return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; |
| 628 | } |
| 629 | |
Jani Nikula | 58704e6 | 2013-10-04 15:08:08 +0300 | [diff] [blame] | 630 | static inline bool |
| 631 | drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) |
| 632 | { |
| 633 | return dpcd[DP_DPCD_REV] >= 0x11 && |
| 634 | (dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP); |
| 635 | } |
| 636 | |
Thierry Reding | c197db7 | 2013-11-28 11:31:00 +0100 | [diff] [blame] | 637 | /* |
| 638 | * DisplayPort AUX channel |
| 639 | */ |
| 640 | |
| 641 | /** |
| 642 | * struct drm_dp_aux_msg - DisplayPort AUX channel transaction |
| 643 | * @address: address of the (first) register to access |
| 644 | * @request: contains the type of transaction (see DP_AUX_* macros) |
| 645 | * @reply: upon completion, contains the reply type of the transaction |
| 646 | * @buffer: pointer to a transmission or reception buffer |
| 647 | * @size: size of @buffer |
| 648 | */ |
| 649 | struct drm_dp_aux_msg { |
| 650 | unsigned int address; |
| 651 | u8 request; |
| 652 | u8 reply; |
| 653 | void *buffer; |
| 654 | size_t size; |
| 655 | }; |
| 656 | |
| 657 | /** |
| 658 | * struct drm_dp_aux - DisplayPort AUX channel |
Thierry Reding | b838058 | 2014-04-23 15:49:04 +0200 | [diff] [blame] | 659 | * @name: user-visible name of this AUX channel and the I2C-over-AUX adapter |
Thierry Reding | 8875968 | 2013-12-12 09:57:53 +0100 | [diff] [blame] | 660 | * @ddc: I2C adapter that can be used for I2C-over-AUX communication |
Thierry Reding | c197db7 | 2013-11-28 11:31:00 +0100 | [diff] [blame] | 661 | * @dev: pointer to struct device that is the parent for this AUX channel |
Dave Airlie | 4f71d0c | 2014-06-04 16:02:28 +1000 | [diff] [blame] | 662 | * @hw_mutex: internal mutex used for locking transfers |
Thierry Reding | c197db7 | 2013-11-28 11:31:00 +0100 | [diff] [blame] | 663 | * @transfer: transfers a message representing a single AUX transaction |
| 664 | * |
| 665 | * The .dev field should be set to a pointer to the device that implements |
| 666 | * the AUX channel. |
| 667 | * |
Jani Nikula | 9dc4056 | 2014-03-14 16:51:12 +0200 | [diff] [blame] | 668 | * The .name field may be used to specify the name of the I2C adapter. If set to |
| 669 | * NULL, dev_name() of .dev will be used. |
| 670 | * |
Thierry Reding | c197db7 | 2013-11-28 11:31:00 +0100 | [diff] [blame] | 671 | * Drivers provide a hardware-specific implementation of how transactions |
| 672 | * are executed via the .transfer() function. A pointer to a drm_dp_aux_msg |
| 673 | * structure describing the transaction is passed into this function. Upon |
| 674 | * success, the implementation should return the number of payload bytes |
| 675 | * that were transferred, or a negative error-code on failure. Helpers |
| 676 | * propagate errors from the .transfer() function, with the exception of |
| 677 | * the -EBUSY error, which causes a transaction to be retried. On a short, |
| 678 | * helpers will return -EPROTO to make it simpler to check for failure. |
Thierry Reding | 8875968 | 2013-12-12 09:57:53 +0100 | [diff] [blame] | 679 | * |
| 680 | * An AUX channel can also be used to transport I2C messages to a sink. A |
| 681 | * typical application of that is to access an EDID that's present in the |
| 682 | * sink device. The .transfer() function can also be used to execute such |
Jon Hunter | 6921f88 | 2015-05-13 12:30:46 +0100 | [diff] [blame] | 683 | * transactions. The drm_dp_aux_register() function registers an I2C |
| 684 | * adapter that can be passed to drm_probe_ddc(). Upon removal, drivers |
| 685 | * should call drm_dp_aux_unregister() to remove the I2C adapter. |
Simon Farnsworth | 1d002fa | 2015-02-10 18:38:08 +0000 | [diff] [blame] | 686 | * The I2C adapter uses long transfers by default; if a partial response is |
| 687 | * received, the adapter will drop down to the size given by the partial |
| 688 | * response for this transaction only. |
Alex Deucher | 732d50b | 2014-04-07 10:33:45 -0400 | [diff] [blame] | 689 | * |
| 690 | * Note that the aux helper code assumes that the .transfer() function |
| 691 | * only modifies the reply field of the drm_dp_aux_msg structure. The |
| 692 | * retry logic and i2c helpers assume this is the case. |
Thierry Reding | c197db7 | 2013-11-28 11:31:00 +0100 | [diff] [blame] | 693 | */ |
| 694 | struct drm_dp_aux { |
Jani Nikula | 9dc4056 | 2014-03-14 16:51:12 +0200 | [diff] [blame] | 695 | const char *name; |
Thierry Reding | 8875968 | 2013-12-12 09:57:53 +0100 | [diff] [blame] | 696 | struct i2c_adapter ddc; |
Thierry Reding | c197db7 | 2013-11-28 11:31:00 +0100 | [diff] [blame] | 697 | struct device *dev; |
Dave Airlie | 4f71d0c | 2014-06-04 16:02:28 +1000 | [diff] [blame] | 698 | struct mutex hw_mutex; |
Thierry Reding | c197db7 | 2013-11-28 11:31:00 +0100 | [diff] [blame] | 699 | ssize_t (*transfer)(struct drm_dp_aux *aux, |
| 700 | struct drm_dp_aux_msg *msg); |
Todd Previte | e9cf619 | 2014-11-04 15:17:35 -0700 | [diff] [blame] | 701 | unsigned i2c_nack_count, i2c_defer_count; |
Thierry Reding | c197db7 | 2013-11-28 11:31:00 +0100 | [diff] [blame] | 702 | }; |
| 703 | |
| 704 | ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset, |
| 705 | void *buffer, size_t size); |
| 706 | ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset, |
| 707 | void *buffer, size_t size); |
| 708 | |
| 709 | /** |
| 710 | * drm_dp_dpcd_readb() - read a single byte from the DPCD |
| 711 | * @aux: DisplayPort AUX channel |
| 712 | * @offset: address of the register to read |
| 713 | * @valuep: location where the value of the register will be stored |
| 714 | * |
| 715 | * Returns the number of bytes transferred (1) on success, or a negative |
| 716 | * error code on failure. |
| 717 | */ |
| 718 | static inline ssize_t drm_dp_dpcd_readb(struct drm_dp_aux *aux, |
| 719 | unsigned int offset, u8 *valuep) |
| 720 | { |
| 721 | return drm_dp_dpcd_read(aux, offset, valuep, 1); |
| 722 | } |
| 723 | |
| 724 | /** |
| 725 | * drm_dp_dpcd_writeb() - write a single byte to the DPCD |
| 726 | * @aux: DisplayPort AUX channel |
| 727 | * @offset: address of the register to write |
| 728 | * @value: value to write to the register |
| 729 | * |
| 730 | * Returns the number of bytes transferred (1) on success, or a negative |
| 731 | * error code on failure. |
| 732 | */ |
| 733 | static inline ssize_t drm_dp_dpcd_writeb(struct drm_dp_aux *aux, |
| 734 | unsigned int offset, u8 value) |
| 735 | { |
| 736 | return drm_dp_dpcd_write(aux, offset, &value, 1); |
| 737 | } |
| 738 | |
Thierry Reding | 8d4adc6 | 2013-11-22 16:37:57 +0100 | [diff] [blame] | 739 | int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux, |
| 740 | u8 status[DP_LINK_STATUS_SIZE]); |
| 741 | |
Thierry Reding | 516c0f7 | 2013-12-09 11:47:55 +0100 | [diff] [blame] | 742 | /* |
| 743 | * DisplayPort link |
| 744 | */ |
| 745 | #define DP_LINK_CAP_ENHANCED_FRAMING (1 << 0) |
| 746 | |
| 747 | struct drm_dp_link { |
| 748 | unsigned char revision; |
| 749 | unsigned int rate; |
| 750 | unsigned int num_lanes; |
| 751 | unsigned long capabilities; |
| 752 | }; |
| 753 | |
| 754 | int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link); |
| 755 | int drm_dp_link_power_up(struct drm_dp_aux *aux, struct drm_dp_link *link); |
Rob Clark | d816f07 | 2014-12-02 10:43:07 -0500 | [diff] [blame] | 756 | int drm_dp_link_power_down(struct drm_dp_aux *aux, struct drm_dp_link *link); |
Thierry Reding | 516c0f7 | 2013-12-09 11:47:55 +0100 | [diff] [blame] | 757 | int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link); |
| 758 | |
Dave Airlie | 4f71d0c | 2014-06-04 16:02:28 +1000 | [diff] [blame] | 759 | int drm_dp_aux_register(struct drm_dp_aux *aux); |
| 760 | void drm_dp_aux_unregister(struct drm_dp_aux *aux); |
Thierry Reding | 8875968 | 2013-12-12 09:57:53 +0100 | [diff] [blame] | 761 | |
Dave Airlie | ab2c067 | 2009-12-04 10:55:24 +1000 | [diff] [blame] | 762 | #endif /* _DRM_DP_HELPER_H_ */ |