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gerrit-public.fairphone.software / kernel / msm-4.9 / 07e9f58703f53b7baf4f9f47bbd2b59320cd504b / . / arch / arm / boot / dts / tegra30.dtsi
blob: b1497c7d7d6851db3753c1210e974cb9e47888c2 [file] [log] [blame]
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]1/include/ "skeleton.dtsi"
2
3/ {
4 compatible = "nvidia,tegra30";
5 interrupt-parent = <&intc>;
6
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]7 intc: interrupt-controller {
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]8 compatible = "arm,cortex-a9-gic";
Stephen Warren5ff48882012-05-11 16:26:03 -0600[diff] [blame]9 reg = <0x50041000 0x1000
10 0x50040100 0x0100>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]11 interrupt-controller;
12 #interrupt-cells = <3>;
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]13 };
14
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]15 apbdma: dma {
Stephen Warren8051b752012-01-11 16:09:54 -0700[diff] [blame]16 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
17 reg = <0x6000a000 0x1400>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]18 interrupts = <0 104 0x04
19 0 105 0x04
20 0 106 0x04
21 0 107 0x04
22 0 108 0x04
23 0 109 0x04
24 0 110 0x04
25 0 111 0x04
26 0 112 0x04
27 0 113 0x04
28 0 114 0x04
29 0 115 0x04
30 0 116 0x04
31 0 117 0x04
32 0 118 0x04
33 0 119 0x04
34 0 128 0x04
35 0 129 0x04
36 0 130 0x04
37 0 131 0x04
38 0 132 0x04
39 0 133 0x04
40 0 134 0x04
41 0 135 0x04
42 0 136 0x04
43 0 137 0x04
44 0 138 0x04
45 0 139 0x04
46 0 140 0x04
47 0 141 0x04
48 0 142 0x04
49 0 143 0x04>;
Stephen Warren8051b752012-01-11 16:09:54 -0700[diff] [blame]50 };
51
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]52 ahb: ahb {
53 compatible = "nvidia,tegra30-ahb";
54 reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */
55 };
56
57 gpio: gpio {
58 compatible = "nvidia,tegra30-gpio", "nvidia,tegra20-gpio";
59 reg = <0x6000d000 0x1000>;
60 interrupts = <0 32 0x04
61 0 33 0x04
62 0 34 0x04
63 0 35 0x04
64 0 55 0x04
65 0 87 0x04
66 0 89 0x04
67 0 125 0x04>;
68 #gpio-cells = <2>;
69 gpio-controller;
70 #interrupt-cells = <2>;
71 interrupt-controller;
72 };
73
74 pinmux: pinmux {
75 compatible = "nvidia,tegra30-pinmux";
76 reg = <0x70000868 0xd0 /* Pad control registers */
77 0x70003000 0x3e0>; /* Mux registers */
78 };
79
80 serial@70006000 {
81 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
82 reg = <0x70006000 0x40>;
83 reg-shift = <2>;
84 interrupts = <0 36 0x04>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]85 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]86 };
87
88 serial@70006040 {
89 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
90 reg = <0x70006040 0x40>;
91 reg-shift = <2>;
92 interrupts = <0 37 0x04>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]93 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]94 };
95
96 serial@70006200 {
97 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
98 reg = <0x70006200 0x100>;
99 reg-shift = <2>;
100 interrupts = <0 46 0x04>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]101 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]102 };
103
104 serial@70006300 {
105 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
106 reg = <0x70006300 0x100>;
107 reg-shift = <2>;
108 interrupts = <0 90 0x04>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]109 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]110 };
111
112 serial@70006400 {
113 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
114 reg = <0x70006400 0x100>;
115 reg-shift = <2>;
116 interrupts = <0 91 0x04>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]117 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]118 };
119
Thierry Reding2b8b15d2012-09-20 17:06:05 +0200[diff] [blame]120 pwm: pwm {
Thierry Reding140fd972011-12-21 08:04:13 +0100[diff] [blame]121 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
122 reg = <0x7000a000 0x100>;
123 #pwm-cells = <2>;
124 };
125
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]126 i2c@7000c000 {
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]127 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
Stephen Warrenba04c282012-05-11 16:28:59 -0600[diff] [blame]128 reg = <0x7000c000 0x100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]129 interrupts = <0 38 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]130 #address-cells = <1>;
131 #size-cells = <0>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]132 status = "disabled";
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]133 };
134
135 i2c@7000c400 {
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]136 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
Stephen Warrenba04c282012-05-11 16:28:59 -0600[diff] [blame]137 reg = <0x7000c400 0x100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]138 interrupts = <0 84 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]139 #address-cells = <1>;
140 #size-cells = <0>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]141 status = "disabled";
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]142 };
143
144 i2c@7000c500 {
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]145 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
Stephen Warrenba04c282012-05-11 16:28:59 -0600[diff] [blame]146 reg = <0x7000c500 0x100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]147 interrupts = <0 92 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]148 #address-cells = <1>;
149 #size-cells = <0>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]150 status = "disabled";
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]151 };
152
153 i2c@7000c700 {
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]154 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
155 reg = <0x7000c700 0x100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]156 interrupts = <0 120 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]157 #address-cells = <1>;
158 #size-cells = <0>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]159 status = "disabled";
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]160 };
161
162 i2c@7000d000 {
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]163 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
Stephen Warrenba04c282012-05-11 16:28:59 -0600[diff] [blame]164 reg = <0x7000d000 0x100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]165 interrupts = <0 53 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]166 #address-cells = <1>;
167 #size-cells = <0>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]168 status = "disabled";
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]169 };
170
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]171 pmc {
172 compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc";
173 reg = <0x7000e400 0x400>;
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]174 };
175
hdoyu@nvidia.coma9140aa2012-05-16 19:47:44 +0000[diff] [blame]176 memory-controller {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]177 compatible = "nvidia,tegra30-mc";
178 reg = <0x7000f000 0x010
179 0x7000f03c 0x1b4
180 0x7000f200 0x028
181 0x7000f284 0x17c>;
182 interrupts = <0 77 0x04>;
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]183 };
184
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]185 smmu {
186 compatible = "nvidia,tegra30-smmu";
187 reg = <0x7000f010 0x02c
188 0x7000f1f0 0x010
189 0x7000f228 0x05c>;
190 nvidia,#asids = <4>; /* # of ASIDs */
191 dma-window = <0 0x40000000>; /* IOVA start & length */
192 nvidia,ahb = <&ahb>;
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]193 };
Stephen Warren9ee6a5c2012-03-27 12:40:53 -0600[diff] [blame]194
195 ahub {
196 compatible = "nvidia,tegra30-ahub";
Stephen Warren5ff48882012-05-11 16:26:03 -0600[diff] [blame]197 reg = <0x70080000 0x200
198 0x70080200 0x100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]199 interrupts = <0 103 0x04>;
Stephen Warren9ee6a5c2012-03-27 12:40:53 -0600[diff] [blame]200 nvidia,dma-request-selector = <&apbdma 1>;
201
202 ranges;
203 #address-cells = <1>;
204 #size-cells = <1>;
205
206 tegra_i2s0: i2s@70080300 {
207 compatible = "nvidia,tegra30-i2s";
208 reg = <0x70080300 0x100>;
209 nvidia,ahub-cif-ids = <4 4>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]210 status = "disabled";
Stephen Warren9ee6a5c2012-03-27 12:40:53 -0600[diff] [blame]211 };
212
213 tegra_i2s1: i2s@70080400 {
214 compatible = "nvidia,tegra30-i2s";
215 reg = <0x70080400 0x100>;
216 nvidia,ahub-cif-ids = <5 5>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]217 status = "disabled";
Stephen Warren9ee6a5c2012-03-27 12:40:53 -0600[diff] [blame]218 };
219
220 tegra_i2s2: i2s@70080500 {
221 compatible = "nvidia,tegra30-i2s";
222 reg = <0x70080500 0x100>;
223 nvidia,ahub-cif-ids = <6 6>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]224 status = "disabled";
Stephen Warren9ee6a5c2012-03-27 12:40:53 -0600[diff] [blame]225 };
226
227 tegra_i2s3: i2s@70080600 {
228 compatible = "nvidia,tegra30-i2s";
229 reg = <0x70080600 0x100>;
230 nvidia,ahub-cif-ids = <7 7>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]231 status = "disabled";
Stephen Warren9ee6a5c2012-03-27 12:40:53 -0600[diff] [blame]232 };
233
234 tegra_i2s4: i2s@70080700 {
235 compatible = "nvidia,tegra30-i2s";
236 reg = <0x70080700 0x100>;
237 nvidia,ahub-cif-ids = <8 8>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]238 status = "disabled";
Stephen Warren9ee6a5c2012-03-27 12:40:53 -0600[diff] [blame]239 };
240 };
Hiroshi DOYU7868a9b2012-05-07 09:43:47 +0300[diff] [blame]241
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]242 sdhci@78000000 {
243 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
244 reg = <0x78000000 0x200>;
245 interrupts = <0 14 0x04>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]246 status = "disabled";
Hiroshi DOYU7868a9b2012-05-07 09:43:47 +0300[diff] [blame]247 };
hdoyu@nvidia.comecf43742012-05-09 21:42:33 +0000[diff] [blame]248
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]249 sdhci@78000200 {
250 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
251 reg = <0x78000200 0x200>;
252 interrupts = <0 15 0x04>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]253 status = "disabled";
hdoyu@nvidia.comecf43742012-05-09 21:42:33 +0000[diff] [blame]254 };
hdoyu@nvidia.com54174a32012-05-09 21:50:21 +0000[diff] [blame]255
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]256 sdhci@78000400 {
257 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
258 reg = <0x78000400 0x200>;
259 interrupts = <0 19 0x04>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]260 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]261 };
262
263 sdhci@78000600 {
264 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
265 reg = <0x78000600 0x200>;
266 interrupts = <0 31 0x04>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]267 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]268 };
269
270 pmu {
271 compatible = "arm,cortex-a9-pmu";
272 interrupts = <0 144 0x04
273 0 145 0x04
274 0 146 0x04
275 0 147 0x04>;
hdoyu@nvidia.com54174a32012-05-09 21:50:21 +0000[diff] [blame]276 };
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]277};