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gerrit-public.fairphone.software / kernel / msm-4.9 / 08571f1ae327bfb631cb7171bde5ea605df626c6 / . / drivers / clk / samsung / clk-exynos4415.c
blob: 2123fc251e0f6960b7566759088914162b840c89 [file] [log] [blame]
Chanwoo Choi384cb2c2014-10-27 10:11:57 +0900[diff] [blame]1/*
2 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
3 * Author: Chanwoo Choi <cw00.choi@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * Common Clock Framework support for Exynos4415 SoC.
10 */
11
12#include <linux/clk.h>
13#include <linux/clkdev.h>
14#include <linux/clk-provider.h>
15#include <linux/of.h>
16#include <linux/of_address.h>
17#include <linux/platform_device.h>
18#include <linux/syscore_ops.h>
19
20#include <dt-bindings/clock/exynos4415.h>
21
22#include "clk.h"
23#include "clk-pll.h"
24
25#define SRC_LEFTBUS 0x4200
26#define DIV_LEFTBUS 0x4500
27#define GATE_IP_LEFTBUS 0x4800
28#define GATE_IP_IMAGE 0x4930
29#define SRC_RIGHTBUS 0x8200
30#define DIV_RIGHTBUS 0x8500
31#define GATE_IP_RIGHTBUS 0x8800
32#define GATE_IP_PERIR 0x8960
33#define EPLL_LOCK 0xc010
34#define G3D_PLL_LOCK 0xc020
35#define DISP_PLL_LOCK 0xc030
36#define ISP_PLL_LOCK 0xc040
37#define EPLL_CON0 0xc110
38#define EPLL_CON1 0xc114
39#define EPLL_CON2 0xc118
40#define G3D_PLL_CON0 0xc120
41#define G3D_PLL_CON1 0xc124
42#define G3D_PLL_CON2 0xc128
43#define ISP_PLL_CON0 0xc130
44#define ISP_PLL_CON1 0xc134
45#define ISP_PLL_CON2 0xc138
46#define DISP_PLL_CON0 0xc140
47#define DISP_PLL_CON1 0xc144
48#define DISP_PLL_CON2 0xc148
49#define SRC_TOP0 0xc210
50#define SRC_TOP1 0xc214
51#define SRC_CAM 0xc220
52#define SRC_TV 0xc224
53#define SRC_MFC 0xc228
54#define SRC_G3D 0xc22c
55#define SRC_LCD 0xc234
56#define SRC_ISP 0xc238
57#define SRC_MAUDIO 0xc23c
58#define SRC_FSYS 0xc240
59#define SRC_PERIL0 0xc250
60#define SRC_PERIL1 0xc254
61#define SRC_CAM1 0xc258
62#define SRC_TOP_ISP0 0xc25c
63#define SRC_TOP_ISP1 0xc260
64#define SRC_MASK_TOP 0xc310
65#define SRC_MASK_CAM 0xc320
66#define SRC_MASK_TV 0xc324
67#define SRC_MASK_LCD 0xc334
68#define SRC_MASK_ISP 0xc338
69#define SRC_MASK_MAUDIO 0xc33c
70#define SRC_MASK_FSYS 0xc340
71#define SRC_MASK_PERIL0 0xc350
72#define SRC_MASK_PERIL1 0xc354
73#define DIV_TOP 0xc510
74#define DIV_CAM 0xc520
75#define DIV_TV 0xc524
76#define DIV_MFC 0xc528
77#define DIV_G3D 0xc52c
78#define DIV_LCD 0xc534
79#define DIV_ISP 0xc538
80#define DIV_MAUDIO 0xc53c
81#define DIV_FSYS0 0xc540
82#define DIV_FSYS1 0xc544
83#define DIV_FSYS2 0xc548
84#define DIV_PERIL0 0xc550
85#define DIV_PERIL1 0xc554
86#define DIV_PERIL2 0xc558
87#define DIV_PERIL3 0xc55c
88#define DIV_PERIL4 0xc560
89#define DIV_PERIL5 0xc564
90#define DIV_CAM1 0xc568
91#define DIV_TOP_ISP1 0xc56c
92#define DIV_TOP_ISP0 0xc570
93#define CLKDIV2_RATIO 0xc580
94#define GATE_SCLK_CAM 0xc820
95#define GATE_SCLK_TV 0xc824
96#define GATE_SCLK_MFC 0xc828
97#define GATE_SCLK_G3D 0xc82c
98#define GATE_SCLK_LCD 0xc834
99#define GATE_SCLK_MAUDIO 0xc83c
100#define GATE_SCLK_FSYS 0xc840
101#define GATE_SCLK_PERIL 0xc850
102#define GATE_IP_CAM 0xc920
103#define GATE_IP_TV 0xc924
104#define GATE_IP_MFC 0xc928
105#define GATE_IP_G3D 0xc92c
106#define GATE_IP_LCD 0xc934
107#define GATE_IP_FSYS 0xc940
108#define GATE_IP_PERIL 0xc950
109#define GATE_BLOCK 0xc970
110#define APLL_LOCK 0x14000
111#define APLL_CON0 0x14100
112#define SRC_CPU 0x14200
113#define DIV_CPU0 0x14500
114#define DIV_CPU1 0x14504
115
116enum exynos4415_plls {
117 apll, epll, g3d_pll, isp_pll, disp_pll,
118 nr_plls,
119};
120
Krzysztof Kozlowskib5f56e12014-12-01 10:12:54 +0100[diff] [blame]121static struct samsung_clk_provider *exynos4415_ctx;
122
Chanwoo Choi384cb2c2014-10-27 10:11:57 +0900[diff] [blame]123/*
124 * Support for CMU save/restore across system suspends
125 */
126#ifdef CONFIG_PM_SLEEP
127static struct samsung_clk_reg_dump *exynos4415_clk_regs;
Chanwoo Choi384cb2c2014-10-27 10:11:57 +0900[diff] [blame]128
129static unsigned long exynos4415_cmu_clk_regs[] __initdata = {
130 SRC_LEFTBUS,
131 DIV_LEFTBUS,
132 GATE_IP_LEFTBUS,
133 GATE_IP_IMAGE,
134 SRC_RIGHTBUS,
135 DIV_RIGHTBUS,
136 GATE_IP_RIGHTBUS,
137 GATE_IP_PERIR,
138 EPLL_LOCK,
139 G3D_PLL_LOCK,
140 DISP_PLL_LOCK,
141 ISP_PLL_LOCK,
142 EPLL_CON0,
143 EPLL_CON1,
144 EPLL_CON2,
145 G3D_PLL_CON0,
146 G3D_PLL_CON1,
147 G3D_PLL_CON2,
148 ISP_PLL_CON0,
149 ISP_PLL_CON1,
150 ISP_PLL_CON2,
151 DISP_PLL_CON0,
152 DISP_PLL_CON1,
153 DISP_PLL_CON2,
154 SRC_TOP0,
155 SRC_TOP1,
156 SRC_CAM,
157 SRC_TV,
158 SRC_MFC,
159 SRC_G3D,
160 SRC_LCD,
161 SRC_ISP,
162 SRC_MAUDIO,
163 SRC_FSYS,
164 SRC_PERIL0,
165 SRC_PERIL1,
166 SRC_CAM1,
167 SRC_TOP_ISP0,
168 SRC_TOP_ISP1,
169 SRC_MASK_TOP,
170 SRC_MASK_CAM,
171 SRC_MASK_TV,
172 SRC_MASK_LCD,
173 SRC_MASK_ISP,
174 SRC_MASK_MAUDIO,
175 SRC_MASK_FSYS,
176 SRC_MASK_PERIL0,
177 SRC_MASK_PERIL1,
178 DIV_TOP,
179 DIV_CAM,
180 DIV_TV,
181 DIV_MFC,
182 DIV_G3D,
183 DIV_LCD,
184 DIV_ISP,
185 DIV_MAUDIO,
186 DIV_FSYS0,
187 DIV_FSYS1,
188 DIV_FSYS2,
189 DIV_PERIL0,
190 DIV_PERIL1,
191 DIV_PERIL2,
192 DIV_PERIL3,
193 DIV_PERIL4,
194 DIV_PERIL5,
195 DIV_CAM1,
196 DIV_TOP_ISP1,
197 DIV_TOP_ISP0,
198 CLKDIV2_RATIO,
199 GATE_SCLK_CAM,
200 GATE_SCLK_TV,
201 GATE_SCLK_MFC,
202 GATE_SCLK_G3D,
203 GATE_SCLK_LCD,
204 GATE_SCLK_MAUDIO,
205 GATE_SCLK_FSYS,
206 GATE_SCLK_PERIL,
207 GATE_IP_CAM,
208 GATE_IP_TV,
209 GATE_IP_MFC,
210 GATE_IP_G3D,
211 GATE_IP_LCD,
212 GATE_IP_FSYS,
213 GATE_IP_PERIL,
214 GATE_BLOCK,
215 APLL_LOCK,
216 APLL_CON0,
217 SRC_CPU,
218 DIV_CPU0,
219 DIV_CPU1,
220};
221
222static int exynos4415_clk_suspend(void)
223{
224 samsung_clk_save(exynos4415_ctx->reg_base, exynos4415_clk_regs,
225 ARRAY_SIZE(exynos4415_cmu_clk_regs));
226
227 return 0;
228}
229
230static void exynos4415_clk_resume(void)
231{
232 samsung_clk_restore(exynos4415_ctx->reg_base, exynos4415_clk_regs,
233 ARRAY_SIZE(exynos4415_cmu_clk_regs));
234}
235
236static struct syscore_ops exynos4415_clk_syscore_ops = {
237 .suspend = exynos4415_clk_suspend,
238 .resume = exynos4415_clk_resume,
239};
240
241static void exynos4415_clk_sleep_init(void)
242{
243 exynos4415_clk_regs =
244 samsung_clk_alloc_reg_dump(exynos4415_cmu_clk_regs,
245 ARRAY_SIZE(exynos4415_cmu_clk_regs));
246 if (!exynos4415_clk_regs) {
247 pr_warn("%s: Failed to allocate sleep save data\n", __func__);
248 return;
249 }
250
251 register_syscore_ops(&exynos4415_clk_syscore_ops);
252}
253#else
254static inline void exynos4415_clk_sleep_init(void) { }
255#endif
256
257/* list of all parent clock list */
258PNAME(mout_g3d_pllsrc_p) = { "fin_pll", };
259
260PNAME(mout_apll_p) = { "fin_pll", "fout_apll", };
261PNAME(mout_g3d_pll_p) = { "fin_pll", "fout_g3d_pll", };
262PNAME(mout_isp_pll_p) = { "fin_pll", "fout_isp_pll", };
263PNAME(mout_disp_pll_p) = { "fin_pll", "fout_disp_pll", };
264
265PNAME(mout_mpll_user_p) = { "fin_pll", "div_mpll_pre", };
266PNAME(mout_epll_p) = { "fin_pll", "fout_epll", };
267PNAME(mout_core_p) = { "mout_apll", "mout_mpll_user_c", };
268PNAME(mout_hpm_p) = { "mout_apll", "mout_mpll_user_c", };
269
270PNAME(mout_ebi_p) = { "div_aclk_200", "div_aclk_160", };
271PNAME(mout_ebi_1_p) = { "mout_ebi", "mout_g3d_pll", };
272
273PNAME(mout_gdl_p) = { "mout_mpll_user_l", };
274PNAME(mout_gdr_p) = { "mout_mpll_user_r", };
275
276PNAME(mout_aclk_266_p) = { "mout_mpll_user_t", "mout_g3d_pll", };
277
278PNAME(group_epll_g3dpll_p) = { "mout_epll", "mout_g3d_pll" };
279PNAME(group_sclk_p) = { "xxti", "xusbxti",
280 "none", "mout_isp_pll",
281 "none", "none", "div_mpll_pre",
282 "mout_epll", "mout_g3d_pll", };
283PNAME(group_spdif_p) = { "mout_audio0", "mout_audio1",
284 "mout_audio2", "spdif_extclk", };
285PNAME(group_sclk_audio2_p) = { "audiocdclk2", "none",
286 "none", "mout_isp_pll",
287 "mout_disp_pll", "xusbxti",
288 "div_mpll_pre", "mout_epll",
289 "mout_g3d_pll", };
290PNAME(group_sclk_audio1_p) = { "audiocdclk1", "none",
291 "none", "mout_isp_pll",
292 "mout_disp_pll", "xusbxti",
293 "div_mpll_pre", "mout_epll",
294 "mout_g3d_pll", };
295PNAME(group_sclk_audio0_p) = { "audiocdclk0", "none",
296 "none", "mout_isp_pll",
297 "mout_disp_pll", "xusbxti",
298 "div_mpll_pre", "mout_epll",
299 "mout_g3d_pll", };
300PNAME(group_fimc_lclk_p) = { "xxti", "xusbxti",
301 "none", "mout_isp_pll",
302 "none", "mout_disp_pll",
303 "mout_mpll_user_t", "mout_epll",
304 "mout_g3d_pll", };
305PNAME(group_sclk_fimd0_p) = { "xxti", "xusbxti",
306 "m_bitclkhsdiv4_4l", "mout_isp_pll",
307 "mout_disp_pll", "sclk_hdmiphy",
308 "div_mpll_pre", "mout_epll",
309 "mout_g3d_pll", };
310PNAME(mout_hdmi_p) = { "sclk_pixel", "sclk_hdmiphy" };
311PNAME(mout_mfc_p) = { "mout_mfc_0", "mout_mfc_1" };
312PNAME(mout_g3d_p) = { "mout_g3d_0", "mout_g3d_1" };
313PNAME(mout_jpeg_p) = { "mout_jpeg_0", "mout_jpeg_1" };
314PNAME(mout_jpeg1_p) = { "mout_epll", "mout_g3d_pll" };
315PNAME(group_aclk_isp0_300_p) = { "mout_isp_pll", "div_mpll_pre" };
316PNAME(group_aclk_isp0_400_user_p) = { "fin_pll", "div_aclk_400_mcuisp" };
317PNAME(group_aclk_isp0_300_user_p) = { "fin_pll", "mout_aclk_isp0_300" };
318PNAME(group_aclk_isp1_300_user_p) = { "fin_pll", "mout_aclk_isp1_300" };
319PNAME(group_mout_mpll_user_t_p) = { "mout_mpll_user_t" };
320
321static struct samsung_fixed_factor_clock exynos4415_fixed_factor_clks[] __initdata = {
322 /* HACK: fin_pll hardcoded to xusbxti until detection is implemented. */
323 FFACTOR(CLK_FIN_PLL, "fin_pll", "xusbxti", 1, 1, 0),
324};
325
326static struct samsung_fixed_rate_clock exynos4415_fixed_rate_clks[] __initdata = {
327 FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 27000000),
328};
329
330static struct samsung_mux_clock exynos4415_mux_clks[] __initdata = {
331 /*
332 * NOTE: Following table is sorted by register address in ascending
333 * order and then bitfield shift in descending order, as it is done
334 * in the User's Manual. When adding new entries, please make sure
335 * that the order is preserved, to avoid merge conflicts and make
336 * further work with defined data easier.
337 */
338
339 /* SRC_LEFTBUS */
340 MUX(CLK_MOUT_MPLL_USER_L, "mout_mpll_user_l", mout_mpll_user_p,
341 SRC_LEFTBUS, 4, 1),
342 MUX(CLK_MOUT_GDL, "mout_gdl", mout_gdl_p, SRC_LEFTBUS, 0, 1),
343
344 /* SRC_RIGHTBUS */
345 MUX(CLK_MOUT_MPLL_USER_R, "mout_mpll_user_r", mout_mpll_user_p,
346 SRC_RIGHTBUS, 4, 1),
347 MUX(CLK_MOUT_GDR, "mout_gdr", mout_gdr_p, SRC_RIGHTBUS, 0, 1),
348
349 /* SRC_TOP0 */
350 MUX(CLK_MOUT_EBI, "mout_ebi", mout_ebi_p, SRC_TOP0, 28, 1),
351 MUX(CLK_MOUT_ACLK_200, "mout_aclk_200", group_mout_mpll_user_t_p,
352 SRC_TOP0, 24, 1),
353 MUX(CLK_MOUT_ACLK_160, "mout_aclk_160", group_mout_mpll_user_t_p,
354 SRC_TOP0, 20, 1),
355 MUX(CLK_MOUT_ACLK_100, "mout_aclk_100", group_mout_mpll_user_t_p,
356 SRC_TOP0, 16, 1),
357 MUX(CLK_MOUT_ACLK_266, "mout_aclk_266", mout_aclk_266_p,
358 SRC_TOP0, 12, 1),
359 MUX(CLK_MOUT_G3D_PLL, "mout_g3d_pll", mout_g3d_pll_p,
360 SRC_TOP0, 8, 1),
361 MUX(CLK_MOUT_EPLL, "mout_epll", mout_epll_p, SRC_TOP0, 4, 1),
362 MUX(CLK_MOUT_EBI_1, "mout_ebi_1", mout_ebi_1_p, SRC_TOP0, 0, 1),
363
364 /* SRC_TOP1 */
365 MUX(CLK_MOUT_ISP_PLL, "mout_isp_pll", mout_isp_pll_p,
366 SRC_TOP1, 28, 1),
367 MUX(CLK_MOUT_DISP_PLL, "mout_disp_pll", mout_disp_pll_p,
368 SRC_TOP1, 16, 1),
369 MUX(CLK_MOUT_MPLL_USER_T, "mout_mpll_user_t", mout_mpll_user_p,
370 SRC_TOP1, 12, 1),
371 MUX(CLK_MOUT_ACLK_400_MCUISP, "mout_aclk_400_mcuisp",
372 group_mout_mpll_user_t_p, SRC_TOP1, 8, 1),
373 MUX(CLK_MOUT_G3D_PLLSRC, "mout_g3d_pllsrc", mout_g3d_pllsrc_p,
374 SRC_TOP1, 0, 1),
375
376 /* SRC_CAM */
377 MUX(CLK_MOUT_CSIS1, "mout_csis1", group_fimc_lclk_p, SRC_CAM, 28, 4),
378 MUX(CLK_MOUT_CSIS0, "mout_csis0", group_fimc_lclk_p, SRC_CAM, 24, 4),
379 MUX(CLK_MOUT_CAM1, "mout_cam1", group_fimc_lclk_p, SRC_CAM, 20, 4),
380 MUX(CLK_MOUT_FIMC3_LCLK, "mout_fimc3_lclk", group_fimc_lclk_p, SRC_CAM,
381 12, 4),
382 MUX(CLK_MOUT_FIMC2_LCLK, "mout_fimc2_lclk", group_fimc_lclk_p, SRC_CAM,
383 8, 4),
384 MUX(CLK_MOUT_FIMC1_LCLK, "mout_fimc1_lclk", group_fimc_lclk_p, SRC_CAM,
385 4, 4),
386 MUX(CLK_MOUT_FIMC0_LCLK, "mout_fimc0_lclk", group_fimc_lclk_p, SRC_CAM,
387 0, 4),
388
389 /* SRC_TV */
390 MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_TV, 0, 1),
391
392 /* SRC_MFC */
393 MUX(CLK_MOUT_MFC, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1),
394 MUX(CLK_MOUT_MFC_1, "mout_mfc_1", group_epll_g3dpll_p, SRC_MFC, 4, 1),
395 MUX(CLK_MOUT_MFC_0, "mout_mfc_0", group_mout_mpll_user_t_p, SRC_MFC, 0,
396 1),
397
398 /* SRC_G3D */
399 MUX(CLK_MOUT_G3D, "mout_g3d", mout_g3d_p, SRC_G3D, 8, 1),
400 MUX(CLK_MOUT_G3D_1, "mout_g3d_1", group_epll_g3dpll_p, SRC_G3D, 4, 1),
401 MUX(CLK_MOUT_G3D_0, "mout_g3d_0", group_mout_mpll_user_t_p, SRC_G3D, 0,
402 1),
403
404 /* SRC_LCD */
405 MUX(CLK_MOUT_MIPI0, "mout_mipi0", group_fimc_lclk_p, SRC_LCD, 12, 4),
406 MUX(CLK_MOUT_FIMD0, "mout_fimd0", group_sclk_fimd0_p, SRC_LCD, 0, 4),
407
408 /* SRC_ISP */
409 MUX(CLK_MOUT_TSADC_ISP, "mout_tsadc_isp", group_fimc_lclk_p, SRC_ISP,
410 16, 4),
411 MUX(CLK_MOUT_UART_ISP, "mout_uart_isp", group_fimc_lclk_p, SRC_ISP,
412 12, 4),
413 MUX(CLK_MOUT_SPI1_ISP, "mout_spi1_isp", group_fimc_lclk_p, SRC_ISP,
414 8, 4),
415 MUX(CLK_MOUT_SPI0_ISP, "mout_spi0_isp", group_fimc_lclk_p, SRC_ISP,
416 4, 4),
417 MUX(CLK_MOUT_PWM_ISP, "mout_pwm_isp", group_fimc_lclk_p, SRC_ISP,
418 0, 4),
419
420 /* SRC_MAUDIO */
421 MUX(CLK_MOUT_AUDIO0, "mout_audio0", group_sclk_audio0_p, SRC_MAUDIO,
422 0, 4),
423
424 /* SRC_FSYS */
425 MUX(CLK_MOUT_TSADC, "mout_tsadc", group_sclk_p, SRC_FSYS, 28, 4),
426 MUX(CLK_MOUT_MMC2, "mout_mmc2", group_sclk_p, SRC_FSYS, 8, 4),
427 MUX(CLK_MOUT_MMC1, "mout_mmc1", group_sclk_p, SRC_FSYS, 4, 4),
428 MUX(CLK_MOUT_MMC0, "mout_mmc0", group_sclk_p, SRC_FSYS, 0, 4),
429
430 /* SRC_PERIL0 */
431 MUX(CLK_MOUT_UART3, "mout_uart3", group_sclk_p, SRC_PERIL0, 12, 4),
432 MUX(CLK_MOUT_UART2, "mout_uart2", group_sclk_p, SRC_PERIL0, 8, 4),
433 MUX(CLK_MOUT_UART1, "mout_uart1", group_sclk_p, SRC_PERIL0, 4, 4),
434 MUX(CLK_MOUT_UART0, "mout_uart0", group_sclk_p, SRC_PERIL0, 0, 4),
435
436 /* SRC_PERIL1 */
437 MUX(CLK_MOUT_SPI2, "mout_spi2", group_sclk_p, SRC_PERIL1, 24, 4),
438 MUX(CLK_MOUT_SPI1, "mout_spi1", group_sclk_p, SRC_PERIL1, 20, 4),
439 MUX(CLK_MOUT_SPI0, "mout_spi0", group_sclk_p, SRC_PERIL1, 16, 4),
440 MUX(CLK_MOUT_SPDIF, "mout_spdif", group_spdif_p, SRC_PERIL1, 8, 4),
441 MUX(CLK_MOUT_AUDIO2, "mout_audio2", group_sclk_audio2_p, SRC_PERIL1,
442 4, 4),
443 MUX(CLK_MOUT_AUDIO1, "mout_audio1", group_sclk_audio1_p, SRC_PERIL1,
444 0, 4),
445
446 /* SRC_CPU */
447 MUX(CLK_MOUT_MPLL_USER_C, "mout_mpll_user_c", mout_mpll_user_p,
448 SRC_CPU, 24, 1),
449 MUX(CLK_MOUT_HPM, "mout_hpm", mout_hpm_p, SRC_CPU, 20, 1),
450 MUX_F(CLK_MOUT_CORE, "mout_core", mout_core_p, SRC_CPU, 16, 1, 0,
451 CLK_MUX_READ_ONLY),
452 MUX_F(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
453 CLK_SET_RATE_PARENT, 0),
454
455 /* SRC_CAM1 */
456 MUX(CLK_MOUT_PXLASYNC_CSIS1_FIMC, "mout_pxlasync_csis1",
457 group_fimc_lclk_p, SRC_CAM1, 20, 1),
458 MUX(CLK_MOUT_PXLASYNC_CSIS0_FIMC, "mout_pxlasync_csis0",
459 group_fimc_lclk_p, SRC_CAM1, 16, 1),
460 MUX(CLK_MOUT_JPEG, "mout_jpeg", mout_jpeg_p, SRC_CAM1, 8, 1),
461 MUX(CLK_MOUT_JPEG1, "mout_jpeg_1", mout_jpeg1_p, SRC_CAM1, 4, 1),
462 MUX(CLK_MOUT_JPEG0, "mout_jpeg_0", group_mout_mpll_user_t_p, SRC_CAM1,
463 0, 1),
464
465 /* SRC_TOP_ISP0 */
466 MUX(CLK_MOUT_ACLK_ISP0_300, "mout_aclk_isp0_300",
467 group_aclk_isp0_300_p, SRC_TOP_ISP0, 8, 1),
468 MUX(CLK_MOUT_ACLK_ISP0_400, "mout_aclk_isp0_400_user",
469 group_aclk_isp0_400_user_p, SRC_TOP_ISP0, 4, 1),
470 MUX(CLK_MOUT_ACLK_ISP0_300_USER, "mout_aclk_isp0_300_user",
471 group_aclk_isp0_300_user_p, SRC_TOP_ISP0, 0, 1),
472
473 /* SRC_TOP_ISP1 */
474 MUX(CLK_MOUT_ACLK_ISP1_300, "mout_aclk_isp1_300",
475 group_aclk_isp0_300_p, SRC_TOP_ISP1, 4, 1),
476 MUX(CLK_MOUT_ACLK_ISP1_300_USER, "mout_aclk_isp1_300_user",
477 group_aclk_isp1_300_user_p, SRC_TOP_ISP1, 0, 1),
478};
479
480static struct samsung_div_clock exynos4415_div_clks[] __initdata = {
481 /*
482 * NOTE: Following table is sorted by register address in ascending
483 * order and then bitfield shift in descending order, as it is done
484 * in the User's Manual. When adding new entries, please make sure
485 * that the order is preserved, to avoid merge conflicts and make
486 * further work with defined data easier.
487 */
488
489 /* DIV_LEFTBUS */
490 DIV(CLK_DIV_GPL, "div_gpl", "div_gdl", DIV_LEFTBUS, 4, 3),
491 DIV(CLK_DIV_GDL, "div_gdl", "mout_gdl", DIV_LEFTBUS, 0, 4),
492
493 /* DIV_RIGHTBUS */
494 DIV(CLK_DIV_GPR, "div_gpr", "div_gdr", DIV_RIGHTBUS, 4, 3),
495 DIV(CLK_DIV_GDR, "div_gdr", "mout_gdr", DIV_RIGHTBUS, 0, 4),
496
497 /* DIV_TOP */
498 DIV(CLK_DIV_ACLK_400_MCUISP, "div_aclk_400_mcuisp",
499 "mout_aclk_400_mcuisp", DIV_TOP, 24, 3),
500 DIV(CLK_DIV_EBI, "div_ebi", "mout_ebi_1", DIV_TOP, 16, 3),
501 DIV(CLK_DIV_ACLK_200, "div_aclk_200", "mout_aclk_200", DIV_TOP, 12, 3),
502 DIV(CLK_DIV_ACLK_160, "div_aclk_160", "mout_aclk_160", DIV_TOP, 8, 3),
503 DIV(CLK_DIV_ACLK_100, "div_aclk_100", "mout_aclk_100", DIV_TOP, 4, 4),
504 DIV(CLK_DIV_ACLK_266, "div_aclk_266", "mout_aclk_266", DIV_TOP, 0, 3),
505
506 /* DIV_CAM */
507 DIV(CLK_DIV_CSIS1, "div_csis1", "mout_csis1", DIV_CAM, 28, 4),
508 DIV(CLK_DIV_CSIS0, "div_csis0", "mout_csis0", DIV_CAM, 24, 4),
509 DIV(CLK_DIV_CAM1, "div_cam1", "mout_cam1", DIV_CAM, 20, 4),
510 DIV(CLK_DIV_FIMC3_LCLK, "div_fimc3_lclk", "mout_fimc3_lclk", DIV_CAM,
511 12, 4),
512 DIV(CLK_DIV_FIMC2_LCLK, "div_fimc2_lclk", "mout_fimc2_lclk", DIV_CAM,
513 8, 4),
514 DIV(CLK_DIV_FIMC1_LCLK, "div_fimc1_lclk", "mout_fimc1_lclk", DIV_CAM,
515 4, 4),
516 DIV(CLK_DIV_FIMC0_LCLK, "div_fimc0_lclk", "mout_fimc0_lclk", DIV_CAM,
517 0, 4),
518
519 /* DIV_TV */
520 DIV(CLK_DIV_TV_BLK, "div_tv_blk", "mout_g3d_pll", DIV_TV, 0, 4),
521
522 /* DIV_MFC */
523 DIV(CLK_DIV_MFC, "div_mfc", "mout_mfc", DIV_MFC, 0, 4),
524
525 /* DIV_G3D */
526 DIV(CLK_DIV_G3D, "div_g3d", "mout_g3d", DIV_G3D, 0, 4),
527
528 /* DIV_LCD */
529 DIV_F(CLK_DIV_MIPI0_PRE, "div_mipi0_pre", "div_mipi0", DIV_LCD, 20, 4,
530 CLK_SET_RATE_PARENT, 0),
531 DIV(CLK_DIV_MIPI0, "div_mipi0", "mout_mipi0", DIV_LCD, 16, 4),
532 DIV(CLK_DIV_FIMD0, "div_fimd0", "mout_fimd0", DIV_LCD, 0, 4),
533
534 /* DIV_ISP */
535 DIV(CLK_DIV_UART_ISP, "div_uart_isp", "mout_uart_isp", DIV_ISP, 28, 4),
536 DIV_F(CLK_DIV_SPI1_ISP_PRE, "div_spi1_isp_pre", "div_spi1_isp",
537 DIV_ISP, 20, 8, CLK_SET_RATE_PARENT, 0),
538 DIV(CLK_DIV_SPI1_ISP, "div_spi1_isp", "mout_spi1_isp", DIV_ISP, 16, 4),
539 DIV_F(CLK_DIV_SPI0_ISP_PRE, "div_spi0_isp_pre", "div_spi0_isp",
540 DIV_ISP, 8, 8, CLK_SET_RATE_PARENT, 0),
541 DIV(CLK_DIV_SPI0_ISP, "div_spi0_isp", "mout_spi0_isp", DIV_ISP, 4, 4),
542 DIV(CLK_DIV_PWM_ISP, "div_pwm_isp", "mout_pwm_isp", DIV_ISP, 0, 4),
543
544 /* DIV_MAUDIO */
545 DIV(CLK_DIV_PCM0, "div_pcm0", "div_audio0", DIV_MAUDIO, 4, 8),
546 DIV(CLK_DIV_AUDIO0, "div_audio0", "mout_audio0", DIV_MAUDIO, 0, 4),
547
548 /* DIV_FSYS0 */
549 DIV_F(CLK_DIV_TSADC_PRE, "div_tsadc_pre", "div_tsadc", DIV_FSYS0, 8, 8,
550 CLK_SET_RATE_PARENT, 0),
551 DIV(CLK_DIV_TSADC, "div_tsadc", "mout_tsadc", DIV_FSYS0, 0, 4),
552
553 /* DIV_FSYS1 */
554 DIV_F(CLK_DIV_MMC1_PRE, "div_mmc1_pre", "div_mmc1", DIV_FSYS1, 24, 8,
555 CLK_SET_RATE_PARENT, 0),
556 DIV(CLK_DIV_MMC1, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
557 DIV_F(CLK_DIV_MMC0_PRE, "div_mmc0_pre", "div_mmc0", DIV_FSYS1, 8, 8,
558 CLK_SET_RATE_PARENT, 0),
559 DIV(CLK_DIV_MMC0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
560
561 /* DIV_FSYS2 */
562 DIV_F(CLK_DIV_MMC2_PRE, "div_mmc2_pre", "div_mmc2", DIV_FSYS2, 8, 8,
563 CLK_SET_RATE_PARENT, 0),
564 DIV_F(CLK_DIV_MMC2_PRE, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4,
565 CLK_SET_RATE_PARENT, 0),
566
567 /* DIV_PERIL0 */
568 DIV(CLK_DIV_UART3, "div_uart3", "mout_uart3", DIV_PERIL0, 12, 4),
569 DIV(CLK_DIV_UART2, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4),
570 DIV(CLK_DIV_UART1, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
571 DIV(CLK_DIV_UART0, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4),
572
573 /* DIV_PERIL1 */
574 DIV_F(CLK_DIV_SPI1_PRE, "div_spi1_pre", "div_spi1", DIV_PERIL1, 24, 8,
575 CLK_SET_RATE_PARENT, 0),
576 DIV(CLK_DIV_SPI1, "div_spi1", "mout_spi1", DIV_PERIL1, 16, 4),
577 DIV_F(CLK_DIV_SPI0_PRE, "div_spi0_pre", "div_spi0", DIV_PERIL1, 8, 8,
578 CLK_SET_RATE_PARENT, 0),
579 DIV(CLK_DIV_SPI0, "div_spi0", "mout_spi0", DIV_PERIL1, 0, 4),
580
581 /* DIV_PERIL2 */
582 DIV_F(CLK_DIV_SPI2_PRE, "div_spi2_pre", "div_spi2", DIV_PERIL2, 8, 8,
583 CLK_SET_RATE_PARENT, 0),
584 DIV(CLK_DIV_SPI2, "div_spi2", "mout_spi2", DIV_PERIL2, 0, 4),
585
586 /* DIV_PERIL4 */
587 DIV(CLK_DIV_PCM2, "div_pcm2", "div_audio2", DIV_PERIL4, 20, 8),
588 DIV(CLK_DIV_AUDIO2, "div_audio2", "mout_audio2", DIV_PERIL4, 16, 4),
589 DIV(CLK_DIV_PCM1, "div_pcm1", "div_audio1", DIV_PERIL4, 20, 8),
590 DIV(CLK_DIV_AUDIO1, "div_audio1", "mout_audio1", DIV_PERIL4, 0, 4),
591
592 /* DIV_PERIL5 */
593 DIV(CLK_DIV_I2S1, "div_i2s1", "div_audio1", DIV_PERIL5, 0, 6),
594
595 /* DIV_CAM1 */
596 DIV(CLK_DIV_PXLASYNC_CSIS1_FIMC, "div_pxlasync_csis1_fimc",
597 "mout_pxlasync_csis1", DIV_CAM1, 24, 4),
598 DIV(CLK_DIV_PXLASYNC_CSIS0_FIMC, "div_pxlasync_csis0_fimc",
599 "mout_pxlasync_csis0", DIV_CAM1, 20, 4),
600 DIV(CLK_DIV_JPEG, "div_jpeg", "mout_jpeg", DIV_CAM1, 0, 4),
601
602 /* DIV_CPU0 */
603 DIV(CLK_DIV_CORE2, "div_core2", "div_core", DIV_CPU0, 28, 3),
604 DIV_F(CLK_DIV_APLL, "div_apll", "mout_apll", DIV_CPU0, 24, 3,
605 CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
606 DIV(CLK_DIV_PCLK_DBG, "div_pclk_dbg", "div_core2", DIV_CPU0, 20, 3),
607 DIV(CLK_DIV_ATB, "div_atb", "div_core2", DIV_CPU0, 16, 3),
608 DIV(CLK_DIV_PERIPH, "div_periph", "div_core2", DIV_CPU0, 12, 3),
609 DIV(CLK_DIV_COREM1, "div_corem1", "div_core2", DIV_CPU0, 8, 3),
610 DIV(CLK_DIV_COREM0, "div_corem0", "div_core2", DIV_CPU0, 4, 3),
611 DIV_F(CLK_DIV_CORE, "div_core", "mout_core", DIV_CPU0, 0, 3,
612 CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
613
614 /* DIV_CPU1 */
615 DIV(CLK_DIV_HPM, "div_hpm", "div_copy", DIV_CPU1, 4, 3),
616 DIV(CLK_DIV_COPY, "div_copy", "mout_hpm", DIV_CPU1, 0, 3),
617};
618
619static struct samsung_gate_clock exynos4415_gate_clks[] __initdata = {
620 /*
621 * NOTE: Following table is sorted by register address in ascending
622 * order and then bitfield shift in descending order, as it is done
623 * in the User's Manual. When adding new entries, please make sure
624 * that the order is preserved, to avoid merge conflicts and make
625 * further work with defined data easier.
626 */
627
628 /* GATE_IP_LEFTBUS */
629 GATE(CLK_ASYNC_G3D, "async_g3d", "div_aclk_100", GATE_IP_LEFTBUS, 6,
630 CLK_IGNORE_UNUSED, 0),
631 GATE(CLK_ASYNC_MFCL, "async_mfcl", "div_aclk_100", GATE_IP_LEFTBUS, 4,
632 CLK_IGNORE_UNUSED, 0),
633 GATE(CLK_ASYNC_TVX, "async_tvx", "div_aclk_100", GATE_IP_LEFTBUS, 3,
634 CLK_IGNORE_UNUSED, 0),
635 GATE(CLK_PPMULEFT, "ppmuleft", "div_aclk_100", GATE_IP_LEFTBUS, 1,
636 CLK_IGNORE_UNUSED, 0),
637 GATE(CLK_GPIO_LEFT, "gpio_left", "div_aclk_100", GATE_IP_LEFTBUS, 0,
638 CLK_IGNORE_UNUSED, 0),
639
640 /* GATE_IP_IMAGE */
641 GATE(CLK_PPMUIMAGE, "ppmuimage", "div_aclk_100", GATE_IP_IMAGE,
642 9, 0, 0),
643 GATE(CLK_QEMDMA2, "qe_mdma2", "div_aclk_100", GATE_IP_IMAGE,
644 8, 0, 0),
645 GATE(CLK_QEROTATOR, "qe_rotator", "div_aclk_100", GATE_IP_IMAGE,
646 7, 0, 0),
647 GATE(CLK_SMMUMDMA2, "smmu_mdam2", "div_aclk_100", GATE_IP_IMAGE,
648 5, 0, 0),
649 GATE(CLK_SMMUROTATOR, "smmu_rotator", "div_aclk_100", GATE_IP_IMAGE,
650 4, 0, 0),
651 GATE(CLK_MDMA2, "mdma2", "div_aclk_100", GATE_IP_IMAGE, 2, 0, 0),
652 GATE(CLK_ROTATOR, "rotator", "div_aclk_100", GATE_IP_IMAGE, 1, 0, 0),
653
654 /* GATE_IP_RIGHTBUS */
655 GATE(CLK_ASYNC_ISPMX, "async_ispmx", "div_aclk_100",
656 GATE_IP_RIGHTBUS, 9, CLK_IGNORE_UNUSED, 0),
657 GATE(CLK_ASYNC_MAUDIOX, "async_maudiox", "div_aclk_100",
658 GATE_IP_RIGHTBUS, 7, CLK_IGNORE_UNUSED, 0),
659 GATE(CLK_ASYNC_MFCR, "async_mfcr", "div_aclk_100",
660 GATE_IP_RIGHTBUS, 6, CLK_IGNORE_UNUSED, 0),
661 GATE(CLK_ASYNC_FSYSD, "async_fsysd", "div_aclk_100",
662 GATE_IP_RIGHTBUS, 5, CLK_IGNORE_UNUSED, 0),
663 GATE(CLK_ASYNC_LCD0X, "async_lcd0x", "div_aclk_100",
664 GATE_IP_RIGHTBUS, 3, CLK_IGNORE_UNUSED, 0),
665 GATE(CLK_ASYNC_CAMX, "async_camx", "div_aclk_100",
666 GATE_IP_RIGHTBUS, 2, CLK_IGNORE_UNUSED, 0),
667 GATE(CLK_PPMURIGHT, "ppmuright", "div_aclk_100",
668 GATE_IP_RIGHTBUS, 1, CLK_IGNORE_UNUSED, 0),
669 GATE(CLK_GPIO_RIGHT, "gpio_right", "div_aclk_100",
670 GATE_IP_RIGHTBUS, 0, CLK_IGNORE_UNUSED, 0),
671
672 /* GATE_IP_PERIR */
673 GATE(CLK_ANTIRBK_APBIF, "antirbk_apbif", "div_aclk_100",
674 GATE_IP_PERIR, 24, CLK_IGNORE_UNUSED, 0),
675 GATE(CLK_EFUSE_WRITER_APBIF, "efuse_writer_apbif", "div_aclk_100",
676 GATE_IP_PERIR, 23, CLK_IGNORE_UNUSED, 0),
677 GATE(CLK_MONOCNT, "monocnt", "div_aclk_100", GATE_IP_PERIR, 22,
678 CLK_IGNORE_UNUSED, 0),
679 GATE(CLK_TZPC6, "tzpc6", "div_aclk_100", GATE_IP_PERIR, 21,
680 CLK_IGNORE_UNUSED, 0),
681 GATE(CLK_PROVISIONKEY1, "provisionkey1", "div_aclk_100",
682 GATE_IP_PERIR, 20, CLK_IGNORE_UNUSED, 0),
683 GATE(CLK_PROVISIONKEY0, "provisionkey0", "div_aclk_100",
684 GATE_IP_PERIR, 19, CLK_IGNORE_UNUSED, 0),
685 GATE(CLK_CMU_ISPPART, "cmu_isppart", "div_aclk_100", GATE_IP_PERIR, 18,
686 CLK_IGNORE_UNUSED, 0),
687 GATE(CLK_TMU_APBIF, "tmu_apbif", "div_aclk_100",
688 GATE_IP_PERIR, 17, 0, 0),
689 GATE(CLK_KEYIF, "keyif", "div_aclk_100", GATE_IP_PERIR, 16, 0, 0),
690 GATE(CLK_RTC, "rtc", "div_aclk_100", GATE_IP_PERIR, 15, 0, 0),
691 GATE(CLK_WDT, "wdt", "div_aclk_100", GATE_IP_PERIR, 14, 0, 0),
692 GATE(CLK_MCT, "mct", "div_aclk_100", GATE_IP_PERIR, 13, 0, 0),
693 GATE(CLK_SECKEY, "seckey", "div_aclk_100", GATE_IP_PERIR, 12,
694 CLK_IGNORE_UNUSED, 0),
695 GATE(CLK_HDMI_CEC, "hdmi_cec", "div_aclk_100", GATE_IP_PERIR, 11,
696 CLK_IGNORE_UNUSED, 0),
697 GATE(CLK_TZPC5, "tzpc5", "div_aclk_100", GATE_IP_PERIR, 10,
698 CLK_IGNORE_UNUSED, 0),
699 GATE(CLK_TZPC4, "tzpc4", "div_aclk_100", GATE_IP_PERIR, 9,
700 CLK_IGNORE_UNUSED, 0),
701 GATE(CLK_TZPC3, "tzpc3", "div_aclk_100", GATE_IP_PERIR, 8,
702 CLK_IGNORE_UNUSED, 0),
703 GATE(CLK_TZPC2, "tzpc2", "div_aclk_100", GATE_IP_PERIR, 7,
704 CLK_IGNORE_UNUSED, 0),
705 GATE(CLK_TZPC1, "tzpc1", "div_aclk_100", GATE_IP_PERIR, 6,
706 CLK_IGNORE_UNUSED, 0),
707 GATE(CLK_TZPC0, "tzpc0", "div_aclk_100", GATE_IP_PERIR, 5,
708 CLK_IGNORE_UNUSED, 0),
709 GATE(CLK_CMU_COREPART, "cmu_corepart", "div_aclk_100", GATE_IP_PERIR, 4,
710 CLK_IGNORE_UNUSED, 0),
711 GATE(CLK_CMU_TOPPART, "cmu_toppart", "div_aclk_100", GATE_IP_PERIR, 3,
712 CLK_IGNORE_UNUSED, 0),
713 GATE(CLK_PMU_APBIF, "pmu_apbif", "div_aclk_100", GATE_IP_PERIR, 2,
714 CLK_IGNORE_UNUSED, 0),
715 GATE(CLK_SYSREG, "sysreg", "div_aclk_100", GATE_IP_PERIR, 1,
716 CLK_IGNORE_UNUSED, 0),
717 GATE(CLK_CHIP_ID, "chip_id", "div_aclk_100", GATE_IP_PERIR, 0,
718 CLK_IGNORE_UNUSED, 0),
719
720 /* GATE_SCLK_CAM - non-completed */
721 GATE(CLK_SCLK_PXLAYSNC_CSIS1_FIMC, "sclk_pxlasync_csis1_fimc",
722 "div_pxlasync_csis1_fimc", GATE_SCLK_CAM, 11,
723 CLK_SET_RATE_PARENT, 0),
724 GATE(CLK_SCLK_PXLAYSNC_CSIS0_FIMC, "sclk_pxlasync_csis0_fimc",
725 "div_pxlasync_csis0_fimc", GATE_SCLK_CAM,
726 10, CLK_SET_RATE_PARENT, 0),
727 GATE(CLK_SCLK_JPEG, "sclk_jpeg", "div_jpeg",
728 GATE_SCLK_CAM, 8, CLK_SET_RATE_PARENT, 0),
729 GATE(CLK_SCLK_CSIS1, "sclk_csis1", "div_csis1",
730 GATE_SCLK_CAM, 7, CLK_SET_RATE_PARENT, 0),
731 GATE(CLK_SCLK_CSIS0, "sclk_csis0", "div_csis0",
732 GATE_SCLK_CAM, 6, CLK_SET_RATE_PARENT, 0),
733 GATE(CLK_SCLK_CAM1, "sclk_cam1", "div_cam1",
734 GATE_SCLK_CAM, 5, CLK_SET_RATE_PARENT, 0),
735 GATE(CLK_SCLK_FIMC3_LCLK, "sclk_fimc3_lclk", "div_fimc3_lclk",
736 GATE_SCLK_CAM, 3, CLK_SET_RATE_PARENT, 0),
737 GATE(CLK_SCLK_FIMC2_LCLK, "sclk_fimc2_lclk", "div_fimc2_lclk",
738 GATE_SCLK_CAM, 2, CLK_SET_RATE_PARENT, 0),
739 GATE(CLK_SCLK_FIMC1_LCLK, "sclk_fimc1_lclk", "div_fimc1_lclk",
740 GATE_SCLK_CAM, 1, CLK_SET_RATE_PARENT, 0),
741 GATE(CLK_SCLK_FIMC0_LCLK, "sclk_fimc0_lclk", "div_fimc0_lclk",
742 GATE_SCLK_CAM, 0, CLK_SET_RATE_PARENT, 0),
743
744 /* GATE_SCLK_TV */
745 GATE(CLK_SCLK_PIXEL, "sclk_pixel", "div_tv_blk",
746 GATE_SCLK_TV, 3, CLK_SET_RATE_PARENT, 0),
747 GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi",
748 GATE_SCLK_TV, 2, CLK_SET_RATE_PARENT, 0),
749 GATE(CLK_SCLK_MIXER, "sclk_mixer", "div_tv_blk",
750 GATE_SCLK_TV, 0, CLK_SET_RATE_PARENT, 0),
751
752 /* GATE_SCLK_MFC */
753 GATE(CLK_SCLK_MFC, "sclk_mfc", "div_mfc",
754 GATE_SCLK_MFC, 0, CLK_SET_RATE_PARENT, 0),
755
756 /* GATE_SCLK_G3D */
757 GATE(CLK_SCLK_G3D, "sclk_g3d", "div_g3d",
758 GATE_SCLK_G3D, 0, CLK_SET_RATE_PARENT, 0),
759
760 /* GATE_SCLK_LCD */
761 GATE(CLK_SCLK_MIPIDPHY4L, "sclk_mipidphy4l", "div_mipi0",
762 GATE_SCLK_LCD, 4, CLK_SET_RATE_PARENT, 0),
763 GATE(CLK_SCLK_MIPI0, "sclk_mipi0", "div_mipi0_pre",
764 GATE_SCLK_LCD, 3, CLK_SET_RATE_PARENT, 0),
765 GATE(CLK_SCLK_MDNIE0, "sclk_mdnie0", "div_fimd0",
766 GATE_SCLK_LCD, 1, CLK_SET_RATE_PARENT, 0),
767 GATE(CLK_SCLK_FIMD0, "sclk_fimd0", "div_fimd0",
768 GATE_SCLK_LCD, 0, CLK_SET_RATE_PARENT, 0),
769
770 /* GATE_SCLK_MAUDIO */
771 GATE(CLK_SCLK_PCM0, "sclk_pcm0", "div_pcm0",
772 GATE_SCLK_MAUDIO, 1, CLK_SET_RATE_PARENT, 0),
773 GATE(CLK_SCLK_AUDIO0, "sclk_audio0", "div_audio0",
774 GATE_SCLK_MAUDIO, 0, CLK_SET_RATE_PARENT, 0),
775
776 /* GATE_SCLK_FSYS */
777 GATE(CLK_SCLK_TSADC, "sclk_tsadc", "div_tsadc_pre",
778 GATE_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
779 GATE(CLK_SCLK_EBI, "sclk_ebi", "div_ebi",
780 GATE_SCLK_FSYS, 6, CLK_SET_RATE_PARENT, 0),
781 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc2_pre",
782 GATE_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
783 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc1_pre",
784 GATE_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0),
785 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc0_pre",
786 GATE_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
787
788 /* GATE_SCLK_PERIL */
789 GATE(CLK_SCLK_I2S, "sclk_i2s1", "div_i2s1",
790 GATE_SCLK_PERIL, 18, CLK_SET_RATE_PARENT, 0),
791 GATE(CLK_SCLK_PCM2, "sclk_pcm2", "div_pcm2",
792 GATE_SCLK_PERIL, 16, CLK_SET_RATE_PARENT, 0),
793 GATE(CLK_SCLK_PCM1, "sclk_pcm1", "div_pcm1",
794 GATE_SCLK_PERIL, 15, CLK_SET_RATE_PARENT, 0),
795 GATE(CLK_SCLK_AUDIO2, "sclk_audio2", "div_audio2",
796 GATE_SCLK_PERIL, 14, CLK_SET_RATE_PARENT, 0),
797 GATE(CLK_SCLK_AUDIO1, "sclk_audio1", "div_audio1",
798 GATE_SCLK_PERIL, 13, CLK_SET_RATE_PARENT, 0),
799 GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif",
800 GATE_SCLK_PERIL, 10, CLK_SET_RATE_PARENT, 0),
801 GATE(CLK_SCLK_SPI2, "sclk_spi2", "div_spi2_pre",
802 GATE_SCLK_PERIL, 8, CLK_SET_RATE_PARENT, 0),
803 GATE(CLK_SCLK_SPI1, "sclk_spi1", "div_spi1_pre",
804 GATE_SCLK_PERIL, 7, CLK_SET_RATE_PARENT, 0),
805 GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi0_pre",
806 GATE_SCLK_PERIL, 6, CLK_SET_RATE_PARENT, 0),
807 GATE(CLK_SCLK_UART3, "sclk_uart3", "div_uart3",
808 GATE_SCLK_PERIL, 3, CLK_SET_RATE_PARENT, 0),
809 GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
810 GATE_SCLK_PERIL, 2, CLK_SET_RATE_PARENT, 0),
811 GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
812 GATE_SCLK_PERIL, 1, CLK_SET_RATE_PARENT, 0),
813 GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
814 GATE_SCLK_PERIL, 0, CLK_SET_RATE_PARENT, 0),
815
816 /* GATE_IP_CAM */
817 GATE(CLK_SMMUFIMC_LITE2, "smmufimc_lite2", "div_aclk_160", GATE_IP_CAM,
818 22, CLK_IGNORE_UNUSED, 0),
819 GATE(CLK_FIMC_LITE2, "fimc_lite2", "div_aclk_160", GATE_IP_CAM,
820 20, CLK_IGNORE_UNUSED, 0),
821 GATE(CLK_PIXELASYNCM1, "pixelasyncm1", "div_aclk_160", GATE_IP_CAM,
822 18, CLK_IGNORE_UNUSED, 0),
823 GATE(CLK_PIXELASYNCM0, "pixelasyncm0", "div_aclk_160", GATE_IP_CAM,
824 17, CLK_IGNORE_UNUSED, 0),
825 GATE(CLK_PPMUCAMIF, "ppmucamif", "div_aclk_160", GATE_IP_CAM,
826 16, CLK_IGNORE_UNUSED, 0),
827 GATE(CLK_SMMUJPEG, "smmujpeg", "div_aclk_160", GATE_IP_CAM, 11, 0, 0),
828 GATE(CLK_SMMUFIMC3, "smmufimc3", "div_aclk_160", GATE_IP_CAM, 10, 0, 0),
829 GATE(CLK_SMMUFIMC2, "smmufimc2", "div_aclk_160", GATE_IP_CAM, 9, 0, 0),
830 GATE(CLK_SMMUFIMC1, "smmufimc1", "div_aclk_160", GATE_IP_CAM, 8, 0, 0),
831 GATE(CLK_SMMUFIMC0, "smmufimc0", "div_aclk_160", GATE_IP_CAM, 7, 0, 0),
832 GATE(CLK_JPEG, "jpeg", "div_aclk_160", GATE_IP_CAM, 6, 0, 0),
833 GATE(CLK_CSIS1, "csis1", "div_aclk_160", GATE_IP_CAM, 5, 0, 0),
834 GATE(CLK_CSIS0, "csis0", "div_aclk_160", GATE_IP_CAM, 4, 0, 0),
835 GATE(CLK_FIMC3, "fimc3", "div_aclk_160", GATE_IP_CAM, 3, 0, 0),
836 GATE(CLK_FIMC2, "fimc2", "div_aclk_160", GATE_IP_CAM, 2, 0, 0),
837 GATE(CLK_FIMC1, "fimc1", "div_aclk_160", GATE_IP_CAM, 1, 0, 0),
838 GATE(CLK_FIMC0, "fimc0", "div_aclk_160", GATE_IP_CAM, 0, 0, 0),
839
840 /* GATE_IP_TV */
841 GATE(CLK_PPMUTV, "ppmutv", "div_aclk_100", GATE_IP_TV, 5, 0, 0),
842 GATE(CLK_SMMUTV, "smmutv", "div_aclk_100", GATE_IP_TV, 4, 0, 0),
843 GATE(CLK_HDMI, "hdmi", "div_aclk_100", GATE_IP_TV, 3, 0, 0),
844 GATE(CLK_MIXER, "mixer", "div_aclk_100", GATE_IP_TV, 1, 0, 0),
845 GATE(CLK_VP, "vp", "div_aclk_100", GATE_IP_TV, 0, 0, 0),
846
847 /* GATE_IP_MFC */
848 GATE(CLK_PPMUMFC_R, "ppmumfc_r", "div_aclk_200", GATE_IP_MFC, 4,
849 CLK_IGNORE_UNUSED, 0),
850 GATE(CLK_PPMUMFC_L, "ppmumfc_l", "div_aclk_200", GATE_IP_MFC, 3,
851 CLK_IGNORE_UNUSED, 0),
852 GATE(CLK_SMMUMFC_R, "smmumfc_r", "div_aclk_200", GATE_IP_MFC, 2, 0, 0),
853 GATE(CLK_SMMUMFC_L, "smmumfc_l", "div_aclk_200", GATE_IP_MFC, 1, 0, 0),
854 GATE(CLK_MFC, "mfc", "div_aclk_200", GATE_IP_MFC, 0, 0, 0),
855
856 /* GATE_IP_G3D */
857 GATE(CLK_PPMUG3D, "ppmug3d", "div_aclk_200", GATE_IP_G3D, 1,
858 CLK_IGNORE_UNUSED, 0),
859 GATE(CLK_G3D, "g3d", "div_aclk_200", GATE_IP_G3D, 0, 0, 0),
860
861 /* GATE_IP_LCD */
862 GATE(CLK_PPMULCD0, "ppmulcd0", "div_aclk_160", GATE_IP_LCD, 5,
863 CLK_IGNORE_UNUSED, 0),
864 GATE(CLK_SMMUFIMD0, "smmufimd0", "div_aclk_160", GATE_IP_LCD, 4, 0, 0),
865 GATE(CLK_DSIM0, "dsim0", "div_aclk_160", GATE_IP_LCD, 3, 0, 0),
866 GATE(CLK_SMIES, "smies", "div_aclk_160", GATE_IP_LCD, 2, 0, 0),
867 GATE(CLK_MIE0, "mie0", "div_aclk_160", GATE_IP_LCD, 1, 0, 0),
868 GATE(CLK_FIMD0, "fimd0", "div_aclk_160", GATE_IP_LCD, 0, 0, 0),
869
870 /* GATE_IP_FSYS */
871 GATE(CLK_TSADC, "tsadc", "div_aclk_200", GATE_IP_FSYS, 20, 0, 0),
872 GATE(CLK_PPMUFILE, "ppmufile", "div_aclk_200", GATE_IP_FSYS, 17,
873 CLK_IGNORE_UNUSED, 0),
874 GATE(CLK_NFCON, "nfcon", "div_aclk_200", GATE_IP_FSYS, 16, 0, 0),
875 GATE(CLK_USBDEVICE, "usbdevice", "div_aclk_200", GATE_IP_FSYS, 13,
876 0, 0),
877 GATE(CLK_USBHOST, "usbhost", "div_aclk_200", GATE_IP_FSYS, 12, 0, 0),
878 GATE(CLK_SROMC, "sromc", "div_aclk_200", GATE_IP_FSYS, 11, 0, 0),
879 GATE(CLK_SDMMC2, "sdmmc2", "div_aclk_200", GATE_IP_FSYS, 7, 0, 0),
880 GATE(CLK_SDMMC1, "sdmmc1", "div_aclk_200", GATE_IP_FSYS, 6, 0, 0),
881 GATE(CLK_SDMMC0, "sdmmc0", "div_aclk_200", GATE_IP_FSYS, 5, 0, 0),
882 GATE(CLK_PDMA1, "pdma1", "div_aclk_200", GATE_IP_FSYS, 1, 0, 0),
883 GATE(CLK_PDMA0, "pdma0", "div_aclk_200", GATE_IP_FSYS, 0, 0, 0),
884
885 /* GATE_IP_PERIL */
886 GATE(CLK_SPDIF, "spdif", "div_aclk_100", GATE_IP_PERIL, 26, 0, 0),
887 GATE(CLK_PWM, "pwm", "div_aclk_100", GATE_IP_PERIL, 24, 0, 0),
888 GATE(CLK_PCM2, "pcm2", "div_aclk_100", GATE_IP_PERIL, 23, 0, 0),
889 GATE(CLK_PCM1, "pcm1", "div_aclk_100", GATE_IP_PERIL, 22, 0, 0),
890 GATE(CLK_I2S1, "i2s1", "div_aclk_100", GATE_IP_PERIL, 20, 0, 0),
891 GATE(CLK_SPI2, "spi2", "div_aclk_100", GATE_IP_PERIL, 18, 0, 0),
892 GATE(CLK_SPI1, "spi1", "div_aclk_100", GATE_IP_PERIL, 17, 0, 0),
893 GATE(CLK_SPI0, "spi0", "div_aclk_100", GATE_IP_PERIL, 16, 0, 0),
894 GATE(CLK_I2CHDMI, "i2chdmi", "div_aclk_100", GATE_IP_PERIL, 14, 0, 0),
895 GATE(CLK_I2C7, "i2c7", "div_aclk_100", GATE_IP_PERIL, 13, 0, 0),
896 GATE(CLK_I2C6, "i2c6", "div_aclk_100", GATE_IP_PERIL, 12, 0, 0),
897 GATE(CLK_I2C5, "i2c5", "div_aclk_100", GATE_IP_PERIL, 11, 0, 0),
898 GATE(CLK_I2C4, "i2c4", "div_aclk_100", GATE_IP_PERIL, 10, 0, 0),
899 GATE(CLK_I2C3, "i2c3", "div_aclk_100", GATE_IP_PERIL, 9, 0, 0),
900 GATE(CLK_I2C2, "i2c2", "div_aclk_100", GATE_IP_PERIL, 8, 0, 0),
901 GATE(CLK_I2C1, "i2c1", "div_aclk_100", GATE_IP_PERIL, 7, 0, 0),
902 GATE(CLK_I2C0, "i2c0", "div_aclk_100", GATE_IP_PERIL, 6, 0, 0),
903 GATE(CLK_UART3, "uart3", "div_aclk_100", GATE_IP_PERIL, 3, 0, 0),
904 GATE(CLK_UART2, "uart2", "div_aclk_100", GATE_IP_PERIL, 2, 0, 0),
905 GATE(CLK_UART1, "uart1", "div_aclk_100", GATE_IP_PERIL, 1, 0, 0),
906 GATE(CLK_UART0, "uart0", "div_aclk_100", GATE_IP_PERIL, 0, 0, 0),
907};
908
909/*
910 * APLL & MPLL & BPLL & ISP_PLL & DISP_PLL & G3D_PLL
911 */
912static struct samsung_pll_rate_table exynos4415_pll_rates[] = {
913 PLL_35XX_RATE(1600000000, 400, 3, 1),
914 PLL_35XX_RATE(1500000000, 250, 2, 1),
915 PLL_35XX_RATE(1400000000, 175, 3, 0),
916 PLL_35XX_RATE(1300000000, 325, 3, 1),
917 PLL_35XX_RATE(1200000000, 400, 4, 1),
918 PLL_35XX_RATE(1100000000, 275, 3, 1),
919 PLL_35XX_RATE(1066000000, 533, 6, 1),
920 PLL_35XX_RATE(1000000000, 250, 3, 1),
921 PLL_35XX_RATE(960000000, 320, 4, 1),
922 PLL_35XX_RATE(900000000, 300, 4, 1),
923 PLL_35XX_RATE(850000000, 425, 6, 1),
924 PLL_35XX_RATE(800000000, 200, 3, 1),
925 PLL_35XX_RATE(700000000, 175, 3, 1),
926 PLL_35XX_RATE(667000000, 667, 12, 1),
927 PLL_35XX_RATE(600000000, 400, 4, 2),
928 PLL_35XX_RATE(550000000, 275, 3, 2),
929 PLL_35XX_RATE(533000000, 533, 6, 2),
930 PLL_35XX_RATE(520000000, 260, 3, 2),
931 PLL_35XX_RATE(500000000, 250, 3, 2),
932 PLL_35XX_RATE(440000000, 220, 3, 2),
933 PLL_35XX_RATE(400000000, 200, 3, 2),
934 PLL_35XX_RATE(350000000, 175, 3, 2),
935 PLL_35XX_RATE(300000000, 300, 3, 3),
936 PLL_35XX_RATE(266000000, 266, 3, 3),
937 PLL_35XX_RATE(200000000, 200, 3, 3),
938 PLL_35XX_RATE(160000000, 160, 3, 3),
939 PLL_35XX_RATE(100000000, 200, 3, 4),
940 { /* sentinel */ }
941};
942
943/* EPLL */
944static struct samsung_pll_rate_table exynos4415_epll_rates[] = {
945 PLL_36XX_RATE(800000000, 200, 3, 1, 0),
946 PLL_36XX_RATE(288000000, 96, 2, 2, 0),
947 PLL_36XX_RATE(192000000, 128, 2, 3, 0),
948 PLL_36XX_RATE(144000000, 96, 2, 3, 0),
949 PLL_36XX_RATE(96000000, 128, 2, 4, 0),
950 PLL_36XX_RATE(84000000, 112, 2, 4, 0),
951 PLL_36XX_RATE(80750011, 107, 2, 4, 43691),
952 PLL_36XX_RATE(73728004, 98, 2, 4, 19923),
953 PLL_36XX_RATE(67987602, 271, 3, 5, 62285),
954 PLL_36XX_RATE(65911004, 175, 2, 5, 49982),
955 PLL_36XX_RATE(50000000, 200, 3, 5, 0),
956 PLL_36XX_RATE(49152003, 131, 2, 5, 4719),
957 PLL_36XX_RATE(48000000, 128, 2, 5, 0),
958 PLL_36XX_RATE(45250000, 181, 3, 5, 0),
959 { /* sentinel */ }
960};
961
962static struct samsung_pll_clock exynos4415_plls[nr_plls] __initdata = {
963 [apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll",
964 APLL_LOCK, APLL_CON0, NULL),
965 [epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll",
966 EPLL_LOCK, EPLL_CON0, NULL),
967 [g3d_pll] = PLL(pll_35xx, CLK_FOUT_G3D_PLL, "fout_g3d_pll",
968 "mout_g3d_pllsrc", G3D_PLL_LOCK, G3D_PLL_CON0, NULL),
969 [isp_pll] = PLL(pll_35xx, CLK_FOUT_ISP_PLL, "fout_isp_pll", "fin_pll",
970 ISP_PLL_LOCK, ISP_PLL_CON0, NULL),
971 [disp_pll] = PLL(pll_35xx, CLK_FOUT_DISP_PLL, "fout_disp_pll",
972 "fin_pll", DISP_PLL_LOCK, DISP_PLL_CON0, NULL),
973};
974
975static void __init exynos4415_cmu_init(struct device_node *np)
976{
977 void __iomem *reg_base;
978
979 reg_base = of_iomap(np, 0);
980 if (!reg_base)
981 panic("%s: failed to map registers\n", __func__);
982
983 exynos4415_ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
984 if (!exynos4415_ctx)
985 panic("%s: unable to allocate context.\n", __func__);
986
987 exynos4415_plls[apll].rate_table = exynos4415_pll_rates;
988 exynos4415_plls[epll].rate_table = exynos4415_epll_rates;
989 exynos4415_plls[g3d_pll].rate_table = exynos4415_pll_rates;
990 exynos4415_plls[isp_pll].rate_table = exynos4415_pll_rates;
991 exynos4415_plls[disp_pll].rate_table = exynos4415_pll_rates;
992
993 samsung_clk_register_fixed_factor(exynos4415_ctx,
994 exynos4415_fixed_factor_clks,
995 ARRAY_SIZE(exynos4415_fixed_factor_clks));
996 samsung_clk_register_fixed_rate(exynos4415_ctx,
997 exynos4415_fixed_rate_clks,
998 ARRAY_SIZE(exynos4415_fixed_rate_clks));
999
1000 samsung_clk_register_pll(exynos4415_ctx, exynos4415_plls,
1001 ARRAY_SIZE(exynos4415_plls), reg_base);
1002 samsung_clk_register_mux(exynos4415_ctx, exynos4415_mux_clks,
1003 ARRAY_SIZE(exynos4415_mux_clks));
1004 samsung_clk_register_div(exynos4415_ctx, exynos4415_div_clks,
1005 ARRAY_SIZE(exynos4415_div_clks));
1006 samsung_clk_register_gate(exynos4415_ctx, exynos4415_gate_clks,
1007 ARRAY_SIZE(exynos4415_gate_clks));
1008
1009 exynos4415_clk_sleep_init();
1010
1011 samsung_clk_of_add_provider(np, exynos4415_ctx);
1012}
1013CLK_OF_DECLARE(exynos4415_cmu, "samsung,exynos4415-cmu", exynos4415_cmu_init);
1014
1015/*
1016 * CMU DMC
1017 */
1018
1019#define MPLL_LOCK 0x008
1020#define MPLL_CON0 0x108
1021#define MPLL_CON1 0x10c
1022#define MPLL_CON2 0x110
1023#define BPLL_LOCK 0x118
1024#define BPLL_CON0 0x218
1025#define BPLL_CON1 0x21c
1026#define BPLL_CON2 0x220
1027#define SRC_DMC 0x300
1028#define DIV_DMC1 0x504
1029
1030enum exynos4415_dmc_plls {
1031 mpll, bpll,
1032 nr_dmc_plls,
1033};
1034
Krzysztof Kozlowskib5f56e12014-12-01 10:12:54 +0100[diff] [blame]1035static struct samsung_clk_provider *exynos4415_dmc_ctx;
1036
Chanwoo Choi384cb2c2014-10-27 10:11:57 +0900[diff] [blame]1037#ifdef CONFIG_PM_SLEEP
1038static struct samsung_clk_reg_dump *exynos4415_dmc_clk_regs;
Chanwoo Choi384cb2c2014-10-27 10:11:57 +0900[diff] [blame]1039
1040static unsigned long exynos4415_cmu_dmc_clk_regs[] __initdata = {
1041 MPLL_LOCK,
1042 MPLL_CON0,
1043 MPLL_CON1,
1044 MPLL_CON2,
1045 BPLL_LOCK,
1046 BPLL_CON0,
1047 BPLL_CON1,
1048 BPLL_CON2,
1049 SRC_DMC,
1050 DIV_DMC1,
1051};
1052
1053static int exynos4415_dmc_clk_suspend(void)
1054{
1055 samsung_clk_save(exynos4415_dmc_ctx->reg_base,
1056 exynos4415_dmc_clk_regs,
1057 ARRAY_SIZE(exynos4415_cmu_dmc_clk_regs));
1058 return 0;
1059}
1060
1061static void exynos4415_dmc_clk_resume(void)
1062{
1063 samsung_clk_restore(exynos4415_dmc_ctx->reg_base,
1064 exynos4415_dmc_clk_regs,
1065 ARRAY_SIZE(exynos4415_cmu_dmc_clk_regs));
1066}
1067
1068static struct syscore_ops exynos4415_dmc_clk_syscore_ops = {
1069 .suspend = exynos4415_dmc_clk_suspend,
1070 .resume = exynos4415_dmc_clk_resume,
1071};
1072
1073static void exynos4415_dmc_clk_sleep_init(void)
1074{
1075 exynos4415_dmc_clk_regs =
1076 samsung_clk_alloc_reg_dump(exynos4415_cmu_dmc_clk_regs,
1077 ARRAY_SIZE(exynos4415_cmu_dmc_clk_regs));
1078 if (!exynos4415_dmc_clk_regs) {
1079 pr_warn("%s: Failed to allocate sleep save data\n", __func__);
1080 return;
1081 }
1082
1083 register_syscore_ops(&exynos4415_dmc_clk_syscore_ops);
1084}
1085#else
1086static inline void exynos4415_dmc_clk_sleep_init(void) { }
1087#endif /* CONFIG_PM_SLEEP */
1088
1089PNAME(mout_mpll_p) = { "fin_pll", "fout_mpll", };
1090PNAME(mout_bpll_p) = { "fin_pll", "fout_bpll", };
1091PNAME(mbpll_p) = { "mout_mpll", "mout_bpll", };
1092
1093static struct samsung_mux_clock exynos4415_dmc_mux_clks[] __initdata = {
1094 MUX(CLK_DMC_MOUT_MPLL, "mout_mpll", mout_mpll_p, SRC_DMC, 12, 1),
1095 MUX(CLK_DMC_MOUT_BPLL, "mout_bpll", mout_bpll_p, SRC_DMC, 10, 1),
1096 MUX(CLK_DMC_MOUT_DPHY, "mout_dphy", mbpll_p, SRC_DMC, 8, 1),
1097 MUX(CLK_DMC_MOUT_DMC_BUS, "mout_dmc_bus", mbpll_p, SRC_DMC, 4, 1),
1098};
1099
1100static struct samsung_div_clock exynos4415_dmc_div_clks[] __initdata = {
1101 DIV(CLK_DMC_DIV_DMC, "div_dmc", "div_dmc_pre", DIV_DMC1, 27, 3),
1102 DIV(CLK_DMC_DIV_DPHY, "div_dphy", "mout_dphy", DIV_DMC1, 23, 3),
1103 DIV(CLK_DMC_DIV_DMC_PRE, "div_dmc_pre", "mout_dmc_bus",
1104 DIV_DMC1, 19, 2),
1105 DIV(CLK_DMC_DIV_DMCP, "div_dmcp", "div_dmcd", DIV_DMC1, 15, 3),
1106 DIV(CLK_DMC_DIV_DMCD, "div_dmcd", "div_dmc", DIV_DMC1, 11, 3),
1107 DIV(CLK_DMC_DIV_MPLL_PRE, "div_mpll_pre", "mout_mpll", DIV_DMC1, 8, 2),
1108};
1109
1110static struct samsung_pll_clock exynos4415_dmc_plls[nr_dmc_plls] __initdata = {
1111 [mpll] = PLL(pll_35xx, CLK_DMC_FOUT_MPLL, "fout_mpll", "fin_pll",
1112 MPLL_LOCK, MPLL_CON0, NULL),
1113 [bpll] = PLL(pll_35xx, CLK_DMC_FOUT_BPLL, "fout_bpll", "fin_pll",
1114 BPLL_LOCK, BPLL_CON0, NULL),
1115};
1116
1117static void __init exynos4415_cmu_dmc_init(struct device_node *np)
1118{
1119 void __iomem *reg_base;
1120
1121 reg_base = of_iomap(np, 0);
1122 if (!reg_base)
1123 panic("%s: failed to map registers\n", __func__);
1124
1125 exynos4415_dmc_ctx = samsung_clk_init(np, reg_base, NR_CLKS_DMC);
1126 if (!exynos4415_dmc_ctx)
1127 panic("%s: unable to allocate context.\n", __func__);
1128
1129 exynos4415_dmc_plls[mpll].rate_table = exynos4415_pll_rates;
1130 exynos4415_dmc_plls[bpll].rate_table = exynos4415_pll_rates;
1131
1132 samsung_clk_register_pll(exynos4415_dmc_ctx, exynos4415_dmc_plls,
1133 ARRAY_SIZE(exynos4415_dmc_plls), reg_base);
1134 samsung_clk_register_mux(exynos4415_dmc_ctx, exynos4415_dmc_mux_clks,
1135 ARRAY_SIZE(exynos4415_dmc_mux_clks));
1136 samsung_clk_register_div(exynos4415_dmc_ctx, exynos4415_dmc_div_clks,
1137 ARRAY_SIZE(exynos4415_dmc_div_clks));
1138
1139 exynos4415_dmc_clk_sleep_init();
1140
1141 samsung_clk_of_add_provider(np, exynos4415_dmc_ctx);
1142}
1143CLK_OF_DECLARE(exynos4415_cmu_dmc, "samsung,exynos4415-cmu-dmc",
1144 exynos4415_cmu_dmc_init);