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viresh kumar4c18e772010-05-03 09:24:30 +01001/*
viresh kumar4c18e772010-05-03 09:24:30 +01002 * SPEAr platform shared irq layer source file
3 *
Viresh Kumardf1590d2012-11-12 22:56:03 +05304 * Copyright (C) 2009-2012 ST Microelectronics
Viresh Kumarda899472015-07-17 16:23:50 -07005 * Viresh Kumar <vireshk@kernel.org>
viresh kumar4c18e772010-05-03 09:24:30 +01006 *
Viresh Kumardf1590d2012-11-12 22:56:03 +05307 * Copyright (C) 2012 ST Microelectronics
Viresh Kumar9cc23682014-04-18 15:07:16 -07008 * Shiraz Hashim <shiraz.linux.kernel@gmail.com>
Viresh Kumardf1590d2012-11-12 22:56:03 +05309 *
viresh kumar4c18e772010-05-03 09:24:30 +010010 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
Shiraz Hashim80515a5a2012-08-03 15:33:10 +053014#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
viresh kumar4c18e772010-05-03 09:24:30 +010015
16#include <linux/err.h>
Shiraz Hashim80515a5a2012-08-03 15:33:10 +053017#include <linux/export.h>
18#include <linux/interrupt.h>
viresh kumar4c18e772010-05-03 09:24:30 +010019#include <linux/io.h>
20#include <linux/irq.h>
Joel Porquet41a83e02015-07-07 17:11:46 -040021#include <linux/irqchip.h>
Shiraz Hashim80515a5a2012-08-03 15:33:10 +053022#include <linux/irqdomain.h>
23#include <linux/of.h>
24#include <linux/of_address.h>
25#include <linux/of_irq.h>
viresh kumar4c18e772010-05-03 09:24:30 +010026#include <linux/spinlock.h>
viresh kumar4c18e772010-05-03 09:24:30 +010027
Thomas Gleixner078bc002014-06-19 21:34:38 +000028/*
Thomas Gleixner078bc002014-06-19 21:34:38 +000029 * struct spear_shirq: shared irq structure
30 *
Thomas Gleixnerc5d1d852014-06-19 21:34:39 +000031 * base: Base register address
Thomas Gleixner1b0a76c2014-06-19 21:34:44 +000032 * status_reg: Status register offset for chained interrupt handler
33 * mask_reg: Mask register offset for irq chip
Thomas Gleixner4ecc8322014-06-19 21:34:41 +000034 * mask: Mask to apply to the status register
Thomas Gleixnerc5d1d852014-06-19 21:34:39 +000035 * virq_base: Base virtual interrupt number
36 * nr_irqs: Number of interrupts handled by this block
37 * offset: Bit offset of the first interrupt
Thomas Gleixnerf07e42f2014-06-19 21:34:43 +000038 * irq_chip: Interrupt controller chip used for this instance,
39 * if NULL group is disabled, but accounted
Thomas Gleixner078bc002014-06-19 21:34:38 +000040 */
41struct spear_shirq {
Thomas Gleixnerc5d1d852014-06-19 21:34:39 +000042 void __iomem *base;
Thomas Gleixner1b0a76c2014-06-19 21:34:44 +000043 u32 status_reg;
44 u32 mask_reg;
Thomas Gleixner4ecc8322014-06-19 21:34:41 +000045 u32 mask;
Thomas Gleixnerc5d1d852014-06-19 21:34:39 +000046 u32 virq_base;
47 u32 nr_irqs;
48 u32 offset;
Thomas Gleixnerf07e42f2014-06-19 21:34:43 +000049 struct irq_chip *irq_chip;
Thomas Gleixner078bc002014-06-19 21:34:38 +000050};
51
Shiraz Hashim80515a5a2012-08-03 15:33:10 +053052/* spear300 shared irq registers offsets and masks */
53#define SPEAR300_INT_ENB_MASK_REG 0x54
54#define SPEAR300_INT_STS_MASK_REG 0x58
55
Thomas Gleixnerf07e42f2014-06-19 21:34:43 +000056static DEFINE_RAW_SPINLOCK(shirq_lock);
57
58static void shirq_irq_mask(struct irq_data *d)
59{
60 struct spear_shirq *shirq = irq_data_get_irq_chip_data(d);
61 u32 val, shift = d->irq - shirq->virq_base + shirq->offset;
Thomas Gleixner1b0a76c2014-06-19 21:34:44 +000062 u32 __iomem *reg = shirq->base + shirq->mask_reg;
Thomas Gleixnerf07e42f2014-06-19 21:34:43 +000063
64 raw_spin_lock(&shirq_lock);
65 val = readl(reg) & ~(0x1 << shift);
66 writel(val, reg);
67 raw_spin_unlock(&shirq_lock);
68}
69
70static void shirq_irq_unmask(struct irq_data *d)
71{
72 struct spear_shirq *shirq = irq_data_get_irq_chip_data(d);
73 u32 val, shift = d->irq - shirq->virq_base + shirq->offset;
Thomas Gleixner1b0a76c2014-06-19 21:34:44 +000074 u32 __iomem *reg = shirq->base + shirq->mask_reg;
Thomas Gleixnerf07e42f2014-06-19 21:34:43 +000075
76 raw_spin_lock(&shirq_lock);
77 val = readl(reg) | (0x1 << shift);
78 writel(val, reg);
79 raw_spin_unlock(&shirq_lock);
80}
81
82static struct irq_chip shirq_chip = {
83 .name = "spear-shirq",
84 .irq_mask = shirq_irq_mask,
85 .irq_unmask = shirq_irq_unmask,
86};
87
Shiraz Hashim80515a5a2012-08-03 15:33:10 +053088static struct spear_shirq spear300_shirq_ras1 = {
Thomas Gleixnerc5d1d852014-06-19 21:34:39 +000089 .offset = 0,
90 .nr_irqs = 9,
Thomas Gleixner4ecc8322014-06-19 21:34:41 +000091 .mask = ((0x1 << 9) - 1) << 0,
Thomas Gleixnerf07e42f2014-06-19 21:34:43 +000092 .irq_chip = &shirq_chip,
Thomas Gleixner1b0a76c2014-06-19 21:34:44 +000093 .status_reg = SPEAR300_INT_STS_MASK_REG,
94 .mask_reg = SPEAR300_INT_ENB_MASK_REG,
Shiraz Hashim80515a5a2012-08-03 15:33:10 +053095};
96
97static struct spear_shirq *spear300_shirq_blocks[] = {
98 &spear300_shirq_ras1,
99};
100
101/* spear310 shared irq registers offsets and masks */
102#define SPEAR310_INT_STS_MASK_REG 0x04
103
104static struct spear_shirq spear310_shirq_ras1 = {
Thomas Gleixnerc5d1d852014-06-19 21:34:39 +0000105 .offset = 0,
106 .nr_irqs = 8,
Thomas Gleixner4ecc8322014-06-19 21:34:41 +0000107 .mask = ((0x1 << 8) - 1) << 0,
Thomas Gleixnerf07e42f2014-06-19 21:34:43 +0000108 .irq_chip = &dummy_irq_chip,
Thomas Gleixner1b0a76c2014-06-19 21:34:44 +0000109 .status_reg = SPEAR310_INT_STS_MASK_REG,
Shiraz Hashim80515a5a2012-08-03 15:33:10 +0530110};
111
112static struct spear_shirq spear310_shirq_ras2 = {
Thomas Gleixnerc5d1d852014-06-19 21:34:39 +0000113 .offset = 8,
114 .nr_irqs = 5,
Thomas Gleixner4ecc8322014-06-19 21:34:41 +0000115 .mask = ((0x1 << 5) - 1) << 8,
Thomas Gleixnerf07e42f2014-06-19 21:34:43 +0000116 .irq_chip = &dummy_irq_chip,
Thomas Gleixner1b0a76c2014-06-19 21:34:44 +0000117 .status_reg = SPEAR310_INT_STS_MASK_REG,
Shiraz Hashim80515a5a2012-08-03 15:33:10 +0530118};
119
120static struct spear_shirq spear310_shirq_ras3 = {
Thomas Gleixnerc5d1d852014-06-19 21:34:39 +0000121 .offset = 13,
122 .nr_irqs = 1,
Thomas Gleixner4ecc8322014-06-19 21:34:41 +0000123 .mask = ((0x1 << 1) - 1) << 13,
Thomas Gleixnerf07e42f2014-06-19 21:34:43 +0000124 .irq_chip = &dummy_irq_chip,
Thomas Gleixner1b0a76c2014-06-19 21:34:44 +0000125 .status_reg = SPEAR310_INT_STS_MASK_REG,
Shiraz Hashim80515a5a2012-08-03 15:33:10 +0530126};
127
128static struct spear_shirq spear310_shirq_intrcomm_ras = {
Thomas Gleixnerc5d1d852014-06-19 21:34:39 +0000129 .offset = 14,
130 .nr_irqs = 3,
Thomas Gleixner4ecc8322014-06-19 21:34:41 +0000131 .mask = ((0x1 << 3) - 1) << 14,
Thomas Gleixnerf07e42f2014-06-19 21:34:43 +0000132 .irq_chip = &dummy_irq_chip,
Thomas Gleixner1b0a76c2014-06-19 21:34:44 +0000133 .status_reg = SPEAR310_INT_STS_MASK_REG,
Shiraz Hashim80515a5a2012-08-03 15:33:10 +0530134};
135
136static struct spear_shirq *spear310_shirq_blocks[] = {
137 &spear310_shirq_ras1,
138 &spear310_shirq_ras2,
139 &spear310_shirq_ras3,
140 &spear310_shirq_intrcomm_ras,
141};
142
143/* spear320 shared irq registers offsets and masks */
144#define SPEAR320_INT_STS_MASK_REG 0x04
145#define SPEAR320_INT_CLR_MASK_REG 0x04
146#define SPEAR320_INT_ENB_MASK_REG 0x08
147
Thomas Gleixner03319a12014-06-19 21:34:40 +0000148static struct spear_shirq spear320_shirq_ras3 = {
149 .offset = 0,
150 .nr_irqs = 7,
Thomas Gleixner4ecc8322014-06-19 21:34:41 +0000151 .mask = ((0x1 << 7) - 1) << 0,
Thomas Gleixner03319a12014-06-19 21:34:40 +0000152};
153
Shiraz Hashim80515a5a2012-08-03 15:33:10 +0530154static struct spear_shirq spear320_shirq_ras1 = {
Thomas Gleixnerc5d1d852014-06-19 21:34:39 +0000155 .offset = 7,
156 .nr_irqs = 3,
Thomas Gleixner4ecc8322014-06-19 21:34:41 +0000157 .mask = ((0x1 << 3) - 1) << 7,
Thomas Gleixnerf07e42f2014-06-19 21:34:43 +0000158 .irq_chip = &dummy_irq_chip,
Thomas Gleixner1b0a76c2014-06-19 21:34:44 +0000159 .status_reg = SPEAR320_INT_STS_MASK_REG,
Shiraz Hashim80515a5a2012-08-03 15:33:10 +0530160};
161
162static struct spear_shirq spear320_shirq_ras2 = {
Thomas Gleixnerc5d1d852014-06-19 21:34:39 +0000163 .offset = 10,
164 .nr_irqs = 1,
Thomas Gleixner4ecc8322014-06-19 21:34:41 +0000165 .mask = ((0x1 << 1) - 1) << 10,
Thomas Gleixnerf07e42f2014-06-19 21:34:43 +0000166 .irq_chip = &dummy_irq_chip,
Thomas Gleixner1b0a76c2014-06-19 21:34:44 +0000167 .status_reg = SPEAR320_INT_STS_MASK_REG,
Shiraz Hashim80515a5a2012-08-03 15:33:10 +0530168};
169
Shiraz Hashim80515a5a2012-08-03 15:33:10 +0530170static struct spear_shirq spear320_shirq_intrcomm_ras = {
Thomas Gleixnerc5d1d852014-06-19 21:34:39 +0000171 .offset = 11,
172 .nr_irqs = 11,
Thomas Gleixner4ecc8322014-06-19 21:34:41 +0000173 .mask = ((0x1 << 11) - 1) << 11,
Thomas Gleixnerf07e42f2014-06-19 21:34:43 +0000174 .irq_chip = &dummy_irq_chip,
Thomas Gleixner1b0a76c2014-06-19 21:34:44 +0000175 .status_reg = SPEAR320_INT_STS_MASK_REG,
Shiraz Hashim80515a5a2012-08-03 15:33:10 +0530176};
177
178static struct spear_shirq *spear320_shirq_blocks[] = {
179 &spear320_shirq_ras3,
180 &spear320_shirq_ras1,
181 &spear320_shirq_ras2,
182 &spear320_shirq_intrcomm_ras,
183};
184
Thomas Gleixnerbd0b9ac2015-09-14 10:42:37 +0200185static void shirq_handler(struct irq_desc *desc)
viresh kumar4c18e772010-05-03 09:24:30 +0100186{
Jiang Liu5b292642015-06-04 12:13:20 +0800187 struct spear_shirq *shirq = irq_desc_get_handler_data(desc);
Thomas Gleixner25dc49e2014-06-19 21:34:42 +0000188 u32 pend;
viresh kumar4c18e772010-05-03 09:24:30 +0100189
Thomas Gleixner1b0a76c2014-06-19 21:34:44 +0000190 pend = readl(shirq->base + shirq->status_reg) & shirq->mask;
Thomas Gleixner25dc49e2014-06-19 21:34:42 +0000191 pend >>= shirq->offset;
Shiraz Hashim80515a5a2012-08-03 15:33:10 +0530192
Thomas Gleixner25dc49e2014-06-19 21:34:42 +0000193 while (pend) {
194 int irq = __ffs(pend);
Shiraz Hashim80515a5a2012-08-03 15:33:10 +0530195
Thomas Gleixner25dc49e2014-06-19 21:34:42 +0000196 pend &= ~(0x1 << irq);
197 generic_handle_irq(shirq->virq_base + irq);
viresh kumar4c18e772010-05-03 09:24:30 +0100198 }
viresh kumar4c18e772010-05-03 09:24:30 +0100199}
200
Thomas Gleixnerf37ecbc2014-06-19 21:34:39 +0000201static void __init spear_shirq_register(struct spear_shirq *shirq,
202 int parent_irq)
viresh kumar4c18e772010-05-03 09:24:30 +0100203{
204 int i;
205
Thomas Gleixnerf07e42f2014-06-19 21:34:43 +0000206 if (!shirq->irq_chip)
Shiraz Hashim80515a5a2012-08-03 15:33:10 +0530207 return;
viresh kumar4c18e772010-05-03 09:24:30 +0100208
Russell King2aedd0f2015-06-16 23:07:01 +0100209 irq_set_chained_handler_and_data(parent_irq, shirq_handler, shirq);
Thomas Gleixnerf37ecbc2014-06-19 21:34:39 +0000210
Thomas Gleixnerc5d1d852014-06-19 21:34:39 +0000211 for (i = 0; i < shirq->nr_irqs; i++) {
212 irq_set_chip_and_handler(shirq->virq_base + i,
Thomas Gleixnerf07e42f2014-06-19 21:34:43 +0000213 shirq->irq_chip, handle_simple_irq);
Thomas Gleixnerc5d1d852014-06-19 21:34:39 +0000214 irq_set_chip_data(shirq->virq_base + i, shirq);
viresh kumar4c18e772010-05-03 09:24:30 +0100215 }
Shiraz Hashim80515a5a2012-08-03 15:33:10 +0530216}
217
218static int __init shirq_init(struct spear_shirq **shirq_blocks, int block_nr,
219 struct device_node *np)
220{
Thomas Gleixnerc5d1d852014-06-19 21:34:39 +0000221 int i, parent_irq, virq_base, hwirq = 0, nr_irqs = 0;
Thomas Gleixnera26c06f2014-06-19 21:34:37 +0000222 struct irq_domain *shirq_domain;
Shiraz Hashim80515a5a2012-08-03 15:33:10 +0530223 void __iomem *base;
224
225 base = of_iomap(np, 0);
226 if (!base) {
227 pr_err("%s: failed to map shirq registers\n", __func__);
228 return -ENXIO;
229 }
230
231 for (i = 0; i < block_nr; i++)
Thomas Gleixnerc5d1d852014-06-19 21:34:39 +0000232 nr_irqs += shirq_blocks[i]->nr_irqs;
Shiraz Hashim80515a5a2012-08-03 15:33:10 +0530233
Thomas Gleixnerc5d1d852014-06-19 21:34:39 +0000234 virq_base = irq_alloc_descs(-1, 0, nr_irqs, 0);
235 if (IS_ERR_VALUE(virq_base)) {
Shiraz Hashim80515a5a2012-08-03 15:33:10 +0530236 pr_err("%s: irq desc alloc failed\n", __func__);
237 goto err_unmap;
238 }
239
Thomas Gleixnerc5d1d852014-06-19 21:34:39 +0000240 shirq_domain = irq_domain_add_legacy(np, nr_irqs, virq_base, 0,
Shiraz Hashim80515a5a2012-08-03 15:33:10 +0530241 &irq_domain_simple_ops, NULL);
242 if (WARN_ON(!shirq_domain)) {
243 pr_warn("%s: irq domain init failed\n", __func__);
244 goto err_free_desc;
245 }
246
247 for (i = 0; i < block_nr; i++) {
248 shirq_blocks[i]->base = base;
Thomas Gleixnerc5d1d852014-06-19 21:34:39 +0000249 shirq_blocks[i]->virq_base = irq_find_mapping(shirq_domain,
Shiraz Hashim80515a5a2012-08-03 15:33:10 +0530250 hwirq);
Shiraz Hashim80515a5a2012-08-03 15:33:10 +0530251
Thomas Gleixnerf37ecbc2014-06-19 21:34:39 +0000252 parent_irq = irq_of_parse_and_map(np, i);
253 spear_shirq_register(shirq_blocks[i], parent_irq);
Thomas Gleixnerc5d1d852014-06-19 21:34:39 +0000254 hwirq += shirq_blocks[i]->nr_irqs;
Shiraz Hashim80515a5a2012-08-03 15:33:10 +0530255 }
256
viresh kumar4c18e772010-05-03 09:24:30 +0100257 return 0;
Shiraz Hashim80515a5a2012-08-03 15:33:10 +0530258
259err_free_desc:
Thomas Gleixnerc5d1d852014-06-19 21:34:39 +0000260 irq_free_descs(virq_base, nr_irqs);
Shiraz Hashim80515a5a2012-08-03 15:33:10 +0530261err_unmap:
262 iounmap(base);
263 return -ENXIO;
264}
265
Thomas Gleixner078bc002014-06-19 21:34:38 +0000266static int __init spear300_shirq_of_init(struct device_node *np,
267 struct device_node *parent)
Shiraz Hashim80515a5a2012-08-03 15:33:10 +0530268{
269 return shirq_init(spear300_shirq_blocks,
270 ARRAY_SIZE(spear300_shirq_blocks), np);
271}
Rob Herringe9c51552013-01-02 09:37:56 -0600272IRQCHIP_DECLARE(spear300_shirq, "st,spear300-shirq", spear300_shirq_of_init);
Shiraz Hashim80515a5a2012-08-03 15:33:10 +0530273
Thomas Gleixner078bc002014-06-19 21:34:38 +0000274static int __init spear310_shirq_of_init(struct device_node *np,
275 struct device_node *parent)
Shiraz Hashim80515a5a2012-08-03 15:33:10 +0530276{
277 return shirq_init(spear310_shirq_blocks,
278 ARRAY_SIZE(spear310_shirq_blocks), np);
279}
Rob Herringe9c51552013-01-02 09:37:56 -0600280IRQCHIP_DECLARE(spear310_shirq, "st,spear310-shirq", spear310_shirq_of_init);
Shiraz Hashim80515a5a2012-08-03 15:33:10 +0530281
Thomas Gleixner078bc002014-06-19 21:34:38 +0000282static int __init spear320_shirq_of_init(struct device_node *np,
283 struct device_node *parent)
Shiraz Hashim80515a5a2012-08-03 15:33:10 +0530284{
285 return shirq_init(spear320_shirq_blocks,
286 ARRAY_SIZE(spear320_shirq_blocks), np);
viresh kumar4c18e772010-05-03 09:24:30 +0100287}
Rob Herringe9c51552013-01-02 09:37:56 -0600288IRQCHIP_DECLARE(spear320_shirq, "st,spear320-shirq", spear320_shirq_of_init);