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Florian Fainelli7ca5dc12009-06-24 11:12:57 +02001/*
2 * Copyright (C) 2006,2007 Felix Fietkau <nbd@openwrt.org>
3 * Copyright (C) 2006,2007 Eugene Konev <ejka@openwrt.org>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */
19
20#ifndef __AR7_H__
21#define __AR7_H__
22
23#include <linux/delay.h>
24#include <linux/io.h>
25#include <linux/errno.h>
26
27#include <asm/addrspace.h>
28
29#define AR7_SDRAM_BASE 0x14000000
30
31#define AR7_REGS_BASE 0x08610000
32
33#define AR7_REGS_MAC0 (AR7_REGS_BASE + 0x0000)
34#define AR7_REGS_GPIO (AR7_REGS_BASE + 0x0900)
35/* 0x08610A00 - 0x08610BFF (512 bytes, 128 bytes / clock) */
36#define AR7_REGS_POWER (AR7_REGS_BASE + 0x0a00)
37#define AR7_REGS_CLOCKS (AR7_REGS_POWER + 0x80)
38#define UR8_REGS_CLOCKS (AR7_REGS_POWER + 0x20)
39#define AR7_REGS_UART0 (AR7_REGS_BASE + 0x0e00)
40#define AR7_REGS_USB (AR7_REGS_BASE + 0x1200)
41#define AR7_REGS_RESET (AR7_REGS_BASE + 0x1600)
Florian Fainelli238dd312010-08-29 17:08:44 +020042#define AR7_REGS_PINSEL (AR7_REGS_BASE + 0x160C)
Florian Fainelli7ca5dc12009-06-24 11:12:57 +020043#define AR7_REGS_VLYNQ0 (AR7_REGS_BASE + 0x1800)
44#define AR7_REGS_DCL (AR7_REGS_BASE + 0x1a00)
45#define AR7_REGS_VLYNQ1 (AR7_REGS_BASE + 0x1c00)
46#define AR7_REGS_MDIO (AR7_REGS_BASE + 0x1e00)
47#define AR7_REGS_IRQ (AR7_REGS_BASE + 0x2400)
48#define AR7_REGS_MAC1 (AR7_REGS_BASE + 0x2800)
49
50#define AR7_REGS_WDT (AR7_REGS_BASE + 0x1f00)
51#define UR8_REGS_WDT (AR7_REGS_BASE + 0x0b00)
52#define UR8_REGS_UART1 (AR7_REGS_BASE + 0x0f00)
53
Florian Fainelli238dd312010-08-29 17:08:44 +020054/* Titan registers */
55#define TITAN_REGS_ESWITCH_BASE (0x08640000)
56#define TITAN_REGS_MAC0 (TITAN_REGS_ESWITCH_BASE)
57#define TITAN_REGS_MAC1 (TITAN_REGS_ESWITCH_BASE + 0x0800)
58#define TITAN_REGS_MDIO (TITAN_REGS_ESWITCH_BASE + 0x02000)
59#define TITAN_REGS_VLYNQ0 (AR7_REGS_BASE + 0x1c00)
60#define TITAN_REGS_VLYNQ1 (AR7_REGS_BASE + 0x1300)
61
Florian Fainellie1df0572010-05-16 15:25:30 +020062#define AR7_RESET_PERIPHERAL 0x0
Florian Fainelli7ca5dc12009-06-24 11:12:57 +020063#define AR7_RESET_SOFTWARE 0x4
64#define AR7_RESET_STATUS 0x8
65
66#define AR7_RESET_BIT_CPMAC_LO 17
67#define AR7_RESET_BIT_CPMAC_HI 21
68#define AR7_RESET_BIT_MDIO 22
69#define AR7_RESET_BIT_EPHY 26
70
Florian Fainelli238dd312010-08-29 17:08:44 +020071#define TITAN_RESET_BIT_EPHY1 28
72
Florian Fainelli7ca5dc12009-06-24 11:12:57 +020073/* GPIO control registers */
74#define AR7_GPIO_INPUT 0x0
75#define AR7_GPIO_OUTPUT 0x4
76#define AR7_GPIO_DIR 0x8
77#define AR7_GPIO_ENABLE 0xc
Florian Fainelli238dd312010-08-29 17:08:44 +020078#define TITAN_GPIO_INPUT_0 0x0
79#define TITAN_GPIO_INPUT_1 0x4
80#define TITAN_GPIO_OUTPUT_0 0x8
81#define TITAN_GPIO_OUTPUT_1 0xc
82#define TITAN_GPIO_DIR_0 0x10
83#define TITAN_GPIO_DIR_1 0x14
84#define TITAN_GPIO_ENBL_0 0x18
85#define TITAN_GPIO_ENBL_1 0x1c
Florian Fainelli7ca5dc12009-06-24 11:12:57 +020086
87#define AR7_CHIP_7100 0x18
88#define AR7_CHIP_7200 0x2b
89#define AR7_CHIP_7300 0x05
Florian Fainelli238dd312010-08-29 17:08:44 +020090#define AR7_CHIP_TITAN 0x07
91#define TITAN_CHIP_1050 0x0f
92#define TITAN_CHIP_1055 0x0e
93#define TITAN_CHIP_1056 0x0d
94#define TITAN_CHIP_1060 0x07
Florian Fainelli7ca5dc12009-06-24 11:12:57 +020095
96/* Interrupts */
97#define AR7_IRQ_UART0 15
98#define AR7_IRQ_UART1 16
99
100/* Clocks */
101#define AR7_AFE_CLOCK 35328000
102#define AR7_REF_CLOCK 25000000
103#define AR7_XTAL_CLOCK 24000000
104
Florian Fainelli72838a12009-08-04 23:09:36 +0200105/* DCL */
106#define AR7_WDT_HW_ENA 0x10
107
Florian Fainelli7ca5dc12009-06-24 11:12:57 +0200108struct plat_cpmac_data {
109 int reset_bit;
110 int power_bit;
111 u32 phy_mask;
112 char dev_addr[6];
113};
114
115struct plat_dsl_data {
116 int reset_bit_dsl;
117 int reset_bit_sar;
118};
119
120extern int ar7_cpu_clock, ar7_bus_clock, ar7_dsp_clock;
121
Florian Fainelli238dd312010-08-29 17:08:44 +0200122static inline int ar7_is_titan(void)
123{
124 return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x24)) & 0xffff) ==
125 AR7_CHIP_TITAN;
126}
127
Florian Fainelli7ca5dc12009-06-24 11:12:57 +0200128static inline u16 ar7_chip_id(void)
129{
Florian Fainelli238dd312010-08-29 17:08:44 +0200130 return ar7_is_titan() ? AR7_CHIP_TITAN : (readl((void *)
131 KSEG1ADDR(AR7_REGS_GPIO + 0x14)) & 0xffff);
132}
133
134static inline u16 titan_chip_id(void)
135{
136 unsigned int val = readl((void *)KSEG1ADDR(AR7_REGS_GPIO +
137 TITAN_GPIO_INPUT_1));
138 return ((val >> 12) & 0x0f);
Florian Fainelli7ca5dc12009-06-24 11:12:57 +0200139}
140
141static inline u8 ar7_chip_rev(void)
142{
Florian Fainelli238dd312010-08-29 17:08:44 +0200143 return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + (ar7_is_titan() ? 0x24 :
144 0x14))) >> 16) & 0xff;
Florian Fainelli7ca5dc12009-06-24 11:12:57 +0200145}
146
Florian Fainelli780019d2010-01-27 09:10:06 +0100147struct clk {
148 unsigned int rate;
149};
Florian Fainelli7ca5dc12009-06-24 11:12:57 +0200150
151static inline int ar7_has_high_cpmac(void)
152{
153 u16 chip_id = ar7_chip_id();
154 switch (chip_id) {
155 case AR7_CHIP_7100:
156 case AR7_CHIP_7200:
157 return 0;
158 case AR7_CHIP_7300:
159 return 1;
160 default:
161 return -ENXIO;
162 }
163}
164#define ar7_has_high_vlynq ar7_has_high_cpmac
165#define ar7_has_second_uart ar7_has_high_cpmac
166
167static inline void ar7_device_enable(u32 bit)
168{
169 void *reset_reg =
Florian Fainellie1df0572010-05-16 15:25:30 +0200170 (void *)KSEG1ADDR(AR7_REGS_RESET + AR7_RESET_PERIPHERAL);
Florian Fainelli7ca5dc12009-06-24 11:12:57 +0200171 writel(readl(reset_reg) | (1 << bit), reset_reg);
172 msleep(20);
173}
174
175static inline void ar7_device_disable(u32 bit)
176{
177 void *reset_reg =
Florian Fainellie1df0572010-05-16 15:25:30 +0200178 (void *)KSEG1ADDR(AR7_REGS_RESET + AR7_RESET_PERIPHERAL);
Florian Fainelli7ca5dc12009-06-24 11:12:57 +0200179 writel(readl(reset_reg) & ~(1 << bit), reset_reg);
180 msleep(20);
181}
182
183static inline void ar7_device_reset(u32 bit)
184{
185 ar7_device_disable(bit);
186 ar7_device_enable(bit);
187}
188
189static inline void ar7_device_on(u32 bit)
190{
191 void *power_reg = (void *)KSEG1ADDR(AR7_REGS_POWER);
192 writel(readl(power_reg) | (1 << bit), power_reg);
193 msleep(20);
194}
195
196static inline void ar7_device_off(u32 bit)
197{
198 void *power_reg = (void *)KSEG1ADDR(AR7_REGS_POWER);
199 writel(readl(power_reg) & ~(1 << bit), power_reg);
200 msleep(20);
201}
202
Florian Fainelli3bc69682010-08-29 17:08:41 +0200203int __init ar7_gpio_init(void);
Florian Fainelli0bc67912010-10-31 23:49:58 +0100204void __init ar7_init_clocks(void);
Florian Fainelli3bc69682010-08-29 17:08:41 +0200205
Florian Fainelli7ca5dc12009-06-24 11:12:57 +0200206#endif /* __AR7_H__ */