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Michal Simek406107d2009-03-27 14:25:11 +01001/*
2 * Generic support for queying CPU info
3 *
4 * Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu>
5 * Copyright (C) 2007-2009 PetaLogix
6 * Copyright (C) 2007 John Williams <jwilliams@itee.uq.edu.au>
7 *
8 * This file is subject to the terms and conditions of the GNU General
9 * Public License. See the file COPYING in the main directory of this
10 * archive for more details.
11 */
12
13#ifndef _ASM_MICROBLAZE_CPUINFO_H
14#define _ASM_MICROBLAZE_CPUINFO_H
15
16#include <asm/prom.h>
17
18/* CPU Version and FPGA Family code conversion table type */
19struct cpu_ver_key {
20 const char *s;
21 const unsigned k;
22};
23
24extern const struct cpu_ver_key cpu_ver_lookup[];
25
26struct family_string_key {
27 const char *s;
28 const unsigned k;
29};
30
31extern const struct family_string_key family_string_lookup[];
32
33struct cpuinfo {
34 /* Core CPU configuration */
35 u32 use_instr;
36 u32 use_mult;
37 u32 use_fpu;
38 u32 use_exc;
39 u32 ver_code;
40 u32 mmu;
41
42 /* CPU caches */
43 u32 use_icache;
44 u32 icache_tagbits;
45 u32 icache_write;
Michal Simek44e4e192009-10-08 13:06:42 +020046 u32 icache_line_length;
Michal Simek406107d2009-03-27 14:25:11 +010047 u32 icache_size;
48 unsigned long icache_base;
49 unsigned long icache_high;
50
51 u32 use_dcache;
52 u32 dcache_tagbits;
53 u32 dcache_write;
Michal Simek44e4e192009-10-08 13:06:42 +020054 u32 dcache_line_length;
Michal Simek406107d2009-03-27 14:25:11 +010055 u32 dcache_size;
Michal Simeke051af52009-10-14 11:12:50 +020056 u32 dcache_wb;
Michal Simek406107d2009-03-27 14:25:11 +010057 unsigned long dcache_base;
58 unsigned long dcache_high;
59
60 /* Bus connections */
61 u32 use_dopb;
62 u32 use_iopb;
63 u32 use_dlmb;
64 u32 use_ilmb;
65 u32 num_fsl;
66
67 /* CPU interrupt line info */
68 u32 irq_edge;
69 u32 irq_positive;
70
71 u32 area_optimised;
72
73 /* HW debug support */
74 u32 hw_debug;
75 u32 num_pc_brk;
76 u32 num_rd_brk;
77 u32 num_wr_brk;
78 u32 cpu_clock_freq; /* store real freq of cpu */
79 u32 freq_div_hz; /* store freq/HZ */
80
81 /* FPGA family */
82 u32 fpga_family_code;
83
84 /* User define */
85 u32 pvr_user1;
86 u32 pvr_user2;
87};
88
89extern struct cpuinfo cpuinfo;
90
91/* fwd declarations of the various CPUinfo populators */
92void setup_cpuinfo(void);
93
94void set_cpuinfo_static(struct cpuinfo *ci, struct device_node *cpu);
95void set_cpuinfo_pvr_full(struct cpuinfo *ci, struct device_node *cpu);
96
97static inline unsigned int fcpu(struct device_node *cpu, char *n)
98{
99 int *val;
100 return (val = (int *) of_get_property(cpu, n, NULL)) ? *val : 0;
101}
102
103#endif /* _ASM_MICROBLAZE_CPUINFO_H */