blob: 0693b3920e688e0a691dfe065298912e1b591581 [file] [log] [blame]
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001/*
2 Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt61pci
23 Abstract: rt61pci device specific routines.
24 Supported chipsets: RT2561, RT2561s, RT2661.
25 */
26
Ivo van Doorn95ea3622007-09-25 17:57:13 -070027#include <linux/delay.h>
28#include <linux/etherdevice.h>
29#include <linux/init.h>
30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/pci.h>
33#include <linux/eeprom_93cx6.h>
34
35#include "rt2x00.h"
36#include "rt2x00pci.h"
37#include "rt61pci.h"
38
39/*
40 * Register access.
41 * BBP and RF register require indirect register access,
42 * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
43 * These indirect registers work with busy bits,
44 * and we will try maximal REGISTER_BUSY_COUNT times to access
45 * the register while taking a REGISTER_BUSY_DELAY us delay
46 * between each attampt. When the busy bit is still set at that time,
47 * the access attempt is considered to have failed,
48 * and we will print an error.
49 */
Adam Baker0e14f6d2007-10-27 13:41:25 +020050static u32 rt61pci_bbp_check(struct rt2x00_dev *rt2x00dev)
Ivo van Doorn95ea3622007-09-25 17:57:13 -070051{
52 u32 reg;
53 unsigned int i;
54
55 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
56 rt2x00pci_register_read(rt2x00dev, PHY_CSR3, &reg);
57 if (!rt2x00_get_field32(reg, PHY_CSR3_BUSY))
58 break;
59 udelay(REGISTER_BUSY_DELAY);
60 }
61
62 return reg;
63}
64
Adam Baker0e14f6d2007-10-27 13:41:25 +020065static void rt61pci_bbp_write(struct rt2x00_dev *rt2x00dev,
Ivo van Doorn95ea3622007-09-25 17:57:13 -070066 const unsigned int word, const u8 value)
67{
68 u32 reg;
69
70 /*
71 * Wait until the BBP becomes ready.
72 */
73 reg = rt61pci_bbp_check(rt2x00dev);
74 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
75 ERROR(rt2x00dev, "PHY_CSR3 register busy. Write failed.\n");
76 return;
77 }
78
79 /*
80 * Write the data into the BBP.
81 */
82 reg = 0;
83 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
84 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
85 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
86 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
87
88 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
89}
90
Adam Baker0e14f6d2007-10-27 13:41:25 +020091static void rt61pci_bbp_read(struct rt2x00_dev *rt2x00dev,
Ivo van Doorn95ea3622007-09-25 17:57:13 -070092 const unsigned int word, u8 *value)
93{
94 u32 reg;
95
96 /*
97 * Wait until the BBP becomes ready.
98 */
99 reg = rt61pci_bbp_check(rt2x00dev);
100 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
101 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
102 return;
103 }
104
105 /*
106 * Write the request into the BBP.
107 */
108 reg = 0;
109 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
110 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
111 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
112
113 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
114
115 /*
116 * Wait until the BBP becomes ready.
117 */
118 reg = rt61pci_bbp_check(rt2x00dev);
119 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
120 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
121 *value = 0xff;
122 return;
123 }
124
125 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
126}
127
Adam Baker0e14f6d2007-10-27 13:41:25 +0200128static void rt61pci_rf_write(struct rt2x00_dev *rt2x00dev,
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700129 const unsigned int word, const u32 value)
130{
131 u32 reg;
132 unsigned int i;
133
134 if (!word)
135 return;
136
137 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
138 rt2x00pci_register_read(rt2x00dev, PHY_CSR4, &reg);
139 if (!rt2x00_get_field32(reg, PHY_CSR4_BUSY))
140 goto rf_write;
141 udelay(REGISTER_BUSY_DELAY);
142 }
143
144 ERROR(rt2x00dev, "PHY_CSR4 register busy. Write failed.\n");
145 return;
146
147rf_write:
148 reg = 0;
149 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
150 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS, 21);
151 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
152 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
153
154 rt2x00pci_register_write(rt2x00dev, PHY_CSR4, reg);
155 rt2x00_rf_write(rt2x00dev, word, value);
156}
157
Adam Baker0e14f6d2007-10-27 13:41:25 +0200158static void rt61pci_mcu_request(struct rt2x00_dev *rt2x00dev,
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700159 const u8 command, const u8 token,
160 const u8 arg0, const u8 arg1)
161{
162 u32 reg;
163
164 rt2x00pci_register_read(rt2x00dev, H2M_MAILBOX_CSR, &reg);
165
166 if (rt2x00_get_field32(reg, H2M_MAILBOX_CSR_OWNER)) {
167 ERROR(rt2x00dev, "mcu request error. "
168 "Request 0x%02x failed for token 0x%02x.\n",
169 command, token);
170 return;
171 }
172
173 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
174 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
175 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
176 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
177 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
178
179 rt2x00pci_register_read(rt2x00dev, HOST_CMD_CSR, &reg);
180 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
181 rt2x00_set_field32(&reg, HOST_CMD_CSR_INTERRUPT_MCU, 1);
182 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
183}
184
185static void rt61pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
186{
187 struct rt2x00_dev *rt2x00dev = eeprom->data;
188 u32 reg;
189
190 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
191
192 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
193 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
194 eeprom->reg_data_clock =
195 !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
196 eeprom->reg_chip_select =
197 !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
198}
199
200static void rt61pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
201{
202 struct rt2x00_dev *rt2x00dev = eeprom->data;
203 u32 reg = 0;
204
205 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
206 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
207 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
208 !!eeprom->reg_data_clock);
209 rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
210 !!eeprom->reg_chip_select);
211
212 rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
213}
214
215#ifdef CONFIG_RT2X00_LIB_DEBUGFS
216#define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
217
Adam Baker0e14f6d2007-10-27 13:41:25 +0200218static void rt61pci_read_csr(struct rt2x00_dev *rt2x00dev,
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700219 const unsigned int word, u32 *data)
220{
221 rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
222}
223
Adam Baker0e14f6d2007-10-27 13:41:25 +0200224static void rt61pci_write_csr(struct rt2x00_dev *rt2x00dev,
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700225 const unsigned int word, u32 data)
226{
227 rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
228}
229
230static const struct rt2x00debug rt61pci_rt2x00debug = {
231 .owner = THIS_MODULE,
232 .csr = {
233 .read = rt61pci_read_csr,
234 .write = rt61pci_write_csr,
235 .word_size = sizeof(u32),
236 .word_count = CSR_REG_SIZE / sizeof(u32),
237 },
238 .eeprom = {
239 .read = rt2x00_eeprom_read,
240 .write = rt2x00_eeprom_write,
241 .word_size = sizeof(u16),
242 .word_count = EEPROM_SIZE / sizeof(u16),
243 },
244 .bbp = {
245 .read = rt61pci_bbp_read,
246 .write = rt61pci_bbp_write,
247 .word_size = sizeof(u8),
248 .word_count = BBP_SIZE / sizeof(u8),
249 },
250 .rf = {
251 .read = rt2x00_rf_read,
252 .write = rt61pci_rf_write,
253 .word_size = sizeof(u32),
254 .word_count = RF_SIZE / sizeof(u32),
255 },
256};
257#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
258
259#ifdef CONFIG_RT61PCI_RFKILL
260static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
261{
262 u32 reg;
263
264 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
265 return rt2x00_get_field32(reg, MAC_CSR13_BIT5);;
266}
Ivo van Doorn81873e92007-10-06 14:14:06 +0200267#else
268#define rt61pci_rfkill_poll NULL
Ivo van Doorndcf54752007-09-25 20:57:25 +0200269#endif /* CONFIG_RT61PCI_RFKILL */
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700270
271/*
272 * Configuration handlers.
273 */
Ivo van Doorn4abee4b2007-10-06 14:11:46 +0200274static void rt61pci_config_mac_addr(struct rt2x00_dev *rt2x00dev, __le32 *mac)
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700275{
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700276 u32 tmp;
277
Ivo van Doorn4abee4b2007-10-06 14:11:46 +0200278 tmp = le32_to_cpu(mac[1]);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700279 rt2x00_set_field32(&tmp, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
Ivo van Doorn4abee4b2007-10-06 14:11:46 +0200280 mac[1] = cpu_to_le32(tmp);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700281
Ivo van Doorn4abee4b2007-10-06 14:11:46 +0200282 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR2, mac,
283 (2 * sizeof(__le32)));
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700284}
285
Ivo van Doorn4abee4b2007-10-06 14:11:46 +0200286static void rt61pci_config_bssid(struct rt2x00_dev *rt2x00dev, __le32 *bssid)
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700287{
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700288 u32 tmp;
289
Ivo van Doorn4abee4b2007-10-06 14:11:46 +0200290 tmp = le32_to_cpu(bssid[1]);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700291 rt2x00_set_field32(&tmp, MAC_CSR5_BSS_ID_MASK, 3);
Ivo van Doorn4abee4b2007-10-06 14:11:46 +0200292 bssid[1] = cpu_to_le32(tmp);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700293
Ivo van Doorn4abee4b2007-10-06 14:11:46 +0200294 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR4, bssid,
295 (2 * sizeof(__le32)));
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700296}
297
Ivo van Doornfeb24692007-10-06 14:14:29 +0200298static void rt61pci_config_type(struct rt2x00_dev *rt2x00dev, const int type,
299 const int tsf_sync)
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700300{
301 u32 reg;
302
303 /*
304 * Clear current synchronisation setup.
305 * For the Beacon base registers we only need to clear
306 * the first byte since that byte contains the VALID and OWNER
307 * bits which (when set to 0) will invalidate the entire beacon.
308 */
309 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0);
310 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
311 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
312 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
313 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
314
315 /*
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700316 * Enable synchronisation.
317 */
318 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
Johannes Berg4150c572007-09-17 01:29:23 -0400319 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
320 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700321 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
Ivo van Doornfeb24692007-10-06 14:14:29 +0200322 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, tsf_sync);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700323 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
324}
325
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200326static void rt61pci_config_preamble(struct rt2x00_dev *rt2x00dev,
327 const int short_preamble,
328 const int ack_timeout,
329 const int ack_consume_time)
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700330{
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700331 u32 reg;
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700332
333 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200334 rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, ack_timeout);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700335 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
336
337 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
Ivo van Doorn4f5af6eb2007-10-06 14:16:30 +0200338 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200339 !!short_preamble);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700340 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
341}
342
343static void rt61pci_config_phymode(struct rt2x00_dev *rt2x00dev,
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200344 const int basic_rate_mask)
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700345{
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200346 rt2x00pci_register_write(rt2x00dev, TXRX_CSR5, basic_rate_mask);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700347}
348
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200349static void rt61pci_config_channel(struct rt2x00_dev *rt2x00dev,
350 struct rf_channel *rf, const int txpower)
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700351{
352 u8 r3;
353 u8 r94;
354 u8 smart;
355
356 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
357 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
358
359 smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
360 rt2x00_rf(&rt2x00dev->chip, RF2527));
361
362 rt61pci_bbp_read(rt2x00dev, 3, &r3);
363 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
364 rt61pci_bbp_write(rt2x00dev, 3, r3);
365
366 r94 = 6;
367 if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
368 r94 += txpower - MAX_TXPOWER;
369 else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
370 r94 += txpower;
371 rt61pci_bbp_write(rt2x00dev, 94, r94);
372
373 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
374 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
375 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
376 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
377
378 udelay(200);
379
380 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
381 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
382 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
383 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
384
385 udelay(200);
386
387 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
388 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
389 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
390 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
391
392 msleep(1);
393}
394
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700395static void rt61pci_config_txpower(struct rt2x00_dev *rt2x00dev,
396 const int txpower)
397{
398 struct rf_channel rf;
399
400 rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
401 rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
402 rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
403 rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
404
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200405 rt61pci_config_channel(rt2x00dev, &rf, txpower);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700406}
407
408static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
Ivo van Doornaddc81bd2007-10-13 16:26:23 +0200409 struct antenna_setup *ant)
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700410{
411 u8 r3;
412 u8 r4;
413 u8 r77;
414
415 rt61pci_bbp_read(rt2x00dev, 3, &r3);
416 rt61pci_bbp_read(rt2x00dev, 4, &r4);
417 rt61pci_bbp_read(rt2x00dev, 77, &r77);
418
419 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
Mattias Nissleracaa4102007-10-27 13:41:53 +0200420 rt2x00_rf(&rt2x00dev->chip, RF5325));
Ivo van Doorne4cd2ff2007-10-27 13:39:57 +0200421
422 /*
423 * Configure the RX antenna.
424 */
Ivo van Doornaddc81bd2007-10-13 16:26:23 +0200425 switch (ant->rx) {
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700426 case ANTENNA_HW_DIVERSITY:
Mattias Nissleracaa4102007-10-27 13:41:53 +0200427 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700428 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
Ivo van Doornddc827f2007-10-13 16:26:42 +0200429 (rt2x00dev->curr_hwmode != HWMODE_A));
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700430 break;
431 case ANTENNA_A:
Mattias Nissleracaa4102007-10-27 13:41:53 +0200432 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700433 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
Mattias Nissleracaa4102007-10-27 13:41:53 +0200434 if (rt2x00dev->curr_hwmode == HWMODE_A)
435 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
436 else
437 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700438 break;
Ivo van Doorn39e75852007-10-13 16:26:27 +0200439 case ANTENNA_SW_DIVERSITY:
440 /*
441 * NOTE: We should never come here because rt2x00lib is
442 * supposed to catch this and send us the correct antenna
443 * explicitely. However we are nog going to bug about this.
444 * Instead, just default to antenna B.
445 */
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700446 case ANTENNA_B:
Mattias Nissleracaa4102007-10-27 13:41:53 +0200447 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700448 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
Mattias Nissleracaa4102007-10-27 13:41:53 +0200449 if (rt2x00dev->curr_hwmode == HWMODE_A)
450 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
451 else
452 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700453 break;
454 }
455
456 rt61pci_bbp_write(rt2x00dev, 77, r77);
457 rt61pci_bbp_write(rt2x00dev, 3, r3);
458 rt61pci_bbp_write(rt2x00dev, 4, r4);
459}
460
461static void rt61pci_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
Ivo van Doornaddc81bd2007-10-13 16:26:23 +0200462 struct antenna_setup *ant)
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700463{
464 u8 r3;
465 u8 r4;
466 u8 r77;
467
468 rt61pci_bbp_read(rt2x00dev, 3, &r3);
469 rt61pci_bbp_read(rt2x00dev, 4, &r4);
470 rt61pci_bbp_read(rt2x00dev, 77, &r77);
471
472 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
Mattias Nissleracaa4102007-10-27 13:41:53 +0200473 rt2x00_rf(&rt2x00dev->chip, RF2529));
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700474 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
475 !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
476
Ivo van Doorne4cd2ff2007-10-27 13:39:57 +0200477 /*
Ivo van Doorne4cd2ff2007-10-27 13:39:57 +0200478 * Configure the RX antenna.
479 */
Ivo van Doornaddc81bd2007-10-13 16:26:23 +0200480 switch (ant->rx) {
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700481 case ANTENNA_HW_DIVERSITY:
Mattias Nissleracaa4102007-10-27 13:41:53 +0200482 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700483 break;
484 case ANTENNA_A:
Mattias Nissleracaa4102007-10-27 13:41:53 +0200485 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
486 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700487 break;
Ivo van Doorn39e75852007-10-13 16:26:27 +0200488 case ANTENNA_SW_DIVERSITY:
489 /*
490 * NOTE: We should never come here because rt2x00lib is
491 * supposed to catch this and send us the correct antenna
492 * explicitely. However we are nog going to bug about this.
493 * Instead, just default to antenna B.
494 */
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700495 case ANTENNA_B:
Mattias Nissleracaa4102007-10-27 13:41:53 +0200496 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
497 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700498 break;
499 }
500
501 rt61pci_bbp_write(rt2x00dev, 77, r77);
502 rt61pci_bbp_write(rt2x00dev, 3, r3);
503 rt61pci_bbp_write(rt2x00dev, 4, r4);
504}
505
506static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev *rt2x00dev,
507 const int p1, const int p2)
508{
509 u32 reg;
510
511 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
512
Mattias Nissleracaa4102007-10-27 13:41:53 +0200513 rt2x00_set_field32(&reg, MAC_CSR13_BIT4, p1);
514 rt2x00_set_field32(&reg, MAC_CSR13_BIT12, 0);
515
516 rt2x00_set_field32(&reg, MAC_CSR13_BIT3, !p2);
517 rt2x00_set_field32(&reg, MAC_CSR13_BIT11, 0);
518
519 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, reg);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700520}
521
522static void rt61pci_config_antenna_2529(struct rt2x00_dev *rt2x00dev,
Ivo van Doornaddc81bd2007-10-13 16:26:23 +0200523 struct antenna_setup *ant)
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700524{
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700525 u8 r3;
526 u8 r4;
527 u8 r77;
528
529 rt61pci_bbp_read(rt2x00dev, 3, &r3);
530 rt61pci_bbp_read(rt2x00dev, 4, &r4);
531 rt61pci_bbp_read(rt2x00dev, 77, &r77);
Ivo van Doorne4cd2ff2007-10-27 13:39:57 +0200532
Mattias Nissleracaa4102007-10-27 13:41:53 +0200533 /* FIXME: Antenna selection for the rf 2529 is very confusing in the
534 * legacy driver. The code below should be ok for non-diversity setups.
Ivo van Doorne4cd2ff2007-10-27 13:39:57 +0200535 */
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700536
Ivo van Doorne4cd2ff2007-10-27 13:39:57 +0200537 /*
538 * Configure the RX antenna.
539 */
540 switch (ant->rx) {
541 case ANTENNA_A:
Mattias Nissleracaa4102007-10-27 13:41:53 +0200542 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
543 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
544 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0);
Ivo van Doorne4cd2ff2007-10-27 13:39:57 +0200545 break;
546 case ANTENNA_SW_DIVERSITY:
547 case ANTENNA_HW_DIVERSITY:
548 /*
549 * NOTE: We should never come here because rt2x00lib is
550 * supposed to catch this and send us the correct antenna
551 * explicitely. However we are nog going to bug about this.
552 * Instead, just default to antenna B.
553 */
554 case ANTENNA_B:
Mattias Nissleracaa4102007-10-27 13:41:53 +0200555 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
556 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
557 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
Ivo van Doorne4cd2ff2007-10-27 13:39:57 +0200558 break;
559 }
560
Ivo van Doorne4cd2ff2007-10-27 13:39:57 +0200561 rt61pci_bbp_write(rt2x00dev, 77, r77);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700562 rt61pci_bbp_write(rt2x00dev, 3, r3);
563 rt61pci_bbp_write(rt2x00dev, 4, r4);
564}
565
566struct antenna_sel {
567 u8 word;
568 /*
569 * value[0] -> non-LNA
570 * value[1] -> LNA
571 */
572 u8 value[2];
573};
574
575static const struct antenna_sel antenna_sel_a[] = {
576 { 96, { 0x58, 0x78 } },
577 { 104, { 0x38, 0x48 } },
578 { 75, { 0xfe, 0x80 } },
579 { 86, { 0xfe, 0x80 } },
580 { 88, { 0xfe, 0x80 } },
581 { 35, { 0x60, 0x60 } },
582 { 97, { 0x58, 0x58 } },
583 { 98, { 0x58, 0x58 } },
584};
585
586static const struct antenna_sel antenna_sel_bg[] = {
587 { 96, { 0x48, 0x68 } },
588 { 104, { 0x2c, 0x3c } },
589 { 75, { 0xfe, 0x80 } },
590 { 86, { 0xfe, 0x80 } },
591 { 88, { 0xfe, 0x80 } },
592 { 35, { 0x50, 0x50 } },
593 { 97, { 0x48, 0x48 } },
594 { 98, { 0x48, 0x48 } },
595};
596
597static void rt61pci_config_antenna(struct rt2x00_dev *rt2x00dev,
Ivo van Doornaddc81bd2007-10-13 16:26:23 +0200598 struct antenna_setup *ant)
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700599{
600 const struct antenna_sel *sel;
601 unsigned int lna;
602 unsigned int i;
603 u32 reg;
604
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700605 if (rt2x00dev->curr_hwmode == HWMODE_A) {
606 sel = antenna_sel_a;
607 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700608 } else {
609 sel = antenna_sel_bg;
610 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700611 }
612
Mattias Nissleracaa4102007-10-27 13:41:53 +0200613 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
614 rt61pci_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
615
616 rt2x00pci_register_read(rt2x00dev, PHY_CSR0, &reg);
617
Ivo van Doornddc827f2007-10-13 16:26:42 +0200618 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
619 (rt2x00dev->curr_hwmode == HWMODE_B ||
620 rt2x00dev->curr_hwmode == HWMODE_G));
621 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
622 (rt2x00dev->curr_hwmode == HWMODE_A));
623
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700624 rt2x00pci_register_write(rt2x00dev, PHY_CSR0, reg);
625
626 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
627 rt2x00_rf(&rt2x00dev->chip, RF5325))
Ivo van Doornaddc81bd2007-10-13 16:26:23 +0200628 rt61pci_config_antenna_5x(rt2x00dev, ant);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700629 else if (rt2x00_rf(&rt2x00dev->chip, RF2527))
Ivo van Doornaddc81bd2007-10-13 16:26:23 +0200630 rt61pci_config_antenna_2x(rt2x00dev, ant);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700631 else if (rt2x00_rf(&rt2x00dev->chip, RF2529)) {
632 if (test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags))
Ivo van Doornaddc81bd2007-10-13 16:26:23 +0200633 rt61pci_config_antenna_2x(rt2x00dev, ant);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700634 else
Ivo van Doornaddc81bd2007-10-13 16:26:23 +0200635 rt61pci_config_antenna_2529(rt2x00dev, ant);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700636 }
637}
638
639static void rt61pci_config_duration(struct rt2x00_dev *rt2x00dev,
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200640 struct rt2x00lib_conf *libconf)
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700641{
642 u32 reg;
643
644 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200645 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, libconf->slot_time);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700646 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
647
648 rt2x00pci_register_read(rt2x00dev, MAC_CSR8, &reg);
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200649 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, libconf->sifs);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700650 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200651 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, libconf->eifs);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700652 rt2x00pci_register_write(rt2x00dev, MAC_CSR8, reg);
653
654 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
655 rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
656 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
657
658 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
659 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
660 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
661
662 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200663 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
664 libconf->conf->beacon_int * 16);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700665 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
666}
667
668static void rt61pci_config(struct rt2x00_dev *rt2x00dev,
669 const unsigned int flags,
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200670 struct rt2x00lib_conf *libconf)
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700671{
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700672 if (flags & CONFIG_UPDATE_PHYMODE)
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200673 rt61pci_config_phymode(rt2x00dev, libconf->basic_rates);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700674 if (flags & CONFIG_UPDATE_CHANNEL)
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200675 rt61pci_config_channel(rt2x00dev, &libconf->rf,
676 libconf->conf->power_level);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700677 if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200678 rt61pci_config_txpower(rt2x00dev, libconf->conf->power_level);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700679 if (flags & CONFIG_UPDATE_ANTENNA)
Ivo van Doornaddc81bd2007-10-13 16:26:23 +0200680 rt61pci_config_antenna(rt2x00dev, &libconf->ant);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700681 if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200682 rt61pci_config_duration(rt2x00dev, libconf);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700683}
684
685/*
686 * LED functions.
687 */
688static void rt61pci_enable_led(struct rt2x00_dev *rt2x00dev)
689{
690 u32 reg;
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700691 u8 arg0;
692 u8 arg1;
693
694 rt2x00pci_register_read(rt2x00dev, MAC_CSR14, &reg);
695 rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, 70);
696 rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, 30);
697 rt2x00pci_register_write(rt2x00dev, MAC_CSR14, reg);
698
Ivo van Doornddc827f2007-10-13 16:26:42 +0200699 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_RADIO_STATUS, 1);
700 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LINK_A_STATUS,
701 (rt2x00dev->rx_status.phymode == MODE_IEEE80211A));
702 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LINK_BG_STATUS,
703 (rt2x00dev->rx_status.phymode != MODE_IEEE80211A));
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700704
Ivo van Doornddc827f2007-10-13 16:26:42 +0200705 arg0 = rt2x00dev->led_reg & 0xff;
706 arg1 = (rt2x00dev->led_reg >> 8) & 0xff;
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700707
708 rt61pci_mcu_request(rt2x00dev, MCU_LED, 0xff, arg0, arg1);
709}
710
711static void rt61pci_disable_led(struct rt2x00_dev *rt2x00dev)
712{
713 u16 led_reg;
714 u8 arg0;
715 u8 arg1;
716
717 led_reg = rt2x00dev->led_reg;
718 rt2x00_set_field16(&led_reg, MCU_LEDCS_RADIO_STATUS, 0);
719 rt2x00_set_field16(&led_reg, MCU_LEDCS_LINK_BG_STATUS, 0);
720 rt2x00_set_field16(&led_reg, MCU_LEDCS_LINK_A_STATUS, 0);
721
722 arg0 = led_reg & 0xff;
723 arg1 = (led_reg >> 8) & 0xff;
724
725 rt61pci_mcu_request(rt2x00dev, MCU_LED, 0xff, arg0, arg1);
726}
727
728static void rt61pci_activity_led(struct rt2x00_dev *rt2x00dev, int rssi)
729{
730 u8 led;
731
732 if (rt2x00dev->led_mode != LED_MODE_SIGNAL_STRENGTH)
733 return;
734
735 /*
736 * Led handling requires a positive value for the rssi,
737 * to do that correctly we need to add the correction.
738 */
739 rssi += rt2x00dev->rssi_offset;
740
741 if (rssi <= 30)
742 led = 0;
743 else if (rssi <= 39)
744 led = 1;
745 else if (rssi <= 49)
746 led = 2;
747 else if (rssi <= 53)
748 led = 3;
749 else if (rssi <= 63)
750 led = 4;
751 else
752 led = 5;
753
754 rt61pci_mcu_request(rt2x00dev, MCU_LED_STRENGTH, 0xff, led, 0);
755}
756
757/*
758 * Link tuning
759 */
Ivo van Doornebcf26d2007-10-13 16:26:12 +0200760static void rt61pci_link_stats(struct rt2x00_dev *rt2x00dev,
761 struct link_qual *qual)
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700762{
763 u32 reg;
764
765 /*
766 * Update FCS error count from register.
767 */
768 rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
Ivo van Doornebcf26d2007-10-13 16:26:12 +0200769 qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700770
771 /*
772 * Update False CCA count from register.
773 */
774 rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
Ivo van Doornebcf26d2007-10-13 16:26:12 +0200775 qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700776}
777
778static void rt61pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
779{
780 rt61pci_bbp_write(rt2x00dev, 17, 0x20);
781 rt2x00dev->link.vgc_level = 0x20;
782}
783
784static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev)
785{
786 int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
787 u8 r17;
788 u8 up_bound;
789 u8 low_bound;
790
791 /*
792 * Update Led strength
793 */
794 rt61pci_activity_led(rt2x00dev, rssi);
795
796 rt61pci_bbp_read(rt2x00dev, 17, &r17);
797
798 /*
799 * Determine r17 bounds.
800 */
801 if (rt2x00dev->rx_status.phymode == MODE_IEEE80211A) {
802 low_bound = 0x28;
803 up_bound = 0x48;
804 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
805 low_bound += 0x10;
806 up_bound += 0x10;
807 }
808 } else {
809 low_bound = 0x20;
810 up_bound = 0x40;
811 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
812 low_bound += 0x10;
813 up_bound += 0x10;
814 }
815 }
816
817 /*
818 * Special big-R17 for very short distance
819 */
820 if (rssi >= -35) {
821 if (r17 != 0x60)
822 rt61pci_bbp_write(rt2x00dev, 17, 0x60);
823 return;
824 }
825
826 /*
827 * Special big-R17 for short distance
828 */
829 if (rssi >= -58) {
830 if (r17 != up_bound)
831 rt61pci_bbp_write(rt2x00dev, 17, up_bound);
832 return;
833 }
834
835 /*
836 * Special big-R17 for middle-short distance
837 */
838 if (rssi >= -66) {
839 low_bound += 0x10;
840 if (r17 != low_bound)
841 rt61pci_bbp_write(rt2x00dev, 17, low_bound);
842 return;
843 }
844
845 /*
846 * Special mid-R17 for middle distance
847 */
848 if (rssi >= -74) {
849 low_bound += 0x08;
850 if (r17 != low_bound)
851 rt61pci_bbp_write(rt2x00dev, 17, low_bound);
852 return;
853 }
854
855 /*
856 * Special case: Change up_bound based on the rssi.
857 * Lower up_bound when rssi is weaker then -74 dBm.
858 */
859 up_bound -= 2 * (-74 - rssi);
860 if (low_bound > up_bound)
861 up_bound = low_bound;
862
863 if (r17 > up_bound) {
864 rt61pci_bbp_write(rt2x00dev, 17, up_bound);
865 return;
866 }
867
868 /*
869 * r17 does not yet exceed upper limit, continue and base
870 * the r17 tuning on the false CCA count.
871 */
Ivo van Doornebcf26d2007-10-13 16:26:12 +0200872 if (rt2x00dev->link.qual.false_cca > 512 && r17 < up_bound) {
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700873 if (++r17 > up_bound)
874 r17 = up_bound;
875 rt61pci_bbp_write(rt2x00dev, 17, r17);
Ivo van Doornebcf26d2007-10-13 16:26:12 +0200876 } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > low_bound) {
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700877 if (--r17 < low_bound)
878 r17 = low_bound;
879 rt61pci_bbp_write(rt2x00dev, 17, r17);
880 }
881}
882
883/*
884 * Firmware name function.
885 */
886static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
887{
888 char *fw_name;
889
890 switch (rt2x00dev->chip.rt) {
891 case RT2561:
892 fw_name = FIRMWARE_RT2561;
893 break;
894 case RT2561s:
895 fw_name = FIRMWARE_RT2561s;
896 break;
897 case RT2661:
898 fw_name = FIRMWARE_RT2661;
899 break;
900 default:
901 fw_name = NULL;
902 break;
903 }
904
905 return fw_name;
906}
907
908/*
909 * Initialization functions.
910 */
911static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev, void *data,
912 const size_t len)
913{
914 int i;
915 u32 reg;
916
917 /*
918 * Wait for stable hardware.
919 */
920 for (i = 0; i < 100; i++) {
921 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
922 if (reg)
923 break;
924 msleep(1);
925 }
926
927 if (!reg) {
928 ERROR(rt2x00dev, "Unstable hardware.\n");
929 return -EBUSY;
930 }
931
932 /*
933 * Prepare MCU and mailbox for firmware loading.
934 */
935 reg = 0;
936 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
937 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
938 rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
939 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
940 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, 0);
941
942 /*
943 * Write firmware to device.
944 */
945 reg = 0;
946 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
947 rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 1);
948 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
949
950 rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
951 data, len);
952
953 rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 0);
954 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
955
956 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 0);
957 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
958
959 for (i = 0; i < 100; i++) {
960 rt2x00pci_register_read(rt2x00dev, MCU_CNTL_CSR, &reg);
961 if (rt2x00_get_field32(reg, MCU_CNTL_CSR_READY))
962 break;
963 msleep(1);
964 }
965
966 if (i == 100) {
967 ERROR(rt2x00dev, "MCU Control register not ready.\n");
968 return -EBUSY;
969 }
970
971 /*
972 * Reset MAC and BBP registers.
973 */
974 reg = 0;
975 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
976 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
977 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
978
979 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
980 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
981 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
982 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
983
984 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
985 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
986 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
987
988 return 0;
989}
990
991static void rt61pci_init_rxring(struct rt2x00_dev *rt2x00dev)
992{
993 struct data_ring *ring = rt2x00dev->rx;
Ivo van Doorn4bd7c452008-01-24 00:48:03 -0800994 __le32 *rxd;
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700995 unsigned int i;
996 u32 word;
997
998 memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
999
1000 for (i = 0; i < ring->stats.limit; i++) {
1001 rxd = ring->entry[i].priv;
1002
1003 rt2x00_desc_read(rxd, 5, &word);
1004 rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS,
1005 ring->entry[i].data_dma);
1006 rt2x00_desc_write(rxd, 5, word);
1007
1008 rt2x00_desc_read(rxd, 0, &word);
1009 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
1010 rt2x00_desc_write(rxd, 0, word);
1011 }
1012
1013 rt2x00_ring_index_clear(rt2x00dev->rx);
1014}
1015
1016static void rt61pci_init_txring(struct rt2x00_dev *rt2x00dev, const int queue)
1017{
1018 struct data_ring *ring = rt2x00lib_get_ring(rt2x00dev, queue);
Ivo van Doorn4bd7c452008-01-24 00:48:03 -08001019 __le32 *txd;
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001020 unsigned int i;
1021 u32 word;
1022
1023 memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
1024
1025 for (i = 0; i < ring->stats.limit; i++) {
1026 txd = ring->entry[i].priv;
1027
1028 rt2x00_desc_read(txd, 1, &word);
1029 rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1);
1030 rt2x00_desc_write(txd, 1, word);
1031
1032 rt2x00_desc_read(txd, 5, &word);
1033 rt2x00_set_field32(&word, TXD_W5_PID_TYPE, queue);
1034 rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE, i);
1035 rt2x00_desc_write(txd, 5, word);
1036
1037 rt2x00_desc_read(txd, 6, &word);
1038 rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS,
1039 ring->entry[i].data_dma);
1040 rt2x00_desc_write(txd, 6, word);
1041
1042 rt2x00_desc_read(txd, 0, &word);
1043 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1044 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
1045 rt2x00_desc_write(txd, 0, word);
1046 }
1047
1048 rt2x00_ring_index_clear(ring);
1049}
1050
1051static int rt61pci_init_rings(struct rt2x00_dev *rt2x00dev)
1052{
1053 u32 reg;
1054
1055 /*
1056 * Initialize rings.
1057 */
1058 rt61pci_init_rxring(rt2x00dev);
1059 rt61pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
1060 rt61pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
1061 rt61pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA2);
1062 rt61pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA3);
1063 rt61pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA4);
1064
1065 /*
1066 * Initialize registers.
1067 */
1068 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR0, &reg);
1069 rt2x00_set_field32(&reg, TX_RING_CSR0_AC0_RING_SIZE,
1070 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].stats.limit);
1071 rt2x00_set_field32(&reg, TX_RING_CSR0_AC1_RING_SIZE,
1072 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].stats.limit);
1073 rt2x00_set_field32(&reg, TX_RING_CSR0_AC2_RING_SIZE,
1074 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA2].stats.limit);
1075 rt2x00_set_field32(&reg, TX_RING_CSR0_AC3_RING_SIZE,
1076 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA3].stats.limit);
1077 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR0, reg);
1078
1079 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR1, &reg);
1080 rt2x00_set_field32(&reg, TX_RING_CSR1_MGMT_RING_SIZE,
1081 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA4].stats.limit);
1082 rt2x00_set_field32(&reg, TX_RING_CSR1_TXD_SIZE,
1083 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].desc_size /
1084 4);
1085 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR1, reg);
1086
1087 rt2x00pci_register_read(rt2x00dev, AC0_BASE_CSR, &reg);
1088 rt2x00_set_field32(&reg, AC0_BASE_CSR_RING_REGISTER,
1089 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].data_dma);
1090 rt2x00pci_register_write(rt2x00dev, AC0_BASE_CSR, reg);
1091
1092 rt2x00pci_register_read(rt2x00dev, AC1_BASE_CSR, &reg);
1093 rt2x00_set_field32(&reg, AC1_BASE_CSR_RING_REGISTER,
1094 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].data_dma);
1095 rt2x00pci_register_write(rt2x00dev, AC1_BASE_CSR, reg);
1096
1097 rt2x00pci_register_read(rt2x00dev, AC2_BASE_CSR, &reg);
1098 rt2x00_set_field32(&reg, AC2_BASE_CSR_RING_REGISTER,
1099 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA2].data_dma);
1100 rt2x00pci_register_write(rt2x00dev, AC2_BASE_CSR, reg);
1101
1102 rt2x00pci_register_read(rt2x00dev, AC3_BASE_CSR, &reg);
1103 rt2x00_set_field32(&reg, AC3_BASE_CSR_RING_REGISTER,
1104 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA3].data_dma);
1105 rt2x00pci_register_write(rt2x00dev, AC3_BASE_CSR, reg);
1106
1107 rt2x00pci_register_read(rt2x00dev, MGMT_BASE_CSR, &reg);
1108 rt2x00_set_field32(&reg, MGMT_BASE_CSR_RING_REGISTER,
1109 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA4].data_dma);
1110 rt2x00pci_register_write(rt2x00dev, MGMT_BASE_CSR, reg);
1111
1112 rt2x00pci_register_read(rt2x00dev, RX_RING_CSR, &reg);
1113 rt2x00_set_field32(&reg, RX_RING_CSR_RING_SIZE,
1114 rt2x00dev->rx->stats.limit);
1115 rt2x00_set_field32(&reg, RX_RING_CSR_RXD_SIZE,
1116 rt2x00dev->rx->desc_size / 4);
1117 rt2x00_set_field32(&reg, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4);
1118 rt2x00pci_register_write(rt2x00dev, RX_RING_CSR, reg);
1119
1120 rt2x00pci_register_read(rt2x00dev, RX_BASE_CSR, &reg);
1121 rt2x00_set_field32(&reg, RX_BASE_CSR_RING_REGISTER,
1122 rt2x00dev->rx->data_dma);
1123 rt2x00pci_register_write(rt2x00dev, RX_BASE_CSR, reg);
1124
1125 rt2x00pci_register_read(rt2x00dev, TX_DMA_DST_CSR, &reg);
1126 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC0, 2);
1127 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC1, 2);
1128 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC2, 2);
1129 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC3, 2);
1130 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_MGMT, 0);
1131 rt2x00pci_register_write(rt2x00dev, TX_DMA_DST_CSR, reg);
1132
1133 rt2x00pci_register_read(rt2x00dev, LOAD_TX_RING_CSR, &reg);
1134 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC0, 1);
1135 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1);
1136 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1);
1137 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1);
1138 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_MGMT, 1);
1139 rt2x00pci_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg);
1140
1141 rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1142 rt2x00_set_field32(&reg, RX_CNTL_CSR_LOAD_RXD, 1);
1143 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1144
1145 return 0;
1146}
1147
1148static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev)
1149{
1150 u32 reg;
1151
1152 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1153 rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
1154 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1155 rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
1156 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1157
1158 rt2x00pci_register_read(rt2x00dev, TXRX_CSR1, &reg);
1159 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1160 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
1161 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1162 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
1163 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1164 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
1165 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1166 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
1167 rt2x00pci_register_write(rt2x00dev, TXRX_CSR1, reg);
1168
1169 /*
1170 * CCK TXD BBP registers
1171 */
1172 rt2x00pci_register_read(rt2x00dev, TXRX_CSR2, &reg);
1173 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
1174 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
1175 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
1176 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
1177 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
1178 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
1179 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
1180 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
1181 rt2x00pci_register_write(rt2x00dev, TXRX_CSR2, reg);
1182
1183 /*
1184 * OFDM TXD BBP registers
1185 */
1186 rt2x00pci_register_read(rt2x00dev, TXRX_CSR3, &reg);
1187 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
1188 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
1189 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
1190 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
1191 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
1192 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
1193 rt2x00pci_register_write(rt2x00dev, TXRX_CSR3, reg);
1194
1195 rt2x00pci_register_read(rt2x00dev, TXRX_CSR7, &reg);
1196 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
1197 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
1198 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
1199 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
1200 rt2x00pci_register_write(rt2x00dev, TXRX_CSR7, reg);
1201
1202 rt2x00pci_register_read(rt2x00dev, TXRX_CSR8, &reg);
1203 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
1204 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
1205 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
1206 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
1207 rt2x00pci_register_write(rt2x00dev, TXRX_CSR8, reg);
1208
1209 rt2x00pci_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1210
1211 rt2x00pci_register_write(rt2x00dev, MAC_CSR6, 0x00000fff);
1212
1213 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
1214 rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1215 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
1216
1217 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x0000071c);
1218
1219 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1220 return -EBUSY;
1221
1222 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, 0x0000e000);
1223
1224 /*
1225 * Invalidate all Shared Keys (SEC_CSR0),
1226 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1227 */
1228 rt2x00pci_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1229 rt2x00pci_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1230 rt2x00pci_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1231
1232 rt2x00pci_register_write(rt2x00dev, PHY_CSR1, 0x000023b0);
1233 rt2x00pci_register_write(rt2x00dev, PHY_CSR5, 0x060a100c);
1234 rt2x00pci_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1235 rt2x00pci_register_write(rt2x00dev, PHY_CSR7, 0x00000a08);
1236
1237 rt2x00pci_register_write(rt2x00dev, PCI_CFG_CSR, 0x28ca4404);
1238
1239 rt2x00pci_register_write(rt2x00dev, TEST_MODE_CSR, 0x00000200);
1240
1241 rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1242
1243 rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR0, &reg);
1244 rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC0_TX_OP, 0);
1245 rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC1_TX_OP, 0);
1246 rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR0, reg);
1247
1248 rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR1, &reg);
1249 rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC2_TX_OP, 192);
1250 rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC3_TX_OP, 48);
1251 rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR1, reg);
1252
1253 /*
1254 * We must clear the error counters.
1255 * These registers are cleared on read,
1256 * so we may pass a useless variable to store the value.
1257 */
1258 rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
1259 rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
1260 rt2x00pci_register_read(rt2x00dev, STA_CSR2, &reg);
1261
1262 /*
1263 * Reset MAC and BBP registers.
1264 */
1265 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1266 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1267 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1268 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1269
1270 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1271 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1272 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1273 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1274
1275 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1276 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1277 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1278
1279 return 0;
1280}
1281
1282static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1283{
1284 unsigned int i;
1285 u16 eeprom;
1286 u8 reg_id;
1287 u8 value;
1288
1289 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1290 rt61pci_bbp_read(rt2x00dev, 0, &value);
1291 if ((value != 0xff) && (value != 0x00))
1292 goto continue_csr_init;
1293 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
1294 udelay(REGISTER_BUSY_DELAY);
1295 }
1296
1297 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1298 return -EACCES;
1299
1300continue_csr_init:
1301 rt61pci_bbp_write(rt2x00dev, 3, 0x00);
1302 rt61pci_bbp_write(rt2x00dev, 15, 0x30);
1303 rt61pci_bbp_write(rt2x00dev, 21, 0xc8);
1304 rt61pci_bbp_write(rt2x00dev, 22, 0x38);
1305 rt61pci_bbp_write(rt2x00dev, 23, 0x06);
1306 rt61pci_bbp_write(rt2x00dev, 24, 0xfe);
1307 rt61pci_bbp_write(rt2x00dev, 25, 0x0a);
1308 rt61pci_bbp_write(rt2x00dev, 26, 0x0d);
1309 rt61pci_bbp_write(rt2x00dev, 34, 0x12);
1310 rt61pci_bbp_write(rt2x00dev, 37, 0x07);
1311 rt61pci_bbp_write(rt2x00dev, 39, 0xf8);
1312 rt61pci_bbp_write(rt2x00dev, 41, 0x60);
1313 rt61pci_bbp_write(rt2x00dev, 53, 0x10);
1314 rt61pci_bbp_write(rt2x00dev, 54, 0x18);
1315 rt61pci_bbp_write(rt2x00dev, 60, 0x10);
1316 rt61pci_bbp_write(rt2x00dev, 61, 0x04);
1317 rt61pci_bbp_write(rt2x00dev, 62, 0x04);
1318 rt61pci_bbp_write(rt2x00dev, 75, 0xfe);
1319 rt61pci_bbp_write(rt2x00dev, 86, 0xfe);
1320 rt61pci_bbp_write(rt2x00dev, 88, 0xfe);
1321 rt61pci_bbp_write(rt2x00dev, 90, 0x0f);
1322 rt61pci_bbp_write(rt2x00dev, 99, 0x00);
1323 rt61pci_bbp_write(rt2x00dev, 102, 0x16);
1324 rt61pci_bbp_write(rt2x00dev, 107, 0x04);
1325
1326 DEBUG(rt2x00dev, "Start initialization from EEPROM...\n");
1327 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1328 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1329
1330 if (eeprom != 0xffff && eeprom != 0x0000) {
1331 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1332 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1333 DEBUG(rt2x00dev, "BBP: 0x%02x, value: 0x%02x.\n",
1334 reg_id, value);
1335 rt61pci_bbp_write(rt2x00dev, reg_id, value);
1336 }
1337 }
1338 DEBUG(rt2x00dev, "...End initialization from EEPROM.\n");
1339
1340 return 0;
1341}
1342
1343/*
1344 * Device state switch handlers.
1345 */
1346static void rt61pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1347 enum dev_state state)
1348{
1349 u32 reg;
1350
1351 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1352 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
1353 state == STATE_RADIO_RX_OFF);
1354 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1355}
1356
1357static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1358 enum dev_state state)
1359{
1360 int mask = (state == STATE_RADIO_IRQ_OFF);
1361 u32 reg;
1362
1363 /*
1364 * When interrupts are being enabled, the interrupt registers
1365 * should clear the register to assure a clean state.
1366 */
1367 if (state == STATE_RADIO_IRQ_ON) {
1368 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1369 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1370
1371 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg);
1372 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg);
1373 }
1374
1375 /*
1376 * Only toggle the interrupts bits we are going to use.
1377 * Non-checked interrupt bits are disabled by default.
1378 */
1379 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
1380 rt2x00_set_field32(&reg, INT_MASK_CSR_TXDONE, mask);
1381 rt2x00_set_field32(&reg, INT_MASK_CSR_RXDONE, mask);
1382 rt2x00_set_field32(&reg, INT_MASK_CSR_ENABLE_MITIGATION, mask);
1383 rt2x00_set_field32(&reg, INT_MASK_CSR_MITIGATION_PERIOD, 0xff);
1384 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
1385
1386 rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, &reg);
1387 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_0, mask);
1388 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_1, mask);
1389 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_2, mask);
1390 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_3, mask);
1391 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_4, mask);
1392 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_5, mask);
1393 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_6, mask);
1394 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_7, mask);
1395 rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
1396}
1397
1398static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1399{
1400 u32 reg;
1401
1402 /*
1403 * Initialize all registers.
1404 */
1405 if (rt61pci_init_rings(rt2x00dev) ||
1406 rt61pci_init_registers(rt2x00dev) ||
1407 rt61pci_init_bbp(rt2x00dev)) {
1408 ERROR(rt2x00dev, "Register initialization failed.\n");
1409 return -EIO;
1410 }
1411
1412 /*
1413 * Enable interrupts.
1414 */
1415 rt61pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
1416
1417 /*
1418 * Enable RX.
1419 */
1420 rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1421 rt2x00_set_field32(&reg, RX_CNTL_CSR_ENABLE_RX_DMA, 1);
1422 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1423
1424 /*
1425 * Enable LED
1426 */
1427 rt61pci_enable_led(rt2x00dev);
1428
1429 return 0;
1430}
1431
1432static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1433{
1434 u32 reg;
1435
1436 /*
1437 * Disable LED
1438 */
1439 rt61pci_disable_led(rt2x00dev);
1440
1441 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1442
1443 /*
1444 * Disable synchronisation.
1445 */
1446 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0);
1447
1448 /*
1449 * Cancel RX and TX.
1450 */
1451 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1452 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC0, 1);
1453 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC1, 1);
1454 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC2, 1);
1455 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC3, 1);
1456 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_MGMT, 1);
1457 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1458
1459 /*
1460 * Disable interrupts.
1461 */
1462 rt61pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
1463}
1464
1465static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1466{
1467 u32 reg;
1468 unsigned int i;
1469 char put_to_sleep;
1470 char current_state;
1471
1472 put_to_sleep = (state != STATE_AWAKE);
1473
1474 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
1475 rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1476 rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1477 rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg);
1478
1479 /*
1480 * Device is not guaranteed to be in the requested state yet.
1481 * We must wait until the register indicates that the
1482 * device has entered the correct state.
1483 */
1484 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1485 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
1486 current_state =
1487 rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1488 if (current_state == !put_to_sleep)
1489 return 0;
1490 msleep(10);
1491 }
1492
1493 NOTICE(rt2x00dev, "Device failed to enter state %d, "
1494 "current device state %d.\n", !put_to_sleep, current_state);
1495
1496 return -EBUSY;
1497}
1498
1499static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1500 enum dev_state state)
1501{
1502 int retval = 0;
1503
1504 switch (state) {
1505 case STATE_RADIO_ON:
1506 retval = rt61pci_enable_radio(rt2x00dev);
1507 break;
1508 case STATE_RADIO_OFF:
1509 rt61pci_disable_radio(rt2x00dev);
1510 break;
1511 case STATE_RADIO_RX_ON:
1512 case STATE_RADIO_RX_OFF:
1513 rt61pci_toggle_rx(rt2x00dev, state);
1514 break;
1515 case STATE_DEEP_SLEEP:
1516 case STATE_SLEEP:
1517 case STATE_STANDBY:
1518 case STATE_AWAKE:
1519 retval = rt61pci_set_state(rt2x00dev, state);
1520 break;
1521 default:
1522 retval = -ENOTSUPP;
1523 break;
1524 }
1525
1526 return retval;
1527}
1528
1529/*
1530 * TX descriptor initialization
1531 */
1532static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
Ivo van Doorn4bd7c452008-01-24 00:48:03 -08001533 __le32 *txd,
Johannes Berg4150c572007-09-17 01:29:23 -04001534 struct txdata_entry_desc *desc,
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001535 struct ieee80211_hdr *ieee80211hdr,
1536 unsigned int length,
1537 struct ieee80211_tx_control *control)
1538{
1539 u32 word;
1540
1541 /*
1542 * Start writing the descriptor words.
1543 */
1544 rt2x00_desc_read(txd, 1, &word);
1545 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, desc->queue);
1546 rt2x00_set_field32(&word, TXD_W1_AIFSN, desc->aifs);
1547 rt2x00_set_field32(&word, TXD_W1_CWMIN, desc->cw_min);
1548 rt2x00_set_field32(&word, TXD_W1_CWMAX, desc->cw_max);
1549 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, IEEE80211_HEADER);
1550 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE, 1);
1551 rt2x00_desc_write(txd, 1, word);
1552
1553 rt2x00_desc_read(txd, 2, &word);
1554 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, desc->signal);
1555 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, desc->service);
1556 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, desc->length_low);
1557 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, desc->length_high);
1558 rt2x00_desc_write(txd, 2, word);
1559
1560 rt2x00_desc_read(txd, 5, &word);
1561 rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1562 TXPOWER_TO_DEV(control->power_level));
1563 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1564 rt2x00_desc_write(txd, 5, word);
1565
1566 rt2x00_desc_read(txd, 11, &word);
1567 rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0, length);
1568 rt2x00_desc_write(txd, 11, word);
1569
1570 rt2x00_desc_read(txd, 0, &word);
1571 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1572 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1573 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1574 test_bit(ENTRY_TXD_MORE_FRAG, &desc->flags));
1575 rt2x00_set_field32(&word, TXD_W0_ACK,
Mattias Nissler2700f8b2007-10-27 13:43:49 +02001576 test_bit(ENTRY_TXD_ACK, &desc->flags));
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001577 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1578 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &desc->flags));
1579 rt2x00_set_field32(&word, TXD_W0_OFDM,
1580 test_bit(ENTRY_TXD_OFDM_RATE, &desc->flags));
1581 rt2x00_set_field32(&word, TXD_W0_IFS, desc->ifs);
1582 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1583 !!(control->flags &
1584 IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1585 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, 0);
1586 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, length);
1587 rt2x00_set_field32(&word, TXD_W0_BURST,
1588 test_bit(ENTRY_TXD_BURST, &desc->flags));
1589 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1590 rt2x00_desc_write(txd, 0, word);
1591}
1592
1593/*
1594 * TX data initialization
1595 */
1596static void rt61pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1597 unsigned int queue)
1598{
1599 u32 reg;
1600
1601 if (queue == IEEE80211_TX_QUEUE_BEACON) {
1602 /*
1603 * For Wi-Fi faily generated beacons between participating
1604 * stations. Set TBTT phase adaptive adjustment step to 8us.
1605 */
1606 rt2x00pci_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1607
1608 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1609 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
1610 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1611 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1612 }
1613 return;
1614 }
1615
1616 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
Ivo van Doornddc827f2007-10-13 16:26:42 +02001617 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC0,
1618 (queue == IEEE80211_TX_QUEUE_DATA0));
1619 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC1,
1620 (queue == IEEE80211_TX_QUEUE_DATA1));
1621 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC2,
1622 (queue == IEEE80211_TX_QUEUE_DATA2));
1623 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC3,
1624 (queue == IEEE80211_TX_QUEUE_DATA3));
1625 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_MGMT,
1626 (queue == IEEE80211_TX_QUEUE_DATA4));
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001627 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1628}
1629
1630/*
1631 * RX control handlers
1632 */
1633static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1634{
1635 u16 eeprom;
1636 u8 offset;
1637 u8 lna;
1638
1639 lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1640 switch (lna) {
1641 case 3:
1642 offset = 90;
1643 break;
1644 case 2:
1645 offset = 74;
1646 break;
1647 case 1:
1648 offset = 64;
1649 break;
1650 default:
1651 return 0;
1652 }
1653
1654 if (rt2x00dev->rx_status.phymode == MODE_IEEE80211A) {
1655 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
1656 offset += 14;
1657
1658 if (lna == 3 || lna == 2)
1659 offset += 10;
1660
1661 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
1662 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
1663 } else {
1664 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
1665 offset += 14;
1666
1667 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
1668 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
1669 }
1670
1671 return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1672}
1673
Johannes Berg4150c572007-09-17 01:29:23 -04001674static void rt61pci_fill_rxdone(struct data_entry *entry,
1675 struct rxdata_entry_desc *desc)
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001676{
Ivo van Doorn4bd7c452008-01-24 00:48:03 -08001677 __le32 *rxd = entry->priv;
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001678 u32 word0;
1679 u32 word1;
1680
1681 rt2x00_desc_read(rxd, 0, &word0);
1682 rt2x00_desc_read(rxd, 1, &word1);
1683
Johannes Berg4150c572007-09-17 01:29:23 -04001684 desc->flags = 0;
1685 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1686 desc->flags |= RX_FLAG_FAILED_FCS_CRC;
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001687
1688 /*
1689 * Obtain the status about this packet.
1690 */
Johannes Berg4150c572007-09-17 01:29:23 -04001691 desc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
1692 desc->rssi = rt61pci_agc_to_rssi(entry->ring->rt2x00dev, word1);
1693 desc->ofdm = rt2x00_get_field32(word0, RXD_W0_OFDM);
1694 desc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001695
Johannes Berg4150c572007-09-17 01:29:23 -04001696 return;
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001697}
1698
1699/*
1700 * Interrupt functions.
1701 */
1702static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
1703{
1704 struct data_ring *ring;
1705 struct data_entry *entry;
Mattias Nissler62bc0602007-11-12 15:03:12 +01001706 struct data_entry *entry_done;
Ivo van Doorn4bd7c452008-01-24 00:48:03 -08001707 __le32 *txd;
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001708 u32 word;
1709 u32 reg;
1710 u32 old_reg;
1711 int type;
1712 int index;
1713 int tx_status;
1714 int retry;
1715
1716 /*
1717 * During each loop we will compare the freshly read
1718 * STA_CSR4 register value with the value read from
1719 * the previous loop. If the 2 values are equal then
1720 * we should stop processing because the chance it
1721 * quite big that the device has been unplugged and
1722 * we risk going into an endless loop.
1723 */
1724 old_reg = 0;
1725
1726 while (1) {
1727 rt2x00pci_register_read(rt2x00dev, STA_CSR4, &reg);
1728 if (!rt2x00_get_field32(reg, STA_CSR4_VALID))
1729 break;
1730
1731 if (old_reg == reg)
1732 break;
1733 old_reg = reg;
1734
1735 /*
1736 * Skip this entry when it contains an invalid
1737 * ring identication number.
1738 */
1739 type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE);
1740 ring = rt2x00lib_get_ring(rt2x00dev, type);
1741 if (unlikely(!ring))
1742 continue;
1743
1744 /*
1745 * Skip this entry when it contains an invalid
1746 * index number.
1747 */
1748 index = rt2x00_get_field32(reg, STA_CSR4_PID_SUBTYPE);
1749 if (unlikely(index >= ring->stats.limit))
1750 continue;
1751
1752 entry = &ring->entry[index];
1753 txd = entry->priv;
1754 rt2x00_desc_read(txd, 0, &word);
1755
1756 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1757 !rt2x00_get_field32(word, TXD_W0_VALID))
1758 return;
1759
Mattias Nissler62bc0602007-11-12 15:03:12 +01001760 entry_done = rt2x00_get_data_entry_done(ring);
1761 while (entry != entry_done) {
1762 /* Catch up. Just report any entries we missed as
1763 * failed. */
1764 WARNING(rt2x00dev,
1765 "TX status report missed for entry %p\n",
1766 entry_done);
1767 rt2x00lib_txdone(entry_done, TX_FAIL_OTHER, 0);
1768 entry_done = rt2x00_get_data_entry_done(ring);
1769 }
1770
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001771 /*
1772 * Obtain the status about this packet.
1773 */
1774 tx_status = rt2x00_get_field32(reg, STA_CSR4_TX_RESULT);
1775 retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT);
1776
Ivo van Doorn3957ccb2007-11-12 15:02:40 +01001777 rt2x00pci_txdone(rt2x00dev, entry, tx_status, retry);
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001778 }
1779}
1780
1781static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance)
1782{
1783 struct rt2x00_dev *rt2x00dev = dev_instance;
1784 u32 reg_mcu;
1785 u32 reg;
1786
1787 /*
1788 * Get the interrupt sources & saved to local variable.
1789 * Write register value back to clear pending interrupts.
1790 */
1791 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg_mcu);
1792 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg_mcu);
1793
1794 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1795 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1796
1797 if (!reg && !reg_mcu)
1798 return IRQ_NONE;
1799
1800 if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1801 return IRQ_HANDLED;
1802
1803 /*
1804 * Handle interrupts, walk through all bits
1805 * and run the tasks, the bits are checked in order of
1806 * priority.
1807 */
1808
1809 /*
1810 * 1 - Rx ring done interrupt.
1811 */
1812 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RXDONE))
1813 rt2x00pci_rxdone(rt2x00dev);
1814
1815 /*
1816 * 2 - Tx ring done interrupt.
1817 */
1818 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TXDONE))
1819 rt61pci_txdone(rt2x00dev);
1820
1821 /*
1822 * 3 - Handle MCU command done.
1823 */
1824 if (reg_mcu)
1825 rt2x00pci_register_write(rt2x00dev,
1826 M2H_CMD_DONE_CSR, 0xffffffff);
1827
1828 return IRQ_HANDLED;
1829}
1830
1831/*
1832 * Device probe functions.
1833 */
1834static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1835{
1836 struct eeprom_93cx6 eeprom;
1837 u32 reg;
1838 u16 word;
1839 u8 *mac;
1840 s8 value;
1841
1842 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
1843
1844 eeprom.data = rt2x00dev;
1845 eeprom.register_read = rt61pci_eepromregister_read;
1846 eeprom.register_write = rt61pci_eepromregister_write;
1847 eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ?
1848 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1849 eeprom.reg_data_in = 0;
1850 eeprom.reg_data_out = 0;
1851 eeprom.reg_data_clock = 0;
1852 eeprom.reg_chip_select = 0;
1853
1854 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1855 EEPROM_SIZE / sizeof(u16));
1856
1857 /*
1858 * Start validation of the data that has been read.
1859 */
1860 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1861 if (!is_valid_ether_addr(mac)) {
Joe Perches0795af52007-10-03 17:59:30 -07001862 DECLARE_MAC_BUF(macbuf);
1863
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001864 random_ether_addr(mac);
Joe Perches0795af52007-10-03 17:59:30 -07001865 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001866 }
1867
1868 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1869 if (word == 0xffff) {
1870 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
Ivo van Doorn362f3b62007-10-13 16:26:18 +02001871 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1872 ANTENNA_B);
1873 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1874 ANTENNA_B);
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001875 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
1876 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1877 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1878 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5225);
1879 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1880 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1881 }
1882
1883 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1884 if (word == 0xffff) {
1885 rt2x00_set_field16(&word, EEPROM_NIC_ENABLE_DIVERSITY, 0);
1886 rt2x00_set_field16(&word, EEPROM_NIC_TX_DIVERSITY, 0);
1887 rt2x00_set_field16(&word, EEPROM_NIC_TX_RX_FIXED, 0);
1888 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
1889 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1890 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
1891 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1892 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1893 }
1894
1895 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
1896 if (word == 0xffff) {
1897 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
1898 LED_MODE_DEFAULT);
1899 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
1900 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
1901 }
1902
1903 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1904 if (word == 0xffff) {
1905 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1906 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
1907 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1908 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1909 }
1910
1911 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
1912 if (word == 0xffff) {
1913 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1914 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1915 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1916 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1917 } else {
1918 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
1919 if (value < -10 || value > 10)
1920 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1921 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
1922 if (value < -10 || value > 10)
1923 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1924 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1925 }
1926
1927 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
1928 if (word == 0xffff) {
1929 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1930 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1931 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1932 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1933 } else {
1934 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
1935 if (value < -10 || value > 10)
1936 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1937 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
1938 if (value < -10 || value > 10)
1939 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1940 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1941 }
1942
1943 return 0;
1944}
1945
1946static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1947{
1948 u32 reg;
1949 u16 value;
1950 u16 eeprom;
1951 u16 device;
1952
1953 /*
1954 * Read EEPROM word for configuration.
1955 */
1956 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1957
1958 /*
1959 * Identify RF chipset.
1960 * To determine the RT chip we have to read the
1961 * PCI header of the device.
1962 */
1963 pci_read_config_word(rt2x00dev_pci(rt2x00dev),
1964 PCI_CONFIG_HEADER_DEVICE, &device);
1965 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1966 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
1967 rt2x00_set_chip(rt2x00dev, device, value, reg);
1968
1969 if (!rt2x00_rf(&rt2x00dev->chip, RF5225) &&
1970 !rt2x00_rf(&rt2x00dev->chip, RF5325) &&
1971 !rt2x00_rf(&rt2x00dev->chip, RF2527) &&
1972 !rt2x00_rf(&rt2x00dev->chip, RF2529)) {
1973 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1974 return -ENODEV;
1975 }
1976
1977 /*
Ivo van Doorne4cd2ff2007-10-27 13:39:57 +02001978 * Determine number of antenna's.
1979 */
1980 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_NUM) == 2)
1981 __set_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags);
1982
1983 /*
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001984 * Identify default antenna configuration.
1985 */
Ivo van Doornaddc81bd2007-10-13 16:26:23 +02001986 rt2x00dev->default_ant.tx =
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001987 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
Ivo van Doornaddc81bd2007-10-13 16:26:23 +02001988 rt2x00dev->default_ant.rx =
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001989 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1990
1991 /*
1992 * Read the Frame type.
1993 */
1994 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
1995 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
1996
1997 /*
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001998 * Detect if this device has an hardware controlled radio.
1999 */
Ivo van Doorn81873e92007-10-06 14:14:06 +02002000#ifdef CONFIG_RT61PCI_RFKILL
Ivo van Doorn95ea3622007-09-25 17:57:13 -07002001 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
Ivo van Doorn066cb632007-09-25 20:55:39 +02002002 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
Ivo van Doorn81873e92007-10-06 14:14:06 +02002003#endif /* CONFIG_RT61PCI_RFKILL */
Ivo van Doorn95ea3622007-09-25 17:57:13 -07002004
2005 /*
2006 * Read frequency offset and RF programming sequence.
2007 */
2008 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2009 if (rt2x00_get_field16(eeprom, EEPROM_FREQ_SEQ))
2010 __set_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags);
2011
2012 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2013
2014 /*
2015 * Read external LNA informations.
2016 */
2017 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2018
2019 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2020 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2021 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2022 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2023
2024 /*
Ivo van Doorne4cd2ff2007-10-27 13:39:57 +02002025 * When working with a RF2529 chip without double antenna
2026 * the antenna settings should be gathered from the NIC
2027 * eeprom word.
2028 */
2029 if (rt2x00_rf(&rt2x00dev->chip, RF2529) &&
2030 !test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags)) {
2031 switch (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_RX_FIXED)) {
2032 case 0:
2033 rt2x00dev->default_ant.tx = ANTENNA_B;
2034 rt2x00dev->default_ant.rx = ANTENNA_A;
2035 break;
2036 case 1:
2037 rt2x00dev->default_ant.tx = ANTENNA_B;
2038 rt2x00dev->default_ant.rx = ANTENNA_B;
2039 break;
2040 case 2:
2041 rt2x00dev->default_ant.tx = ANTENNA_A;
2042 rt2x00dev->default_ant.rx = ANTENNA_A;
2043 break;
2044 case 3:
2045 rt2x00dev->default_ant.tx = ANTENNA_A;
2046 rt2x00dev->default_ant.rx = ANTENNA_B;
2047 break;
2048 }
2049
2050 if (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY))
2051 rt2x00dev->default_ant.tx = ANTENNA_SW_DIVERSITY;
2052 if (rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY))
2053 rt2x00dev->default_ant.rx = ANTENNA_SW_DIVERSITY;
2054 }
2055
2056 /*
Ivo van Doorn95ea3622007-09-25 17:57:13 -07002057 * Store led settings, for correct led behaviour.
2058 * If the eeprom value is invalid,
2059 * switch to default led mode.
2060 */
2061 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
2062
2063 rt2x00dev->led_mode = rt2x00_get_field16(eeprom, EEPROM_LED_LED_MODE);
2064
2065 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LED_MODE,
2066 rt2x00dev->led_mode);
2067 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_0,
2068 rt2x00_get_field16(eeprom,
2069 EEPROM_LED_POLARITY_GPIO_0));
2070 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_1,
2071 rt2x00_get_field16(eeprom,
2072 EEPROM_LED_POLARITY_GPIO_1));
2073 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_2,
2074 rt2x00_get_field16(eeprom,
2075 EEPROM_LED_POLARITY_GPIO_2));
2076 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_3,
2077 rt2x00_get_field16(eeprom,
2078 EEPROM_LED_POLARITY_GPIO_3));
2079 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_4,
2080 rt2x00_get_field16(eeprom,
2081 EEPROM_LED_POLARITY_GPIO_4));
2082 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_ACT,
2083 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
2084 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_READY_BG,
2085 rt2x00_get_field16(eeprom,
2086 EEPROM_LED_POLARITY_RDY_G));
2087 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_READY_A,
2088 rt2x00_get_field16(eeprom,
2089 EEPROM_LED_POLARITY_RDY_A));
2090
2091 return 0;
2092}
2093
2094/*
2095 * RF value list for RF5225 & RF5325
2096 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence disabled
2097 */
2098static const struct rf_channel rf_vals_noseq[] = {
2099 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2100 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2101 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2102 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2103 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2104 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2105 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2106 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2107 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2108 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2109 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2110 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2111 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2112 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2113
2114 /* 802.11 UNI / HyperLan 2 */
2115 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2116 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2117 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2118 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2119 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2120 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2121 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2122 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2123
2124 /* 802.11 HyperLan 2 */
2125 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2126 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2127 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2128 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2129 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2130 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2131 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2132 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2133 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2134 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2135
2136 /* 802.11 UNII */
2137 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2138 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2139 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2140 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2141 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2142 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2143
2144 /* MMAC(Japan)J52 ch 34,38,42,46 */
2145 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2146 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2147 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2148 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2149};
2150
2151/*
2152 * RF value list for RF5225 & RF5325
2153 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence enabled
2154 */
2155static const struct rf_channel rf_vals_seq[] = {
2156 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2157 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2158 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2159 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2160 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2161 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2162 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2163 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2164 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2165 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2166 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2167 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2168 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2169 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2170
2171 /* 802.11 UNI / HyperLan 2 */
2172 { 36, 0x00002cd4, 0x0004481a, 0x00098455, 0x000c0a03 },
2173 { 40, 0x00002cd0, 0x00044682, 0x00098455, 0x000c0a03 },
2174 { 44, 0x00002cd0, 0x00044686, 0x00098455, 0x000c0a1b },
2175 { 48, 0x00002cd0, 0x0004468e, 0x00098655, 0x000c0a0b },
2176 { 52, 0x00002cd0, 0x00044692, 0x00098855, 0x000c0a23 },
2177 { 56, 0x00002cd0, 0x0004469a, 0x00098c55, 0x000c0a13 },
2178 { 60, 0x00002cd0, 0x000446a2, 0x00098e55, 0x000c0a03 },
2179 { 64, 0x00002cd0, 0x000446a6, 0x00099255, 0x000c0a1b },
2180
2181 /* 802.11 HyperLan 2 */
2182 { 100, 0x00002cd4, 0x0004489a, 0x000b9855, 0x000c0a03 },
2183 { 104, 0x00002cd4, 0x000448a2, 0x000b9855, 0x000c0a03 },
2184 { 108, 0x00002cd4, 0x000448aa, 0x000b9855, 0x000c0a03 },
2185 { 112, 0x00002cd4, 0x000448b2, 0x000b9a55, 0x000c0a03 },
2186 { 116, 0x00002cd4, 0x000448ba, 0x000b9a55, 0x000c0a03 },
2187 { 120, 0x00002cd0, 0x00044702, 0x000b9a55, 0x000c0a03 },
2188 { 124, 0x00002cd0, 0x00044706, 0x000b9a55, 0x000c0a1b },
2189 { 128, 0x00002cd0, 0x0004470e, 0x000b9c55, 0x000c0a0b },
2190 { 132, 0x00002cd0, 0x00044712, 0x000b9c55, 0x000c0a23 },
2191 { 136, 0x00002cd0, 0x0004471a, 0x000b9e55, 0x000c0a13 },
2192
2193 /* 802.11 UNII */
2194 { 140, 0x00002cd0, 0x00044722, 0x000b9e55, 0x000c0a03 },
2195 { 149, 0x00002cd0, 0x0004472e, 0x000ba255, 0x000c0a1b },
2196 { 153, 0x00002cd0, 0x00044736, 0x000ba255, 0x000c0a0b },
2197 { 157, 0x00002cd4, 0x0004490a, 0x000ba255, 0x000c0a17 },
2198 { 161, 0x00002cd4, 0x00044912, 0x000ba255, 0x000c0a17 },
2199 { 165, 0x00002cd4, 0x0004491a, 0x000ba255, 0x000c0a17 },
2200
2201 /* MMAC(Japan)J52 ch 34,38,42,46 */
2202 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000c0a0b },
2203 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000c0a13 },
2204 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000c0a1b },
2205 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000c0a23 },
2206};
2207
2208static void rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2209{
2210 struct hw_mode_spec *spec = &rt2x00dev->spec;
2211 u8 *txpower;
2212 unsigned int i;
2213
2214 /*
2215 * Initialize all hw fields.
2216 */
2217 rt2x00dev->hw->flags =
2218 IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
Johannes Berg4150c572007-09-17 01:29:23 -04002219 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
Ivo van Doorn95ea3622007-09-25 17:57:13 -07002220 rt2x00dev->hw->extra_tx_headroom = 0;
2221 rt2x00dev->hw->max_signal = MAX_SIGNAL;
2222 rt2x00dev->hw->max_rssi = MAX_RX_SSI;
2223 rt2x00dev->hw->queues = 5;
2224
2225 SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
2226 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2227 rt2x00_eeprom_addr(rt2x00dev,
2228 EEPROM_MAC_ADDR_0));
2229
2230 /*
2231 * Convert tx_power array in eeprom.
2232 */
2233 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2234 for (i = 0; i < 14; i++)
2235 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
2236
2237 /*
2238 * Initialize hw_mode information.
2239 */
2240 spec->num_modes = 2;
2241 spec->num_rates = 12;
2242 spec->tx_power_a = NULL;
2243 spec->tx_power_bg = txpower;
2244 spec->tx_power_default = DEFAULT_TXPOWER;
2245
2246 if (!test_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags)) {
2247 spec->num_channels = 14;
2248 spec->channels = rf_vals_noseq;
2249 } else {
2250 spec->num_channels = 14;
2251 spec->channels = rf_vals_seq;
2252 }
2253
2254 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
2255 rt2x00_rf(&rt2x00dev->chip, RF5325)) {
2256 spec->num_modes = 3;
2257 spec->num_channels = ARRAY_SIZE(rf_vals_seq);
2258
2259 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2260 for (i = 0; i < 14; i++)
2261 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
2262
2263 spec->tx_power_a = txpower;
2264 }
2265}
2266
2267static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2268{
2269 int retval;
2270
2271 /*
2272 * Allocate eeprom data.
2273 */
2274 retval = rt61pci_validate_eeprom(rt2x00dev);
2275 if (retval)
2276 return retval;
2277
2278 retval = rt61pci_init_eeprom(rt2x00dev);
2279 if (retval)
2280 return retval;
2281
2282 /*
2283 * Initialize hw specifications.
2284 */
2285 rt61pci_probe_hw_mode(rt2x00dev);
2286
2287 /*
2288 * This device requires firmware
2289 */
Ivo van Doorn066cb632007-09-25 20:55:39 +02002290 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
Ivo van Doorn95ea3622007-09-25 17:57:13 -07002291
2292 /*
2293 * Set the rssi offset.
2294 */
2295 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2296
2297 return 0;
2298}
2299
2300/*
2301 * IEEE80211 stack callback functions.
2302 */
Johannes Berg4150c572007-09-17 01:29:23 -04002303static void rt61pci_configure_filter(struct ieee80211_hw *hw,
2304 unsigned int changed_flags,
2305 unsigned int *total_flags,
2306 int mc_count,
2307 struct dev_addr_list *mc_list)
2308{
2309 struct rt2x00_dev *rt2x00dev = hw->priv;
2310 struct interface *intf = &rt2x00dev->interface;
2311 u32 reg;
2312
2313 /*
2314 * Mask off any flags we are going to ignore from
2315 * the total_flags field.
2316 */
2317 *total_flags &=
2318 FIF_ALLMULTI |
2319 FIF_FCSFAIL |
2320 FIF_PLCPFAIL |
2321 FIF_CONTROL |
2322 FIF_OTHER_BSS |
2323 FIF_PROMISC_IN_BSS;
2324
2325 /*
2326 * Apply some rules to the filters:
2327 * - Some filters imply different filters to be set.
2328 * - Some things we can't filter out at all.
2329 * - Some filters are set based on interface type.
2330 */
2331 if (mc_count)
2332 *total_flags |= FIF_ALLMULTI;
Ivo van Doorn5886d0d2007-10-06 14:13:38 +02002333 if (*total_flags & FIF_OTHER_BSS ||
2334 *total_flags & FIF_PROMISC_IN_BSS)
Johannes Berg4150c572007-09-17 01:29:23 -04002335 *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
2336 if (is_interface_type(intf, IEEE80211_IF_TYPE_AP))
2337 *total_flags |= FIF_PROMISC_IN_BSS;
2338
2339 /*
2340 * Check if there is any work left for us.
2341 */
2342 if (intf->filter == *total_flags)
2343 return;
2344 intf->filter = *total_flags;
2345
2346 /*
2347 * Start configuration steps.
2348 * Note that the version error will always be dropped
2349 * and broadcast frames will always be accepted since
2350 * there is no filter for it at this time.
2351 */
2352 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
2353 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
2354 !(*total_flags & FIF_FCSFAIL));
2355 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
2356 !(*total_flags & FIF_PLCPFAIL));
2357 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
2358 !(*total_flags & FIF_CONTROL));
2359 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
2360 !(*total_flags & FIF_PROMISC_IN_BSS));
2361 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
2362 !(*total_flags & FIF_PROMISC_IN_BSS));
2363 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
2364 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
2365 !(*total_flags & FIF_ALLMULTI));
2366 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BORADCAST, 0);
2367 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS, 1);
2368 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
2369}
2370
Ivo van Doorn95ea3622007-09-25 17:57:13 -07002371static int rt61pci_set_retry_limit(struct ieee80211_hw *hw,
2372 u32 short_retry, u32 long_retry)
2373{
2374 struct rt2x00_dev *rt2x00dev = hw->priv;
2375 u32 reg;
2376
2377 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
2378 rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT, long_retry);
2379 rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT, short_retry);
2380 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
2381
2382 return 0;
2383}
2384
2385static u64 rt61pci_get_tsf(struct ieee80211_hw *hw)
2386{
2387 struct rt2x00_dev *rt2x00dev = hw->priv;
2388 u64 tsf;
2389 u32 reg;
2390
2391 rt2x00pci_register_read(rt2x00dev, TXRX_CSR13, &reg);
2392 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
2393 rt2x00pci_register_read(rt2x00dev, TXRX_CSR12, &reg);
2394 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2395
2396 return tsf;
2397}
2398
2399static void rt61pci_reset_tsf(struct ieee80211_hw *hw)
2400{
2401 struct rt2x00_dev *rt2x00dev = hw->priv;
2402
2403 rt2x00pci_register_write(rt2x00dev, TXRX_CSR12, 0);
2404 rt2x00pci_register_write(rt2x00dev, TXRX_CSR13, 0);
2405}
2406
Ivo van Doorn24845912007-09-25 20:53:43 +02002407static int rt61pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
Ivo van Doorn95ea3622007-09-25 17:57:13 -07002408 struct ieee80211_tx_control *control)
2409{
2410 struct rt2x00_dev *rt2x00dev = hw->priv;
Ivo van Doorn08992f72008-01-24 01:56:25 -08002411 struct skb_desc *desc;
2412 struct data_ring *ring;
2413 struct data_entry *entry;
Ivo van Doorn95ea3622007-09-25 17:57:13 -07002414
2415 /*
2416 * Just in case the ieee80211 doesn't set this,
2417 * but we need this queue set for the descriptor
2418 * initialization.
2419 */
2420 control->queue = IEEE80211_TX_QUEUE_BEACON;
Ivo van Doorn08992f72008-01-24 01:56:25 -08002421 ring = rt2x00lib_get_ring(rt2x00dev, control->queue);
2422 entry = rt2x00_get_data_entry(ring);
Ivo van Doorn95ea3622007-09-25 17:57:13 -07002423
2424 /*
2425 * We need to append the descriptor in front of the
2426 * beacon frame.
2427 */
2428 if (skb_headroom(skb) < TXD_DESC_SIZE) {
2429 if (pskb_expand_head(skb, TXD_DESC_SIZE, 0, GFP_ATOMIC)) {
2430 dev_kfree_skb(skb);
2431 return -ENOMEM;
2432 }
2433 }
2434
2435 /*
Ivo van Doorn08992f72008-01-24 01:56:25 -08002436 * Add the descriptor in front of the skb.
Ivo van Doorn95ea3622007-09-25 17:57:13 -07002437 */
Ivo van Doorn08992f72008-01-24 01:56:25 -08002438 skb_push(skb, ring->desc_size);
2439 memset(skb->data, 0, ring->desc_size);
Ivo van Doornc22eb872007-10-06 14:18:22 +02002440
Ivo van Doorn08992f72008-01-24 01:56:25 -08002441 /*
2442 * Fill in skb descriptor
2443 */
2444 desc = get_skb_desc(skb);
2445 desc->desc_len = ring->desc_size;
2446 desc->data_len = skb->len - ring->desc_size;
2447 desc->desc = skb->data;
2448 desc->data = skb->data + ring->desc_size;
2449 desc->ring = ring;
2450 desc->entry = entry;
2451
2452 rt2x00lib_write_tx_desc(rt2x00dev, skb, control);
Ivo van Doorn95ea3622007-09-25 17:57:13 -07002453
2454 /*
2455 * Write entire beacon with descriptor to register,
2456 * and kick the beacon generator.
2457 */
Ivo van Doorn9ee8f572007-10-06 14:15:20 +02002458 rt2x00pci_register_multiwrite(rt2x00dev, HW_BEACON_BASE0,
2459 skb->data, skb->len);
Ivo van Doorn95ea3622007-09-25 17:57:13 -07002460 rt61pci_kick_tx_queue(rt2x00dev, IEEE80211_TX_QUEUE_BEACON);
2461
2462 return 0;
2463}
2464
2465static const struct ieee80211_ops rt61pci_mac80211_ops = {
2466 .tx = rt2x00mac_tx,
Johannes Berg4150c572007-09-17 01:29:23 -04002467 .start = rt2x00mac_start,
2468 .stop = rt2x00mac_stop,
Ivo van Doorn95ea3622007-09-25 17:57:13 -07002469 .add_interface = rt2x00mac_add_interface,
2470 .remove_interface = rt2x00mac_remove_interface,
2471 .config = rt2x00mac_config,
2472 .config_interface = rt2x00mac_config_interface,
Johannes Berg4150c572007-09-17 01:29:23 -04002473 .configure_filter = rt61pci_configure_filter,
Ivo van Doorn95ea3622007-09-25 17:57:13 -07002474 .get_stats = rt2x00mac_get_stats,
2475 .set_retry_limit = rt61pci_set_retry_limit,
Ivo van Doorn5c58ee52007-10-06 13:34:52 +02002476 .erp_ie_changed = rt2x00mac_erp_ie_changed,
Ivo van Doorn95ea3622007-09-25 17:57:13 -07002477 .conf_tx = rt2x00mac_conf_tx,
2478 .get_tx_stats = rt2x00mac_get_tx_stats,
2479 .get_tsf = rt61pci_get_tsf,
2480 .reset_tsf = rt61pci_reset_tsf,
2481 .beacon_update = rt61pci_beacon_update,
2482};
2483
2484static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
2485 .irq_handler = rt61pci_interrupt,
2486 .probe_hw = rt61pci_probe_hw,
2487 .get_firmware_name = rt61pci_get_firmware_name,
2488 .load_firmware = rt61pci_load_firmware,
2489 .initialize = rt2x00pci_initialize,
2490 .uninitialize = rt2x00pci_uninitialize,
2491 .set_device_state = rt61pci_set_device_state,
Ivo van Doorn95ea3622007-09-25 17:57:13 -07002492 .rfkill_poll = rt61pci_rfkill_poll,
Ivo van Doorn95ea3622007-09-25 17:57:13 -07002493 .link_stats = rt61pci_link_stats,
2494 .reset_tuner = rt61pci_reset_tuner,
2495 .link_tuner = rt61pci_link_tuner,
2496 .write_tx_desc = rt61pci_write_tx_desc,
2497 .write_tx_data = rt2x00pci_write_tx_data,
2498 .kick_tx_queue = rt61pci_kick_tx_queue,
2499 .fill_rxdone = rt61pci_fill_rxdone,
2500 .config_mac_addr = rt61pci_config_mac_addr,
2501 .config_bssid = rt61pci_config_bssid,
Ivo van Doorn95ea3622007-09-25 17:57:13 -07002502 .config_type = rt61pci_config_type,
Ivo van Doorn5c58ee52007-10-06 13:34:52 +02002503 .config_preamble = rt61pci_config_preamble,
Ivo van Doorn95ea3622007-09-25 17:57:13 -07002504 .config = rt61pci_config,
2505};
2506
2507static const struct rt2x00_ops rt61pci_ops = {
Ivo van Doorn23601572007-11-27 21:47:34 +01002508 .name = KBUILD_MODNAME,
Ivo van Doorn95ea3622007-09-25 17:57:13 -07002509 .rxd_size = RXD_DESC_SIZE,
2510 .txd_size = TXD_DESC_SIZE,
2511 .eeprom_size = EEPROM_SIZE,
2512 .rf_size = RF_SIZE,
2513 .lib = &rt61pci_rt2x00_ops,
2514 .hw = &rt61pci_mac80211_ops,
2515#ifdef CONFIG_RT2X00_LIB_DEBUGFS
2516 .debugfs = &rt61pci_rt2x00debug,
2517#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2518};
2519
2520/*
2521 * RT61pci module information.
2522 */
2523static struct pci_device_id rt61pci_device_table[] = {
2524 /* RT2561s */
2525 { PCI_DEVICE(0x1814, 0x0301), PCI_DEVICE_DATA(&rt61pci_ops) },
2526 /* RT2561 v2 */
2527 { PCI_DEVICE(0x1814, 0x0302), PCI_DEVICE_DATA(&rt61pci_ops) },
2528 /* RT2661 */
2529 { PCI_DEVICE(0x1814, 0x0401), PCI_DEVICE_DATA(&rt61pci_ops) },
2530 { 0, }
2531};
2532
2533MODULE_AUTHOR(DRV_PROJECT);
2534MODULE_VERSION(DRV_VERSION);
2535MODULE_DESCRIPTION("Ralink RT61 PCI & PCMCIA Wireless LAN driver.");
2536MODULE_SUPPORTED_DEVICE("Ralink RT2561, RT2561s & RT2661 "
2537 "PCI & PCMCIA chipset based cards");
2538MODULE_DEVICE_TABLE(pci, rt61pci_device_table);
2539MODULE_FIRMWARE(FIRMWARE_RT2561);
2540MODULE_FIRMWARE(FIRMWARE_RT2561s);
2541MODULE_FIRMWARE(FIRMWARE_RT2661);
2542MODULE_LICENSE("GPL");
2543
2544static struct pci_driver rt61pci_driver = {
Ivo van Doorn23601572007-11-27 21:47:34 +01002545 .name = KBUILD_MODNAME,
Ivo van Doorn95ea3622007-09-25 17:57:13 -07002546 .id_table = rt61pci_device_table,
2547 .probe = rt2x00pci_probe,
2548 .remove = __devexit_p(rt2x00pci_remove),
2549 .suspend = rt2x00pci_suspend,
2550 .resume = rt2x00pci_resume,
2551};
2552
2553static int __init rt61pci_init(void)
2554{
2555 return pci_register_driver(&rt61pci_driver);
2556}
2557
2558static void __exit rt61pci_exit(void)
2559{
2560 pci_unregister_driver(&rt61pci_driver);
2561}
2562
2563module_init(rt61pci_init);
2564module_exit(rt61pci_exit);