Dinh Nguyen | eede211 | 2013-06-12 10:18:51 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Altera SoCFPGA Specific Extensions for Synopsys DW Multimedia Card Interface |
| 3 | * driver |
| 4 | * |
| 5 | * Copyright (C) 2012, Samsung Electronics Co., Ltd. |
| 6 | * Copyright (C) 2013 Altera Corporation |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; either version 2 of the License, or |
| 11 | * (at your option) any later version. |
| 12 | * |
| 13 | * Taken from dw_mmc-exynos.c |
| 14 | */ |
| 15 | #include <linux/clk.h> |
| 16 | #include <linux/mfd/syscon.h> |
| 17 | #include <linux/mmc/host.h> |
| 18 | #include <linux/mmc/dw_mmc.h> |
| 19 | #include <linux/module.h> |
| 20 | #include <linux/of.h> |
| 21 | #include <linux/platform_device.h> |
| 22 | #include <linux/regmap.h> |
| 23 | |
| 24 | #include "dw_mmc.h" |
| 25 | #include "dw_mmc-pltfm.h" |
| 26 | |
| 27 | #define SYSMGR_SDMMCGRP_CTRL_OFFSET 0x108 |
| 28 | #define DRV_CLK_PHASE_SHIFT_SEL_MASK 0x7 |
| 29 | #define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \ |
| 30 | ((((smplsel) & 0x7) << 3) | (((drvsel) & 0x7) << 0)) |
| 31 | |
| 32 | /* SOCFPGA implementation specific driver private data */ |
| 33 | struct dw_mci_socfpga_priv_data { |
| 34 | u8 ciu_div; /* card interface unit divisor */ |
| 35 | u32 hs_timing; /* bitmask for CIU clock phase shift */ |
| 36 | struct regmap *sysreg; /* regmap for system manager register */ |
| 37 | }; |
| 38 | |
| 39 | static int dw_mci_socfpga_priv_init(struct dw_mci *host) |
| 40 | { |
Dinh Nguyen | eede211 | 2013-06-12 10:18:51 -0500 | [diff] [blame] | 41 | return 0; |
| 42 | } |
| 43 | |
| 44 | static int dw_mci_socfpga_setup_clock(struct dw_mci *host) |
| 45 | { |
| 46 | struct dw_mci_socfpga_priv_data *priv = host->priv; |
| 47 | |
| 48 | clk_disable_unprepare(host->ciu_clk); |
| 49 | regmap_write(priv->sysreg, SYSMGR_SDMMCGRP_CTRL_OFFSET, |
| 50 | priv->hs_timing); |
| 51 | clk_prepare_enable(host->ciu_clk); |
| 52 | |
| 53 | host->bus_hz /= (priv->ciu_div + 1); |
| 54 | return 0; |
| 55 | } |
| 56 | |
| 57 | static void dw_mci_socfpga_prepare_command(struct dw_mci *host, u32 *cmdr) |
| 58 | { |
| 59 | struct dw_mci_socfpga_priv_data *priv = host->priv; |
| 60 | |
| 61 | if (priv->hs_timing & DRV_CLK_PHASE_SHIFT_SEL_MASK) |
| 62 | *cmdr |= SDMMC_CMD_USE_HOLD_REG; |
| 63 | } |
| 64 | |
| 65 | static int dw_mci_socfpga_parse_dt(struct dw_mci *host) |
| 66 | { |
Yuvaraj Kumar C D | 3aa741f | 2013-08-31 00:12:10 +0900 | [diff] [blame] | 67 | struct dw_mci_socfpga_priv_data *priv; |
Dinh Nguyen | eede211 | 2013-06-12 10:18:51 -0500 | [diff] [blame] | 68 | struct device_node *np = host->dev->of_node; |
| 69 | u32 timing[2]; |
| 70 | u32 div = 0; |
| 71 | int ret; |
| 72 | |
Yuvaraj Kumar C D | 3aa741f | 2013-08-31 00:12:10 +0900 | [diff] [blame] | 73 | priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL); |
| 74 | if (!priv) { |
| 75 | dev_err(host->dev, "mem alloc failed for private data\n"); |
| 76 | return -ENOMEM; |
| 77 | } |
| 78 | |
| 79 | priv->sysreg = syscon_regmap_lookup_by_compatible("altr,sys-mgr"); |
| 80 | if (IS_ERR(priv->sysreg)) { |
| 81 | dev_err(host->dev, "regmap for altr,sys-mgr lookup failed.\n"); |
| 82 | return PTR_ERR(priv->sysreg); |
| 83 | } |
| 84 | |
Dinh Nguyen | eede211 | 2013-06-12 10:18:51 -0500 | [diff] [blame] | 85 | ret = of_property_read_u32(np, "altr,dw-mshc-ciu-div", &div); |
| 86 | if (ret) |
| 87 | dev_info(host->dev, "No dw-mshc-ciu-div specified, assuming 1"); |
| 88 | priv->ciu_div = div; |
| 89 | |
| 90 | ret = of_property_read_u32_array(np, |
| 91 | "altr,dw-mshc-sdr-timing", timing, 2); |
| 92 | if (ret) |
| 93 | return ret; |
| 94 | |
| 95 | priv->hs_timing = SYSMGR_SDMMC_CTRL_SET(timing[0], timing[1]); |
Yuvaraj Kumar C D | 3aa741f | 2013-08-31 00:12:10 +0900 | [diff] [blame] | 96 | host->priv = priv; |
Dinh Nguyen | eede211 | 2013-06-12 10:18:51 -0500 | [diff] [blame] | 97 | return 0; |
| 98 | } |
| 99 | |
| 100 | static const struct dw_mci_drv_data socfpga_drv_data = { |
| 101 | .init = dw_mci_socfpga_priv_init, |
| 102 | .setup_clock = dw_mci_socfpga_setup_clock, |
| 103 | .prepare_command = dw_mci_socfpga_prepare_command, |
| 104 | .parse_dt = dw_mci_socfpga_parse_dt, |
| 105 | }; |
| 106 | |
| 107 | static const struct of_device_id dw_mci_socfpga_match[] = { |
| 108 | { .compatible = "altr,socfpga-dw-mshc", |
| 109 | .data = &socfpga_drv_data, }, |
| 110 | {}, |
| 111 | }; |
| 112 | MODULE_DEVICE_TABLE(of, dw_mci_socfpga_match); |
| 113 | |
Sachin Kamat | 08de89b | 2013-09-12 12:16:36 +0530 | [diff] [blame^] | 114 | static int dw_mci_socfpga_probe(struct platform_device *pdev) |
Dinh Nguyen | eede211 | 2013-06-12 10:18:51 -0500 | [diff] [blame] | 115 | { |
| 116 | const struct dw_mci_drv_data *drv_data; |
| 117 | const struct of_device_id *match; |
| 118 | |
| 119 | match = of_match_node(dw_mci_socfpga_match, pdev->dev.of_node); |
| 120 | drv_data = match->data; |
| 121 | return dw_mci_pltfm_register(pdev, drv_data); |
| 122 | } |
| 123 | |
| 124 | static struct platform_driver dw_mci_socfpga_pltfm_driver = { |
| 125 | .probe = dw_mci_socfpga_probe, |
| 126 | .remove = __exit_p(dw_mci_pltfm_remove), |
| 127 | .driver = { |
| 128 | .name = "dwmmc_socfpga", |
Sachin Kamat | 21f67c2 | 2013-09-12 12:16:35 +0530 | [diff] [blame] | 129 | .of_match_table = dw_mci_socfpga_match, |
Dinh Nguyen | eede211 | 2013-06-12 10:18:51 -0500 | [diff] [blame] | 130 | .pm = &dw_mci_pltfm_pmops, |
| 131 | }, |
| 132 | }; |
| 133 | |
| 134 | module_platform_driver(dw_mci_socfpga_pltfm_driver); |
| 135 | |
| 136 | MODULE_DESCRIPTION("Altera SOCFPGA Specific DW-MSHC Driver Extension"); |
| 137 | MODULE_LICENSE("GPL v2"); |
| 138 | MODULE_ALIAS("platform:dwmmc-socfpga"); |