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Kim Phillips728de4c92007-04-13 01:26:03 -05001/*
2 * drivers/net/ucc_geth_mii.c
3 *
Kim Phillips4e19b5c2007-05-11 18:25:07 -05004 * QE UCC Gigabit Ethernet Driver -- MII Management Bus Implementation
5 * Provides Bus interface for MII Management regs in the UCC register space
Kim Phillips728de4c92007-04-13 01:26:03 -05006 *
Kim Phillips4e19b5c2007-05-11 18:25:07 -05007 * Copyright (C) 2007 Freescale Semiconductor, Inc.
Kim Phillips728de4c92007-04-13 01:26:03 -05008 *
Kim Phillips4e19b5c2007-05-11 18:25:07 -05009 * Authors: Li Yang <leoli@freescale.com>
10 * Kim Phillips <kim.phillips@freescale.com>
Kim Phillips728de4c92007-04-13 01:26:03 -050011 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 *
17 */
18
19#include <linux/kernel.h>
20#include <linux/sched.h>
21#include <linux/string.h>
22#include <linux/errno.h>
23#include <linux/unistd.h>
24#include <linux/slab.h>
25#include <linux/interrupt.h>
26#include <linux/init.h>
27#include <linux/delay.h>
28#include <linux/netdevice.h>
29#include <linux/etherdevice.h>
30#include <linux/skbuff.h>
31#include <linux/spinlock.h>
32#include <linux/mm.h>
33#include <linux/module.h>
34#include <linux/platform_device.h>
35#include <asm/ocp.h>
36#include <linux/crc32.h>
37#include <linux/mii.h>
38#include <linux/phy.h>
39#include <linux/fsl_devices.h>
40
41#include <asm/of_platform.h>
42#include <asm/io.h>
43#include <asm/irq.h>
44#include <asm/uaccess.h>
45#include <asm/ucc.h>
46
47#include "ucc_geth_mii.h"
48#include "ucc_geth.h"
49
50#define DEBUG
51#ifdef DEBUG
52#define vdbg(format, arg...) printk(KERN_DEBUG , format "\n" , ## arg)
53#else
54#define vdbg(format, arg...) do {} while(0)
55#endif
56
57#define DRV_DESC "QE UCC Ethernet Controller MII Bus"
58#define DRV_NAME "fsl-uec_mdio"
59
60/* Write value to the PHY for this device to the register at regnum, */
61/* waiting until the write is done before it returns. All PHY */
62/* configuration has to be done through the master UEC MIIM regs */
63int uec_mdio_write(struct mii_bus *bus, int mii_id, int regnum, u16 value)
64{
65 struct ucc_mii_mng __iomem *regs = (void __iomem *)bus->priv;
66
67 /* Setting up the MII Mangement Address Register */
68 out_be32(&regs->miimadd,
69 (mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | regnum);
70
71 /* Setting up the MII Mangement Control Register with the value */
72 out_be32(&regs->miimcon, value);
73
74 /* Wait till MII management write is complete */
75 while ((in_be32(&regs->miimind)) & MIIMIND_BUSY)
76 cpu_relax();
77
78 return 0;
79}
80
81/* Reads from register regnum in the PHY for device dev, */
82/* returning the value. Clears miimcom first. All PHY */
83/* configuration has to be done through the TSEC1 MIIM regs */
84int uec_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
85{
86 struct ucc_mii_mng __iomem *regs = (void __iomem *)bus->priv;
87 u16 value;
88
89 /* Setting up the MII Mangement Address Register */
90 out_be32(&regs->miimadd,
91 (mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | regnum);
92
93 /* Clear miimcom, perform an MII management read cycle */
94 out_be32(&regs->miimcom, 0);
95 out_be32(&regs->miimcom, MIIMCOM_READ_CYCLE);
96
97 /* Wait till MII management write is complete */
98 while ((in_be32(&regs->miimind)) & (MIIMIND_BUSY | MIIMIND_NOT_VALID))
99 cpu_relax();
100
101 /* Read MII management status */
102 value = in_be32(&regs->miimstat);
103
104 return value;
105}
106
107/* Reset the MIIM registers, and wait for the bus to free */
108int uec_mdio_reset(struct mii_bus *bus)
109{
110 struct ucc_mii_mng __iomem *regs = (void __iomem *)bus->priv;
111 unsigned int timeout = PHY_INIT_TIMEOUT;
112
113 spin_lock_bh(&bus->mdio_lock);
114
115 /* Reset the management interface */
116 out_be32(&regs->miimcfg, MIIMCFG_RESET_MANAGEMENT);
117
118 /* Setup the MII Mgmt clock speed */
119 out_be32(&regs->miimcfg, MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_112);
120
121 /* Wait until the bus is free */
122 while ((in_be32(&regs->miimind) & MIIMIND_BUSY) && timeout--)
123 cpu_relax();
124
125 spin_unlock_bh(&bus->mdio_lock);
126
127 if (timeout <= 0) {
128 printk(KERN_ERR "%s: The MII Bus is stuck!\n", bus->name);
129 return -EBUSY;
130 }
131
132 return 0;
133}
134
135static int uec_mdio_probe(struct of_device *ofdev, const struct of_device_id *match)
136{
137 struct device *device = &ofdev->dev;
138 struct device_node *np = ofdev->node, *tempnp = NULL;
139 struct device_node *child = NULL;
140 struct ucc_mii_mng __iomem *regs;
141 struct mii_bus *new_bus;
142 struct resource res;
143 int k, err = 0;
144
145 new_bus = kzalloc(sizeof(struct mii_bus), GFP_KERNEL);
146
147 if (NULL == new_bus)
148 return -ENOMEM;
149
150 new_bus->name = "UCC Ethernet Controller MII Bus";
151 new_bus->read = &uec_mdio_read;
152 new_bus->write = &uec_mdio_write;
153 new_bus->reset = &uec_mdio_reset;
154
155 memset(&res, 0, sizeof(res));
156
157 err = of_address_to_resource(np, 0, &res);
158 if (err)
159 goto reg_map_fail;
160
161 new_bus->id = res.start;
162
163 new_bus->irq = kmalloc(32 * sizeof(int), GFP_KERNEL);
164
165 if (NULL == new_bus->irq) {
166 err = -ENOMEM;
167 goto reg_map_fail;
168 }
169
170 for (k = 0; k < 32; k++)
171 new_bus->irq[k] = PHY_POLL;
172
173 while ((child = of_get_next_child(np, child)) != NULL) {
174 int irq = irq_of_parse_and_map(child, 0);
175 if (irq != NO_IRQ) {
Stephen Rothwell40cd3a42007-05-01 13:54:02 +1000176 const u32 *id = of_get_property(child, "reg", NULL);
Kim Phillips728de4c92007-04-13 01:26:03 -0500177 new_bus->irq[*id] = irq;
178 }
179 }
180
181 /* Set the base address */
182 regs = ioremap(res.start, sizeof(struct ucc_mii_mng));
183
184 if (NULL == regs) {
185 err = -ENOMEM;
186 goto ioremap_fail;
187 }
188
189 new_bus->priv = (void __force *)regs;
190
191 new_bus->dev = device;
192 dev_set_drvdata(device, new_bus);
193
194 /* Read MII management master from device tree */
195 while ((tempnp = of_find_compatible_node(tempnp, "network", "ucc_geth"))
196 != NULL) {
197 struct resource tempres;
198
199 err = of_address_to_resource(tempnp, 0, &tempres);
200 if (err)
201 goto bus_register_fail;
202
203 /* if our mdio regs fall within this UCC regs range */
204 if ((res.start >= tempres.start) &&
205 (res.end <= tempres.end)) {
206 /* set this UCC to be the MII master */
Stephen Rothwell40cd3a42007-05-01 13:54:02 +1000207 const u32 *id = of_get_property(tempnp, "device-id", NULL);
Kim Phillips728de4c92007-04-13 01:26:03 -0500208 if (id == NULL)
209 goto bus_register_fail;
210
211 ucc_set_qe_mux_mii_mng(*id - 1);
212
213 /* assign the TBI an address which won't
214 * conflict with the PHYs */
215 out_be32(&regs->utbipar, UTBIPAR_INIT_TBIPA);
216 break;
217 }
218 }
219
220 err = mdiobus_register(new_bus);
221 if (0 != err) {
222 printk(KERN_ERR "%s: Cannot register as MDIO bus\n",
223 new_bus->name);
224 goto bus_register_fail;
225 }
226
227 return 0;
228
229bus_register_fail:
230 iounmap(regs);
231ioremap_fail:
232 kfree(new_bus->irq);
233reg_map_fail:
234 kfree(new_bus);
235
236 return err;
237}
238
239int uec_mdio_remove(struct of_device *ofdev)
240{
241 struct device *device = &ofdev->dev;
242 struct mii_bus *bus = dev_get_drvdata(device);
243
244 mdiobus_unregister(bus);
245
246 dev_set_drvdata(device, NULL);
247
248 iounmap((void __iomem *)bus->priv);
249 bus->priv = NULL;
250 kfree(bus);
251
252 return 0;
253}
254
255static struct of_device_id uec_mdio_match[] = {
256 {
257 .type = "mdio",
258 .compatible = "ucc_geth_phy",
259 },
260 {},
261};
262
Kim Phillips728de4c92007-04-13 01:26:03 -0500263static struct of_platform_driver uec_mdio_driver = {
264 .name = DRV_NAME,
265 .probe = uec_mdio_probe,
266 .remove = uec_mdio_remove,
267 .match_table = uec_mdio_match,
268};
269
270int __init uec_mdio_init(void)
271{
272 return of_register_platform_driver(&uec_mdio_driver);
273}
274
275void __exit uec_mdio_exit(void)
276{
277 of_unregister_platform_driver(&uec_mdio_driver);
278}