| Chaithrika U S | 06e61f8 | 2009-05-07 09:30:01 -0300 | [diff] [blame] | 1 | /* |
| 2 | * ADV7343 header file |
| 3 | * |
| 4 | * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation version 2. |
| 9 | * |
| 10 | * This program is distributed .as is. WITHOUT ANY WARRANTY of any |
| 11 | * kind, whether express or implied; without even the implied warranty |
| 12 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
| 16 | #ifndef ADV7343_H |
| 17 | #define ADV7343_H |
| 18 | |
| 19 | #define ADV7343_COMPOSITE_ID (0) |
| 20 | #define ADV7343_COMPONENT_ID (1) |
| 21 | #define ADV7343_SVIDEO_ID (2) |
| 22 | |
| Lad, Prabhakar | 0b302d8 | 2013-01-22 01:19:50 -0300 | [diff] [blame] | 23 | /** |
| 24 | * adv7343_power_mode - power mode configuration. |
| 25 | * @sleep_mode: on enable the current consumption is reduced to micro ampere |
| 26 | * level. All DACs and the internal PLL circuit are disabled. |
| 27 | * Registers can be read from and written in sleep mode. |
| 28 | * @pll_control: PLL and oversampling control. This control allows internal |
| 29 | * PLL 1 circuit to be powered down and the oversampling to be |
| 30 | * switched off. |
| 31 | * @dac_1: power on/off DAC 1. |
| 32 | * @dac_2: power on/off DAC 2. |
| 33 | * @dac_3: power on/off DAC 3. |
| 34 | * @dac_4: power on/off DAC 4. |
| 35 | * @dac_5: power on/off DAC 5. |
| 36 | * @dac_6: power on/off DAC 6. |
| 37 | * |
| 38 | * Power mode register (Register 0x0), for more info refer REGISTER MAP ACCESS |
| 39 | * section of datasheet[1], table 17 page no 30. |
| 40 | * |
| 41 | * [1] http://www.analog.com/static/imported-files/data_sheets/ADV7342_7343.pdf |
| 42 | */ |
| 43 | struct adv7343_power_mode { |
| 44 | bool sleep_mode; |
| 45 | bool pll_control; |
| 46 | bool dac_1; |
| 47 | bool dac_2; |
| 48 | bool dac_3; |
| 49 | bool dac_4; |
| 50 | bool dac_5; |
| 51 | bool dac_6; |
| 52 | }; |
| 53 | |
| 54 | /** |
| 55 | * struct adv7343_sd_config - SD Only Output Configuration. |
| 56 | * @sd_dac_out1: Configure SD DAC Output 1. |
| 57 | * @sd_dac_out2: Configure SD DAC Output 2. |
| 58 | */ |
| 59 | struct adv7343_sd_config { |
| 60 | /* SD only Output Configuration */ |
| 61 | bool sd_dac_out1; |
| 62 | bool sd_dac_out2; |
| 63 | }; |
| 64 | |
| 65 | /** |
| 66 | * struct adv7343_platform_data - Platform data values and access functions. |
| 67 | * @mode_config: Configuration for power mode. |
| 68 | * @sd_config: SD Only Configuration. |
| 69 | */ |
| 70 | struct adv7343_platform_data { |
| 71 | struct adv7343_power_mode mode_config; |
| 72 | struct adv7343_sd_config sd_config; |
| 73 | }; |
| 74 | |
| Chaithrika U S | 06e61f8 | 2009-05-07 09:30:01 -0300 | [diff] [blame] | 75 | #endif /* End of #ifndef ADV7343_H */ |