| Subhash Jadavani | 9c80770 | 2017-04-01 00:35:51 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2013-2017, The Linux Foundation. All rights reserved. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 and |
| 6 | * only version 2 as published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | * |
| 13 | */ |
| 14 | |
| 15 | #ifndef UFS_QCOM_PHY_QMP_V3_660_H_ |
| 16 | #define UFS_QCOM_PHY_QMP_V3_660_H_ |
| 17 | |
| 18 | #include "phy-qcom-ufs-i.h" |
| 19 | |
| 20 | /* QCOM UFS PHY control registers */ |
| 21 | #define COM_BASE 0x000 |
| 22 | #define COM_OFF(x) (COM_BASE + x) |
| 23 | #define COM_SIZE 0x1C0 |
| 24 | |
| 25 | #define TX_BASE 0x400 |
| 26 | #define TX_OFF(x) (TX_BASE + x) |
| 27 | #define TX_SIZE 0x128 |
| 28 | |
| 29 | #define RX_BASE 0x600 |
| 30 | #define RX_OFF(x) (RX_BASE + x) |
| 31 | #define RX_SIZE 0x1FC |
| 32 | |
| 33 | #define PHY_BASE 0xC00 |
| 34 | #define PHY_OFF(x) (PHY_BASE + x) |
| 35 | #define PHY_SIZE 0x1B4 |
| 36 | |
| 37 | /* UFS PHY QSERDES COM registers */ |
| 38 | #define QSERDES_COM_ATB_SEL1 COM_OFF(0x00) |
| 39 | #define QSERDES_COM_ATB_SEL2 COM_OFF(0x04) |
| 40 | #define QSERDES_COM_FREQ_UPDATE COM_OFF(0x08) |
| 41 | #define QSERDES_COM_BG_TIMER COM_OFF(0x0C) |
| 42 | #define QSERDES_COM_SSC_EN_CENTER COM_OFF(0x10) |
| 43 | #define QSERDES_COM_SSC_ADJ_PER1 COM_OFF(0x14) |
| 44 | #define QSERDES_COM_SSC_ADJ_PER2 COM_OFF(0x18) |
| 45 | #define QSERDES_COM_SSC_PER1 COM_OFF(0x1C) |
| 46 | #define QSERDES_COM_SSC_PER2 COM_OFF(0x20) |
| 47 | #define QSERDES_COM_SSC_STEP_SIZE1 COM_OFF(0x24) |
| 48 | #define QSERDES_COM_SSC_STEP_SIZE2 COM_OFF(0x28) |
| 49 | #define QSERDES_COM_POST_DIV COM_OFF(0x2C) |
| 50 | #define QSERDES_COM_POST_DIV_MUX COM_OFF(0x30) |
| 51 | #define QSERDES_COM_BIAS_EN_CLKBUFLR_EN COM_OFF(0x34) |
| 52 | #define QSERDES_COM_CLK_ENABLE1 COM_OFF(0x38) |
| 53 | #define QSERDES_COM_SYS_CLK_CTRL COM_OFF(0x3C) |
| 54 | #define QSERDES_COM_SYSCLK_BUF_ENABLE COM_OFF(0x40) |
| 55 | #define QSERDES_COM_PLL_EN COM_OFF(0x44) |
| 56 | #define QSERDES_COM_PLL_IVCO COM_OFF(0x48) |
| 57 | #define QSERDES_COM_LOCK_CMP1_MODE0 COM_OFF(0X4C) |
| 58 | #define QSERDES_COM_LOCK_CMP2_MODE0 COM_OFF(0X50) |
| 59 | #define QSERDES_COM_LOCK_CMP3_MODE0 COM_OFF(0X54) |
| 60 | #define QSERDES_COM_LOCK_CMP1_MODE1 COM_OFF(0X58) |
| 61 | #define QSERDES_COM_LOCK_CMP2_MODE1 COM_OFF(0X5C) |
| 62 | #define QSERDES_COM_LOCK_CMP3_MODE1 COM_OFF(0X60) |
| 63 | #define QSERDES_COM_CMD_RSVD0 COM_OFF(0x64) |
| 64 | #define QSERDES_COM_EP_CLOCK_DETECT_CTRL COM_OFF(0x68) |
| 65 | #define QSERDES_COM_SYSCLK_DET_COMP_STATUS COM_OFF(0x6C) |
| 66 | #define QSERDES_COM_BG_TRIM COM_OFF(0x70) |
| 67 | #define QSERDES_COM_CLK_EP_DIV COM_OFF(0x74) |
| 68 | #define QSERDES_COM_CP_CTRL_MODE0 COM_OFF(0x78) |
| 69 | #define QSERDES_COM_CP_CTRL_MODE1 COM_OFF(0x7C) |
| 70 | #define QSERDES_COM_CMN_RSVD1 COM_OFF(0x80) |
| 71 | #define QSERDES_COM_PLL_RCTRL_MODE0 COM_OFF(0x84) |
| 72 | #define QSERDES_COM_PLL_RCTRL_MODE1 COM_OFF(0x88) |
| 73 | #define QSERDES_COM_CMN_RSVD2 COM_OFF(0x8C) |
| 74 | #define QSERDES_COM_PLL_CCTRL_MODE0 COM_OFF(0x90) |
| 75 | #define QSERDES_COM_PLL_CCTRL_MODE1 COM_OFF(0x94) |
| 76 | #define QSERDES_COM_CMN_RSVD3 COM_OFF(0x98) |
| 77 | #define QSERDES_COM_PLL_CNTRL COM_OFF(0x9C) |
| 78 | #define QSERDES_COM_PHASE_SEL_CTRL COM_OFF(0xA0) |
| 79 | #define QSERDES_COM_PHASE_SEL_DC COM_OFF(0xA4) |
| 80 | #define QSERDES_COM_BIAS_EN_CTRL_BY_PSM COM_OFF(0xA8) |
| 81 | #define QSERDES_COM_SYSCLK_EN_SEL COM_OFF(0xAC) |
| 82 | #define QSERDES_COM_CML_SYSCLK_SEL COM_OFF(0xB0) |
| 83 | #define QSERDES_COM_RESETSM_CNTRL COM_OFF(0xB4) |
| 84 | #define QSERDES_COM_RESETSM_CNTRL2 COM_OFF(0xB8) |
| 85 | #define QSERDES_COM_RESTRIM_CTRL COM_OFF(0xBC) |
| 86 | #define QSERDES_COM_RESTRIM_CTRL2 COM_OFF(0xC0) |
| 87 | #define QSERDES_COM_LOCK_CMP_EN COM_OFF(0xC8) |
| 88 | #define QSERDES_COM_LOCK_CMP_CFG COM_OFF(0xCC) |
| 89 | #define QSERDES_COM_DEC_START_MODE0 COM_OFF(0xD0) |
| 90 | #define QSERDES_COM_DEC_START_MODE1 COM_OFF(0xD4) |
| 91 | #define QSERDES_COM_VCOCAL_DEADMAN_CTRL COM_OFF(0xD8) |
| 92 | #define QSERDES_COM_DIV_FRAC_START1_MODE0 COM_OFF(0xDC) |
| 93 | #define QSERDES_COM_DIV_FRAC_START2_MODE0 COM_OFF(0xE0) |
| 94 | #define QSERDES_COM_DIV_FRAC_START3_MODE0 COM_OFF(0xE4) |
| 95 | #define QSERDES_COM_DIV_FRAC_START1_MODE1 COM_OFF(0xE8) |
| 96 | #define QSERDES_COM_DIV_FRAC_START2_MODE1 COM_OFF(0xEC) |
| 97 | #define QSERDES_COM_DIV_FRAC_START3_MODE1 COM_OFF(0xF0) |
| 98 | #define QSERDES_COM_VCO_TUNE_MINVAL1 COM_OFF(0xF4) |
| 99 | #define QSERDES_COM_VCO_TUNE_MINVAL2 COM_OFF(0xF8) |
| 100 | #define QSERDES_COM_CMN_RSVD4 COM_OFF(0xFC) |
| 101 | #define QSERDES_COM_INTEGLOOP_INITVAL COM_OFF(0x100) |
| 102 | #define QSERDES_COM_INTEGLOOP_EN COM_OFF(0x104) |
| 103 | #define QSERDES_COM_INTEGLOOP_GAIN0_MODE0 COM_OFF(0x108) |
| 104 | #define QSERDES_COM_INTEGLOOP_GAIN1_MODE0 COM_OFF(0x10C) |
| 105 | #define QSERDES_COM_INTEGLOOP_GAIN0_MODE1 COM_OFF(0x110) |
| 106 | #define QSERDES_COM_INTEGLOOP_GAIN1_MODE1 COM_OFF(0x114) |
| 107 | #define QSERDES_COM_VCO_TUNE_MAXVAL1 COM_OFF(0x118) |
| 108 | #define QSERDES_COM_VCO_TUNE_MAXVAL2 COM_OFF(0x11C) |
| 109 | #define QSERDES_COM_RES_TRIM_CONTROL2 COM_OFF(0x120) |
| 110 | #define QSERDES_COM_VCO_TUNE_CTRL COM_OFF(0x124) |
| 111 | #define QSERDES_COM_VCO_TUNE_MAP COM_OFF(0x128) |
| 112 | #define QSERDES_COM_VCO_TUNE1_MODE0 COM_OFF(0x12C) |
| 113 | #define QSERDES_COM_VCO_TUNE2_MODE0 COM_OFF(0x130) |
| 114 | #define QSERDES_COM_VCO_TUNE1_MODE1 COM_OFF(0x134) |
| 115 | #define QSERDES_COM_VCO_TUNE2_MODE1 COM_OFF(0x138) |
| 116 | #define QSERDES_COM_VCO_TUNE_INITVAL1 COM_OFF(0x13C) |
| 117 | #define QSERDES_COM_VCO_TUNE_INITVAL2 COM_OFF(0x140) |
| 118 | #define QSERDES_COM_VCO_TUNE_TIMER1 COM_OFF(0x144) |
| 119 | #define QSERDES_COM_VCO_TUNE_TIMER2 COM_OFF(0x148) |
| 120 | #define QSERDES_COM_SAR COM_OFF(0x14C) |
| 121 | #define QSERDES_COM_SAR_CLK COM_OFF(0x150) |
| 122 | #define QSERDES_COM_SAR_CODE_OUT_STATUS COM_OFF(0x154) |
| 123 | #define QSERDES_COM_SAR_CODE_READY_STATUS COM_OFF(0x158) |
| 124 | #define QSERDES_COM_CMN_STATUS COM_OFF(0x15C) |
| 125 | #define QSERDES_COM_RESET_SM_STATUS COM_OFF(0x160) |
| 126 | #define QSERDES_COM_RESTRIM_CODE_STATUS COM_OFF(0x164) |
| 127 | #define QSERDES_COM_PLLCAL_CODE1_STATUS COM_OFF(0x168) |
| 128 | #define QSERDES_COM_PLLCAL_CODE2_STATUS COM_OFF(0x16C) |
| 129 | #define QSERDES_COM_BG_CTRL COM_OFF(0x170) |
| 130 | #define QSERDES_COM_CLK_SELECT COM_OFF(0x174) |
| 131 | #define QSERDES_COM_HSCLK_SEL COM_OFF(0x178) |
| 132 | #define QSERDES_COM_INTEGLOOP_BINCODE_STATUS COM_OFF(0x17C) |
| 133 | #define QSERDES_COM_PLL_ANALOG COM_OFF(0x180) |
| 134 | #define QSERDES_COM_CORECLK_DIV COM_OFF(0x184) |
| 135 | #define QSERDES_COM_SW_RESET COM_OFF(0x188) |
| 136 | #define QSERDES_COM_CORE_CLK_EN COM_OFF(0x18C) |
| 137 | #define QSERDES_COM_C_READY_STATUS COM_OFF(0x190) |
| 138 | #define QSERDES_COM_CMN_CONFIG COM_OFF(0x194) |
| 139 | #define QSERDES_COM_CMN_RATE_OVERRIDE COM_OFF(0x198) |
| 140 | #define QSERDES_COM_SVS_MODE_CLK_SEL COM_OFF(0x19C) |
| 141 | #define QSERDES_COM_DEBUG_BUS0 COM_OFF(0x1A0) |
| 142 | #define QSERDES_COM_DEBUG_BUS1 COM_OFF(0x1A4) |
| 143 | #define QSERDES_COM_DEBUG_BUS2 COM_OFF(0x1A8) |
| 144 | #define QSERDES_COM_DEBUG_BUS3 COM_OFF(0x1AC) |
| 145 | #define QSERDES_COM_DEBUG_BUS_SEL COM_OFF(0x1B0) |
| 146 | #define QSERDES_COM_CMN_MISC1 COM_OFF(0x1B4) |
| 147 | #define QSERDES_COM_CORECLK_DIV_MODE1 COM_OFF(0x1BC) |
| 148 | #define QSERDES_COM_CMN_RSVD5 COM_OFF(0x1C0) |
| 149 | |
| 150 | /* UFS PHY registers */ |
| 151 | #define UFS_PHY_PHY_START PHY_OFF(0x00) |
| 152 | #define UFS_PHY_POWER_DOWN_CONTROL PHY_OFF(0x04) |
| 153 | #define UFS_PHY_TX_LARGE_AMP_DRV_LVL PHY_OFF(0x34) |
| 154 | #define UFS_PHY_TX_SMALL_AMP_DRV_LVL PHY_OFF(0x3C) |
| 155 | #define UFS_PHY_RX_MIN_STALL_NOCONFIG_TIME_CAP PHY_OFF(0xCC) |
| 156 | #define UFS_PHY_LINECFG_DISABLE PHY_OFF(0x138) |
| 157 | #define UFS_PHY_RX_SYM_RESYNC_CTRL PHY_OFF(0x13C) |
| 158 | #define UFS_PHY_RX_SIGDET_CTRL2 PHY_OFF(0x148) |
| 159 | #define UFS_PHY_RX_PWM_GEAR_BAND PHY_OFF(0x154) |
| 160 | #define UFS_PHY_PCS_READY_STATUS PHY_OFF(0x168) |
| 161 | |
| 162 | /* UFS PHY TX registers */ |
| 163 | #define QSERDES_TX_HIGHZ_TRANSCEIVER_BIAS_DRVR_EN TX_OFF(0x68) |
| 164 | #define QSERDES_TX_LANE_MODE TX_OFF(0x94) |
| 165 | |
| 166 | /* UFS PHY RX registers */ |
| 167 | #define QSERDES_RX_UCDR_SVS_SO_GAIN_HALF RX_OFF(0x30) |
| 168 | #define QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER RX_OFF(0x34) |
| 169 | #define QSERDES_RX_UCDR_SVS_SO_GAIN_EIGHTH RX_OFF(0x38) |
| 170 | #define QSERDES_RX_UCDR_SVS_SO_GAIN RX_OFF(0x3C) |
| 171 | #define QSERDES_RX_UCDR_FASTLOCK_FO_GAIN RX_OFF(0x40) |
| 172 | #define QSERDES_RX_UCDR_SO_SATURATION_ENABLE RX_OFF(0x48) |
| 173 | #define QSERDES_RX_RX_TERM_BW RX_OFF(0x90) |
| 174 | #define QSERDES_RX_RX_EQ_GAIN1_LSB RX_OFF(0xC4) |
| 175 | #define QSERDES_RX_RX_EQ_GAIN1_MSB RX_OFF(0xC8) |
| 176 | #define QSERDES_RX_RX_EQ_GAIN2_LSB RX_OFF(0xCC) |
| 177 | #define QSERDES_RX_RX_EQ_GAIN2_MSB RX_OFF(0xD0) |
| 178 | #define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 RX_OFF(0xD8) |
| 179 | #define QSERDES_RX_SIGDET_CNTRL RX_OFF(0x114) |
| 180 | #define QSERDES_RX_SIGDET_LVL RX_OFF(0x118) |
| 181 | #define QSERDES_RX_SIGDET_DEGLITCH_CNTRL RX_OFF(0x11C) |
| 182 | #define QSERDES_RX_RX_INTERFACE_MODE RX_OFF(0x12C) |
| 183 | |
| 184 | |
| 185 | #define UFS_PHY_RX_LINECFG_DISABLE_BIT BIT(1) |
| 186 | |
| 187 | /* |
| 188 | * This structure represents the v3 660 specific phy. |
| 189 | * common_cfg MUST remain the first field in this structure |
| 190 | * in case extra fields are added. This way, when calling |
| 191 | * get_ufs_qcom_phy() of generic phy, we can extract the |
| 192 | * common phy structure (struct ufs_qcom_phy) out of it |
| 193 | * regardless of the relevant specific phy. |
| 194 | */ |
| 195 | struct ufs_qcom_phy_qmp_v3_660 { |
| 196 | struct ufs_qcom_phy common_cfg; |
| 197 | }; |
| 198 | |
| 199 | static struct ufs_qcom_phy_calibration phy_cal_table_rate_A_3_1_1[] = { |
| 200 | UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_POWER_DOWN_CONTROL, 0x01), |
| 201 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CMN_CONFIG, 0x0e), |
| 202 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYSCLK_EN_SEL, 0x14), |
| 203 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CLK_SELECT, 0x30), |
| 204 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYS_CLK_CTRL, 0x02), |
| 205 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), |
| 206 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BG_TIMER, 0x0a), |
| 207 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_HSCLK_SEL, 0x00), |
| 208 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CORECLK_DIV, 0x0a), |
| 209 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a), |
| 210 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP_EN, 0x01), |
| 211 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_CTRL, 0x00), |
| 212 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_RESETSM_CNTRL, 0x20), |
| 213 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CORE_CLK_EN, 0x00), |
| 214 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP_CFG, 0x00), |
| 215 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), |
| 216 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f), |
| 217 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_MAP, 0x04), |
| 218 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05), |
| 219 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START_MODE0, 0x82), |
| 220 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00), |
| 221 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00), |
| 222 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00), |
| 223 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CP_CTRL_MODE0, 0x0b), |
| 224 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), |
| 225 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), |
| 226 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), |
| 227 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00), |
| 228 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE1_MODE0, 0x28), |
| 229 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE2_MODE0, 0x02), |
| 230 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP1_MODE0, 0xff), |
| 231 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c), |
| 232 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), |
| 233 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START_MODE1, 0x98), |
| 234 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00), |
| 235 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00), |
| 236 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00), |
| 237 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CP_CTRL_MODE1, 0x0b), |
| 238 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RCTRL_MODE1, 0x16), |
| 239 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CCTRL_MODE1, 0x28), |
| 240 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80), |
| 241 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00), |
| 242 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6), |
| 243 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE2_MODE1, 0x00), |
| 244 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP1_MODE1, 0x32), |
| 245 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f), |
| 246 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP3_MODE1, 0x00), |
| 247 | |
| 248 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_HIGHZ_TRANSCEIVER_BIAS_DRVR_EN, 0x45), |
| 249 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_LANE_MODE, 0x06), |
| 250 | |
| 251 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_LVL, 0x24), |
| 252 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_CNTRL, 0x0F), |
| 253 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_INTERFACE_MODE, 0x40), |
| 254 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E), |
| 255 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B), |
| 256 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_TERM_BW, 0x5B), |
| 257 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xFF), |
| 258 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3F), |
| 259 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xFF), |
| 260 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x3F), |
| 261 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0D), |
| 262 | |
| 263 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IVCO, 0x0F), |
| 264 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BG_TRIM, 0x0F), |
| 265 | UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_PWM_GEAR_BAND, 0x15), |
| 266 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_SVS_SO_GAIN_HALF, 0x04), |
| 267 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04), |
| 268 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_SVS_SO_GAIN, 0x04), |
| 269 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_SO_SATURATION_ENABLE, 0x4B), |
| 270 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_INITVAL1, 0xFF), |
| 271 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00), |
| 272 | UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SIGDET_CTRL2, 0x6c), |
| 273 | UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_LARGE_AMP_DRV_LVL, 0x0A), |
| 274 | UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_SMALL_AMP_DRV_LVL, 0x02), |
| 275 | UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28), |
| 276 | UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SYM_RESYNC_CTRL, 0x03), |
| 277 | }; |
| 278 | |
| 279 | static struct ufs_qcom_phy_calibration phy_cal_table_rate_B[] = { |
| 280 | UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_MAP, 0x44), |
| 281 | }; |
| 282 | |
| 283 | #endif |