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Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -08001# Put here option for CPU selection and depending optimization
2if !X86_ELAN
3
4choice
5 prompt "Processor family"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +01006 default M686 if X86_32
7 default GENERIC_CPU if X86_64
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -08008
9config M386
10 bool "386"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +010011 depends on X86_32 && !UML
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -080012 ---help---
13 This is the processor type of your CPU. This information is used for
14 optimizing purposes. In order to compile a kernel that can run on
15 all x86 CPU types (albeit not optimally fast), you can specify
16 "386" here.
17
18 The kernel will not necessarily run on earlier architectures than
19 the one you have chosen, e.g. a Pentium optimized kernel will run on
20 a PPro, but not necessarily on a i486.
21
22 Here are the settings recommended for greatest speed:
23 - "386" for the AMD/Cyrix/Intel 386DX/DXL/SL/SLC/SX, Cyrix/TI
24 486DLC/DLC2, UMC 486SX-S and NexGen Nx586. Only "386" kernels
25 will run on a 386 class machine.
26 - "486" for the AMD/Cyrix/IBM/Intel 486DX/DX2/DX4 or
27 SL/SLC/SLC2/SLC3/SX/SX2 and UMC U5D or U5S.
28 - "586" for generic Pentium CPUs lacking the TSC
29 (time stamp counter) register.
30 - "Pentium-Classic" for the Intel Pentium.
31 - "Pentium-MMX" for the Intel Pentium MMX.
32 - "Pentium-Pro" for the Intel Pentium Pro.
33 - "Pentium-II" for the Intel Pentium II or pre-Coppermine Celeron.
34 - "Pentium-III" for the Intel Pentium III or Coppermine Celeron.
35 - "Pentium-4" for the Intel Pentium 4 or P4-based Celeron.
36 - "K6" for the AMD K6, K6-II and K6-III (aka K6-3D).
37 - "Athlon" for the AMD K7 family (Athlon/Duron/Thunderbird).
38 - "Crusoe" for the Transmeta Crusoe series.
39 - "Efficeon" for the Transmeta Efficeon series.
40 - "Winchip-C6" for original IDT Winchip.
41 - "Winchip-2" for IDT Winchip 2.
42 - "Winchip-2A" for IDT Winchips with 3dNow! capabilities.
43 - "GeodeGX1" for Geode GX1 (Cyrix MediaGX).
Jordan Crousef90b8112006-01-06 00:12:14 -080044 - "Geode GX/LX" For AMD Geode GX and LX processors.
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -080045 - "CyrixIII/VIA C3" for VIA Cyrix III or VIA C3.
Egry Gabor48a12042006-06-26 18:47:15 +020046 - "VIA C3-2" for VIA C3-2 "Nehemiah" (model 9 and above).
Simon Arlott0949be32007-05-02 19:27:05 +020047 - "VIA C7" for VIA C7.
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -080048
49 If you don't know what to do, choose "386".
50
51config M486
52 bool "486"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +010053 depends on X86_32
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -080054 help
55 Select this for a 486 series processor, either Intel or one of the
56 compatible processors from AMD, Cyrix, IBM, or Intel. Includes DX,
57 DX2, and DX4 variants; also SL/SLC/SLC2/SLC3/SX/SX2 and UMC U5D or
58 U5S.
59
60config M586
61 bool "586/K5/5x86/6x86/6x86MX"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +010062 depends on X86_32
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -080063 help
64 Select this for an 586 or 686 series processor such as the AMD K5,
65 the Cyrix 5x86, 6x86 and 6x86MX. This choice does not
66 assume the RDTSC (Read Time Stamp Counter) instruction.
67
68config M586TSC
69 bool "Pentium-Classic"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +010070 depends on X86_32
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -080071 help
72 Select this for a Pentium Classic processor with the RDTSC (Read
73 Time Stamp Counter) instruction for benchmarking.
74
75config M586MMX
76 bool "Pentium-MMX"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +010077 depends on X86_32
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -080078 help
79 Select this for a Pentium with the MMX graphics/multimedia
80 extended instructions.
81
82config M686
83 bool "Pentium-Pro"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +010084 depends on X86_32
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -080085 help
86 Select this for Intel Pentium Pro chips. This enables the use of
87 Pentium Pro extended instructions, and disables the init-time guard
88 against the f00f bug found in earlier Pentiums.
89
90config MPENTIUMII
91 bool "Pentium-II/Celeron(pre-Coppermine)"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +010092 depends on X86_32
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -080093 help
94 Select this for Intel chips based on the Pentium-II and
95 pre-Coppermine Celeron core. This option enables an unaligned
96 copy optimization, compiles the kernel with optimization flags
97 tailored for the chip, and applies any applicable Pentium Pro
98 optimizations.
99
100config MPENTIUMIII
101 bool "Pentium-III/Celeron(Coppermine)/Pentium-III Xeon"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100102 depends on X86_32
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800103 help
104 Select this for Intel chips based on the Pentium-III and
105 Celeron-Coppermine core. This option enables use of some
106 extended prefetch instructions in addition to the Pentium II
107 extensions.
108
109config MPENTIUMM
110 bool "Pentium M"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100111 depends on X86_32
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800112 help
113 Select this for Intel Pentium M (not Pentium-4 M)
114 notebook chips.
115
116config MPENTIUM4
Andi Kleenc55d92d2006-12-07 02:14:09 +0100117 bool "Pentium-4/Celeron(P4-based)/Pentium-4 M/older Xeon"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100118 depends on X86_32
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800119 help
120 Select this for Intel Pentium 4 chips. This includes the
Oliver Pinter75e38082007-10-17 18:04:36 +0200121 Pentium 4, Pentium D, P4-based Celeron and Xeon, and
122 Pentium-4 M (not Pentium M) chips. This option enables compile
123 flags optimized for the chip, uses the correct cache line size, and
124 applies any applicable optimizations.
125
126 CPUIDs: F[0-6][1-A] (in /proc/cpuinfo show = cpu family : 15 )
127
128 Select this for:
129 Pentiums (Pentium 4, Pentium D, Celeron, Celeron D) corename:
130 -Willamette
131 -Northwood
132 -Mobile Pentium 4
133 -Mobile Pentium 4 M
134 -Extreme Edition (Gallatin)
135 -Prescott
136 -Prescott 2M
137 -Cedar Mill
138 -Presler
139 -Smithfiled
140 Xeons (Intel Xeon, Xeon MP, Xeon LV, Xeon MV) corename:
141 -Foster
142 -Prestonia
143 -Gallatin
144 -Nocona
145 -Irwindale
146 -Cranford
147 -Potomac
148 -Paxville
149 -Dempsey
150
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800151
152config MK6
153 bool "K6/K6-II/K6-III"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100154 depends on X86_32
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800155 help
156 Select this for an AMD K6-family processor. Enables use of
157 some extended instructions, and passes appropriate optimization
158 flags to GCC.
159
160config MK7
161 bool "Athlon/Duron/K7"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100162 depends on X86_32
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800163 help
164 Select this for an AMD Athlon K7-family processor. Enables use of
165 some extended instructions, and passes appropriate optimization
166 flags to GCC.
167
168config MK8
169 bool "Opteron/Athlon64/Hammer/K8"
170 help
171 Select this for an AMD Opteron or Athlon64 Hammer-family processor. Enables
172 use of some extended instructions, and passes appropriate optimization
173 flags to GCC.
174
175config MCRUSOE
176 bool "Crusoe"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100177 depends on X86_32
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800178 help
179 Select this for a Transmeta Crusoe processor. Treats the processor
180 like a 586 with TSC, and sets some GCC optimization flags (like a
181 Pentium Pro with no alignment requirements).
182
183config MEFFICEON
184 bool "Efficeon"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100185 depends on X86_32
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800186 help
187 Select this for a Transmeta Efficeon processor.
188
189config MWINCHIPC6
190 bool "Winchip-C6"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100191 depends on X86_32
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800192 help
193 Select this for an IDT Winchip C6 chip. Linux and GCC
194 treat this chip as a 586TSC with some extended instructions
195 and alignment requirements.
196
197config MWINCHIP2
198 bool "Winchip-2"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100199 depends on X86_32
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800200 help
201 Select this for an IDT Winchip-2. Linux and GCC
202 treat this chip as a 586TSC with some extended instructions
203 and alignment requirements.
204
205config MWINCHIP3D
206 bool "Winchip-2A/Winchip-3"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100207 depends on X86_32
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800208 help
209 Select this for an IDT Winchip-2A or 3. Linux and GCC
210 treat this chip as a 586TSC with some extended instructions
David Sterba3dde6ad2007-05-09 07:12:20 +0200211 and alignment requirements. Also enable out of order memory
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800212 stores for this CPU, which can increase performance of some
213 operations.
214
215config MGEODEGX1
216 bool "GeodeGX1"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100217 depends on X86_32
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800218 help
219 Select this for a Geode GX1 (Cyrix MediaGX) chip.
220
Jordan Crousef90b8112006-01-06 00:12:14 -0800221config MGEODE_LX
Harvey Harrison96daa8c2008-01-30 13:31:03 +0100222 bool "Geode GX/LX"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100223 depends on X86_32
Harvey Harrison96daa8c2008-01-30 13:31:03 +0100224 help
225 Select this for AMD Geode GX and LX processors.
Jordan Crousef90b8112006-01-06 00:12:14 -0800226
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800227config MCYRIXIII
228 bool "CyrixIII/VIA-C3"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100229 depends on X86_32
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800230 help
231 Select this for a Cyrix III or C3 chip. Presently Linux and GCC
232 treat this chip as a generic 586. Whilst the CPU is 686 class,
233 it lacks the cmov extension which gcc assumes is present when
234 generating 686 code.
235 Note that Nehemiah (Model 9) and above will not boot with this
236 kernel due to them lacking the 3DNow! instructions used in earlier
237 incarnations of the CPU.
238
239config MVIAC3_2
240 bool "VIA C3-2 (Nehemiah)"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100241 depends on X86_32
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800242 help
243 Select this for a VIA C3 "Nehemiah". Selecting this enables usage
244 of SSE and tells gcc to treat the CPU as a 686.
245 Note, this kernel will not boot on older (pre model 9) C3s.
246
Simon Arlott0949be32007-05-02 19:27:05 +0200247config MVIAC7
248 bool "VIA C7"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100249 depends on X86_32
Simon Arlott0949be32007-05-02 19:27:05 +0200250 help
251 Select this for a VIA C7. Selecting this uses the correct cache
252 shift and tells gcc to treat the CPU as a 686.
253
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100254config MPSC
255 bool "Intel P4 / older Netburst based Xeon"
256 depends on X86_64
257 help
258 Optimize for Intel Pentium 4, Pentium D and older Nocona/Dempsey
259 Xeon CPUs with Intel 64bit which is compatible with x86-64.
260 Note that the latest Xeons (Xeon 51xx and 53xx) are not based on the
Harvey Harrison96daa8c2008-01-30 13:31:03 +0100261 Netburst core and shouldn't use this option. You can distinguish them
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100262 using the cpu family field
263 in /proc/cpuinfo. Family 15 is an older Xeon, Family 6 a newer one.
264
265config MCORE2
266 bool "Core 2/newer Xeon"
267 help
268 Select this for Intel Core 2 and newer Core 2 Xeons (Xeon 51xx and 53xx)
269 CPUs. You can distinguish newer from older Xeons by the CPU family
270 in /proc/cpuinfo. Newer ones have 6 and older ones 15 (not a typo)
271
272config GENERIC_CPU
273 bool "Generic-x86-64"
274 depends on X86_64
275 help
276 Generic x86-64 CPU.
277 Run equally well on all x86-64 CPUs.
278
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800279endchoice
280
281config X86_GENERIC
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100282 bool "Generic x86 support"
283 depends on X86_32
284 help
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800285 Instead of just including optimizations for the selected
286 x86 variant (e.g. PII, Crusoe or Athlon), include some more
287 generic optimizations as well. This will make the kernel
288 perform better on x86 CPUs other than that selected.
289
290 This is really intended for distributors who need more
291 generic optimizations.
292
293endif
294
295#
296# Define implied options from the CPU selection here
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100297config X86_L1_CACHE_BYTES
298 int
299 default "128" if GENERIC_CPU || MPSC
300 default "64" if MK8 || MCORE2
301 depends on X86_64
302
303config X86_INTERNODE_CACHE_BYTES
304 int
305 default "4096" if X86_VSMP
306 default X86_L1_CACHE_BYTES if !X86_VSMP
307 depends on X86_64
308
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800309config X86_CMPXCHG
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100310 def_bool X86_64 || (X86_32 && !M386)
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800311
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800312config X86_L1_CACHE_SHIFT
313 int
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100314 default "7" if MPENTIUM4 || X86_GENERIC || GENERIC_CPU || MPSC
Jordan Crousef90b8112006-01-06 00:12:14 -0800315 default "4" if X86_ELAN || M486 || M386 || MGEODEGX1
316 default "5" if MWINCHIP3D || MWINCHIP2 || MWINCHIPC6 || MCRUSOE || MEFFICEON || MCYRIXIII || MK6 || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || M586 || MVIAC3_2 || MGEODE_LX
Simon Arlott0949be32007-05-02 19:27:05 +0200317 default "6" if MK7 || MK8 || MPENTIUMM || MCORE2 || MVIAC7
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800318
Andi Kleenc7f81c92007-05-02 19:27:20 +0200319config X86_XADD
Harvey Harrison96daa8c2008-01-30 13:31:03 +0100320 def_bool y
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100321 depends on X86_32 && !M386
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800322
323config X86_PPRO_FENCE
Nick Pigginfb0328e2008-01-30 13:32:31 +0100324 bool "PentiumPro memory ordering errata workaround"
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800325 depends on M686 || M586MMX || M586TSC || M586 || M486 || M386 || MGEODEGX1
Nick Pigginfb0328e2008-01-30 13:32:31 +0100326 help
327 Old PentiumPro multiprocessor systems had errata that could cause memory
328 operations to violate the x86 ordering standard in rare cases. Enabling this
329 option will attempt to work around some (but not all) occurances of
330 this problem, at the cost of much heavier spinlock and memory barrier
331 operations.
332
333 If unsure, say n here. Even distro kernels should think twice before enabling
334 this: there are few systems, and an unlikely bug.
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800335
336config X86_F00F_BUG
Harvey Harrison96daa8c2008-01-30 13:31:03 +0100337 def_bool y
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800338 depends on M586MMX || M586TSC || M586 || M486 || M386
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800339
340config X86_WP_WORKS_OK
Harvey Harrison96daa8c2008-01-30 13:31:03 +0100341 def_bool y
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100342 depends on X86_32 && !M386
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800343
344config X86_INVLPG
Harvey Harrison96daa8c2008-01-30 13:31:03 +0100345 def_bool y
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100346 depends on X86_32 && !M386
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800347
348config X86_BSWAP
Harvey Harrison96daa8c2008-01-30 13:31:03 +0100349 def_bool y
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100350 depends on X86_32 && !M386
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800351
352config X86_POPAD_OK
Harvey Harrison96daa8c2008-01-30 13:31:03 +0100353 def_bool y
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100354 depends on X86_32 && !M386
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800355
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800356config X86_ALIGNMENT_16
Harvey Harrison96daa8c2008-01-30 13:31:03 +0100357 def_bool y
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800358 depends on MWINCHIP3D || MWINCHIP2 || MWINCHIPC6 || MCYRIXIII || X86_ELAN || MK6 || M586MMX || M586TSC || M586 || M486 || MVIAC3_2 || MGEODEGX1
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800359
360config X86_GOOD_APIC
Harvey Harrison96daa8c2008-01-30 13:31:03 +0100361 def_bool y
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100362 depends on MK7 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || MK8 || MEFFICEON || MCORE2 || MVIAC7 || X86_64
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800363
364config X86_INTEL_USERCOPY
Harvey Harrison96daa8c2008-01-30 13:31:03 +0100365 def_bool y
Andi Kleenc55d92d2006-12-07 02:14:09 +0100366 depends on MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M586MMX || X86_GENERIC || MK8 || MK7 || MEFFICEON || MCORE2
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800367
368config X86_USE_PPRO_CHECKSUM
Harvey Harrison96daa8c2008-01-30 13:31:03 +0100369 def_bool y
Andi Kleenc55d92d2006-12-07 02:14:09 +0100370 depends on MWINCHIP3D || MWINCHIP2 || MWINCHIPC6 || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MK8 || MVIAC3_2 || MEFFICEON || MGEODE_LX || MCORE2
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800371
372config X86_USE_3DNOW
Harvey Harrison96daa8c2008-01-30 13:31:03 +0100373 def_bool y
Paolo 'Blaisorblade' Giarrusso1b4ad242006-10-11 01:21:35 -0700374 depends on (MCYRIXIII || MK7 || MGEODE_LX) && !UML
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800375
376config X86_OOSTORE
Harvey Harrison96daa8c2008-01-30 13:31:03 +0100377 def_bool y
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800378 depends on (MWINCHIP3D || MWINCHIP2 || MWINCHIPC6) && MTRR
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800379
H. Peter Anvin959b3be2008-02-14 14:56:45 -0800380#
381# P6_NOPs are a relatively minor optimization that require a family >=
382# 6 processor, except that it is broken on certain VIA chips.
383# Furthermore, AMD chips prefer a totally different sequence of NOPs
384# (which work on all CPUs). As a result, disallow these if we're
385# compiling X86_GENERIC but not X86_64 (these NOPs do work on all
386# x86-64 capable chips); the list of processors in the right-hand clause
387# are the cores that benefit from this optimization.
388#
H. Peter Anvin7343b3b2008-02-14 14:52:05 -0800389config X86_P6_NOP
390 def_bool y
Hugh Dickinsfcab59a2008-03-04 19:33:24 +0000391 depends on (X86_64 || !X86_GENERIC) && (M686 || MPENTIUMII || MPENTIUMIII || MPENTIUMM || MCORE2 || MPENTIUM4)
H. Peter Anvin7343b3b2008-02-14 14:52:05 -0800392
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800393config X86_TSC
Harvey Harrison96daa8c2008-01-30 13:31:03 +0100394 def_bool y
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100395 depends on ((MWINCHIP3D || MWINCHIP2 || MCRUSOE || MEFFICEON || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || MK8 || MVIAC3_2 || MVIAC7 || MGEODEGX1 || MGEODE_LX || MCORE2) && !X86_NUMAQ) || X86_64
Andi Kleenc7f81c92007-05-02 19:27:20 +0200396
397# this should be set for all -march=.. options where the compiler
398# generates cmov.
399config X86_CMOV
Harvey Harrison96daa8c2008-01-30 13:31:03 +0100400 def_bool y
Andi Kleenc7f81c92007-05-02 19:27:20 +0200401 depends on (MK7 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MVIAC3_2 || MVIAC7)
Andi Kleenc7f81c92007-05-02 19:27:20 +0200402
H. Peter Anvinde32e042007-07-11 12:18:30 -0700403config X86_MINIMUM_CPU_FAMILY
Andi Kleenc7f81c92007-05-02 19:27:20 +0200404 int
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100405 default "64" if X86_64
H. Peter Anvin7343b3b2008-02-14 14:52:05 -0800406 default "6" if X86_32 && X86_P6_NOP
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100407 default "4" if X86_32 && (X86_XADD || X86_CMPXCHG || X86_BSWAP || X86_WP_WORKS_OK)
H. Peter Anvinde32e042007-07-11 12:18:30 -0700408 default "3"
Andi Kleenc7f81c92007-05-02 19:27:20 +0200409
Roland McGrath0a049bb2008-01-30 13:30:54 +0100410config X86_DEBUGCTLMSR
Harvey Harrison96daa8c2008-01-30 13:31:03 +0100411 def_bool y
Roland McGrath0a049bb2008-01-30 13:30:54 +0100412 depends on !(M586MMX || M586TSC || M586 || M486 || M386)