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Ben Dooksc6184e22007-02-17 00:52:37 +01001/* linux/arch/arm/mach-s3c2410/mach-qt2410.c
2 *
3 * Copyright (C) 2006 by OpenMoko, Inc.
4 * Author: Harald Welte <laforge@openmoko.org>
5 * All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 *
22 */
23
24#include <linux/kernel.h>
25#include <linux/types.h>
26#include <linux/interrupt.h>
27#include <linux/list.h>
28#include <linux/timer.h>
29#include <linux/init.h>
Ben Dooks333a42e2007-05-20 11:55:53 +010030#include <linux/sysdev.h>
Ben Dooksc6184e22007-02-17 00:52:37 +010031#include <linux/platform_device.h>
32#include <linux/serial_core.h>
Ben Dooksc6184e22007-02-17 00:52:37 +010033#include <linux/spi/spi.h>
34#include <linux/spi/spi_bitbang.h>
35
36#include <linux/mtd/mtd.h>
37#include <linux/mtd/nand.h>
38#include <linux/mtd/nand_ecc.h>
39#include <linux/mtd/partitions.h>
40
41#include <asm/mach/arch.h>
42#include <asm/mach/map.h>
43#include <asm/mach/irq.h>
44
45#include <asm/hardware.h>
46#include <asm/io.h>
47#include <asm/irq.h>
48#include <asm/mach-types.h>
49
50#include <asm/arch/regs-gpio.h>
51#include <asm/arch/leds-gpio.h>
Ben Dooks531b6172007-07-22 16:05:25 +010052#include <asm/plat-s3c/regs-serial.h>
Ben Dooksc6184e22007-02-17 00:52:37 +010053#include <asm/arch/fb.h>
Ben Dooks531b6172007-07-22 16:05:25 +010054#include <asm/plat-s3c/nand.h>
Ben Dooks06cfa552007-07-22 16:23:02 +010055#include <asm/plat-s3c24xx/udc.h>
Ben Dooksc6184e22007-02-17 00:52:37 +010056#include <asm/arch/spi.h>
57#include <asm/arch/spi-gpio.h>
58
59#include <asm/plat-s3c24xx/common-smdk.h>
60#include <asm/plat-s3c24xx/devs.h>
61#include <asm/plat-s3c24xx/cpu.h>
62#include <asm/plat-s3c24xx/pm.h>
63
64static struct map_desc qt2410_iodesc[] __initdata = {
65 { 0xe0000000, __phys_to_pfn(S3C2410_CS3+0x01000000), SZ_1M, MT_DEVICE }
66};
67
68#define UCON S3C2410_UCON_DEFAULT
69#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
70#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
71
72static struct s3c2410_uartcfg smdk2410_uartcfgs[] = {
73 [0] = {
74 .hwport = 0,
75 .flags = 0,
76 .ucon = UCON,
77 .ulcon = ULCON,
78 .ufcon = UFCON,
79 },
80 [1] = {
81 .hwport = 1,
82 .flags = 0,
83 .ucon = UCON,
84 .ulcon = ULCON,
85 .ufcon = UFCON,
86 },
87 [2] = {
88 .hwport = 2,
89 .flags = 0,
90 .ucon = UCON,
91 .ulcon = ULCON,
92 .ufcon = UFCON,
93 }
94};
95
96/* LCD driver info */
97
Krzysztof Helt09fe75f2007-10-16 01:28:56 -070098static struct s3c2410fb_display qt2410_lcd_cfg[] __initdata = {
99 {
100 /* Configuration for 640x480 SHARP LQ080V3DG01 */
101 .regs = {
Ben Dooksc6184e22007-02-17 00:52:37 +0100102
Krzysztof Helt09fe75f2007-10-16 01:28:56 -0700103 .lcdcon1 = S3C2410_LCDCON1_TFT16BPP |
104 S3C2410_LCDCON1_TFT |
105 S3C2410_LCDCON1_CLKVAL(0x01), /* HCLK/4 */
Ben Dooksc6184e22007-02-17 00:52:37 +0100106
Krzysztof Helt09fe75f2007-10-16 01:28:56 -0700107 .lcdcon2 = S3C2410_LCDCON2_VBPD(18) | /* 19 */
108 S3C2410_LCDCON2_LINEVAL(479) |
109 S3C2410_LCDCON2_VFPD(10) | /* 11 */
110 S3C2410_LCDCON2_VSPW(14), /* 15 */
Ben Dooksc6184e22007-02-17 00:52:37 +0100111
Krzysztof Helt09fe75f2007-10-16 01:28:56 -0700112 .lcdcon3 = S3C2410_LCDCON3_HBPD(43) | /* 44 */
113 S3C2410_LCDCON3_HOZVAL(639) | /* 640 */
114 S3C2410_LCDCON3_HFPD(115), /* 116 */
Ben Dooksc6184e22007-02-17 00:52:37 +0100115
Krzysztof Helt09fe75f2007-10-16 01:28:56 -0700116 .lcdcon4 = S3C2410_LCDCON4_MVAL(0) |
117 S3C2410_LCDCON4_HSPW(95), /* 96 */
Ben Dooksc6184e22007-02-17 00:52:37 +0100118
Krzysztof Helt09fe75f2007-10-16 01:28:56 -0700119 .lcdcon5 = S3C2410_LCDCON5_FRM565 |
120 S3C2410_LCDCON5_INVVLINE |
121 S3C2410_LCDCON5_INVVFRAME |
122 S3C2410_LCDCON5_PWREN |
123 S3C2410_LCDCON5_HWSWP,
124 },
125
126 .width = 640,
127 .height = 480,
128
129 .xres = 640,
130 .yres = 480,
131 .bpp = 16,
Ben Dooksc6184e22007-02-17 00:52:37 +0100132 },
Krzysztof Helt09fe75f2007-10-16 01:28:56 -0700133 {
134 /* Configuration for 480x640 toppoly TD028TTEC1 */
135 .regs = {
Ben Dooksc6184e22007-02-17 00:52:37 +0100136
Krzysztof Helt09fe75f2007-10-16 01:28:56 -0700137 .lcdcon1 = S3C2410_LCDCON1_TFT16BPP |
138 S3C2410_LCDCON1_TFT |
139 S3C2410_LCDCON1_CLKVAL(0x01), /* HCLK/4 */
Ben Dooksc6184e22007-02-17 00:52:37 +0100140
Krzysztof Helt09fe75f2007-10-16 01:28:56 -0700141 .lcdcon2 = S3C2410_LCDCON2_VBPD(1) | /* 2 */
142 S3C2410_LCDCON2_LINEVAL(639) |/* 640 */
143 S3C2410_LCDCON2_VFPD(3) | /* 4 */
144 S3C2410_LCDCON2_VSPW(1), /* 2 */
Ben Dooksc6184e22007-02-17 00:52:37 +0100145
Krzysztof Helt09fe75f2007-10-16 01:28:56 -0700146 .lcdcon3 = S3C2410_LCDCON3_HBPD(7) | /* 8 */
147 S3C2410_LCDCON3_HOZVAL(479) | /* 479 */
148 S3C2410_LCDCON3_HFPD(23), /* 24 */
149
150 .lcdcon4 = S3C2410_LCDCON4_MVAL(0) |
151 S3C2410_LCDCON4_HSPW(7), /* 8 */
152
153 .lcdcon5 = S3C2410_LCDCON5_FRM565 |
154 S3C2410_LCDCON5_INVVLINE |
155 S3C2410_LCDCON5_INVVFRAME |
156 S3C2410_LCDCON5_PWREN |
157 S3C2410_LCDCON5_HWSWP,
158 },
159
160 .width = 480,
161 .height = 640,
162 .xres = 480,
163 .yres = 640,
164 .bpp = 16,
Ben Dooksc6184e22007-02-17 00:52:37 +0100165 },
Krzysztof Helt09fe75f2007-10-16 01:28:56 -0700166 {
167 /* Config for 240x320 LCD */
168 .regs = {
Ben Dooksc6184e22007-02-17 00:52:37 +0100169
Krzysztof Helt09fe75f2007-10-16 01:28:56 -0700170 .lcdcon1 = S3C2410_LCDCON1_TFT16BPP |
171 S3C2410_LCDCON1_TFT |
172 S3C2410_LCDCON1_CLKVAL(0x04),
Ben Dooksc6184e22007-02-17 00:52:37 +0100173
Krzysztof Helt09fe75f2007-10-16 01:28:56 -0700174 .lcdcon2 = S3C2410_LCDCON2_VBPD(1) |
175 S3C2410_LCDCON2_LINEVAL(319) |
176 S3C2410_LCDCON2_VFPD(6) |
177 S3C2410_LCDCON2_VSPW(3),
178
179 .lcdcon3 = S3C2410_LCDCON3_HBPD(12) |
180 S3C2410_LCDCON3_HOZVAL(239) |
181 S3C2410_LCDCON3_HFPD(7),
182
183 .lcdcon4 = S3C2410_LCDCON4_MVAL(0) |
184 S3C2410_LCDCON4_HSPW(3),
185
186 .lcdcon5 = S3C2410_LCDCON5_FRM565 |
187 S3C2410_LCDCON5_INVVLINE |
188 S3C2410_LCDCON5_INVVFRAME |
189 S3C2410_LCDCON5_PWREN |
190 S3C2410_LCDCON5_HWSWP,
191 },
192
193 .width = 240,
194 .height = 320,
195 .xres = 240,
196 .yres = 320,
197 .bpp = 16,
Ben Dooksc6184e22007-02-17 00:52:37 +0100198 },
199};
200
Ben Dooksc6184e22007-02-17 00:52:37 +0100201
Krzysztof Helt09fe75f2007-10-16 01:28:56 -0700202static struct s3c2410fb_mach_info qt2410_fb_info __initdata = {
203 .displays = qt2410_lcd_cfg,
204 .num_displays = ARRAY_SIZE(qt2410_lcd_cfg),
205 .default_display = 0,
Ben Dooksc6184e22007-02-17 00:52:37 +0100206
207 .lpcsel = ((0xCE6) & ~7) | 1<<4,
Ben Dooksc6184e22007-02-17 00:52:37 +0100208};
209
210/* CS8900 */
211
212static struct resource qt2410_cs89x0_resources[] = {
213 [0] = {
214 .start = 0x19000000,
215 .end = 0x19000000 + 16,
216 .flags = IORESOURCE_MEM,
217 },
218 [1] = {
219 .start = IRQ_EINT9,
220 .end = IRQ_EINT9,
221 .flags = IORESOURCE_IRQ,
222 },
223};
224
225static struct platform_device qt2410_cs89x0 = {
226 .name = "cirrus-cs89x0",
227 .num_resources = ARRAY_SIZE(qt2410_cs89x0_resources),
228 .resource = qt2410_cs89x0_resources,
229};
230
231/* LED */
232
233static struct s3c24xx_led_platdata qt2410_pdata_led = {
234 .gpio = S3C2410_GPB0,
235 .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
236 .name = "led",
237 .def_trigger = "timer",
238};
239
240static struct platform_device qt2410_led = {
241 .name = "s3c24xx_led",
242 .id = 0,
243 .dev = {
244 .platform_data = &qt2410_pdata_led,
245 },
246};
247
248/* SPI */
249
250static void spi_gpio_cs(struct s3c2410_spigpio_info *spi, int cs)
251{
252 switch (cs) {
253 case BITBANG_CS_ACTIVE:
254 s3c2410_gpio_setpin(S3C2410_GPB5, 0);
255 break;
256 case BITBANG_CS_INACTIVE:
257 s3c2410_gpio_setpin(S3C2410_GPB5, 1);
258 break;
259 }
260}
261
262static struct s3c2410_spigpio_info spi_gpio_cfg = {
263 .pin_clk = S3C2410_GPG7,
264 .pin_mosi = S3C2410_GPG6,
265 .pin_miso = S3C2410_GPG5,
266 .chip_select = &spi_gpio_cs,
267};
268
269
270static struct platform_device qt2410_spi = {
271 .name = "s3c24xx-spi-gpio",
272 .id = 1,
273 .dev = {
274 .platform_data = &spi_gpio_cfg,
275 },
276};
277
278/* Board devices */
279
280static struct platform_device *qt2410_devices[] __initdata = {
281 &s3c_device_usb,
282 &s3c_device_lcd,
283 &s3c_device_wdt,
284 &s3c_device_i2c,
285 &s3c_device_iis,
286 &s3c_device_sdi,
287 &s3c_device_usbgadget,
288 &qt2410_spi,
289 &qt2410_cs89x0,
290 &qt2410_led,
291};
292
Ben Dooksc6184e22007-02-17 00:52:37 +0100293static struct mtd_partition qt2410_nand_part[] = {
294 [0] = {
295 .name = "U-Boot",
296 .size = 0x30000,
297 .offset = 0,
298 },
299 [1] = {
300 .name = "U-Boot environment",
301 .offset = 0x30000,
302 .size = 0x4000,
303 },
304 [2] = {
305 .name = "kernel",
306 .offset = 0x34000,
307 .size = SZ_2M,
308 },
309 [3] = {
310 .name = "initrd",
311 .offset = 0x234000,
312 .size = SZ_4M,
313 },
314 [4] = {
315 .name = "jffs2",
316 .offset = 0x634000,
317 .size = 0x39cc000,
318 },
319};
320
321static struct s3c2410_nand_set qt2410_nand_sets[] = {
322 [0] = {
323 .name = "NAND",
324 .nr_chips = 1,
325 .nr_partitions = ARRAY_SIZE(qt2410_nand_part),
326 .partitions = qt2410_nand_part,
327 },
328};
329
330/* choose a set of timings which should suit most 512Mbit
331 * chips and beyond.
332 */
333
334static struct s3c2410_platform_nand qt2410_nand_info = {
335 .tacls = 20,
336 .twrph0 = 60,
337 .twrph1 = 20,
338 .nr_sets = ARRAY_SIZE(qt2410_nand_sets),
339 .sets = qt2410_nand_sets,
340};
341
342/* UDC */
343
344static struct s3c2410_udc_mach_info qt2410_udc_cfg = {
345};
346
347static char tft_type = 's';
348
349static int __init qt2410_tft_setup(char *str)
350{
351 tft_type = str[0];
352 return 1;
353}
354
355__setup("tft=", qt2410_tft_setup);
356
357static void __init qt2410_map_io(void)
358{
359 s3c24xx_init_io(qt2410_iodesc, ARRAY_SIZE(qt2410_iodesc));
360 s3c24xx_init_clocks(12*1000*1000);
361 s3c24xx_init_uarts(smdk2410_uartcfgs, ARRAY_SIZE(smdk2410_uartcfgs));
Ben Dooksc6184e22007-02-17 00:52:37 +0100362}
363
364static void __init qt2410_machine_init(void)
365{
366 s3c_device_nand.dev.platform_data = &qt2410_nand_info;
367
368 switch (tft_type) {
369 case 'p': /* production */
Krzysztof Helt09fe75f2007-10-16 01:28:56 -0700370 qt2410_fb_info.default_display = 1;
Ben Dooksc6184e22007-02-17 00:52:37 +0100371 break;
372 case 'b': /* big */
Krzysztof Helt09fe75f2007-10-16 01:28:56 -0700373 qt2410_fb_info.default_display = 0;
Ben Dooksc6184e22007-02-17 00:52:37 +0100374 break;
375 case 's': /* small */
376 default:
Krzysztof Helt09fe75f2007-10-16 01:28:56 -0700377 qt2410_fb_info.default_display = 2;
Ben Dooksc6184e22007-02-17 00:52:37 +0100378 break;
379 }
Krzysztof Helt09fe75f2007-10-16 01:28:56 -0700380 s3c24xx_fb_set_platdata(&qt2410_fb_info);
Ben Dooksc6184e22007-02-17 00:52:37 +0100381
382 s3c2410_gpio_cfgpin(S3C2410_GPB0, S3C2410_GPIO_OUTPUT);
383 s3c2410_gpio_setpin(S3C2410_GPB0, 1);
384
385 s3c24xx_udc_set_platdata(&qt2410_udc_cfg);
386
387 s3c2410_gpio_cfgpin(S3C2410_GPB5, S3C2410_GPIO_OUTPUT);
388
Ben Dooks57e51712007-04-20 11:19:16 +0100389 platform_add_devices(qt2410_devices, ARRAY_SIZE(qt2410_devices));
Ben Dooksc6184e22007-02-17 00:52:37 +0100390 s3c2410_pm_init();
391}
392
393MACHINE_START(QT2410, "QT2410")
394 .phys_io = S3C2410_PA_UART,
395 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
396 .boot_params = S3C2410_SDRAM_PA + 0x100,
397 .map_io = qt2410_map_io,
398 .init_irq = s3c24xx_init_irq,
399 .init_machine = qt2410_machine_init,
400 .timer = &s3c24xx_timer,
401MACHINE_END
402
403