David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2012-2017, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | #define pr_fmt(fmt) "%s: " fmt, __func__ |
| 14 | |
| 15 | #include <linux/interrupt.h> |
| 16 | #include <linux/regmap.h> |
| 17 | #include <linux/types.h> |
| 18 | #include <linux/spmi.h> |
| 19 | #include <linux/platform_device.h> |
| 20 | #include <linux/platform_device.h> |
| 21 | #include <linux/debugfs.h> |
| 22 | #include <linux/gpio.h> |
| 23 | #include <linux/slab.h> |
| 24 | #include <linux/of.h> |
| 25 | #include <linux/of_gpio.h> |
| 26 | #include <linux/of_irq.h> |
| 27 | #include <linux/export.h> |
| 28 | #include <linux/module.h> |
| 29 | #include <linux/export.h> |
| 30 | #include <linux/qpnp/pin.h> |
| 31 | |
| 32 | #define Q_REG_ADDR(q_spec, reg_index) \ |
| 33 | ((q_spec)->offset + reg_index) |
| 34 | |
| 35 | #define Q_REG_STATUS1 0x8 |
| 36 | #define Q_REG_STATUS1_VAL_MASK 0x1 |
| 37 | #define Q_REG_STATUS1_GPIO_EN_REV0_MASK 0x2 |
| 38 | #define Q_REG_STATUS1_GPIO_EN_MASK 0x80 |
| 39 | #define Q_REG_STATUS1_MPP_EN_MASK 0x80 |
| 40 | |
| 41 | #define Q_NUM_CTL_REGS 0xD |
| 42 | |
| 43 | /* revision registers base address offsets */ |
| 44 | #define Q_REG_DIG_MINOR_REV 0x0 |
| 45 | #define Q_REG_DIG_MAJOR_REV 0x1 |
| 46 | #define Q_REG_ANA_MINOR_REV 0x2 |
| 47 | |
| 48 | /* type registers base address offsets */ |
| 49 | #define Q_REG_TYPE 0x4 |
| 50 | #define Q_REG_SUBTYPE 0x5 |
| 51 | |
| 52 | /* gpio peripheral type and subtype values */ |
| 53 | #define Q_GPIO_TYPE 0x10 |
| 54 | #define Q_GPIO_SUBTYPE_GPIO_4CH 0x1 |
| 55 | #define Q_GPIO_SUBTYPE_GPIOC_4CH 0x5 |
| 56 | #define Q_GPIO_SUBTYPE_GPIO_8CH 0x9 |
| 57 | #define Q_GPIO_SUBTYPE_GPIOC_8CH 0xD |
| 58 | #define Q_GPIO_SUBTYPE_GPIO_LV 0x10 |
| 59 | #define Q_GPIO_SUBTYPE_GPIO_MV 0x11 |
| 60 | |
| 61 | /* mpp peripheral type and subtype values */ |
| 62 | #define Q_MPP_TYPE 0x11 |
| 63 | #define Q_MPP_SUBTYPE_4CH_NO_ANA_OUT 0x3 |
| 64 | #define Q_MPP_SUBTYPE_ULT_4CH_NO_ANA_OUT 0x4 |
| 65 | #define Q_MPP_SUBTYPE_4CH_NO_SINK 0x5 |
| 66 | #define Q_MPP_SUBTYPE_ULT_4CH_NO_SINK 0x6 |
| 67 | #define Q_MPP_SUBTYPE_4CH_FULL_FUNC 0x7 |
| 68 | #define Q_MPP_SUBTYPE_8CH_FULL_FUNC 0xF |
| 69 | |
| 70 | /* control register base address offsets */ |
| 71 | #define Q_REG_MODE_CTL 0x40 |
| 72 | #define Q_REG_DIG_VIN_CTL 0x41 |
| 73 | #define Q_REG_DIG_PULL_CTL 0x42 |
| 74 | #define Q_REG_DIG_IN_CTL 0x43 |
| 75 | #define Q_REG_DIG_OUT_SRC_CTL 0x44 |
| 76 | #define Q_REG_DIG_OUT_CTL 0x45 |
| 77 | #define Q_REG_EN_CTL 0x46 |
| 78 | #define Q_REG_AOUT_CTL 0x48 |
| 79 | #define Q_REG_AIN_CTL 0x4A |
| 80 | #define Q_REG_APASS_SEL_CTL 0x4A |
| 81 | #define Q_REG_SINK_CTL 0x4C |
| 82 | |
| 83 | /* control register regs array indices */ |
| 84 | #define Q_REG_I_MODE_CTL 0 |
| 85 | #define Q_REG_I_DIG_VIN_CTL 1 |
| 86 | #define Q_REG_I_DIG_PULL_CTL 2 |
| 87 | #define Q_REG_I_DIG_IN_CTL 3 |
| 88 | #define Q_REG_I_DIG_OUT_SRC_CTL 4 |
| 89 | #define Q_REG_I_DIG_OUT_CTL 5 |
| 90 | #define Q_REG_I_EN_CTL 6 |
| 91 | #define Q_REG_I_AOUT_CTL 8 |
| 92 | #define Q_REG_I_APASS_SEL_CTL 10 |
| 93 | #define Q_REG_I_AIN_CTL 10 |
| 94 | #define Q_REG_I_SINK_CTL 12 |
| 95 | |
| 96 | /* control reg: mode */ |
| 97 | #define Q_REG_OUT_INVERT_SHIFT 0 |
| 98 | #define Q_REG_OUT_INVERT_MASK 0x1 |
| 99 | #define Q_REG_SRC_SEL_SHIFT 1 |
| 100 | #define Q_REG_SRC_SEL_MASK 0xE |
| 101 | #define Q_REG_MODE_SEL_SHIFT 4 |
| 102 | #define Q_REG_MODE_SEL_MASK 0x70 |
| 103 | #define Q_REG_LV_MV_MODE_SEL_SHIFT 0 |
| 104 | #define Q_REG_LV_MV_MODE_SEL_MASK 0x3 |
| 105 | |
| 106 | /* control reg: dig_out_src (GPIO LV/MV only) */ |
| 107 | #define Q_REG_DIG_OUT_SRC_SRC_SEL_SHIFT 0 |
| 108 | #define Q_REG_DIG_OUT_SRC_SRC_SEL_MASK 0xF |
| 109 | #define Q_REG_DIG_OUT_SRC_INVERT_SHIFT 7 |
| 110 | #define Q_REG_DIG_OUT_SRC_INVERT_MASK 0x80 |
| 111 | |
| 112 | /* control reg: dig_vin */ |
| 113 | #define Q_REG_VIN_SHIFT 0 |
| 114 | #define Q_REG_VIN_MASK 0x7 |
| 115 | |
| 116 | /* control reg: dig_pull */ |
| 117 | #define Q_REG_PULL_SHIFT 0 |
| 118 | #define Q_REG_PULL_MASK 0x7 |
| 119 | |
| 120 | /* control reg: dig_out */ |
| 121 | #define Q_REG_OUT_STRENGTH_SHIFT 0 |
| 122 | #define Q_REG_OUT_STRENGTH_MASK 0x3 |
| 123 | #define Q_REG_OUT_TYPE_SHIFT 4 |
| 124 | #define Q_REG_OUT_TYPE_MASK 0x30 |
| 125 | |
| 126 | /* control reg: dig_in_ctl */ |
| 127 | #define Q_REG_DTEST_SEL_SHIFT 0 |
| 128 | #define Q_REG_DTEST_SEL_MASK 0xF |
| 129 | #define Q_REG_LV_MV_DTEST_SEL_CFG_SHIFT 0 |
| 130 | #define Q_REG_LV_MV_DTEST_SEL_CFG_MASK 0x7 |
| 131 | #define Q_REG_LV_MV_DTEST_SEL_EN_SHIFT 7 |
| 132 | #define Q_REG_LV_MV_DTEST_SEL_EN_MASK 0x80 |
| 133 | |
| 134 | /* control reg: en */ |
| 135 | #define Q_REG_MASTER_EN_SHIFT 7 |
| 136 | #define Q_REG_MASTER_EN_MASK 0x80 |
| 137 | |
| 138 | /* control reg: ana_out */ |
| 139 | #define Q_REG_AOUT_REF_SHIFT 0 |
| 140 | #define Q_REG_AOUT_REF_MASK 0x7 |
| 141 | |
| 142 | /* control reg: ana_in */ |
| 143 | #define Q_REG_AIN_ROUTE_SHIFT 0 |
| 144 | #define Q_REG_AIN_ROUTE_MASK 0x7 |
| 145 | |
| 146 | /* control reg: sink */ |
| 147 | #define Q_REG_CS_OUT_SHIFT 0 |
| 148 | #define Q_REG_CS_OUT_MASK 0x7 |
| 149 | |
| 150 | /* control ref: apass_sel */ |
| 151 | #define Q_REG_APASS_SEL_SHIFT 0 |
| 152 | #define Q_REG_APASS_SEL_MASK 0x3 |
| 153 | |
| 154 | enum qpnp_pin_param_type { |
| 155 | Q_PIN_CFG_MODE, |
| 156 | Q_PIN_CFG_OUTPUT_TYPE, |
| 157 | Q_PIN_CFG_INVERT, |
| 158 | Q_PIN_CFG_PULL, |
| 159 | Q_PIN_CFG_VIN_SEL, |
| 160 | Q_PIN_CFG_OUT_STRENGTH, |
| 161 | Q_PIN_CFG_SRC_SEL, |
| 162 | Q_PIN_CFG_MASTER_EN, |
| 163 | Q_PIN_CFG_AOUT_REF, |
| 164 | Q_PIN_CFG_AIN_ROUTE, |
| 165 | Q_PIN_CFG_CS_OUT, |
| 166 | Q_PIN_CFG_APASS_SEL, |
| 167 | Q_PIN_CFG_DTEST_SEL, |
| 168 | Q_PIN_CFG_INVALID, |
| 169 | }; |
| 170 | |
| 171 | #define Q_NUM_PARAMS Q_PIN_CFG_INVALID |
| 172 | |
| 173 | /* param error checking */ |
| 174 | #define QPNP_PIN_GPIO_MODE_INVALID 3 |
| 175 | #define QPNP_PIN_GPIO_LV_MV_MODE_INVALID 4 |
| 176 | #define QPNP_PIN_MPP_MODE_INVALID 7 |
| 177 | #define QPNP_PIN_INVERT_INVALID 2 |
| 178 | #define QPNP_PIN_OUT_BUF_INVALID 3 |
| 179 | #define QPNP_PIN_GPIO_LV_MV_OUT_BUF_INVALID 4 |
| 180 | #define QPNP_PIN_VIN_4CH_INVALID 5 |
| 181 | #define QPNP_PIN_VIN_8CH_INVALID 8 |
| 182 | #define QPNP_PIN_GPIO_LV_VIN_INVALID 1 |
| 183 | #define QPNP_PIN_GPIO_MV_VIN_INVALID 2 |
| 184 | #define QPNP_PIN_GPIO_PULL_INVALID 6 |
| 185 | #define QPNP_PIN_MPP_PULL_INVALID 4 |
| 186 | #define QPNP_PIN_OUT_STRENGTH_INVALID 4 |
| 187 | #define QPNP_PIN_SRC_INVALID 8 |
| 188 | #define QPNP_PIN_GPIO_LV_MV_SRC_INVALID 16 |
| 189 | #define QPNP_PIN_MASTER_INVALID 2 |
| 190 | #define QPNP_PIN_AOUT_REF_INVALID 8 |
| 191 | #define QPNP_PIN_AIN_ROUTE_INVALID 8 |
| 192 | #define QPNP_PIN_CS_OUT_INVALID 8 |
| 193 | #define QPNP_PIN_APASS_SEL_INVALID 4 |
| 194 | #define QPNP_PIN_DTEST_SEL_INVALID 4 |
| 195 | |
| 196 | struct qpnp_pin_spec { |
| 197 | uint8_t slave; /* 0-15 */ |
| 198 | uint16_t offset; /* 0-255 */ |
| 199 | uint32_t gpio_chip_idx; /* offset from gpio_chip base */ |
| 200 | uint32_t pmic_pin; /* PMIC pin number */ |
| 201 | int irq; /* logical IRQ number */ |
| 202 | u8 regs[Q_NUM_CTL_REGS]; /* Control regs */ |
| 203 | u8 num_ctl_regs; /* usable number on this pin */ |
| 204 | u8 type; /* peripheral type */ |
| 205 | u8 subtype; /* peripheral subtype */ |
| 206 | u8 dig_major_rev; |
| 207 | struct device_node *node; |
| 208 | enum qpnp_pin_param_type params[Q_NUM_PARAMS]; |
| 209 | struct qpnp_pin_chip *q_chip; |
| 210 | }; |
| 211 | |
| 212 | struct qpnp_pin_chip { |
| 213 | struct gpio_chip gpio_chip; |
| 214 | struct platform_device *pdev; |
| 215 | struct regmap *regmap; |
| 216 | struct qpnp_pin_spec **pmic_pins; |
| 217 | struct qpnp_pin_spec **chip_gpios; |
| 218 | uint32_t pmic_pin_lowest; |
| 219 | uint32_t pmic_pin_highest; |
| 220 | struct device_node *int_ctrl; |
| 221 | struct list_head chip_list; |
| 222 | struct dentry *dfs_dir; |
| 223 | bool chip_registered; |
| 224 | }; |
| 225 | |
| 226 | static LIST_HEAD(qpnp_pin_chips); |
| 227 | static DEFINE_MUTEX(qpnp_pin_chips_lock); |
| 228 | |
| 229 | static inline void qpnp_pmic_pin_set_spec(struct qpnp_pin_chip *q_chip, |
| 230 | uint32_t pmic_pin, |
| 231 | struct qpnp_pin_spec *spec) |
| 232 | { |
| 233 | q_chip->pmic_pins[pmic_pin - q_chip->pmic_pin_lowest] = spec; |
| 234 | } |
| 235 | |
| 236 | static inline struct qpnp_pin_spec *qpnp_pmic_pin_get_spec( |
| 237 | struct qpnp_pin_chip *q_chip, |
| 238 | uint32_t pmic_pin) |
| 239 | { |
| 240 | if (pmic_pin < q_chip->pmic_pin_lowest || |
| 241 | pmic_pin > q_chip->pmic_pin_highest) |
| 242 | return NULL; |
| 243 | |
| 244 | return q_chip->pmic_pins[pmic_pin - q_chip->pmic_pin_lowest]; |
| 245 | } |
| 246 | |
| 247 | static inline struct qpnp_pin_spec *qpnp_chip_gpio_get_spec( |
| 248 | struct qpnp_pin_chip *q_chip, |
| 249 | uint32_t chip_gpio) |
| 250 | { |
| 251 | if (chip_gpio >= q_chip->gpio_chip.ngpio) |
| 252 | return NULL; |
| 253 | |
| 254 | return q_chip->chip_gpios[chip_gpio]; |
| 255 | } |
| 256 | |
| 257 | static inline void qpnp_chip_gpio_set_spec(struct qpnp_pin_chip *q_chip, |
| 258 | uint32_t chip_gpio, |
| 259 | struct qpnp_pin_spec *spec) |
| 260 | { |
| 261 | q_chip->chip_gpios[chip_gpio] = spec; |
| 262 | } |
| 263 | |
| 264 | static bool is_gpio_lv_mv(struct qpnp_pin_spec *q_spec) |
| 265 | { |
| 266 | if ((q_spec->type == Q_GPIO_TYPE) && |
| 267 | (q_spec->subtype == Q_GPIO_SUBTYPE_GPIO_LV || |
| 268 | q_spec->subtype == Q_GPIO_SUBTYPE_GPIO_MV)) |
| 269 | return true; |
| 270 | |
| 271 | return false; |
| 272 | } |
| 273 | |
| 274 | /* |
| 275 | * Determines whether a specified param's configuration is correct. |
| 276 | * This check is two tier. First a check is done whether the hardware |
| 277 | * supports this param and value requested. The second check validates |
| 278 | * that the configuration is correct, given the fact that the hardware |
| 279 | * supports it. |
| 280 | * |
| 281 | * Returns |
| 282 | * -ENXIO is the hardware does not support this param. |
| 283 | * -EINVAL if the the hardware does support this param, but the |
| 284 | * requested value is outside the supported range. |
| 285 | */ |
| 286 | static int qpnp_pin_check_config(enum qpnp_pin_param_type idx, |
| 287 | struct qpnp_pin_spec *q_spec, uint32_t val) |
| 288 | { |
| 289 | u8 subtype = q_spec->subtype; |
| 290 | |
| 291 | switch (idx) { |
| 292 | case Q_PIN_CFG_MODE: |
| 293 | if (q_spec->type == Q_GPIO_TYPE) { |
| 294 | if (is_gpio_lv_mv(q_spec)) { |
| 295 | if (val >= QPNP_PIN_GPIO_LV_MV_MODE_INVALID) |
| 296 | return -EINVAL; |
| 297 | } else if (val >= QPNP_PIN_GPIO_MODE_INVALID) { |
| 298 | return -EINVAL; |
| 299 | } |
| 300 | } else if (q_spec->type == Q_MPP_TYPE) { |
| 301 | if (val >= QPNP_PIN_MPP_MODE_INVALID) |
| 302 | return -EINVAL; |
| 303 | if ((subtype == Q_MPP_SUBTYPE_ULT_4CH_NO_ANA_OUT || |
| 304 | subtype == Q_MPP_SUBTYPE_ULT_4CH_NO_SINK) && |
| 305 | (val == QPNP_PIN_MODE_BIDIR)) |
| 306 | return -ENXIO; |
| 307 | } |
| 308 | break; |
| 309 | case Q_PIN_CFG_OUTPUT_TYPE: |
| 310 | if (q_spec->type != Q_GPIO_TYPE) |
| 311 | return -ENXIO; |
| 312 | if ((val == QPNP_PIN_OUT_BUF_OPEN_DRAIN_NMOS || |
| 313 | val == QPNP_PIN_OUT_BUF_OPEN_DRAIN_PMOS) && |
| 314 | (subtype == Q_GPIO_SUBTYPE_GPIOC_4CH || |
| 315 | (subtype == Q_GPIO_SUBTYPE_GPIOC_8CH))) |
| 316 | return -EINVAL; |
| 317 | else if (is_gpio_lv_mv(q_spec) && |
| 318 | val >= QPNP_PIN_GPIO_LV_MV_OUT_BUF_INVALID) |
| 319 | return -EINVAL; |
| 320 | else if (val >= QPNP_PIN_OUT_BUF_INVALID) |
| 321 | return -EINVAL; |
| 322 | break; |
| 323 | case Q_PIN_CFG_INVERT: |
| 324 | if (val >= QPNP_PIN_INVERT_INVALID) |
| 325 | return -EINVAL; |
| 326 | break; |
| 327 | case Q_PIN_CFG_PULL: |
| 328 | if (q_spec->type == Q_GPIO_TYPE && |
| 329 | val >= QPNP_PIN_GPIO_PULL_INVALID) |
| 330 | return -EINVAL; |
| 331 | if (q_spec->type == Q_MPP_TYPE) { |
| 332 | if (val >= QPNP_PIN_MPP_PULL_INVALID) |
| 333 | return -EINVAL; |
| 334 | if (subtype == Q_MPP_SUBTYPE_ULT_4CH_NO_ANA_OUT || |
| 335 | subtype == Q_MPP_SUBTYPE_ULT_4CH_NO_SINK) |
| 336 | return -ENXIO; |
| 337 | } |
| 338 | break; |
| 339 | case Q_PIN_CFG_VIN_SEL: |
| 340 | if (is_gpio_lv_mv(q_spec)) { |
| 341 | if (subtype == Q_GPIO_SUBTYPE_GPIO_LV) { |
| 342 | if (val >= QPNP_PIN_GPIO_LV_VIN_INVALID) |
| 343 | return -EINVAL; |
| 344 | } else { |
| 345 | if (val >= QPNP_PIN_GPIO_MV_VIN_INVALID) |
| 346 | return -EINVAL; |
| 347 | } |
| 348 | } else if (val >= QPNP_PIN_VIN_8CH_INVALID) { |
| 349 | return -EINVAL; |
| 350 | } else if (val >= QPNP_PIN_VIN_4CH_INVALID) { |
| 351 | if (q_spec->type == Q_GPIO_TYPE && |
| 352 | (subtype == Q_GPIO_SUBTYPE_GPIO_4CH || |
| 353 | subtype == Q_GPIO_SUBTYPE_GPIOC_4CH)) |
| 354 | return -EINVAL; |
| 355 | if (q_spec->type == Q_MPP_TYPE && |
| 356 | (subtype == Q_MPP_SUBTYPE_4CH_NO_ANA_OUT || |
| 357 | subtype == Q_MPP_SUBTYPE_4CH_NO_SINK || |
| 358 | subtype == Q_MPP_SUBTYPE_4CH_FULL_FUNC || |
| 359 | subtype == Q_MPP_SUBTYPE_ULT_4CH_NO_ANA_OUT || |
| 360 | subtype == Q_MPP_SUBTYPE_ULT_4CH_NO_SINK)) |
| 361 | return -EINVAL; |
| 362 | } |
| 363 | break; |
| 364 | case Q_PIN_CFG_OUT_STRENGTH: |
| 365 | if (q_spec->type != Q_GPIO_TYPE) |
| 366 | return -ENXIO; |
| 367 | if (val >= QPNP_PIN_OUT_STRENGTH_INVALID || |
| 368 | val == 0) |
| 369 | return -EINVAL; |
| 370 | break; |
| 371 | case Q_PIN_CFG_SRC_SEL: |
| 372 | if (q_spec->type == Q_MPP_TYPE && |
| 373 | (val == QPNP_PIN_SEL_FUNC_1 || |
| 374 | val == QPNP_PIN_SEL_FUNC_2)) |
| 375 | return -EINVAL; |
| 376 | if (is_gpio_lv_mv(q_spec)) { |
| 377 | if (val >= QPNP_PIN_GPIO_LV_MV_SRC_INVALID) |
| 378 | return -EINVAL; |
| 379 | } else if (val >= QPNP_PIN_SRC_INVALID) { |
| 380 | return -EINVAL; |
| 381 | } |
| 382 | break; |
| 383 | case Q_PIN_CFG_MASTER_EN: |
| 384 | if (val >= QPNP_PIN_MASTER_INVALID) |
| 385 | return -EINVAL; |
| 386 | break; |
| 387 | case Q_PIN_CFG_AOUT_REF: |
| 388 | if (q_spec->type != Q_MPP_TYPE) |
| 389 | return -ENXIO; |
| 390 | if (subtype == Q_MPP_SUBTYPE_4CH_NO_ANA_OUT || |
| 391 | subtype == Q_MPP_SUBTYPE_ULT_4CH_NO_ANA_OUT) |
| 392 | return -ENXIO; |
| 393 | if (val >= QPNP_PIN_AOUT_REF_INVALID) |
| 394 | return -EINVAL; |
| 395 | break; |
| 396 | case Q_PIN_CFG_AIN_ROUTE: |
| 397 | if (q_spec->type != Q_MPP_TYPE) |
| 398 | return -ENXIO; |
| 399 | if (val >= QPNP_PIN_AIN_ROUTE_INVALID) |
| 400 | return -EINVAL; |
| 401 | break; |
| 402 | case Q_PIN_CFG_CS_OUT: |
| 403 | if (q_spec->type != Q_MPP_TYPE) |
| 404 | return -ENXIO; |
| 405 | if (subtype == Q_MPP_SUBTYPE_4CH_NO_SINK || |
| 406 | subtype == Q_MPP_SUBTYPE_ULT_4CH_NO_SINK) |
| 407 | return -ENXIO; |
| 408 | if (val >= QPNP_PIN_CS_OUT_INVALID) |
| 409 | return -EINVAL; |
| 410 | break; |
| 411 | case Q_PIN_CFG_APASS_SEL: |
| 412 | if (!is_gpio_lv_mv(q_spec)) |
| 413 | return -ENXIO; |
| 414 | if (val >= QPNP_PIN_APASS_SEL_INVALID) |
| 415 | return -EINVAL; |
| 416 | break; |
| 417 | case Q_PIN_CFG_DTEST_SEL: |
| 418 | if (val > QPNP_PIN_DTEST_SEL_INVALID) |
| 419 | return -EINVAL; |
| 420 | break; |
| 421 | default: |
| 422 | pr_err("invalid param type %u specified\n", idx); |
| 423 | return -EINVAL; |
| 424 | } |
| 425 | return 0; |
| 426 | } |
| 427 | |
| 428 | #define Q_CHK_INVALID(idx, q_spec, val) \ |
| 429 | (qpnp_pin_check_config(idx, q_spec, val) == -EINVAL) |
| 430 | |
| 431 | static int qpnp_pin_check_constraints(struct qpnp_pin_spec *q_spec, |
| 432 | struct qpnp_pin_cfg *param) |
| 433 | { |
| 434 | int pin = q_spec->pmic_pin; |
| 435 | const char *name; |
| 436 | |
| 437 | name = (q_spec->type == Q_GPIO_TYPE) ? "gpio" : "mpp"; |
| 438 | |
| 439 | if (Q_CHK_INVALID(Q_PIN_CFG_MODE, q_spec, param->mode)) |
| 440 | pr_err("invalid direction value %d for %s %d\n", |
| 441 | param->mode, name, pin); |
| 442 | else if (Q_CHK_INVALID(Q_PIN_CFG_INVERT, q_spec, param->invert)) |
| 443 | pr_err("invalid invert polarity value %d for %s %d\n", |
| 444 | param->invert, name, pin); |
| 445 | else if (Q_CHK_INVALID(Q_PIN_CFG_SRC_SEL, q_spec, param->src_sel)) |
| 446 | pr_err("invalid source select value %d for %s %d\n", |
| 447 | param->src_sel, name, pin); |
| 448 | else if (Q_CHK_INVALID(Q_PIN_CFG_OUT_STRENGTH, |
| 449 | q_spec, param->out_strength)) |
| 450 | pr_err("invalid out strength value %d for %s %d\n", |
| 451 | param->out_strength, name, pin); |
| 452 | else if (Q_CHK_INVALID(Q_PIN_CFG_OUTPUT_TYPE, |
| 453 | q_spec, param->output_type)) |
| 454 | pr_err("invalid out type value %d for %s %d\n", |
| 455 | param->output_type, name, pin); |
| 456 | else if (Q_CHK_INVALID(Q_PIN_CFG_VIN_SEL, q_spec, param->vin_sel)) |
| 457 | pr_err("invalid vin select %d value for %s %d\n", |
| 458 | param->vin_sel, name, pin); |
| 459 | else if (Q_CHK_INVALID(Q_PIN_CFG_PULL, q_spec, param->pull)) |
| 460 | pr_err("invalid pull value %d for pin %s %d\n", |
| 461 | param->pull, name, pin); |
| 462 | else if (Q_CHK_INVALID(Q_PIN_CFG_MASTER_EN, q_spec, param->master_en)) |
| 463 | pr_err("invalid master_en value %d for %s %d\n", |
| 464 | param->master_en, name, pin); |
| 465 | else if (Q_CHK_INVALID(Q_PIN_CFG_AOUT_REF, q_spec, param->aout_ref)) |
| 466 | pr_err("invalid aout_reg value %d for %s %d\n", |
| 467 | param->aout_ref, name, pin); |
| 468 | else if (Q_CHK_INVALID(Q_PIN_CFG_AIN_ROUTE, q_spec, param->ain_route)) |
| 469 | pr_err("invalid ain_route value %d for %s %d\n", |
| 470 | param->ain_route, name, pin); |
| 471 | else if (Q_CHK_INVALID(Q_PIN_CFG_CS_OUT, q_spec, param->cs_out)) |
| 472 | pr_err("invalid cs_out value %d for %s %d\n", |
| 473 | param->cs_out, name, pin); |
| 474 | else if (Q_CHK_INVALID(Q_PIN_CFG_APASS_SEL, q_spec, param->apass_sel)) |
| 475 | pr_err("invalid apass_sel value %d for %s %d\n", |
| 476 | param->apass_sel, name, pin); |
| 477 | else if (Q_CHK_INVALID(Q_PIN_CFG_DTEST_SEL, q_spec, param->dtest_sel)) |
| 478 | pr_err("invalid dtest_sel value %d for %s %d\n", |
| 479 | param->dtest_sel, name, pin); |
| 480 | else |
| 481 | return 0; |
| 482 | |
| 483 | return -EINVAL; |
| 484 | } |
| 485 | |
| 486 | static inline u8 q_reg_get(u8 *reg, int shift, int mask) |
| 487 | { |
| 488 | return (*reg & mask) >> shift; |
| 489 | } |
| 490 | |
| 491 | static inline void q_reg_set(u8 *reg, int shift, int mask, int value) |
| 492 | { |
| 493 | *reg |= (value << shift) & mask; |
| 494 | } |
| 495 | |
| 496 | static inline void q_reg_clr_set(u8 *reg, int shift, int mask, int value) |
| 497 | { |
| 498 | *reg &= ~mask; |
| 499 | *reg |= (value << shift) & mask; |
| 500 | } |
| 501 | |
| 502 | /* |
| 503 | * Calculate the minimum number of registers that must be read / written |
| 504 | * in order to satisfy the full feature set of the given pin. |
| 505 | */ |
| 506 | static int qpnp_pin_ctl_regs_init(struct qpnp_pin_spec *q_spec) |
| 507 | { |
| 508 | if (q_spec->type == Q_GPIO_TYPE) { |
| 509 | if (is_gpio_lv_mv(q_spec)) |
| 510 | q_spec->num_ctl_regs = 11; |
| 511 | else |
| 512 | q_spec->num_ctl_regs = 7; |
| 513 | } else if (q_spec->type == Q_MPP_TYPE) { |
| 514 | switch (q_spec->subtype) { |
| 515 | case Q_MPP_SUBTYPE_4CH_NO_SINK: |
| 516 | case Q_MPP_SUBTYPE_ULT_4CH_NO_SINK: |
| 517 | q_spec->num_ctl_regs = 12; |
| 518 | break; |
| 519 | case Q_MPP_SUBTYPE_4CH_NO_ANA_OUT: |
| 520 | case Q_MPP_SUBTYPE_ULT_4CH_NO_ANA_OUT: |
| 521 | case Q_MPP_SUBTYPE_4CH_FULL_FUNC: |
| 522 | case Q_MPP_SUBTYPE_8CH_FULL_FUNC: |
| 523 | q_spec->num_ctl_regs = 13; |
| 524 | break; |
| 525 | default: |
| 526 | pr_err("Invalid MPP subtype 0x%x\n", q_spec->subtype); |
| 527 | return -EINVAL; |
| 528 | } |
| 529 | } else { |
| 530 | pr_err("Invalid type 0x%x\n", q_spec->type); |
| 531 | return -EINVAL; |
| 532 | } |
| 533 | return 0; |
| 534 | } |
| 535 | |
| 536 | static int qpnp_pin_read_regs(struct qpnp_pin_chip *q_chip, |
| 537 | struct qpnp_pin_spec *q_spec) |
| 538 | { |
| 539 | int bytes_left = q_spec->num_ctl_regs; |
| 540 | int rc; |
| 541 | char *buf_p = &q_spec->regs[0]; |
| 542 | u16 reg_addr = Q_REG_ADDR(q_spec, Q_REG_MODE_CTL); |
| 543 | |
| 544 | while (bytes_left > 0) { |
| 545 | rc = regmap_bulk_read(q_chip->regmap, reg_addr, buf_p, |
| 546 | bytes_left < 8 ? bytes_left : 8); |
| 547 | if (rc) |
| 548 | return rc; |
| 549 | bytes_left -= 8; |
| 550 | buf_p += 8; |
| 551 | reg_addr += 8; |
| 552 | } |
| 553 | return 0; |
| 554 | } |
| 555 | |
| 556 | static int qpnp_pin_write_regs(struct qpnp_pin_chip *q_chip, |
| 557 | struct qpnp_pin_spec *q_spec) |
| 558 | { |
| 559 | int bytes_left = q_spec->num_ctl_regs; |
| 560 | int rc; |
| 561 | char *buf_p = &q_spec->regs[0]; |
| 562 | u16 reg_addr = Q_REG_ADDR(q_spec, Q_REG_MODE_CTL); |
| 563 | |
| 564 | while (bytes_left > 0) { |
| 565 | rc = regmap_bulk_write(q_chip->regmap, reg_addr, buf_p, |
| 566 | bytes_left < 8 ? bytes_left : 8); |
| 567 | if (rc) |
| 568 | return rc; |
| 569 | bytes_left -= 8; |
| 570 | buf_p += 8; |
| 571 | reg_addr += 8; |
| 572 | } |
| 573 | return 0; |
| 574 | } |
| 575 | |
| 576 | static int qpnp_pin_cache_regs(struct qpnp_pin_chip *q_chip, |
| 577 | struct qpnp_pin_spec *q_spec) |
| 578 | { |
| 579 | int rc; |
| 580 | struct device *dev = &q_chip->pdev->dev; |
| 581 | |
| 582 | rc = qpnp_pin_read_regs(q_chip, q_spec); |
| 583 | if (rc) |
| 584 | dev_err(dev, "%s: unable to read control regs\n", __func__); |
| 585 | |
| 586 | return rc; |
| 587 | } |
| 588 | |
| 589 | #define Q_HAVE_HW_SP(idx, q_spec, val) \ |
| 590 | (qpnp_pin_check_config(idx, q_spec, val) == 0) |
| 591 | |
| 592 | static int _qpnp_pin_config(struct qpnp_pin_chip *q_chip, |
| 593 | struct qpnp_pin_spec *q_spec, |
| 594 | struct qpnp_pin_cfg *param) |
| 595 | { |
| 596 | struct device *dev = &q_chip->pdev->dev; |
| 597 | int rc; |
| 598 | u8 shift, mask, *reg; |
| 599 | |
| 600 | rc = qpnp_pin_check_constraints(q_spec, param); |
| 601 | if (rc) |
| 602 | goto gpio_cfg; |
| 603 | |
| 604 | /* set mode */ |
| 605 | if (Q_HAVE_HW_SP(Q_PIN_CFG_MODE, q_spec, param->mode)) { |
| 606 | if (is_gpio_lv_mv(q_spec)) { |
| 607 | shift = Q_REG_LV_MV_MODE_SEL_SHIFT; |
| 608 | mask = Q_REG_LV_MV_MODE_SEL_MASK; |
| 609 | } else { |
| 610 | shift = Q_REG_MODE_SEL_SHIFT; |
| 611 | mask = Q_REG_MODE_SEL_MASK; |
| 612 | } |
| 613 | q_reg_clr_set(&q_spec->regs[Q_REG_I_MODE_CTL], |
| 614 | shift, mask, param->mode); |
| 615 | } |
| 616 | |
| 617 | /* output specific configuration */ |
| 618 | if (Q_HAVE_HW_SP(Q_PIN_CFG_INVERT, q_spec, param->invert)) { |
| 619 | if (is_gpio_lv_mv(q_spec)) { |
| 620 | shift = Q_REG_DIG_OUT_SRC_INVERT_SHIFT; |
| 621 | mask = Q_REG_DIG_OUT_SRC_INVERT_MASK; |
| 622 | reg = &q_spec->regs[Q_REG_I_DIG_OUT_SRC_CTL]; |
| 623 | } else { |
| 624 | shift = Q_REG_OUT_INVERT_SHIFT; |
| 625 | mask = Q_REG_OUT_INVERT_MASK; |
| 626 | reg = &q_spec->regs[Q_REG_I_MODE_CTL]; |
| 627 | } |
| 628 | q_reg_clr_set(reg, shift, mask, param->invert); |
| 629 | } |
| 630 | |
| 631 | if (Q_HAVE_HW_SP(Q_PIN_CFG_SRC_SEL, q_spec, param->src_sel)) { |
| 632 | if (is_gpio_lv_mv(q_spec)) { |
| 633 | shift = Q_REG_DIG_OUT_SRC_SRC_SEL_SHIFT; |
| 634 | mask = Q_REG_DIG_OUT_SRC_SRC_SEL_MASK; |
| 635 | reg = &q_spec->regs[Q_REG_I_DIG_OUT_SRC_CTL]; |
| 636 | } else { |
| 637 | shift = Q_REG_SRC_SEL_SHIFT; |
| 638 | mask = Q_REG_SRC_SEL_MASK; |
| 639 | reg = &q_spec->regs[Q_REG_I_MODE_CTL]; |
| 640 | } |
| 641 | q_reg_clr_set(reg, shift, mask, param->src_sel); |
| 642 | } |
| 643 | |
| 644 | if (Q_HAVE_HW_SP(Q_PIN_CFG_OUT_STRENGTH, q_spec, param->out_strength)) |
| 645 | q_reg_clr_set(&q_spec->regs[Q_REG_I_DIG_OUT_CTL], |
| 646 | Q_REG_OUT_STRENGTH_SHIFT, Q_REG_OUT_STRENGTH_MASK, |
| 647 | param->out_strength); |
| 648 | if (Q_HAVE_HW_SP(Q_PIN_CFG_OUTPUT_TYPE, q_spec, param->output_type)) |
| 649 | q_reg_clr_set(&q_spec->regs[Q_REG_I_DIG_OUT_CTL], |
| 650 | Q_REG_OUT_TYPE_SHIFT, Q_REG_OUT_TYPE_MASK, |
| 651 | param->output_type); |
| 652 | |
| 653 | /* input config */ |
| 654 | if (Q_HAVE_HW_SP(Q_PIN_CFG_DTEST_SEL, q_spec, param->dtest_sel) |
| 655 | && param->dtest_sel) { |
| 656 | if (is_gpio_lv_mv(q_spec)) { |
| 657 | q_reg_clr_set(&q_spec->regs[Q_REG_I_DIG_IN_CTL], |
| 658 | Q_REG_LV_MV_DTEST_SEL_CFG_SHIFT, |
| 659 | Q_REG_LV_MV_DTEST_SEL_CFG_MASK, |
| 660 | param->dtest_sel - 1); |
| 661 | q_reg_clr_set(&q_spec->regs[Q_REG_I_DIG_IN_CTL], |
| 662 | Q_REG_LV_MV_DTEST_SEL_EN_SHIFT, |
| 663 | Q_REG_LV_MV_DTEST_SEL_EN_MASK, 0x1); |
| 664 | } else { |
| 665 | q_reg_clr_set(&q_spec->regs[Q_REG_I_DIG_IN_CTL], |
| 666 | Q_REG_DTEST_SEL_SHIFT, |
| 667 | Q_REG_DTEST_SEL_MASK, |
| 668 | BIT(param->dtest_sel - 1)); |
| 669 | } |
| 670 | } |
| 671 | |
| 672 | /* config applicable for both input / output */ |
| 673 | if (Q_HAVE_HW_SP(Q_PIN_CFG_VIN_SEL, q_spec, param->vin_sel)) |
| 674 | q_reg_clr_set(&q_spec->regs[Q_REG_I_DIG_VIN_CTL], |
| 675 | Q_REG_VIN_SHIFT, Q_REG_VIN_MASK, |
| 676 | param->vin_sel); |
| 677 | if (Q_HAVE_HW_SP(Q_PIN_CFG_PULL, q_spec, param->pull)) |
| 678 | q_reg_clr_set(&q_spec->regs[Q_REG_I_DIG_PULL_CTL], |
| 679 | Q_REG_PULL_SHIFT, Q_REG_PULL_MASK, |
| 680 | param->pull); |
| 681 | if (Q_HAVE_HW_SP(Q_PIN_CFG_MASTER_EN, q_spec, param->master_en)) |
| 682 | q_reg_clr_set(&q_spec->regs[Q_REG_I_EN_CTL], |
| 683 | Q_REG_MASTER_EN_SHIFT, Q_REG_MASTER_EN_MASK, |
| 684 | param->master_en); |
| 685 | |
| 686 | /* mpp specific config */ |
| 687 | if (Q_HAVE_HW_SP(Q_PIN_CFG_AOUT_REF, q_spec, param->aout_ref)) |
| 688 | q_reg_clr_set(&q_spec->regs[Q_REG_I_AOUT_CTL], |
| 689 | Q_REG_AOUT_REF_SHIFT, Q_REG_AOUT_REF_MASK, |
| 690 | param->aout_ref); |
| 691 | if (Q_HAVE_HW_SP(Q_PIN_CFG_AIN_ROUTE, q_spec, param->ain_route)) |
| 692 | q_reg_clr_set(&q_spec->regs[Q_REG_I_AIN_CTL], |
| 693 | Q_REG_AIN_ROUTE_SHIFT, Q_REG_AIN_ROUTE_MASK, |
| 694 | param->ain_route); |
| 695 | if (Q_HAVE_HW_SP(Q_PIN_CFG_CS_OUT, q_spec, param->cs_out)) |
| 696 | q_reg_clr_set(&q_spec->regs[Q_REG_I_SINK_CTL], |
| 697 | Q_REG_CS_OUT_SHIFT, Q_REG_CS_OUT_MASK, |
| 698 | param->cs_out); |
| 699 | if (Q_HAVE_HW_SP(Q_PIN_CFG_APASS_SEL, q_spec, param->apass_sel)) |
| 700 | q_reg_clr_set(&q_spec->regs[Q_REG_I_APASS_SEL_CTL], |
| 701 | Q_REG_APASS_SEL_SHIFT, Q_REG_APASS_SEL_MASK, |
| 702 | param->apass_sel); |
| 703 | |
| 704 | rc = qpnp_pin_write_regs(q_chip, q_spec); |
| 705 | if (rc) { |
| 706 | dev_err(&q_chip->pdev->dev, |
| 707 | "%s: unable to write master enable\n", |
| 708 | __func__); |
| 709 | goto gpio_cfg; |
| 710 | } |
| 711 | |
| 712 | return 0; |
| 713 | |
| 714 | gpio_cfg: |
| 715 | dev_err(dev, "%s: unable to set default config for pmic pin %d\n", |
| 716 | __func__, q_spec->pmic_pin); |
| 717 | |
| 718 | return rc; |
| 719 | } |
| 720 | |
| 721 | int qpnp_pin_config(int gpio, struct qpnp_pin_cfg *param) |
| 722 | { |
| 723 | int rc, chip_offset; |
| 724 | struct qpnp_pin_chip *q_chip; |
| 725 | struct qpnp_pin_spec *q_spec = NULL; |
| 726 | struct gpio_chip *gpio_chip; |
| 727 | |
| 728 | if (param == NULL) |
| 729 | return -EINVAL; |
| 730 | |
| 731 | mutex_lock(&qpnp_pin_chips_lock); |
| 732 | list_for_each_entry(q_chip, &qpnp_pin_chips, chip_list) { |
| 733 | gpio_chip = &q_chip->gpio_chip; |
| 734 | if (gpio >= gpio_chip->base |
| 735 | && gpio < gpio_chip->base + gpio_chip->ngpio) { |
| 736 | chip_offset = gpio - gpio_chip->base; |
| 737 | q_spec = qpnp_chip_gpio_get_spec(q_chip, chip_offset); |
| 738 | if (WARN_ON(!q_spec)) { |
| 739 | mutex_unlock(&qpnp_pin_chips_lock); |
| 740 | return -ENODEV; |
| 741 | } |
| 742 | break; |
| 743 | } |
| 744 | } |
| 745 | mutex_unlock(&qpnp_pin_chips_lock); |
| 746 | |
| 747 | if (!q_spec) |
| 748 | return -ENODEV; |
| 749 | |
| 750 | rc = _qpnp_pin_config(q_chip, q_spec, param); |
| 751 | |
| 752 | return rc; |
| 753 | } |
| 754 | EXPORT_SYMBOL(qpnp_pin_config); |
| 755 | |
| 756 | int qpnp_pin_map(const char *name, uint32_t pmic_pin) |
| 757 | { |
| 758 | struct qpnp_pin_chip *q_chip; |
| 759 | struct qpnp_pin_spec *q_spec = NULL; |
| 760 | |
| 761 | if (!name) |
| 762 | return -EINVAL; |
| 763 | |
| 764 | mutex_lock(&qpnp_pin_chips_lock); |
| 765 | list_for_each_entry(q_chip, &qpnp_pin_chips, chip_list) { |
| 766 | if (strcmp(q_chip->gpio_chip.label, name) != 0) |
| 767 | continue; |
| 768 | if (q_chip->pmic_pin_lowest <= pmic_pin && |
| 769 | q_chip->pmic_pin_highest >= pmic_pin) { |
| 770 | q_spec = qpnp_pmic_pin_get_spec(q_chip, pmic_pin); |
| 771 | mutex_unlock(&qpnp_pin_chips_lock); |
| 772 | if (WARN_ON(!q_spec)) |
| 773 | return -ENODEV; |
| 774 | return q_chip->gpio_chip.base + q_spec->gpio_chip_idx; |
| 775 | } |
| 776 | } |
| 777 | mutex_unlock(&qpnp_pin_chips_lock); |
| 778 | return -EINVAL; |
| 779 | } |
| 780 | EXPORT_SYMBOL(qpnp_pin_map); |
| 781 | |
| 782 | static int qpnp_pin_to_irq(struct gpio_chip *gpio_chip, unsigned int offset) |
| 783 | { |
| 784 | struct qpnp_pin_chip *q_chip = gpiochip_get_data(gpio_chip); |
| 785 | struct qpnp_pin_spec *q_spec; |
| 786 | struct of_phandle_args oirq; |
| 787 | |
| 788 | q_spec = qpnp_chip_gpio_get_spec(q_chip, offset); |
| 789 | if (!q_spec) |
| 790 | return -EINVAL; |
| 791 | |
| 792 | /* if we have mapped this pin previously return the virq */ |
| 793 | if (q_spec->irq) |
| 794 | return q_spec->irq; |
| 795 | |
| 796 | /* call into irq_domain to get irq mapping */ |
| 797 | oirq.np = q_chip->int_ctrl; |
| 798 | oirq.args[0] = to_spmi_device(q_chip->pdev->dev.parent)->usid; |
| 799 | oirq.args[1] = (q_spec->offset >> 8) & 0xFF; |
| 800 | oirq.args[2] = 0; |
| 801 | oirq.args[3] = IRQ_TYPE_NONE; |
| 802 | oirq.args_count = 4; |
| 803 | |
| 804 | q_spec->irq = irq_create_of_mapping(&oirq); |
| 805 | if (!q_spec->irq) { |
| 806 | dev_err(&q_chip->pdev->dev, "%s: invalid irq for gpio %u\n", |
| 807 | __func__, q_spec->pmic_pin); |
| 808 | WARN_ON(1); |
| 809 | return -EINVAL; |
| 810 | } |
| 811 | |
| 812 | return q_spec->irq; |
| 813 | } |
| 814 | |
| 815 | static int qpnp_pin_get(struct gpio_chip *gpio_chip, unsigned int offset) |
| 816 | { |
| 817 | struct qpnp_pin_chip *q_chip = gpiochip_get_data(gpio_chip); |
| 818 | struct qpnp_pin_spec *q_spec = NULL; |
| 819 | u8 buf, en_mask, shift, mask, reg; |
| 820 | unsigned int val; |
| 821 | int rc; |
| 822 | |
| 823 | if (WARN_ON(!q_chip)) |
| 824 | return -ENODEV; |
| 825 | |
| 826 | q_spec = qpnp_chip_gpio_get_spec(q_chip, offset); |
| 827 | if (WARN_ON(!q_spec)) |
| 828 | return -ENODEV; |
| 829 | |
| 830 | if (is_gpio_lv_mv(q_spec)) { |
| 831 | mask = Q_REG_LV_MV_MODE_SEL_MASK; |
| 832 | shift = Q_REG_LV_MV_MODE_SEL_SHIFT; |
| 833 | } else { |
| 834 | mask = Q_REG_MODE_SEL_MASK; |
| 835 | shift = Q_REG_MODE_SEL_SHIFT; |
| 836 | } |
| 837 | |
| 838 | /* gpio val is from RT status iff input is enabled */ |
| 839 | if (q_reg_get(&q_spec->regs[Q_REG_I_MODE_CTL], shift, mask) |
| 840 | == QPNP_PIN_MODE_DIG_IN) { |
| 841 | rc = regmap_read(q_chip->regmap, |
| 842 | Q_REG_ADDR(q_spec, Q_REG_STATUS1), &val); |
| 843 | if (rc) |
| 844 | return rc; |
| 845 | buf = val; |
| 846 | |
| 847 | if (q_spec->type == Q_GPIO_TYPE && q_spec->dig_major_rev == 0) |
| 848 | en_mask = Q_REG_STATUS1_GPIO_EN_REV0_MASK; |
| 849 | else if (q_spec->type == Q_GPIO_TYPE && |
| 850 | q_spec->dig_major_rev > 0) |
| 851 | en_mask = Q_REG_STATUS1_GPIO_EN_MASK; |
| 852 | else /* MPP */ |
| 853 | en_mask = Q_REG_STATUS1_MPP_EN_MASK; |
| 854 | |
| 855 | if (!(buf & en_mask)) |
| 856 | return -EPERM; |
| 857 | |
| 858 | return buf & Q_REG_STATUS1_VAL_MASK; |
| 859 | } |
| 860 | |
| 861 | if (is_gpio_lv_mv(q_spec)) { |
| 862 | shift = Q_REG_DIG_OUT_SRC_INVERT_SHIFT; |
| 863 | mask = Q_REG_DIG_OUT_SRC_INVERT_MASK; |
| 864 | reg = q_spec->regs[Q_REG_I_DIG_OUT_SRC_CTL]; |
| 865 | } else { |
| 866 | shift = Q_REG_OUT_INVERT_SHIFT; |
| 867 | mask = Q_REG_OUT_INVERT_MASK; |
| 868 | reg = q_spec->regs[Q_REG_I_MODE_CTL]; |
| 869 | } |
| 870 | |
| 871 | return (reg & mask) >> shift; |
| 872 | } |
| 873 | |
| 874 | static int __qpnp_pin_set(struct qpnp_pin_chip *q_chip, |
| 875 | struct qpnp_pin_spec *q_spec, int value) |
| 876 | { |
| 877 | int rc; |
| 878 | u8 shift, mask, *reg; |
| 879 | u16 address; |
| 880 | |
| 881 | if (!q_chip || !q_spec) |
| 882 | return -EINVAL; |
| 883 | |
| 884 | if (is_gpio_lv_mv(q_spec)) { |
| 885 | shift = Q_REG_DIG_OUT_SRC_INVERT_SHIFT; |
| 886 | mask = Q_REG_DIG_OUT_SRC_INVERT_MASK; |
| 887 | reg = &q_spec->regs[Q_REG_I_DIG_OUT_SRC_CTL]; |
| 888 | address = Q_REG_ADDR(q_spec, Q_REG_DIG_OUT_SRC_CTL); |
| 889 | } else { |
| 890 | shift = Q_REG_OUT_INVERT_SHIFT; |
| 891 | mask = Q_REG_OUT_INVERT_MASK; |
| 892 | reg = &q_spec->regs[Q_REG_I_MODE_CTL]; |
| 893 | address = Q_REG_ADDR(q_spec, Q_REG_MODE_CTL); |
| 894 | } |
| 895 | |
| 896 | q_reg_clr_set(reg, shift, mask, !!value); |
| 897 | |
| 898 | rc = regmap_write(q_chip->regmap, address, *reg); |
| 899 | if (rc) |
| 900 | dev_err(&q_chip->pdev->dev, "%s: spmi write failed\n", |
| 901 | __func__); |
| 902 | return rc; |
| 903 | } |
| 904 | |
| 905 | |
| 906 | static void qpnp_pin_set(struct gpio_chip *gpio_chip, |
| 907 | unsigned int offset, int value) |
| 908 | { |
| 909 | struct qpnp_pin_chip *q_chip = gpiochip_get_data(gpio_chip); |
| 910 | struct qpnp_pin_spec *q_spec; |
| 911 | |
| 912 | if (WARN_ON(!q_chip)) |
| 913 | return; |
| 914 | |
| 915 | q_spec = qpnp_chip_gpio_get_spec(q_chip, offset); |
| 916 | if (WARN_ON(!q_spec)) |
| 917 | return; |
| 918 | |
| 919 | __qpnp_pin_set(q_chip, q_spec, value); |
| 920 | } |
| 921 | |
| 922 | static int qpnp_pin_set_mode(struct qpnp_pin_chip *q_chip, |
| 923 | struct qpnp_pin_spec *q_spec, int mode) |
| 924 | { |
| 925 | int rc; |
| 926 | u8 shift, mask; |
| 927 | |
| 928 | if (!q_chip || !q_spec) |
| 929 | return -EINVAL; |
| 930 | |
| 931 | if (qpnp_pin_check_config(Q_PIN_CFG_MODE, q_spec, mode)) { |
| 932 | pr_err("invalid mode specification %d\n", mode); |
| 933 | return -EINVAL; |
| 934 | } |
| 935 | |
| 936 | if (is_gpio_lv_mv(q_spec)) { |
| 937 | shift = Q_REG_LV_MV_MODE_SEL_SHIFT; |
| 938 | mask = Q_REG_LV_MV_MODE_SEL_MASK; |
| 939 | } else { |
| 940 | shift = Q_REG_MODE_SEL_SHIFT; |
| 941 | mask = Q_REG_MODE_SEL_MASK; |
| 942 | } |
| 943 | |
| 944 | q_reg_clr_set(&q_spec->regs[Q_REG_I_MODE_CTL], shift, mask, mode); |
| 945 | |
| 946 | rc = regmap_write(q_chip->regmap, Q_REG_ADDR(q_spec, Q_REG_MODE_CTL), |
| 947 | *&q_spec->regs[Q_REG_I_MODE_CTL]); |
| 948 | return rc; |
| 949 | } |
| 950 | |
| 951 | static int qpnp_pin_direction_input(struct gpio_chip *gpio_chip, |
| 952 | unsigned int offset) |
| 953 | { |
| 954 | struct qpnp_pin_chip *q_chip = gpiochip_get_data(gpio_chip); |
| 955 | struct qpnp_pin_spec *q_spec; |
| 956 | |
| 957 | if (WARN_ON(!q_chip)) |
| 958 | return -ENODEV; |
| 959 | |
| 960 | q_spec = qpnp_chip_gpio_get_spec(q_chip, offset); |
| 961 | if (WARN_ON(!q_spec)) |
| 962 | return -ENODEV; |
| 963 | |
| 964 | return qpnp_pin_set_mode(q_chip, q_spec, QPNP_PIN_MODE_DIG_IN); |
| 965 | } |
| 966 | |
| 967 | static int qpnp_pin_direction_output(struct gpio_chip *gpio_chip, |
| 968 | unsigned int offset, int val) |
| 969 | { |
| 970 | int rc; |
| 971 | struct qpnp_pin_chip *q_chip = gpiochip_get_data(gpio_chip); |
| 972 | struct qpnp_pin_spec *q_spec; |
| 973 | |
| 974 | if (WARN_ON(!q_chip)) |
| 975 | return -ENODEV; |
| 976 | |
| 977 | q_spec = qpnp_chip_gpio_get_spec(q_chip, offset); |
| 978 | if (WARN_ON(!q_spec)) |
| 979 | return -ENODEV; |
| 980 | |
| 981 | rc = __qpnp_pin_set(q_chip, q_spec, val); |
| 982 | if (rc) |
| 983 | return rc; |
| 984 | |
| 985 | rc = qpnp_pin_set_mode(q_chip, q_spec, QPNP_PIN_MODE_DIG_OUT); |
| 986 | |
| 987 | return rc; |
| 988 | } |
| 989 | |
| 990 | static int qpnp_pin_of_gpio_xlate(struct gpio_chip *gpio_chip, |
| 991 | const struct of_phandle_args *gpio_spec, |
| 992 | u32 *flags) |
| 993 | { |
| 994 | struct qpnp_pin_chip *q_chip = gpiochip_get_data(gpio_chip); |
| 995 | struct qpnp_pin_spec *q_spec; |
| 996 | |
| 997 | if (WARN_ON(gpio_chip->of_gpio_n_cells < 2)) { |
| 998 | pr_err("of_gpio_n_cells < 2\n"); |
| 999 | return -EINVAL; |
| 1000 | } |
| 1001 | |
| 1002 | q_spec = qpnp_pmic_pin_get_spec(q_chip, gpio_spec->args[0]); |
| 1003 | if (!q_spec) { |
| 1004 | pr_err("no such PMIC gpio %u in device topology\n", |
| 1005 | gpio_spec->args[0]); |
| 1006 | return -EINVAL; |
| 1007 | } |
| 1008 | |
| 1009 | if (flags) |
| 1010 | *flags = gpio_spec->args[1]; |
| 1011 | |
| 1012 | return q_spec->gpio_chip_idx; |
| 1013 | } |
| 1014 | |
| 1015 | static int qpnp_pin_apply_config(struct qpnp_pin_chip *q_chip, |
| 1016 | struct qpnp_pin_spec *q_spec) |
| 1017 | { |
| 1018 | struct qpnp_pin_cfg param; |
| 1019 | struct device_node *node = q_spec->node; |
| 1020 | int rc; |
| 1021 | u8 shift, mask, *reg; |
| 1022 | |
| 1023 | if (is_gpio_lv_mv(q_spec)) { |
| 1024 | shift = Q_REG_LV_MV_MODE_SEL_SHIFT; |
| 1025 | mask = Q_REG_LV_MV_MODE_SEL_MASK; |
| 1026 | } else { |
| 1027 | shift = Q_REG_MODE_SEL_SHIFT; |
| 1028 | mask = Q_REG_MODE_SEL_MASK; |
| 1029 | } |
| 1030 | param.mode = q_reg_get(&q_spec->regs[Q_REG_I_MODE_CTL], |
| 1031 | shift, mask); |
| 1032 | |
| 1033 | param.output_type = q_reg_get(&q_spec->regs[Q_REG_I_DIG_OUT_CTL], |
| 1034 | Q_REG_OUT_TYPE_SHIFT, |
| 1035 | Q_REG_OUT_TYPE_MASK); |
| 1036 | |
| 1037 | if (is_gpio_lv_mv(q_spec)) { |
| 1038 | shift = Q_REG_DIG_OUT_SRC_INVERT_SHIFT; |
| 1039 | mask = Q_REG_DIG_OUT_SRC_INVERT_MASK; |
| 1040 | reg = &q_spec->regs[Q_REG_I_DIG_OUT_SRC_CTL]; |
| 1041 | } else { |
| 1042 | shift = Q_REG_OUT_INVERT_SHIFT; |
| 1043 | mask = Q_REG_OUT_INVERT_MASK; |
| 1044 | reg = &q_spec->regs[Q_REG_I_MODE_CTL]; |
| 1045 | } |
| 1046 | param.invert = q_reg_get(reg, shift, mask); |
| 1047 | |
| 1048 | param.pull = q_reg_get(&q_spec->regs[Q_REG_I_DIG_PULL_CTL], |
| 1049 | Q_REG_PULL_SHIFT, Q_REG_PULL_MASK); |
| 1050 | param.vin_sel = q_reg_get(&q_spec->regs[Q_REG_I_DIG_VIN_CTL], |
| 1051 | Q_REG_VIN_SHIFT, Q_REG_VIN_MASK); |
| 1052 | param.out_strength = q_reg_get(&q_spec->regs[Q_REG_I_DIG_OUT_CTL], |
| 1053 | Q_REG_OUT_STRENGTH_SHIFT, |
| 1054 | Q_REG_OUT_STRENGTH_MASK); |
| 1055 | |
| 1056 | if (is_gpio_lv_mv(q_spec)) { |
| 1057 | shift = Q_REG_DIG_OUT_SRC_SRC_SEL_SHIFT; |
| 1058 | mask = Q_REG_DIG_OUT_SRC_SRC_SEL_MASK; |
| 1059 | reg = &q_spec->regs[Q_REG_I_DIG_OUT_SRC_CTL]; |
| 1060 | } else { |
| 1061 | shift = Q_REG_SRC_SEL_SHIFT; |
| 1062 | mask = Q_REG_SRC_SEL_MASK; |
| 1063 | reg = &q_spec->regs[Q_REG_I_MODE_CTL]; |
| 1064 | } |
| 1065 | param.src_sel = q_reg_get(reg, shift, mask); |
| 1066 | |
| 1067 | param.master_en = q_reg_get(&q_spec->regs[Q_REG_I_EN_CTL], |
| 1068 | Q_REG_MASTER_EN_SHIFT, |
| 1069 | Q_REG_MASTER_EN_MASK); |
| 1070 | param.aout_ref = q_reg_get(&q_spec->regs[Q_REG_I_AOUT_CTL], |
| 1071 | Q_REG_AOUT_REF_SHIFT, |
| 1072 | Q_REG_AOUT_REF_MASK); |
| 1073 | param.ain_route = q_reg_get(&q_spec->regs[Q_REG_I_AIN_CTL], |
| 1074 | Q_REG_AIN_ROUTE_SHIFT, |
| 1075 | Q_REG_AIN_ROUTE_MASK); |
| 1076 | param.cs_out = q_reg_get(&q_spec->regs[Q_REG_I_SINK_CTL], |
| 1077 | Q_REG_CS_OUT_SHIFT, |
| 1078 | Q_REG_CS_OUT_MASK); |
| 1079 | param.apass_sel = q_reg_get(&q_spec->regs[Q_REG_I_APASS_SEL_CTL], |
| 1080 | Q_REG_APASS_SEL_SHIFT, |
| 1081 | Q_REG_APASS_SEL_MASK); |
| 1082 | if (is_gpio_lv_mv(q_spec)) { |
| 1083 | param.dtest_sel = q_reg_get(&q_spec->regs[Q_REG_I_DIG_IN_CTL], |
| 1084 | Q_REG_LV_MV_DTEST_SEL_CFG_SHIFT, |
| 1085 | Q_REG_LV_MV_DTEST_SEL_CFG_MASK); |
| 1086 | } else { |
| 1087 | param.dtest_sel = q_reg_get(&q_spec->regs[Q_REG_I_DIG_IN_CTL], |
| 1088 | Q_REG_DTEST_SEL_SHIFT, |
| 1089 | Q_REG_DTEST_SEL_MASK); |
| 1090 | } |
| 1091 | |
| 1092 | of_property_read_u32(node, "qcom,mode", |
| 1093 | ¶m.mode); |
| 1094 | of_property_read_u32(node, "qcom,output-type", |
| 1095 | ¶m.output_type); |
| 1096 | of_property_read_u32(node, "qcom,invert", |
| 1097 | ¶m.invert); |
| 1098 | of_property_read_u32(node, "qcom,pull", |
| 1099 | ¶m.pull); |
| 1100 | of_property_read_u32(node, "qcom,vin-sel", |
| 1101 | ¶m.vin_sel); |
| 1102 | of_property_read_u32(node, "qcom,out-strength", |
| 1103 | ¶m.out_strength); |
| 1104 | of_property_read_u32(node, "qcom,src-sel", |
| 1105 | ¶m.src_sel); |
| 1106 | of_property_read_u32(node, "qcom,master-en", |
| 1107 | ¶m.master_en); |
| 1108 | of_property_read_u32(node, "qcom,aout-ref", |
| 1109 | ¶m.aout_ref); |
| 1110 | of_property_read_u32(node, "qcom,ain-route", |
| 1111 | ¶m.ain_route); |
| 1112 | of_property_read_u32(node, "qcom,cs-out", |
| 1113 | ¶m.cs_out); |
| 1114 | of_property_read_u32(node, "qcom,apass-sel", |
| 1115 | ¶m.apass_sel); |
| 1116 | of_property_read_u32(node, "qcom,dtest-sel", |
| 1117 | ¶m.dtest_sel); |
| 1118 | |
| 1119 | rc = _qpnp_pin_config(q_chip, q_spec, ¶m); |
| 1120 | |
| 1121 | return rc; |
| 1122 | } |
| 1123 | |
| 1124 | static int qpnp_pin_free_chip(struct qpnp_pin_chip *q_chip) |
| 1125 | { |
| 1126 | int i, rc = 0; |
| 1127 | |
| 1128 | if (q_chip->chip_gpios) |
| 1129 | for (i = 0; i < q_chip->gpio_chip.ngpio; i++) |
| 1130 | kfree(q_chip->chip_gpios[i]); |
| 1131 | |
| 1132 | mutex_lock(&qpnp_pin_chips_lock); |
| 1133 | list_del(&q_chip->chip_list); |
| 1134 | mutex_unlock(&qpnp_pin_chips_lock); |
| 1135 | if (q_chip->chip_registered) |
| 1136 | gpiochip_remove(&q_chip->gpio_chip); |
| 1137 | |
| 1138 | kfree(q_chip->chip_gpios); |
| 1139 | kfree(q_chip->pmic_pins); |
| 1140 | kfree(q_chip); |
| 1141 | return rc; |
| 1142 | } |
| 1143 | |
| 1144 | #ifdef CONFIG_GPIO_QPNP_PIN_DEBUG |
| 1145 | struct qpnp_pin_reg { |
| 1146 | uint32_t addr; |
| 1147 | uint32_t idx; |
| 1148 | uint32_t shift; |
| 1149 | uint32_t mask; |
| 1150 | }; |
| 1151 | |
| 1152 | static struct dentry *driver_dfs_dir; |
| 1153 | |
| 1154 | static int qpnp_pin_reg_attr(enum qpnp_pin_param_type type, |
| 1155 | struct qpnp_pin_reg *cfg, |
| 1156 | struct qpnp_pin_spec *q_spec) |
| 1157 | { |
| 1158 | switch (type) { |
| 1159 | case Q_PIN_CFG_MODE: |
| 1160 | if (is_gpio_lv_mv(q_spec)) { |
| 1161 | cfg->shift = Q_REG_LV_MV_MODE_SEL_SHIFT; |
| 1162 | cfg->mask = Q_REG_LV_MV_MODE_SEL_MASK; |
| 1163 | } else { |
| 1164 | cfg->shift = Q_REG_MODE_SEL_SHIFT; |
| 1165 | cfg->mask = Q_REG_MODE_SEL_MASK; |
| 1166 | } |
| 1167 | cfg->addr = Q_REG_MODE_CTL; |
| 1168 | cfg->idx = Q_REG_I_MODE_CTL; |
| 1169 | break; |
| 1170 | case Q_PIN_CFG_OUTPUT_TYPE: |
| 1171 | cfg->addr = Q_REG_DIG_OUT_CTL; |
| 1172 | cfg->idx = Q_REG_I_DIG_OUT_CTL; |
| 1173 | cfg->shift = Q_REG_OUT_TYPE_SHIFT; |
| 1174 | cfg->mask = Q_REG_OUT_TYPE_MASK; |
| 1175 | break; |
| 1176 | case Q_PIN_CFG_INVERT: |
| 1177 | if (is_gpio_lv_mv(q_spec)) { |
| 1178 | cfg->addr = Q_REG_DIG_OUT_SRC_CTL; |
| 1179 | cfg->idx = Q_REG_I_DIG_OUT_SRC_CTL; |
| 1180 | cfg->shift = Q_REG_DIG_OUT_SRC_INVERT_SHIFT; |
| 1181 | cfg->mask = Q_REG_DIG_OUT_SRC_INVERT_MASK; |
| 1182 | } else { |
| 1183 | cfg->addr = Q_REG_MODE_CTL; |
| 1184 | cfg->idx = Q_REG_I_MODE_CTL; |
| 1185 | cfg->shift = Q_REG_OUT_INVERT_SHIFT; |
| 1186 | cfg->mask = Q_REG_OUT_INVERT_MASK; |
| 1187 | } |
| 1188 | break; |
| 1189 | case Q_PIN_CFG_PULL: |
| 1190 | cfg->addr = Q_REG_DIG_PULL_CTL; |
| 1191 | cfg->idx = Q_REG_I_DIG_PULL_CTL; |
| 1192 | cfg->shift = Q_REG_PULL_SHIFT; |
| 1193 | cfg->mask = Q_REG_PULL_MASK; |
| 1194 | break; |
| 1195 | case Q_PIN_CFG_VIN_SEL: |
| 1196 | cfg->addr = Q_REG_DIG_VIN_CTL; |
| 1197 | cfg->idx = Q_REG_I_DIG_VIN_CTL; |
| 1198 | cfg->shift = Q_REG_VIN_SHIFT; |
| 1199 | cfg->mask = Q_REG_VIN_MASK; |
| 1200 | break; |
| 1201 | case Q_PIN_CFG_OUT_STRENGTH: |
| 1202 | cfg->addr = Q_REG_DIG_OUT_CTL; |
| 1203 | cfg->idx = Q_REG_I_DIG_OUT_CTL; |
| 1204 | cfg->shift = Q_REG_OUT_STRENGTH_SHIFT; |
| 1205 | cfg->mask = Q_REG_OUT_STRENGTH_MASK; |
| 1206 | break; |
| 1207 | case Q_PIN_CFG_SRC_SEL: |
| 1208 | if (is_gpio_lv_mv(q_spec)) { |
| 1209 | cfg->addr = Q_REG_DIG_OUT_SRC_CTL; |
| 1210 | cfg->idx = Q_REG_I_DIG_OUT_SRC_CTL; |
| 1211 | cfg->shift = Q_REG_DIG_OUT_SRC_SRC_SEL_SHIFT; |
| 1212 | cfg->mask = Q_REG_DIG_OUT_SRC_SRC_SEL_MASK; |
| 1213 | } else { |
| 1214 | cfg->addr = Q_REG_MODE_CTL; |
| 1215 | cfg->idx = Q_REG_I_MODE_CTL; |
| 1216 | cfg->shift = Q_REG_SRC_SEL_SHIFT; |
| 1217 | cfg->mask = Q_REG_SRC_SEL_MASK; |
| 1218 | } |
| 1219 | break; |
| 1220 | case Q_PIN_CFG_MASTER_EN: |
| 1221 | cfg->addr = Q_REG_EN_CTL; |
| 1222 | cfg->idx = Q_REG_I_EN_CTL; |
| 1223 | cfg->shift = Q_REG_MASTER_EN_SHIFT; |
| 1224 | cfg->mask = Q_REG_MASTER_EN_MASK; |
| 1225 | break; |
| 1226 | case Q_PIN_CFG_AOUT_REF: |
| 1227 | cfg->addr = Q_REG_AOUT_CTL; |
| 1228 | cfg->idx = Q_REG_I_AOUT_CTL; |
| 1229 | cfg->shift = Q_REG_AOUT_REF_SHIFT; |
| 1230 | cfg->mask = Q_REG_AOUT_REF_MASK; |
| 1231 | break; |
| 1232 | case Q_PIN_CFG_AIN_ROUTE: |
| 1233 | cfg->addr = Q_REG_AIN_CTL; |
| 1234 | cfg->idx = Q_REG_I_AIN_CTL; |
| 1235 | cfg->shift = Q_REG_AIN_ROUTE_SHIFT; |
| 1236 | cfg->mask = Q_REG_AIN_ROUTE_MASK; |
| 1237 | break; |
| 1238 | case Q_PIN_CFG_CS_OUT: |
| 1239 | cfg->addr = Q_REG_SINK_CTL; |
| 1240 | cfg->idx = Q_REG_I_SINK_CTL; |
| 1241 | cfg->shift = Q_REG_CS_OUT_SHIFT; |
| 1242 | cfg->mask = Q_REG_CS_OUT_MASK; |
| 1243 | break; |
| 1244 | case Q_PIN_CFG_APASS_SEL: |
| 1245 | cfg->addr = Q_REG_APASS_SEL_CTL; |
| 1246 | cfg->idx = Q_REG_I_APASS_SEL_CTL; |
| 1247 | cfg->shift = Q_REG_APASS_SEL_SHIFT; |
| 1248 | cfg->mask = Q_REG_APASS_SEL_MASK; |
| 1249 | break; |
| 1250 | case Q_PIN_CFG_DTEST_SEL: |
| 1251 | if (is_gpio_lv_mv(q_spec)) { |
| 1252 | cfg->shift = Q_REG_LV_MV_DTEST_SEL_CFG_SHIFT; |
| 1253 | cfg->mask = Q_REG_LV_MV_DTEST_SEL_CFG_MASK; |
| 1254 | } else { |
| 1255 | cfg->shift = Q_REG_DTEST_SEL_SHIFT; |
| 1256 | cfg->mask = Q_REG_DTEST_SEL_MASK; |
| 1257 | } |
| 1258 | cfg->addr = Q_REG_DIG_IN_CTL; |
| 1259 | cfg->idx = Q_REG_I_DIG_IN_CTL; |
| 1260 | break; |
| 1261 | default: |
| 1262 | return -EINVAL; |
| 1263 | } |
| 1264 | |
| 1265 | return 0; |
| 1266 | } |
| 1267 | |
| 1268 | static int qpnp_pin_debugfs_get(void *data, u64 *val) |
| 1269 | { |
| 1270 | enum qpnp_pin_param_type *idx = data; |
| 1271 | struct qpnp_pin_spec *q_spec; |
| 1272 | struct qpnp_pin_reg cfg = {}; |
| 1273 | int rc; |
| 1274 | |
| 1275 | q_spec = container_of(idx, struct qpnp_pin_spec, params[*idx]); |
| 1276 | |
| 1277 | rc = qpnp_pin_reg_attr(*idx, &cfg, q_spec); |
| 1278 | if (rc) |
| 1279 | return rc; |
| 1280 | |
| 1281 | *val = q_reg_get(&q_spec->regs[cfg.idx], cfg.shift, cfg.mask); |
| 1282 | return 0; |
| 1283 | } |
| 1284 | |
| 1285 | static int qpnp_pin_debugfs_set(void *data, u64 val) |
| 1286 | { |
| 1287 | enum qpnp_pin_param_type *idx = data; |
| 1288 | struct qpnp_pin_spec *q_spec; |
| 1289 | struct qpnp_pin_chip *q_chip; |
| 1290 | struct qpnp_pin_reg cfg = {}; |
| 1291 | int rc; |
| 1292 | |
| 1293 | q_spec = container_of(idx, struct qpnp_pin_spec, params[*idx]); |
| 1294 | q_chip = q_spec->q_chip; |
| 1295 | |
| 1296 | /* |
| 1297 | * special handling for GPIO_LV/MV 'dtest-sel' |
| 1298 | * if (dtest_sel == 0) then disable dtest-sel |
| 1299 | * else enable and set dtest. |
| 1300 | */ |
| 1301 | if ((q_spec->subtype == Q_GPIO_SUBTYPE_GPIO_LV || |
| 1302 | q_spec->subtype == Q_GPIO_SUBTYPE_GPIO_MV) && |
| 1303 | *idx == Q_PIN_CFG_DTEST_SEL) { |
| 1304 | /* enable/disable DTEST */ |
| 1305 | cfg.shift = Q_REG_LV_MV_DTEST_SEL_EN_SHIFT; |
| 1306 | cfg.mask = Q_REG_LV_MV_DTEST_SEL_EN_MASK; |
| 1307 | cfg.addr = Q_REG_DIG_IN_CTL; |
| 1308 | cfg.idx = Q_REG_I_DIG_IN_CTL; |
| 1309 | q_reg_clr_set(&q_spec->regs[cfg.idx], |
| 1310 | cfg.shift, cfg.mask, !!val); |
| 1311 | } |
| 1312 | |
| 1313 | rc = qpnp_pin_check_config(*idx, q_spec, val); |
| 1314 | if (rc) |
| 1315 | return rc; |
| 1316 | |
| 1317 | rc = qpnp_pin_reg_attr(*idx, &cfg, q_spec); |
| 1318 | if (rc) |
| 1319 | return rc; |
| 1320 | |
| 1321 | if (*idx == Q_PIN_CFG_DTEST_SEL && val) { |
| 1322 | if (is_gpio_lv_mv(q_spec)) |
| 1323 | val -= 1; |
| 1324 | else |
| 1325 | val = BIT(val - 1); |
| 1326 | } |
| 1327 | |
| 1328 | q_reg_clr_set(&q_spec->regs[cfg.idx], cfg.shift, cfg.mask, val); |
| 1329 | rc = regmap_write(q_chip->regmap, Q_REG_ADDR(q_spec, cfg.addr), |
| 1330 | *&q_spec->regs[cfg.idx]); |
| 1331 | |
| 1332 | return rc; |
| 1333 | } |
| 1334 | DEFINE_SIMPLE_ATTRIBUTE(qpnp_pin_fops, qpnp_pin_debugfs_get, |
| 1335 | qpnp_pin_debugfs_set, "%llu\n"); |
| 1336 | |
| 1337 | #define DEBUGFS_BUF_SIZE 11 /* supports 2^32 in decimal */ |
| 1338 | |
| 1339 | struct qpnp_pin_debugfs_args { |
| 1340 | enum qpnp_pin_param_type type; |
| 1341 | const char *filename; |
| 1342 | }; |
| 1343 | |
| 1344 | static struct qpnp_pin_debugfs_args dfs_args[Q_NUM_PARAMS] = { |
| 1345 | { Q_PIN_CFG_MODE, "mode" }, |
| 1346 | { Q_PIN_CFG_OUTPUT_TYPE, "output_type" }, |
| 1347 | { Q_PIN_CFG_INVERT, "invert" }, |
| 1348 | { Q_PIN_CFG_PULL, "pull" }, |
| 1349 | { Q_PIN_CFG_VIN_SEL, "vin_sel" }, |
| 1350 | { Q_PIN_CFG_OUT_STRENGTH, "out_strength" }, |
| 1351 | { Q_PIN_CFG_SRC_SEL, "src_sel" }, |
| 1352 | { Q_PIN_CFG_MASTER_EN, "master_en" }, |
| 1353 | { Q_PIN_CFG_AOUT_REF, "aout_ref" }, |
| 1354 | { Q_PIN_CFG_AIN_ROUTE, "ain_route" }, |
| 1355 | { Q_PIN_CFG_CS_OUT, "cs_out" }, |
| 1356 | { Q_PIN_CFG_APASS_SEL, "apass_sel" }, |
| 1357 | { Q_PIN_CFG_DTEST_SEL, "dtest-sel" }, |
| 1358 | }; |
| 1359 | |
| 1360 | static int qpnp_pin_debugfs_create(struct qpnp_pin_chip *q_chip) |
| 1361 | { |
| 1362 | struct platform_device *pdev = q_chip->pdev; |
| 1363 | struct device *dev = &pdev->dev; |
| 1364 | struct qpnp_pin_spec *q_spec; |
| 1365 | enum qpnp_pin_param_type *params; |
| 1366 | enum qpnp_pin_param_type type; |
| 1367 | char pmic_pin[DEBUGFS_BUF_SIZE]; |
| 1368 | const char *filename; |
| 1369 | struct dentry *dfs, *dfs_io_dir; |
| 1370 | int i, j, rc; |
| 1371 | |
| 1372 | q_chip->dfs_dir = debugfs_create_dir(q_chip->gpio_chip.label, |
| 1373 | driver_dfs_dir); |
| 1374 | if (q_chip->dfs_dir == NULL) { |
| 1375 | dev_err(dev, "%s: cannot register chip debugfs directory %s\n", |
| 1376 | __func__, dev->of_node->name); |
| 1377 | return -ENODEV; |
| 1378 | } |
| 1379 | |
| 1380 | for (i = 0; i < q_chip->gpio_chip.ngpio; i++) { |
| 1381 | q_spec = qpnp_chip_gpio_get_spec(q_chip, i); |
| 1382 | params = q_spec->params; |
| 1383 | snprintf(pmic_pin, DEBUGFS_BUF_SIZE, "%u", q_spec->pmic_pin); |
| 1384 | dfs_io_dir = debugfs_create_dir(pmic_pin, q_chip->dfs_dir); |
| 1385 | if (dfs_io_dir == NULL) |
| 1386 | goto dfs_err; |
| 1387 | |
| 1388 | for (j = 0; j < Q_NUM_PARAMS; j++) { |
| 1389 | type = dfs_args[j].type; |
| 1390 | filename = dfs_args[j].filename; |
| 1391 | |
| 1392 | /* |
| 1393 | * Use a value of '0' to see if the pin has even basic |
| 1394 | * support for a function. Do not create a file if |
| 1395 | * it doesn't. |
| 1396 | */ |
| 1397 | rc = qpnp_pin_check_config(type, q_spec, 0); |
| 1398 | if (rc == -ENXIO) |
| 1399 | continue; |
| 1400 | |
| 1401 | params[type] = type; |
| 1402 | dfs = debugfs_create_file(filename, 0644, dfs_io_dir, |
| 1403 | &q_spec->params[type], &qpnp_pin_fops); |
| 1404 | if (dfs == NULL) |
| 1405 | goto dfs_err; |
| 1406 | } |
| 1407 | } |
| 1408 | return 0; |
| 1409 | dfs_err: |
| 1410 | dev_err(dev, "%s: cannot register debugfs for pmic gpio %u on chip %s\n", |
| 1411 | __func__, q_spec->pmic_pin, dev->of_node->name); |
| 1412 | debugfs_remove_recursive(q_chip->dfs_dir); |
| 1413 | return -ENFILE; |
| 1414 | } |
| 1415 | #else |
| 1416 | static int qpnp_pin_debugfs_create(struct qpnp_pin_chip *q_chip) |
| 1417 | { |
| 1418 | return 0; |
| 1419 | } |
| 1420 | #endif |
| 1421 | |
| 1422 | static int qpnp_pin_is_valid_pin(struct qpnp_pin_spec *q_spec) |
| 1423 | { |
| 1424 | if (q_spec->type == Q_GPIO_TYPE) |
| 1425 | switch (q_spec->subtype) { |
| 1426 | case Q_GPIO_SUBTYPE_GPIO_4CH: |
| 1427 | case Q_GPIO_SUBTYPE_GPIOC_4CH: |
| 1428 | case Q_GPIO_SUBTYPE_GPIO_8CH: |
| 1429 | case Q_GPIO_SUBTYPE_GPIOC_8CH: |
| 1430 | case Q_GPIO_SUBTYPE_GPIO_LV: |
| 1431 | case Q_GPIO_SUBTYPE_GPIO_MV: |
| 1432 | return 1; |
| 1433 | } |
| 1434 | else if (q_spec->type == Q_MPP_TYPE) |
| 1435 | switch (q_spec->subtype) { |
| 1436 | case Q_MPP_SUBTYPE_4CH_NO_ANA_OUT: |
| 1437 | case Q_MPP_SUBTYPE_ULT_4CH_NO_ANA_OUT: |
| 1438 | case Q_MPP_SUBTYPE_4CH_NO_SINK: |
| 1439 | case Q_MPP_SUBTYPE_ULT_4CH_NO_SINK: |
| 1440 | case Q_MPP_SUBTYPE_4CH_FULL_FUNC: |
| 1441 | case Q_MPP_SUBTYPE_8CH_FULL_FUNC: |
| 1442 | return 1; |
| 1443 | } |
| 1444 | |
| 1445 | return 0; |
| 1446 | } |
| 1447 | |
| 1448 | static int qpnp_pin_probe(struct platform_device *pdev) |
| 1449 | { |
| 1450 | struct qpnp_pin_chip *q_chip; |
| 1451 | struct qpnp_pin_spec *q_spec; |
| 1452 | unsigned int base; |
| 1453 | struct device_node *child; |
| 1454 | int i, rc; |
| 1455 | u32 lowest_gpio = UINT_MAX, highest_gpio = 0; |
| 1456 | u32 gpio; |
| 1457 | char version[Q_REG_SUBTYPE - Q_REG_DIG_MAJOR_REV + 1]; |
| 1458 | const char *pin_dev_name; |
| 1459 | |
| 1460 | pin_dev_name = dev_name(&pdev->dev); |
| 1461 | if (!pin_dev_name) { |
| 1462 | dev_err(&pdev->dev, |
| 1463 | "%s: label binding undefined for node %s\n", |
| 1464 | __func__, |
| 1465 | pdev->dev.of_node->full_name); |
| 1466 | return -EINVAL; |
| 1467 | } |
| 1468 | |
| 1469 | q_chip = kzalloc(sizeof(*q_chip), GFP_KERNEL); |
| 1470 | if (!q_chip) |
| 1471 | return -ENOMEM; |
| 1472 | |
| 1473 | q_chip->regmap = dev_get_regmap(pdev->dev.parent, NULL); |
| 1474 | if (!q_chip->regmap) { |
| 1475 | dev_err(&pdev->dev, "Couldn't get parent's regmap\n"); |
| 1476 | return -EINVAL; |
| 1477 | } |
| 1478 | q_chip->pdev = pdev; |
| 1479 | dev_set_drvdata(&pdev->dev, q_chip); |
| 1480 | |
| 1481 | mutex_lock(&qpnp_pin_chips_lock); |
| 1482 | list_add(&q_chip->chip_list, &qpnp_pin_chips); |
| 1483 | mutex_unlock(&qpnp_pin_chips_lock); |
| 1484 | |
| 1485 | /* first scan through nodes to find the range required for allocation */ |
| 1486 | i = 0; |
| 1487 | for_each_available_child_of_node(pdev->dev.of_node, child) { |
| 1488 | rc = of_property_read_u32(child, "qcom,pin-num", &gpio); |
| 1489 | if (rc) { |
| 1490 | dev_err(&pdev->dev, |
| 1491 | "%s: unable to get qcom,pin-num property\n", |
| 1492 | __func__); |
| 1493 | goto err_probe; |
| 1494 | } |
| 1495 | |
| 1496 | if (gpio < lowest_gpio) |
| 1497 | lowest_gpio = gpio; |
| 1498 | if (gpio > highest_gpio) |
| 1499 | highest_gpio = gpio; |
| 1500 | i++; |
| 1501 | } |
| 1502 | q_chip->gpio_chip.ngpio = i; |
| 1503 | |
| 1504 | if (highest_gpio < lowest_gpio) { |
| 1505 | dev_err(&pdev->dev, |
| 1506 | "%s: no device nodes specified in topology\n", |
| 1507 | __func__); |
| 1508 | rc = -EINVAL; |
| 1509 | goto err_probe; |
| 1510 | } else if (lowest_gpio == 0) { |
| 1511 | dev_err(&pdev->dev, "%s: 0 is not a valid PMIC GPIO\n", |
| 1512 | __func__); |
| 1513 | rc = -EINVAL; |
| 1514 | goto err_probe; |
| 1515 | } |
| 1516 | |
| 1517 | q_chip->pmic_pin_lowest = lowest_gpio; |
| 1518 | q_chip->pmic_pin_highest = highest_gpio; |
| 1519 | |
| 1520 | /* allocate gpio lookup tables */ |
| 1521 | q_chip->pmic_pins = kzalloc(sizeof(struct qpnp_pin_spec *) * |
| 1522 | (highest_gpio - lowest_gpio + 1), |
| 1523 | GFP_KERNEL); |
| 1524 | q_chip->chip_gpios = kzalloc(sizeof(struct qpnp_pin_spec *) * |
| 1525 | q_chip->gpio_chip.ngpio, |
| 1526 | GFP_KERNEL); |
| 1527 | if (!q_chip->pmic_pins || !q_chip->chip_gpios) { |
| 1528 | dev_err(&pdev->dev, "%s: unable to allocate memory\n", |
| 1529 | __func__); |
| 1530 | rc = -ENOMEM; |
| 1531 | goto err_probe; |
| 1532 | } |
| 1533 | |
| 1534 | /* get interrupt controller device_node */ |
| 1535 | q_chip->int_ctrl = of_irq_find_parent(pdev->dev.of_node); |
| 1536 | if (!q_chip->int_ctrl) { |
| 1537 | dev_err(&pdev->dev, "%s: Can't find interrupt parent\n", |
| 1538 | __func__); |
| 1539 | rc = -EINVAL; |
| 1540 | goto err_probe; |
| 1541 | } |
| 1542 | i = 0; |
| 1543 | /* now scan through again and populate the lookup table */ |
| 1544 | for_each_available_child_of_node(pdev->dev.of_node, child) { |
| 1545 | rc = of_property_read_u32(child, "reg", &base); |
| 1546 | if (rc < 0) { |
| 1547 | dev_err(&pdev->dev, |
| 1548 | "Couldn't find reg in node = %s rc = %d\n", |
| 1549 | child->full_name, rc); |
| 1550 | goto err_probe; |
| 1551 | } |
| 1552 | |
| 1553 | rc = of_property_read_u32(child, "qcom,pin-num", &gpio); |
| 1554 | if (rc) { |
| 1555 | dev_err(&pdev->dev, |
| 1556 | "%s: unable to get qcom,pin-num property\n", |
| 1557 | __func__); |
| 1558 | goto err_probe; |
| 1559 | } |
| 1560 | |
| 1561 | q_spec = kzalloc(sizeof(struct qpnp_pin_spec), GFP_KERNEL); |
| 1562 | if (!q_spec) { |
| 1563 | rc = -ENOMEM; |
| 1564 | goto err_probe; |
| 1565 | } |
| 1566 | |
| 1567 | q_spec->slave = to_spmi_device(pdev->dev.parent)->usid; |
| 1568 | q_spec->offset = base; |
| 1569 | q_spec->gpio_chip_idx = i; |
| 1570 | q_spec->pmic_pin = gpio; |
| 1571 | q_spec->node = child; |
| 1572 | q_spec->q_chip = q_chip; |
| 1573 | |
| 1574 | rc = regmap_bulk_read(q_chip->regmap, |
| 1575 | Q_REG_ADDR(q_spec, Q_REG_DIG_MAJOR_REV), |
| 1576 | &version[0], |
| 1577 | ARRAY_SIZE(version)); |
| 1578 | if (rc) { |
| 1579 | dev_err(&pdev->dev, "%s: unable to read type regs\n", |
| 1580 | __func__); |
| 1581 | goto err_probe; |
| 1582 | } |
| 1583 | q_spec->dig_major_rev = version[Q_REG_DIG_MAJOR_REV - |
| 1584 | Q_REG_DIG_MAJOR_REV]; |
| 1585 | q_spec->type = version[Q_REG_TYPE - Q_REG_DIG_MAJOR_REV]; |
| 1586 | q_spec->subtype = version[Q_REG_SUBTYPE - Q_REG_DIG_MAJOR_REV]; |
| 1587 | |
| 1588 | if (!qpnp_pin_is_valid_pin(q_spec)) { |
| 1589 | dev_err(&pdev->dev, |
| 1590 | "%s: invalid pin type (type=0x%x subtype=0x%x)\n", |
| 1591 | __func__, q_spec->type, q_spec->subtype); |
| 1592 | goto err_probe; |
| 1593 | } |
| 1594 | |
| 1595 | rc = qpnp_pin_ctl_regs_init(q_spec); |
| 1596 | if (rc) |
| 1597 | goto err_probe; |
| 1598 | |
| 1599 | /* initialize lookup table params */ |
| 1600 | qpnp_pmic_pin_set_spec(q_chip, gpio, q_spec); |
| 1601 | qpnp_chip_gpio_set_spec(q_chip, i, q_spec); |
| 1602 | i++; |
| 1603 | } |
| 1604 | |
| 1605 | q_chip->gpio_chip.base = -1; |
| 1606 | q_chip->gpio_chip.label = pin_dev_name; |
| 1607 | q_chip->gpio_chip.direction_input = qpnp_pin_direction_input; |
| 1608 | q_chip->gpio_chip.direction_output = qpnp_pin_direction_output; |
| 1609 | q_chip->gpio_chip.to_irq = qpnp_pin_to_irq; |
| 1610 | q_chip->gpio_chip.get = qpnp_pin_get; |
| 1611 | q_chip->gpio_chip.set = qpnp_pin_set; |
| 1612 | q_chip->gpio_chip.parent = &pdev->dev; |
| 1613 | q_chip->gpio_chip.of_xlate = qpnp_pin_of_gpio_xlate; |
| 1614 | q_chip->gpio_chip.of_gpio_n_cells = 2; |
| 1615 | q_chip->gpio_chip.can_sleep = 0; |
| 1616 | |
| 1617 | rc = gpiochip_add_data(&q_chip->gpio_chip, q_chip); |
| 1618 | if (rc) { |
| 1619 | dev_err(&pdev->dev, "%s: Can't add gpio chip, rc = %d\n", |
| 1620 | __func__, rc); |
| 1621 | goto err_probe; |
| 1622 | } |
| 1623 | |
| 1624 | q_chip->chip_registered = true; |
| 1625 | /* now configure gpio config defaults if they exist */ |
| 1626 | for (i = 0; i < q_chip->gpio_chip.ngpio; i++) { |
| 1627 | q_spec = qpnp_chip_gpio_get_spec(q_chip, i); |
| 1628 | if (WARN_ON(!q_spec)) { |
| 1629 | rc = -ENODEV; |
| 1630 | goto err_probe; |
| 1631 | } |
| 1632 | |
| 1633 | rc = qpnp_pin_cache_regs(q_chip, q_spec); |
| 1634 | if (rc) |
| 1635 | goto err_probe; |
| 1636 | |
| 1637 | rc = qpnp_pin_apply_config(q_chip, q_spec); |
| 1638 | if (rc) |
| 1639 | goto err_probe; |
| 1640 | } |
| 1641 | |
| 1642 | dev_dbg(&pdev->dev, "%s: gpio_chip registered between %d-%u\n", |
| 1643 | __func__, q_chip->gpio_chip.base, |
| 1644 | (q_chip->gpio_chip.base + q_chip->gpio_chip.ngpio) - 1); |
| 1645 | |
| 1646 | rc = qpnp_pin_debugfs_create(q_chip); |
| 1647 | if (rc) { |
| 1648 | dev_err(&pdev->dev, "%s: debugfs creation failed\n", |
| 1649 | __func__); |
| 1650 | goto err_probe; |
| 1651 | } |
| 1652 | |
| 1653 | return 0; |
| 1654 | |
| 1655 | err_probe: |
| 1656 | qpnp_pin_free_chip(q_chip); |
| 1657 | return rc; |
| 1658 | } |
| 1659 | |
| 1660 | static int qpnp_pin_remove(struct platform_device *pdev) |
| 1661 | { |
| 1662 | struct qpnp_pin_chip *q_chip = dev_get_drvdata(&pdev->dev); |
| 1663 | |
| 1664 | debugfs_remove_recursive(q_chip->dfs_dir); |
| 1665 | |
| 1666 | return qpnp_pin_free_chip(q_chip); |
| 1667 | } |
| 1668 | |
| 1669 | static const struct of_device_id spmi_match_table[] = { |
| 1670 | { .compatible = "qcom,qpnp-pin", |
| 1671 | }, |
| 1672 | {} |
| 1673 | }; |
| 1674 | |
| 1675 | static const struct platform_device_id qpnp_pin_id[] = { |
| 1676 | { "qcom,qpnp-pin", 0 }, |
| 1677 | { } |
| 1678 | }; |
| 1679 | MODULE_DEVICE_TABLE(spmi, qpnp_pin_id); |
| 1680 | |
| 1681 | static struct platform_driver qpnp_pin_driver = { |
| 1682 | .driver = { |
| 1683 | .name = "qcom,qpnp-pin", |
| 1684 | .of_match_table = spmi_match_table, |
| 1685 | }, |
| 1686 | .probe = qpnp_pin_probe, |
| 1687 | .remove = qpnp_pin_remove, |
| 1688 | .id_table = qpnp_pin_id, |
| 1689 | }; |
| 1690 | |
| 1691 | static int __init qpnp_pin_init(void) |
| 1692 | { |
| 1693 | #ifdef CONFIG_GPIO_QPNP_PIN_DEBUG |
| 1694 | driver_dfs_dir = debugfs_create_dir("qpnp_pin", NULL); |
| 1695 | if (driver_dfs_dir == NULL) |
| 1696 | pr_err("Cannot register top level debugfs directory\n"); |
| 1697 | #endif |
| 1698 | |
| 1699 | return platform_driver_register(&qpnp_pin_driver); |
| 1700 | } |
| 1701 | |
| 1702 | static void __exit qpnp_pin_exit(void) |
| 1703 | { |
| 1704 | #ifdef CONFIG_GPIO_QPNP_PIN_DEBUG |
| 1705 | debugfs_remove_recursive(driver_dfs_dir); |
| 1706 | #endif |
| 1707 | platform_driver_unregister(&qpnp_pin_driver); |
| 1708 | } |
| 1709 | |
| 1710 | MODULE_DESCRIPTION("QPNP PMIC gpio driver"); |
| 1711 | MODULE_LICENSE("GPL v2"); |
| 1712 | |
| 1713 | subsys_initcall(qpnp_pin_init); |
| 1714 | module_exit(qpnp_pin_exit); |