H. Peter Anvin | 05e4d31 | 2008-10-23 00:01:39 -0700 | [diff] [blame] | 1 | #ifndef _ASM_X86_MACH_DEFAULT_MACH_APIC_H |
| 2 | #define _ASM_X86_MACH_DEFAULT_MACH_APIC_H |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3 | |
Glauber Costa | dd46e3c | 2008-03-25 18:10:46 -0300 | [diff] [blame] | 4 | #ifdef CONFIG_X86_LOCAL_APIC |
| 5 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6 | #include <mach_apicdef.h> |
| 7 | #include <asm/smp.h> |
| 8 | |
| 9 | #define APIC_DFR_VALUE (APIC_DFR_FLAT) |
| 10 | |
Mike Travis | bcda016 | 2008-12-16 17:33:59 -0800 | [diff] [blame] | 11 | static inline const struct cpumask *target_cpus(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 12 | { |
| 13 | #ifdef CONFIG_SMP |
Mike Travis | bcda016 | 2008-12-16 17:33:59 -0800 | [diff] [blame] | 14 | return cpu_online_mask; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15 | #else |
Mike Travis | bcda016 | 2008-12-16 17:33:59 -0800 | [diff] [blame] | 16 | return cpumask_of(0); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 17 | #endif |
| 18 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 19 | |
| 20 | #define NO_BALANCE_IRQ (0) |
| 21 | #define esr_disable (0) |
| 22 | |
Glauber Costa | dd46e3c | 2008-03-25 18:10:46 -0300 | [diff] [blame] | 23 | #ifdef CONFIG_X86_64 |
| 24 | #include <asm/genapic.h> |
Ingo Molnar | c8d46cf | 2009-01-28 00:14:11 +0100 | [diff] [blame] | 25 | #define TARGET_CPUS (apic->target_cpus()) |
Ingo Molnar | c8d46cf | 2009-01-28 00:14:11 +0100 | [diff] [blame] | 26 | #define init_apic_ldr (apic->init_apic_ldr) |
| 27 | #define cpu_mask_to_apicid (apic->cpu_mask_to_apicid) |
| 28 | #define cpu_mask_to_apicid_and (apic->cpu_mask_to_apicid_and) |
| 29 | #define phys_pkg_id (apic->phys_pkg_id) |
| 30 | #define vector_allocation_domain (apic->vector_allocation_domain) |
Yinghai Lu | f910a9d | 2008-07-12 01:01:20 -0700 | [diff] [blame] | 31 | #define read_apic_id() (GET_APIC_ID(apic_read(APIC_ID))) |
Ingo Molnar | c8d46cf | 2009-01-28 00:14:11 +0100 | [diff] [blame] | 32 | #define send_IPI_self (apic->send_IPI_self) |
| 33 | #define wakeup_secondary_cpu (apic->wakeup_cpu) |
Glauber Costa | dd46e3c | 2008-03-25 18:10:46 -0300 | [diff] [blame] | 34 | extern void setup_apic_routing(void); |
| 35 | #else |
Glauber Costa | dd46e3c | 2008-03-25 18:10:46 -0300 | [diff] [blame] | 36 | #define TARGET_CPUS (target_cpus()) |
Yinghai Lu | 54ac14a | 2008-11-17 15:19:53 -0800 | [diff] [blame] | 37 | #define wakeup_secondary_cpu wakeup_secondary_cpu_via_init |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 38 | /* |
| 39 | * Set up the logical destination ID. |
| 40 | * |
| 41 | * Intel recommends to set DFR, LDR and TPR before enabling |
| 42 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel |
| 43 | * document number 292116). So here it goes... |
| 44 | */ |
| 45 | static inline void init_apic_ldr(void) |
| 46 | { |
| 47 | unsigned long val; |
| 48 | |
Maciej W. Rozycki | 593f4a7 | 2008-07-16 19:15:30 +0100 | [diff] [blame] | 49 | apic_write(APIC_DFR, APIC_DFR_VALUE); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 50 | val = apic_read(APIC_LDR) & ~APIC_LDR_MASK; |
| 51 | val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id()); |
Maciej W. Rozycki | 593f4a7 | 2008-07-16 19:15:30 +0100 | [diff] [blame] | 52 | apic_write(APIC_LDR, val); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 53 | } |
| 54 | |
Ingo Molnar | 7ed248d | 2009-01-28 03:43:47 +0100 | [diff] [blame] | 55 | static inline int default_apic_id_registered(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 56 | { |
Yinghai Lu | 4c9961d | 2008-07-11 18:44:16 -0700 | [diff] [blame] | 57 | return physid_isset(read_apic_id(), phys_cpu_present_map); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 58 | } |
| 59 | |
Mike Travis | bcda016 | 2008-12-16 17:33:59 -0800 | [diff] [blame] | 60 | static inline unsigned int cpu_mask_to_apicid(const struct cpumask *cpumask) |
Glauber Costa | dd46e3c | 2008-03-25 18:10:46 -0300 | [diff] [blame] | 61 | { |
Mike Travis | bcda016 | 2008-12-16 17:33:59 -0800 | [diff] [blame] | 62 | return cpumask_bits(cpumask)[0]; |
Glauber Costa | dd46e3c | 2008-03-25 18:10:46 -0300 | [diff] [blame] | 63 | } |
| 64 | |
Mike Travis | 6eeb7c5 | 2008-12-16 17:33:55 -0800 | [diff] [blame] | 65 | static inline unsigned int cpu_mask_to_apicid_and(const struct cpumask *cpumask, |
| 66 | const struct cpumask *andmask) |
Mike Travis | 95d313c | 2008-12-16 17:33:54 -0800 | [diff] [blame] | 67 | { |
Mike Travis | 6eeb7c5 | 2008-12-16 17:33:55 -0800 | [diff] [blame] | 68 | unsigned long mask1 = cpumask_bits(cpumask)[0]; |
| 69 | unsigned long mask2 = cpumask_bits(andmask)[0]; |
Mike Travis | a775a38 | 2008-12-17 15:21:39 -0800 | [diff] [blame] | 70 | unsigned long mask3 = cpumask_bits(cpu_online_mask)[0]; |
Mike Travis | 95d313c | 2008-12-16 17:33:54 -0800 | [diff] [blame] | 71 | |
Mike Travis | a775a38 | 2008-12-17 15:21:39 -0800 | [diff] [blame] | 72 | return (unsigned int)(mask1 & mask2 & mask3); |
Mike Travis | 95d313c | 2008-12-16 17:33:54 -0800 | [diff] [blame] | 73 | } |
| 74 | |
Glauber Costa | dd46e3c | 2008-03-25 18:10:46 -0300 | [diff] [blame] | 75 | static inline u32 phys_pkg_id(u32 cpuid_apic, int index_msb) |
| 76 | { |
| 77 | return cpuid_apic >> index_msb; |
| 78 | } |
| 79 | |
Ingo Molnar | 3c43f03 | 2007-05-02 19:27:04 +0200 | [diff] [blame] | 80 | static inline void setup_apic_routing(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 81 | { |
Alexey Starikovskiy | 61048c6 | 2008-04-04 23:41:07 +0400 | [diff] [blame] | 82 | #ifdef CONFIG_X86_IO_APIC |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 83 | printk("Enabling APIC mode: %s. Using %d I/O APICs\n", |
| 84 | "Flat", nr_ioapics); |
Alexey Starikovskiy | 61048c6 | 2008-04-04 23:41:07 +0400 | [diff] [blame] | 85 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 86 | } |
| 87 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 88 | static inline int apicid_to_node(int logical_apicid) |
| 89 | { |
Yinghai Lu | f47f9d5 | 2008-06-24 22:13:15 -0700 | [diff] [blame] | 90 | #ifdef CONFIG_SMP |
| 91 | return apicid_2_node[hard_smp_processor_id()]; |
| 92 | #else |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 93 | return 0; |
Yinghai Lu | f47f9d5 | 2008-06-24 22:13:15 -0700 | [diff] [blame] | 94 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 95 | } |
Yinghai Lu | 497c9a1 | 2008-08-19 20:50:28 -0700 | [diff] [blame] | 96 | |
Mike Travis | bcda016 | 2008-12-16 17:33:59 -0800 | [diff] [blame] | 97 | static inline void vector_allocation_domain(int cpu, struct cpumask *retmask) |
Yinghai Lu | 497c9a1 | 2008-08-19 20:50:28 -0700 | [diff] [blame] | 98 | { |
| 99 | /* Careful. Some cpus do not strictly honor the set of cpus |
| 100 | * specified in the interrupt destination when using lowest |
| 101 | * priority interrupt delivery mode. |
| 102 | * |
| 103 | * In particular there was a hyperthreading cpu observed to |
| 104 | * deliver interrupts to the wrong hyperthread when only one |
| 105 | * hyperthread was specified in the interrupt desitination. |
| 106 | */ |
Mike Travis | e798673 | 2008-12-16 17:33:52 -0800 | [diff] [blame] | 107 | *retmask = (cpumask_t) { { [0] = APIC_ALL_CPUS } }; |
Yinghai Lu | 497c9a1 | 2008-08-19 20:50:28 -0700 | [diff] [blame] | 108 | } |
Glauber de Oliveira Costa | f6bc402 | 2008-03-19 14:25:53 -0300 | [diff] [blame] | 109 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 110 | |
Glauber Costa | dd46e3c | 2008-03-25 18:10:46 -0300 | [diff] [blame] | 111 | static inline unsigned long check_apicid_used(physid_mask_t bitmap, int apicid) |
| 112 | { |
| 113 | return physid_isset(apicid, bitmap); |
| 114 | } |
| 115 | |
| 116 | static inline unsigned long check_apicid_present(int bit) |
| 117 | { |
| 118 | return physid_isset(bit, phys_cpu_present_map); |
| 119 | } |
| 120 | |
| 121 | static inline physid_mask_t ioapic_phys_id_map(physid_mask_t phys_map) |
| 122 | { |
| 123 | return phys_map; |
| 124 | } |
| 125 | |
| 126 | static inline int multi_timer_check(int apic, int irq) |
| 127 | { |
| 128 | return 0; |
| 129 | } |
| 130 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 131 | /* Mapping from cpu number to logical apicid */ |
| 132 | static inline int cpu_to_logical_apicid(int cpu) |
| 133 | { |
| 134 | return 1 << cpu; |
| 135 | } |
| 136 | |
| 137 | static inline int cpu_present_to_apicid(int mps_cpu) |
| 138 | { |
Mike Travis | e798673 | 2008-12-16 17:33:52 -0800 | [diff] [blame] | 139 | if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu)) |
Glauber de Oliveira Costa | f6bc402 | 2008-03-19 14:25:53 -0300 | [diff] [blame] | 140 | return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 141 | else |
| 142 | return BAD_APICID; |
| 143 | } |
| 144 | |
| 145 | static inline physid_mask_t apicid_to_cpu_present(int phys_apicid) |
| 146 | { |
| 147 | return physid_mask_of_physid(phys_apicid); |
| 148 | } |
| 149 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 150 | static inline void setup_portio_remap(void) |
| 151 | { |
| 152 | } |
| 153 | |
| 154 | static inline int check_phys_apicid_present(int boot_cpu_physical_apicid) |
| 155 | { |
| 156 | return physid_isset(boot_cpu_physical_apicid, phys_cpu_present_map); |
| 157 | } |
| 158 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 159 | static inline void enable_apic_mode(void) |
| 160 | { |
| 161 | } |
Glauber Costa | dd46e3c | 2008-03-25 18:10:46 -0300 | [diff] [blame] | 162 | #endif /* CONFIG_X86_LOCAL_APIC */ |
H. Peter Anvin | 05e4d31 | 2008-10-23 00:01:39 -0700 | [diff] [blame] | 163 | #endif /* _ASM_X86_MACH_DEFAULT_MACH_APIC_H */ |