Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2008,2010 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | * Chris Wilson <chris@chris-wilson.co.uk> |
| 26 | * |
| 27 | */ |
| 28 | |
| 29 | #include "drmP.h" |
| 30 | #include "drm.h" |
| 31 | #include "i915_drm.h" |
| 32 | #include "i915_drv.h" |
| 33 | #include "i915_trace.h" |
| 34 | #include "intel_drv.h" |
Eugeni Dodonov | f45b555 | 2011-12-09 17:16:37 -0800 | [diff] [blame] | 35 | #include <linux/dma_remapping.h> |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 36 | |
| 37 | struct change_domains { |
| 38 | uint32_t invalidate_domains; |
| 39 | uint32_t flush_domains; |
| 40 | uint32_t flush_rings; |
Chris Wilson | c59a333 | 2011-03-06 13:51:29 +0000 | [diff] [blame] | 41 | uint32_t flips; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 42 | }; |
| 43 | |
| 44 | /* |
| 45 | * Set the next domain for the specified object. This |
| 46 | * may not actually perform the necessary flushing/invaliding though, |
| 47 | * as that may want to be batched with other set_domain operations |
| 48 | * |
| 49 | * This is (we hope) the only really tricky part of gem. The goal |
| 50 | * is fairly simple -- track which caches hold bits of the object |
| 51 | * and make sure they remain coherent. A few concrete examples may |
| 52 | * help to explain how it works. For shorthand, we use the notation |
| 53 | * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the |
| 54 | * a pair of read and write domain masks. |
| 55 | * |
| 56 | * Case 1: the batch buffer |
| 57 | * |
| 58 | * 1. Allocated |
| 59 | * 2. Written by CPU |
| 60 | * 3. Mapped to GTT |
| 61 | * 4. Read by GPU |
| 62 | * 5. Unmapped from GTT |
| 63 | * 6. Freed |
| 64 | * |
| 65 | * Let's take these a step at a time |
| 66 | * |
| 67 | * 1. Allocated |
| 68 | * Pages allocated from the kernel may still have |
| 69 | * cache contents, so we set them to (CPU, CPU) always. |
| 70 | * 2. Written by CPU (using pwrite) |
| 71 | * The pwrite function calls set_domain (CPU, CPU) and |
| 72 | * this function does nothing (as nothing changes) |
| 73 | * 3. Mapped by GTT |
| 74 | * This function asserts that the object is not |
| 75 | * currently in any GPU-based read or write domains |
| 76 | * 4. Read by GPU |
| 77 | * i915_gem_execbuffer calls set_domain (COMMAND, 0). |
| 78 | * As write_domain is zero, this function adds in the |
| 79 | * current read domains (CPU+COMMAND, 0). |
| 80 | * flush_domains is set to CPU. |
| 81 | * invalidate_domains is set to COMMAND |
| 82 | * clflush is run to get data out of the CPU caches |
| 83 | * then i915_dev_set_domain calls i915_gem_flush to |
| 84 | * emit an MI_FLUSH and drm_agp_chipset_flush |
| 85 | * 5. Unmapped from GTT |
| 86 | * i915_gem_object_unbind calls set_domain (CPU, CPU) |
| 87 | * flush_domains and invalidate_domains end up both zero |
| 88 | * so no flushing/invalidating happens |
| 89 | * 6. Freed |
| 90 | * yay, done |
| 91 | * |
| 92 | * Case 2: The shared render buffer |
| 93 | * |
| 94 | * 1. Allocated |
| 95 | * 2. Mapped to GTT |
| 96 | * 3. Read/written by GPU |
| 97 | * 4. set_domain to (CPU,CPU) |
| 98 | * 5. Read/written by CPU |
| 99 | * 6. Read/written by GPU |
| 100 | * |
| 101 | * 1. Allocated |
| 102 | * Same as last example, (CPU, CPU) |
| 103 | * 2. Mapped to GTT |
| 104 | * Nothing changes (assertions find that it is not in the GPU) |
| 105 | * 3. Read/written by GPU |
| 106 | * execbuffer calls set_domain (RENDER, RENDER) |
| 107 | * flush_domains gets CPU |
| 108 | * invalidate_domains gets GPU |
| 109 | * clflush (obj) |
| 110 | * MI_FLUSH and drm_agp_chipset_flush |
| 111 | * 4. set_domain (CPU, CPU) |
| 112 | * flush_domains gets GPU |
| 113 | * invalidate_domains gets CPU |
| 114 | * wait_rendering (obj) to make sure all drawing is complete. |
| 115 | * This will include an MI_FLUSH to get the data from GPU |
| 116 | * to memory |
| 117 | * clflush (obj) to invalidate the CPU cache |
| 118 | * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?) |
| 119 | * 5. Read/written by CPU |
| 120 | * cache lines are loaded and dirtied |
| 121 | * 6. Read written by GPU |
| 122 | * Same as last GPU access |
| 123 | * |
| 124 | * Case 3: The constant buffer |
| 125 | * |
| 126 | * 1. Allocated |
| 127 | * 2. Written by CPU |
| 128 | * 3. Read by GPU |
| 129 | * 4. Updated (written) by CPU again |
| 130 | * 5. Read by GPU |
| 131 | * |
| 132 | * 1. Allocated |
| 133 | * (CPU, CPU) |
| 134 | * 2. Written by CPU |
| 135 | * (CPU, CPU) |
| 136 | * 3. Read by GPU |
| 137 | * (CPU+RENDER, 0) |
| 138 | * flush_domains = CPU |
| 139 | * invalidate_domains = RENDER |
| 140 | * clflush (obj) |
| 141 | * MI_FLUSH |
| 142 | * drm_agp_chipset_flush |
| 143 | * 4. Updated (written) by CPU again |
| 144 | * (CPU, CPU) |
| 145 | * flush_domains = 0 (no previous write domain) |
| 146 | * invalidate_domains = 0 (no new read domains) |
| 147 | * 5. Read by GPU |
| 148 | * (CPU+RENDER, 0) |
| 149 | * flush_domains = CPU |
| 150 | * invalidate_domains = RENDER |
| 151 | * clflush (obj) |
| 152 | * MI_FLUSH |
| 153 | * drm_agp_chipset_flush |
| 154 | */ |
| 155 | static void |
| 156 | i915_gem_object_set_to_gpu_domain(struct drm_i915_gem_object *obj, |
| 157 | struct intel_ring_buffer *ring, |
| 158 | struct change_domains *cd) |
| 159 | { |
| 160 | uint32_t invalidate_domains = 0, flush_domains = 0; |
| 161 | |
| 162 | /* |
| 163 | * If the object isn't moving to a new write domain, |
| 164 | * let the object stay in multiple read domains |
| 165 | */ |
| 166 | if (obj->base.pending_write_domain == 0) |
| 167 | obj->base.pending_read_domains |= obj->base.read_domains; |
| 168 | |
| 169 | /* |
| 170 | * Flush the current write domain if |
| 171 | * the new read domains don't match. Invalidate |
| 172 | * any read domains which differ from the old |
| 173 | * write domain |
| 174 | */ |
| 175 | if (obj->base.write_domain && |
| 176 | (((obj->base.write_domain != obj->base.pending_read_domains || |
| 177 | obj->ring != ring)) || |
| 178 | (obj->fenced_gpu_access && !obj->pending_fenced_gpu_access))) { |
| 179 | flush_domains |= obj->base.write_domain; |
| 180 | invalidate_domains |= |
| 181 | obj->base.pending_read_domains & ~obj->base.write_domain; |
| 182 | } |
| 183 | /* |
| 184 | * Invalidate any read caches which may have |
| 185 | * stale data. That is, any new read domains. |
| 186 | */ |
| 187 | invalidate_domains |= obj->base.pending_read_domains & ~obj->base.read_domains; |
| 188 | if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) |
| 189 | i915_gem_clflush_object(obj); |
| 190 | |
Chris Wilson | c59a333 | 2011-03-06 13:51:29 +0000 | [diff] [blame] | 191 | if (obj->base.pending_write_domain) |
| 192 | cd->flips |= atomic_read(&obj->pending_flip); |
| 193 | |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 194 | /* The actual obj->write_domain will be updated with |
| 195 | * pending_write_domain after we emit the accumulated flush for all |
| 196 | * of our domain changes in execbuffers (which clears objects' |
| 197 | * write_domains). So if we have a current write domain that we |
| 198 | * aren't changing, set pending_write_domain to that. |
| 199 | */ |
| 200 | if (flush_domains == 0 && obj->base.pending_write_domain == 0) |
| 201 | obj->base.pending_write_domain = obj->base.write_domain; |
| 202 | |
| 203 | cd->invalidate_domains |= invalidate_domains; |
| 204 | cd->flush_domains |= flush_domains; |
| 205 | if (flush_domains & I915_GEM_GPU_DOMAINS) |
Daniel Vetter | 96154f2 | 2011-12-14 13:57:00 +0100 | [diff] [blame] | 206 | cd->flush_rings |= intel_ring_flag(obj->ring); |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 207 | if (invalidate_domains & I915_GEM_GPU_DOMAINS) |
Daniel Vetter | 96154f2 | 2011-12-14 13:57:00 +0100 | [diff] [blame] | 208 | cd->flush_rings |= intel_ring_flag(ring); |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 209 | } |
| 210 | |
Chris Wilson | 67731b8 | 2010-12-08 10:38:14 +0000 | [diff] [blame] | 211 | struct eb_objects { |
| 212 | int and; |
| 213 | struct hlist_head buckets[0]; |
| 214 | }; |
| 215 | |
| 216 | static struct eb_objects * |
| 217 | eb_create(int size) |
| 218 | { |
| 219 | struct eb_objects *eb; |
| 220 | int count = PAGE_SIZE / sizeof(struct hlist_head) / 2; |
| 221 | while (count > size) |
| 222 | count >>= 1; |
| 223 | eb = kzalloc(count*sizeof(struct hlist_head) + |
| 224 | sizeof(struct eb_objects), |
| 225 | GFP_KERNEL); |
| 226 | if (eb == NULL) |
| 227 | return eb; |
| 228 | |
| 229 | eb->and = count - 1; |
| 230 | return eb; |
| 231 | } |
| 232 | |
| 233 | static void |
| 234 | eb_reset(struct eb_objects *eb) |
| 235 | { |
| 236 | memset(eb->buckets, 0, (eb->and+1)*sizeof(struct hlist_head)); |
| 237 | } |
| 238 | |
| 239 | static void |
| 240 | eb_add_object(struct eb_objects *eb, struct drm_i915_gem_object *obj) |
| 241 | { |
| 242 | hlist_add_head(&obj->exec_node, |
| 243 | &eb->buckets[obj->exec_handle & eb->and]); |
| 244 | } |
| 245 | |
| 246 | static struct drm_i915_gem_object * |
| 247 | eb_get_object(struct eb_objects *eb, unsigned long handle) |
| 248 | { |
| 249 | struct hlist_head *head; |
| 250 | struct hlist_node *node; |
| 251 | struct drm_i915_gem_object *obj; |
| 252 | |
| 253 | head = &eb->buckets[handle & eb->and]; |
| 254 | hlist_for_each(node, head) { |
| 255 | obj = hlist_entry(node, struct drm_i915_gem_object, exec_node); |
| 256 | if (obj->exec_handle == handle) |
| 257 | return obj; |
| 258 | } |
| 259 | |
| 260 | return NULL; |
| 261 | } |
| 262 | |
| 263 | static void |
| 264 | eb_destroy(struct eb_objects *eb) |
| 265 | { |
| 266 | kfree(eb); |
| 267 | } |
| 268 | |
Chris Wilson | dabdfe0 | 2012-03-26 10:10:27 +0200 | [diff] [blame] | 269 | static inline int use_cpu_reloc(struct drm_i915_gem_object *obj) |
| 270 | { |
| 271 | return (obj->base.write_domain == I915_GEM_DOMAIN_CPU || |
| 272 | obj->cache_level != I915_CACHE_NONE); |
| 273 | } |
| 274 | |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 275 | static int |
| 276 | i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj, |
Chris Wilson | 67731b8 | 2010-12-08 10:38:14 +0000 | [diff] [blame] | 277 | struct eb_objects *eb, |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 278 | struct drm_i915_gem_relocation_entry *reloc) |
| 279 | { |
| 280 | struct drm_device *dev = obj->base.dev; |
| 281 | struct drm_gem_object *target_obj; |
Daniel Vetter | 149c840 | 2012-02-15 23:50:23 +0100 | [diff] [blame] | 282 | struct drm_i915_gem_object *target_i915_obj; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 283 | uint32_t target_offset; |
| 284 | int ret = -EINVAL; |
| 285 | |
Chris Wilson | 67731b8 | 2010-12-08 10:38:14 +0000 | [diff] [blame] | 286 | /* we've already hold a reference to all valid objects */ |
| 287 | target_obj = &eb_get_object(eb, reloc->target_handle)->base; |
| 288 | if (unlikely(target_obj == NULL)) |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 289 | return -ENOENT; |
| 290 | |
Daniel Vetter | 149c840 | 2012-02-15 23:50:23 +0100 | [diff] [blame] | 291 | target_i915_obj = to_intel_bo(target_obj); |
| 292 | target_offset = target_i915_obj->gtt_offset; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 293 | |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 294 | /* The target buffer should have appeared before us in the |
| 295 | * exec_object list, so it should have a GTT space bound by now. |
| 296 | */ |
Chris Wilson | b8f7ab1 | 2010-12-08 10:43:06 +0000 | [diff] [blame] | 297 | if (unlikely(target_offset == 0)) { |
Daniel Vetter | ff24019 | 2012-01-31 21:08:14 +0100 | [diff] [blame] | 298 | DRM_DEBUG("No GTT space found for object %d\n", |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 299 | reloc->target_handle); |
Chris Wilson | 67731b8 | 2010-12-08 10:38:14 +0000 | [diff] [blame] | 300 | return ret; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 301 | } |
| 302 | |
| 303 | /* Validate that the target is in a valid r/w GPU domain */ |
Chris Wilson | b8f7ab1 | 2010-12-08 10:43:06 +0000 | [diff] [blame] | 304 | if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) { |
Daniel Vetter | ff24019 | 2012-01-31 21:08:14 +0100 | [diff] [blame] | 305 | DRM_DEBUG("reloc with multiple write domains: " |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 306 | "obj %p target %d offset %d " |
| 307 | "read %08x write %08x", |
| 308 | obj, reloc->target_handle, |
| 309 | (int) reloc->offset, |
| 310 | reloc->read_domains, |
| 311 | reloc->write_domain); |
Chris Wilson | 67731b8 | 2010-12-08 10:38:14 +0000 | [diff] [blame] | 312 | return ret; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 313 | } |
Daniel Vetter | 4ca4a25 | 2011-12-14 13:57:27 +0100 | [diff] [blame] | 314 | if (unlikely((reloc->write_domain | reloc->read_domains) |
| 315 | & ~I915_GEM_GPU_DOMAINS)) { |
Daniel Vetter | ff24019 | 2012-01-31 21:08:14 +0100 | [diff] [blame] | 316 | DRM_DEBUG("reloc with read/write non-GPU domains: " |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 317 | "obj %p target %d offset %d " |
| 318 | "read %08x write %08x", |
| 319 | obj, reloc->target_handle, |
| 320 | (int) reloc->offset, |
| 321 | reloc->read_domains, |
| 322 | reloc->write_domain); |
Chris Wilson | 67731b8 | 2010-12-08 10:38:14 +0000 | [diff] [blame] | 323 | return ret; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 324 | } |
Chris Wilson | b8f7ab1 | 2010-12-08 10:43:06 +0000 | [diff] [blame] | 325 | if (unlikely(reloc->write_domain && target_obj->pending_write_domain && |
| 326 | reloc->write_domain != target_obj->pending_write_domain)) { |
Daniel Vetter | ff24019 | 2012-01-31 21:08:14 +0100 | [diff] [blame] | 327 | DRM_DEBUG("Write domain conflict: " |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 328 | "obj %p target %d offset %d " |
| 329 | "new %08x old %08x\n", |
| 330 | obj, reloc->target_handle, |
| 331 | (int) reloc->offset, |
| 332 | reloc->write_domain, |
| 333 | target_obj->pending_write_domain); |
Chris Wilson | 67731b8 | 2010-12-08 10:38:14 +0000 | [diff] [blame] | 334 | return ret; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 335 | } |
| 336 | |
| 337 | target_obj->pending_read_domains |= reloc->read_domains; |
| 338 | target_obj->pending_write_domain |= reloc->write_domain; |
| 339 | |
| 340 | /* If the relocation already has the right value in it, no |
| 341 | * more work needs to be done. |
| 342 | */ |
| 343 | if (target_offset == reloc->presumed_offset) |
Chris Wilson | 67731b8 | 2010-12-08 10:38:14 +0000 | [diff] [blame] | 344 | return 0; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 345 | |
| 346 | /* Check that the relocation address is valid... */ |
Chris Wilson | b8f7ab1 | 2010-12-08 10:43:06 +0000 | [diff] [blame] | 347 | if (unlikely(reloc->offset > obj->base.size - 4)) { |
Daniel Vetter | ff24019 | 2012-01-31 21:08:14 +0100 | [diff] [blame] | 348 | DRM_DEBUG("Relocation beyond object bounds: " |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 349 | "obj %p target %d offset %d size %d.\n", |
| 350 | obj, reloc->target_handle, |
| 351 | (int) reloc->offset, |
| 352 | (int) obj->base.size); |
Chris Wilson | 67731b8 | 2010-12-08 10:38:14 +0000 | [diff] [blame] | 353 | return ret; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 354 | } |
Chris Wilson | b8f7ab1 | 2010-12-08 10:43:06 +0000 | [diff] [blame] | 355 | if (unlikely(reloc->offset & 3)) { |
Daniel Vetter | ff24019 | 2012-01-31 21:08:14 +0100 | [diff] [blame] | 356 | DRM_DEBUG("Relocation not 4-byte aligned: " |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 357 | "obj %p target %d offset %d.\n", |
| 358 | obj, reloc->target_handle, |
| 359 | (int) reloc->offset); |
Chris Wilson | 67731b8 | 2010-12-08 10:38:14 +0000 | [diff] [blame] | 360 | return ret; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 361 | } |
| 362 | |
Chris Wilson | dabdfe0 | 2012-03-26 10:10:27 +0200 | [diff] [blame] | 363 | /* We can't wait for rendering with pagefaults disabled */ |
| 364 | if (obj->active && in_atomic()) |
| 365 | return -EFAULT; |
| 366 | |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 367 | reloc->delta += target_offset; |
Chris Wilson | dabdfe0 | 2012-03-26 10:10:27 +0200 | [diff] [blame] | 368 | if (use_cpu_reloc(obj)) { |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 369 | uint32_t page_offset = reloc->offset & ~PAGE_MASK; |
| 370 | char *vaddr; |
| 371 | |
Chris Wilson | dabdfe0 | 2012-03-26 10:10:27 +0200 | [diff] [blame] | 372 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
| 373 | if (ret) |
| 374 | return ret; |
| 375 | |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 376 | vaddr = kmap_atomic(obj->pages[reloc->offset >> PAGE_SHIFT]); |
| 377 | *(uint32_t *)(vaddr + page_offset) = reloc->delta; |
| 378 | kunmap_atomic(vaddr); |
| 379 | } else { |
| 380 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 381 | uint32_t __iomem *reloc_entry; |
| 382 | void __iomem *reloc_page; |
| 383 | |
Chris Wilson | 7b09638 | 2012-04-14 09:55:51 +0100 | [diff] [blame] | 384 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
| 385 | if (ret) |
| 386 | return ret; |
| 387 | |
| 388 | ret = i915_gem_object_put_fence(obj); |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 389 | if (ret) |
Chris Wilson | 67731b8 | 2010-12-08 10:38:14 +0000 | [diff] [blame] | 390 | return ret; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 391 | |
| 392 | /* Map the page containing the relocation we're going to perform. */ |
| 393 | reloc->offset += obj->gtt_offset; |
| 394 | reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping, |
| 395 | reloc->offset & PAGE_MASK); |
| 396 | reloc_entry = (uint32_t __iomem *) |
| 397 | (reloc_page + (reloc->offset & ~PAGE_MASK)); |
| 398 | iowrite32(reloc->delta, reloc_entry); |
| 399 | io_mapping_unmap_atomic(reloc_page); |
| 400 | } |
| 401 | |
Daniel Vetter | 149c840 | 2012-02-15 23:50:23 +0100 | [diff] [blame] | 402 | /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and |
| 403 | * pipe_control writes because the gpu doesn't properly redirect them |
| 404 | * through the ppgtt for non_secure batchbuffers. */ |
| 405 | if (unlikely(IS_GEN6(dev) && |
| 406 | reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION && |
| 407 | !target_i915_obj->has_global_gtt_mapping)) { |
| 408 | i915_gem_gtt_bind_object(target_i915_obj, |
| 409 | target_i915_obj->cache_level); |
| 410 | } |
| 411 | |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 412 | /* and update the user's relocation entry */ |
| 413 | reloc->presumed_offset = target_offset; |
| 414 | |
Chris Wilson | 67731b8 | 2010-12-08 10:38:14 +0000 | [diff] [blame] | 415 | return 0; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 416 | } |
| 417 | |
| 418 | static int |
| 419 | i915_gem_execbuffer_relocate_object(struct drm_i915_gem_object *obj, |
Chris Wilson | 6fe4f14 | 2011-01-10 17:35:37 +0000 | [diff] [blame] | 420 | struct eb_objects *eb) |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 421 | { |
Chris Wilson | 1d83f44 | 2012-03-24 20:12:53 +0000 | [diff] [blame] | 422 | #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry)) |
| 423 | struct drm_i915_gem_relocation_entry stack_reloc[N_RELOC(512)]; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 424 | struct drm_i915_gem_relocation_entry __user *user_relocs; |
Chris Wilson | 6fe4f14 | 2011-01-10 17:35:37 +0000 | [diff] [blame] | 425 | struct drm_i915_gem_exec_object2 *entry = obj->exec_entry; |
Chris Wilson | 1d83f44 | 2012-03-24 20:12:53 +0000 | [diff] [blame] | 426 | int remain, ret; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 427 | |
| 428 | user_relocs = (void __user *)(uintptr_t)entry->relocs_ptr; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 429 | |
Chris Wilson | 1d83f44 | 2012-03-24 20:12:53 +0000 | [diff] [blame] | 430 | remain = entry->relocation_count; |
| 431 | while (remain) { |
| 432 | struct drm_i915_gem_relocation_entry *r = stack_reloc; |
| 433 | int count = remain; |
| 434 | if (count > ARRAY_SIZE(stack_reloc)) |
| 435 | count = ARRAY_SIZE(stack_reloc); |
| 436 | remain -= count; |
| 437 | |
| 438 | if (__copy_from_user_inatomic(r, user_relocs, count*sizeof(r[0]))) |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 439 | return -EFAULT; |
| 440 | |
Chris Wilson | 1d83f44 | 2012-03-24 20:12:53 +0000 | [diff] [blame] | 441 | do { |
| 442 | u64 offset = r->presumed_offset; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 443 | |
Chris Wilson | 1d83f44 | 2012-03-24 20:12:53 +0000 | [diff] [blame] | 444 | ret = i915_gem_execbuffer_relocate_entry(obj, eb, r); |
| 445 | if (ret) |
| 446 | return ret; |
| 447 | |
| 448 | if (r->presumed_offset != offset && |
| 449 | __copy_to_user_inatomic(&user_relocs->presumed_offset, |
| 450 | &r->presumed_offset, |
| 451 | sizeof(r->presumed_offset))) { |
| 452 | return -EFAULT; |
| 453 | } |
| 454 | |
| 455 | user_relocs++; |
| 456 | r++; |
| 457 | } while (--count); |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 458 | } |
| 459 | |
| 460 | return 0; |
Chris Wilson | 1d83f44 | 2012-03-24 20:12:53 +0000 | [diff] [blame] | 461 | #undef N_RELOC |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 462 | } |
| 463 | |
| 464 | static int |
| 465 | i915_gem_execbuffer_relocate_object_slow(struct drm_i915_gem_object *obj, |
Chris Wilson | 67731b8 | 2010-12-08 10:38:14 +0000 | [diff] [blame] | 466 | struct eb_objects *eb, |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 467 | struct drm_i915_gem_relocation_entry *relocs) |
| 468 | { |
Chris Wilson | 6fe4f14 | 2011-01-10 17:35:37 +0000 | [diff] [blame] | 469 | const struct drm_i915_gem_exec_object2 *entry = obj->exec_entry; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 470 | int i, ret; |
| 471 | |
| 472 | for (i = 0; i < entry->relocation_count; i++) { |
Chris Wilson | 6fe4f14 | 2011-01-10 17:35:37 +0000 | [diff] [blame] | 473 | ret = i915_gem_execbuffer_relocate_entry(obj, eb, &relocs[i]); |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 474 | if (ret) |
| 475 | return ret; |
| 476 | } |
| 477 | |
| 478 | return 0; |
| 479 | } |
| 480 | |
| 481 | static int |
| 482 | i915_gem_execbuffer_relocate(struct drm_device *dev, |
Chris Wilson | 67731b8 | 2010-12-08 10:38:14 +0000 | [diff] [blame] | 483 | struct eb_objects *eb, |
Chris Wilson | 6fe4f14 | 2011-01-10 17:35:37 +0000 | [diff] [blame] | 484 | struct list_head *objects) |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 485 | { |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 486 | struct drm_i915_gem_object *obj; |
Chris Wilson | d4aeee7 | 2011-03-14 15:11:24 +0000 | [diff] [blame] | 487 | int ret = 0; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 488 | |
Chris Wilson | d4aeee7 | 2011-03-14 15:11:24 +0000 | [diff] [blame] | 489 | /* This is the fast path and we cannot handle a pagefault whilst |
| 490 | * holding the struct mutex lest the user pass in the relocations |
| 491 | * contained within a mmaped bo. For in such a case we, the page |
| 492 | * fault handler would call i915_gem_fault() and we would try to |
| 493 | * acquire the struct mutex again. Obviously this is bad and so |
| 494 | * lockdep complains vehemently. |
| 495 | */ |
| 496 | pagefault_disable(); |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 497 | list_for_each_entry(obj, objects, exec_list) { |
Chris Wilson | 6fe4f14 | 2011-01-10 17:35:37 +0000 | [diff] [blame] | 498 | ret = i915_gem_execbuffer_relocate_object(obj, eb); |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 499 | if (ret) |
Chris Wilson | d4aeee7 | 2011-03-14 15:11:24 +0000 | [diff] [blame] | 500 | break; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 501 | } |
Chris Wilson | d4aeee7 | 2011-03-14 15:11:24 +0000 | [diff] [blame] | 502 | pagefault_enable(); |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 503 | |
Chris Wilson | d4aeee7 | 2011-03-14 15:11:24 +0000 | [diff] [blame] | 504 | return ret; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 505 | } |
| 506 | |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 507 | #define __EXEC_OBJECT_HAS_FENCE (1<<31) |
| 508 | |
| 509 | static int |
Chris Wilson | dabdfe0 | 2012-03-26 10:10:27 +0200 | [diff] [blame] | 510 | need_reloc_mappable(struct drm_i915_gem_object *obj) |
| 511 | { |
| 512 | struct drm_i915_gem_exec_object2 *entry = obj->exec_entry; |
| 513 | return entry->relocation_count && !use_cpu_reloc(obj); |
| 514 | } |
| 515 | |
| 516 | static int |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 517 | pin_and_fence_object(struct drm_i915_gem_object *obj, |
| 518 | struct intel_ring_buffer *ring) |
| 519 | { |
| 520 | struct drm_i915_gem_exec_object2 *entry = obj->exec_entry; |
| 521 | bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4; |
| 522 | bool need_fence, need_mappable; |
| 523 | int ret; |
| 524 | |
| 525 | need_fence = |
| 526 | has_fenced_gpu_access && |
| 527 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && |
| 528 | obj->tiling_mode != I915_TILING_NONE; |
Chris Wilson | dabdfe0 | 2012-03-26 10:10:27 +0200 | [diff] [blame] | 529 | need_mappable = need_fence || need_reloc_mappable(obj); |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 530 | |
| 531 | ret = i915_gem_object_pin(obj, entry->alignment, need_mappable); |
| 532 | if (ret) |
| 533 | return ret; |
| 534 | |
| 535 | if (has_fenced_gpu_access) { |
| 536 | if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) { |
Chris Wilson | 06d9813 | 2012-04-17 15:31:24 +0100 | [diff] [blame] | 537 | ret = i915_gem_object_get_fence(obj); |
Chris Wilson | 9a5a53b | 2012-03-22 15:10:00 +0000 | [diff] [blame] | 538 | if (ret) |
| 539 | goto err_unpin; |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 540 | |
Chris Wilson | 9a5a53b | 2012-03-22 15:10:00 +0000 | [diff] [blame] | 541 | if (i915_gem_object_pin_fence(obj)) |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 542 | entry->flags |= __EXEC_OBJECT_HAS_FENCE; |
Chris Wilson | 9a5a53b | 2012-03-22 15:10:00 +0000 | [diff] [blame] | 543 | |
Chris Wilson | 7dd4906 | 2012-03-21 10:48:18 +0000 | [diff] [blame] | 544 | obj->pending_fenced_gpu_access = true; |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 545 | } |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 546 | } |
| 547 | |
| 548 | entry->offset = obj->gtt_offset; |
| 549 | return 0; |
| 550 | |
| 551 | err_unpin: |
| 552 | i915_gem_object_unpin(obj); |
| 553 | return ret; |
| 554 | } |
| 555 | |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 556 | static int |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 557 | i915_gem_execbuffer_reserve(struct intel_ring_buffer *ring, |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 558 | struct drm_file *file, |
Chris Wilson | 6fe4f14 | 2011-01-10 17:35:37 +0000 | [diff] [blame] | 559 | struct list_head *objects) |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 560 | { |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 561 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 562 | struct drm_i915_gem_object *obj; |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 563 | int ret, retry; |
Chris Wilson | 9b3826b | 2010-12-05 17:11:54 +0000 | [diff] [blame] | 564 | bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4; |
Chris Wilson | 6fe4f14 | 2011-01-10 17:35:37 +0000 | [diff] [blame] | 565 | struct list_head ordered_objects; |
| 566 | |
| 567 | INIT_LIST_HEAD(&ordered_objects); |
| 568 | while (!list_empty(objects)) { |
| 569 | struct drm_i915_gem_exec_object2 *entry; |
| 570 | bool need_fence, need_mappable; |
| 571 | |
| 572 | obj = list_first_entry(objects, |
| 573 | struct drm_i915_gem_object, |
| 574 | exec_list); |
| 575 | entry = obj->exec_entry; |
| 576 | |
| 577 | need_fence = |
| 578 | has_fenced_gpu_access && |
| 579 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && |
| 580 | obj->tiling_mode != I915_TILING_NONE; |
Chris Wilson | dabdfe0 | 2012-03-26 10:10:27 +0200 | [diff] [blame] | 581 | need_mappable = need_fence || need_reloc_mappable(obj); |
Chris Wilson | 6fe4f14 | 2011-01-10 17:35:37 +0000 | [diff] [blame] | 582 | |
| 583 | if (need_mappable) |
| 584 | list_move(&obj->exec_list, &ordered_objects); |
| 585 | else |
| 586 | list_move_tail(&obj->exec_list, &ordered_objects); |
Chris Wilson | 595dad7 | 2011-01-13 11:03:48 +0000 | [diff] [blame] | 587 | |
| 588 | obj->base.pending_read_domains = 0; |
| 589 | obj->base.pending_write_domain = 0; |
Chris Wilson | 6fe4f14 | 2011-01-10 17:35:37 +0000 | [diff] [blame] | 590 | } |
| 591 | list_splice(&ordered_objects, objects); |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 592 | |
| 593 | /* Attempt to pin all of the buffers into the GTT. |
| 594 | * This is done in 3 phases: |
| 595 | * |
| 596 | * 1a. Unbind all objects that do not match the GTT constraints for |
| 597 | * the execbuffer (fenceable, mappable, alignment etc). |
| 598 | * 1b. Increment pin count for already bound objects. |
| 599 | * 2. Bind new objects. |
| 600 | * 3. Decrement pin count. |
| 601 | * |
| 602 | * This avoid unnecessary unbinding of later objects in order to makr |
| 603 | * room for the earlier objects *unless* we need to defragment. |
| 604 | */ |
| 605 | retry = 0; |
| 606 | do { |
| 607 | ret = 0; |
| 608 | |
| 609 | /* Unbind any ill-fitting objects or pin. */ |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 610 | list_for_each_entry(obj, objects, exec_list) { |
Chris Wilson | 6fe4f14 | 2011-01-10 17:35:37 +0000 | [diff] [blame] | 611 | struct drm_i915_gem_exec_object2 *entry = obj->exec_entry; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 612 | bool need_fence, need_mappable; |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 613 | |
Chris Wilson | 6fe4f14 | 2011-01-10 17:35:37 +0000 | [diff] [blame] | 614 | if (!obj->gtt_space) |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 615 | continue; |
| 616 | |
| 617 | need_fence = |
Chris Wilson | 9b3826b | 2010-12-05 17:11:54 +0000 | [diff] [blame] | 618 | has_fenced_gpu_access && |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 619 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && |
| 620 | obj->tiling_mode != I915_TILING_NONE; |
Chris Wilson | dabdfe0 | 2012-03-26 10:10:27 +0200 | [diff] [blame] | 621 | need_mappable = need_fence || need_reloc_mappable(obj); |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 622 | |
| 623 | if ((entry->alignment && obj->gtt_offset & (entry->alignment - 1)) || |
| 624 | (need_mappable && !obj->map_and_fenceable)) |
| 625 | ret = i915_gem_object_unbind(obj); |
| 626 | else |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 627 | ret = pin_and_fence_object(obj, ring); |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 628 | if (ret) |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 629 | goto err; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 630 | } |
| 631 | |
| 632 | /* Bind fresh objects */ |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 633 | list_for_each_entry(obj, objects, exec_list) { |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 634 | if (obj->gtt_space) |
| 635 | continue; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 636 | |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 637 | ret = pin_and_fence_object(obj, ring); |
| 638 | if (ret) { |
| 639 | int ret_ignore; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 640 | |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 641 | /* This can potentially raise a harmless |
| 642 | * -EINVAL if we failed to bind in the above |
| 643 | * call. It cannot raise -EINTR since we know |
| 644 | * that the bo is freshly bound and so will |
| 645 | * not need to be flushed or waited upon. |
| 646 | */ |
| 647 | ret_ignore = i915_gem_object_unbind(obj); |
| 648 | (void)ret_ignore; |
| 649 | WARN_ON(obj->gtt_space); |
| 650 | break; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 651 | } |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 652 | } |
| 653 | |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 654 | /* Decrement pin count for bound objects */ |
| 655 | list_for_each_entry(obj, objects, exec_list) { |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 656 | struct drm_i915_gem_exec_object2 *entry; |
| 657 | |
| 658 | if (!obj->gtt_space) |
| 659 | continue; |
| 660 | |
| 661 | entry = obj->exec_entry; |
| 662 | if (entry->flags & __EXEC_OBJECT_HAS_FENCE) { |
| 663 | i915_gem_object_unpin_fence(obj); |
| 664 | entry->flags &= ~__EXEC_OBJECT_HAS_FENCE; |
| 665 | } |
| 666 | |
| 667 | i915_gem_object_unpin(obj); |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 668 | |
| 669 | /* ... and ensure ppgtt mapping exist if needed. */ |
| 670 | if (dev_priv->mm.aliasing_ppgtt && !obj->has_aliasing_ppgtt_mapping) { |
| 671 | i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt, |
| 672 | obj, obj->cache_level); |
| 673 | |
| 674 | obj->has_aliasing_ppgtt_mapping = 1; |
| 675 | } |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 676 | } |
| 677 | |
| 678 | if (ret != -ENOSPC || retry > 1) |
| 679 | return ret; |
| 680 | |
| 681 | /* First attempt, just clear anything that is purgeable. |
| 682 | * Second attempt, clear the entire GTT. |
| 683 | */ |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 684 | ret = i915_gem_evict_everything(ring->dev, retry == 0); |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 685 | if (ret) |
| 686 | return ret; |
| 687 | |
| 688 | retry++; |
| 689 | } while (1); |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 690 | |
| 691 | err: |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 692 | list_for_each_entry_continue_reverse(obj, objects, exec_list) { |
| 693 | struct drm_i915_gem_exec_object2 *entry; |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 694 | |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 695 | if (!obj->gtt_space) |
| 696 | continue; |
| 697 | |
| 698 | entry = obj->exec_entry; |
| 699 | if (entry->flags & __EXEC_OBJECT_HAS_FENCE) { |
| 700 | i915_gem_object_unpin_fence(obj); |
| 701 | entry->flags &= ~__EXEC_OBJECT_HAS_FENCE; |
| 702 | } |
| 703 | |
| 704 | i915_gem_object_unpin(obj); |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 705 | } |
| 706 | |
| 707 | return ret; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 708 | } |
| 709 | |
| 710 | static int |
| 711 | i915_gem_execbuffer_relocate_slow(struct drm_device *dev, |
| 712 | struct drm_file *file, |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 713 | struct intel_ring_buffer *ring, |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 714 | struct list_head *objects, |
Chris Wilson | 67731b8 | 2010-12-08 10:38:14 +0000 | [diff] [blame] | 715 | struct eb_objects *eb, |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 716 | struct drm_i915_gem_exec_object2 *exec, |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 717 | int count) |
| 718 | { |
| 719 | struct drm_i915_gem_relocation_entry *reloc; |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 720 | struct drm_i915_gem_object *obj; |
Chris Wilson | dd6864a | 2011-01-12 23:49:13 +0000 | [diff] [blame] | 721 | int *reloc_offset; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 722 | int i, total, ret; |
| 723 | |
Chris Wilson | 67731b8 | 2010-12-08 10:38:14 +0000 | [diff] [blame] | 724 | /* We may process another execbuffer during the unlock... */ |
Chris Wilson | 36cf174 | 2011-01-10 12:09:12 +0000 | [diff] [blame] | 725 | while (!list_empty(objects)) { |
Chris Wilson | 67731b8 | 2010-12-08 10:38:14 +0000 | [diff] [blame] | 726 | obj = list_first_entry(objects, |
| 727 | struct drm_i915_gem_object, |
| 728 | exec_list); |
| 729 | list_del_init(&obj->exec_list); |
| 730 | drm_gem_object_unreference(&obj->base); |
| 731 | } |
| 732 | |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 733 | mutex_unlock(&dev->struct_mutex); |
| 734 | |
| 735 | total = 0; |
| 736 | for (i = 0; i < count; i++) |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 737 | total += exec[i].relocation_count; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 738 | |
Chris Wilson | dd6864a | 2011-01-12 23:49:13 +0000 | [diff] [blame] | 739 | reloc_offset = drm_malloc_ab(count, sizeof(*reloc_offset)); |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 740 | reloc = drm_malloc_ab(total, sizeof(*reloc)); |
Chris Wilson | dd6864a | 2011-01-12 23:49:13 +0000 | [diff] [blame] | 741 | if (reloc == NULL || reloc_offset == NULL) { |
| 742 | drm_free_large(reloc); |
| 743 | drm_free_large(reloc_offset); |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 744 | mutex_lock(&dev->struct_mutex); |
| 745 | return -ENOMEM; |
| 746 | } |
| 747 | |
| 748 | total = 0; |
| 749 | for (i = 0; i < count; i++) { |
| 750 | struct drm_i915_gem_relocation_entry __user *user_relocs; |
| 751 | |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 752 | user_relocs = (void __user *)(uintptr_t)exec[i].relocs_ptr; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 753 | |
| 754 | if (copy_from_user(reloc+total, user_relocs, |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 755 | exec[i].relocation_count * sizeof(*reloc))) { |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 756 | ret = -EFAULT; |
| 757 | mutex_lock(&dev->struct_mutex); |
| 758 | goto err; |
| 759 | } |
| 760 | |
Chris Wilson | dd6864a | 2011-01-12 23:49:13 +0000 | [diff] [blame] | 761 | reloc_offset[i] = total; |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 762 | total += exec[i].relocation_count; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 763 | } |
| 764 | |
| 765 | ret = i915_mutex_lock_interruptible(dev); |
| 766 | if (ret) { |
| 767 | mutex_lock(&dev->struct_mutex); |
| 768 | goto err; |
| 769 | } |
| 770 | |
Chris Wilson | 67731b8 | 2010-12-08 10:38:14 +0000 | [diff] [blame] | 771 | /* reacquire the objects */ |
Chris Wilson | 67731b8 | 2010-12-08 10:38:14 +0000 | [diff] [blame] | 772 | eb_reset(eb); |
| 773 | for (i = 0; i < count; i++) { |
Chris Wilson | 67731b8 | 2010-12-08 10:38:14 +0000 | [diff] [blame] | 774 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, |
| 775 | exec[i].handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 776 | if (&obj->base == NULL) { |
Daniel Vetter | ff24019 | 2012-01-31 21:08:14 +0100 | [diff] [blame] | 777 | DRM_DEBUG("Invalid object handle %d at index %d\n", |
Chris Wilson | 67731b8 | 2010-12-08 10:38:14 +0000 | [diff] [blame] | 778 | exec[i].handle, i); |
| 779 | ret = -ENOENT; |
| 780 | goto err; |
| 781 | } |
| 782 | |
| 783 | list_add_tail(&obj->exec_list, objects); |
| 784 | obj->exec_handle = exec[i].handle; |
Chris Wilson | 6fe4f14 | 2011-01-10 17:35:37 +0000 | [diff] [blame] | 785 | obj->exec_entry = &exec[i]; |
Chris Wilson | 67731b8 | 2010-12-08 10:38:14 +0000 | [diff] [blame] | 786 | eb_add_object(eb, obj); |
| 787 | } |
| 788 | |
Chris Wilson | 6fe4f14 | 2011-01-10 17:35:37 +0000 | [diff] [blame] | 789 | ret = i915_gem_execbuffer_reserve(ring, file, objects); |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 790 | if (ret) |
| 791 | goto err; |
| 792 | |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 793 | list_for_each_entry(obj, objects, exec_list) { |
Chris Wilson | dd6864a | 2011-01-12 23:49:13 +0000 | [diff] [blame] | 794 | int offset = obj->exec_entry - exec; |
Chris Wilson | 67731b8 | 2010-12-08 10:38:14 +0000 | [diff] [blame] | 795 | ret = i915_gem_execbuffer_relocate_object_slow(obj, eb, |
Chris Wilson | dd6864a | 2011-01-12 23:49:13 +0000 | [diff] [blame] | 796 | reloc + reloc_offset[offset]); |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 797 | if (ret) |
| 798 | goto err; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 799 | } |
| 800 | |
| 801 | /* Leave the user relocations as are, this is the painfully slow path, |
| 802 | * and we want to avoid the complication of dropping the lock whilst |
| 803 | * having buffers reserved in the aperture and so causing spurious |
| 804 | * ENOSPC for random operations. |
| 805 | */ |
| 806 | |
| 807 | err: |
| 808 | drm_free_large(reloc); |
Chris Wilson | dd6864a | 2011-01-12 23:49:13 +0000 | [diff] [blame] | 809 | drm_free_large(reloc_offset); |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 810 | return ret; |
| 811 | } |
| 812 | |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 813 | static int |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 814 | i915_gem_execbuffer_flush(struct drm_device *dev, |
| 815 | uint32_t invalidate_domains, |
| 816 | uint32_t flush_domains, |
| 817 | uint32_t flush_rings) |
| 818 | { |
| 819 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 820 | int i, ret; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 821 | |
| 822 | if (flush_domains & I915_GEM_DOMAIN_CPU) |
| 823 | intel_gtt_chipset_flush(); |
| 824 | |
Chris Wilson | 63256ec | 2011-01-04 18:42:07 +0000 | [diff] [blame] | 825 | if (flush_domains & I915_GEM_DOMAIN_GTT) |
| 826 | wmb(); |
| 827 | |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 828 | if ((flush_domains | invalidate_domains) & I915_GEM_GPU_DOMAINS) { |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 829 | for (i = 0; i < I915_NUM_RINGS; i++) |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 830 | if (flush_rings & (1 << i)) { |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 831 | ret = i915_gem_flush_ring(&dev_priv->ring[i], |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 832 | invalidate_domains, |
| 833 | flush_domains); |
| 834 | if (ret) |
| 835 | return ret; |
| 836 | } |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 837 | } |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 838 | |
| 839 | return 0; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 840 | } |
| 841 | |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 842 | static int |
Chris Wilson | c59a333 | 2011-03-06 13:51:29 +0000 | [diff] [blame] | 843 | i915_gem_execbuffer_wait_for_flips(struct intel_ring_buffer *ring, u32 flips) |
| 844 | { |
| 845 | u32 plane, flip_mask; |
| 846 | int ret; |
| 847 | |
| 848 | /* Check for any pending flips. As we only maintain a flip queue depth |
| 849 | * of 1, we can simply insert a WAIT for the next display flip prior |
| 850 | * to executing the batch and avoid stalling the CPU. |
| 851 | */ |
| 852 | |
| 853 | for (plane = 0; flips >> plane; plane++) { |
| 854 | if (((flips >> plane) & 1) == 0) |
| 855 | continue; |
| 856 | |
| 857 | if (plane) |
| 858 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; |
| 859 | else |
| 860 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; |
| 861 | |
| 862 | ret = intel_ring_begin(ring, 2); |
| 863 | if (ret) |
| 864 | return ret; |
| 865 | |
| 866 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
| 867 | intel_ring_emit(ring, MI_NOOP); |
| 868 | intel_ring_advance(ring); |
| 869 | } |
| 870 | |
| 871 | return 0; |
| 872 | } |
| 873 | |
| 874 | |
| 875 | static int |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 876 | i915_gem_execbuffer_move_to_gpu(struct intel_ring_buffer *ring, |
| 877 | struct list_head *objects) |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 878 | { |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 879 | struct drm_i915_gem_object *obj; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 880 | struct change_domains cd; |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 881 | int ret; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 882 | |
Chris Wilson | c59a333 | 2011-03-06 13:51:29 +0000 | [diff] [blame] | 883 | memset(&cd, 0, sizeof(cd)); |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 884 | list_for_each_entry(obj, objects, exec_list) |
| 885 | i915_gem_object_set_to_gpu_domain(obj, ring, &cd); |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 886 | |
| 887 | if (cd.invalidate_domains | cd.flush_domains) { |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 888 | ret = i915_gem_execbuffer_flush(ring->dev, |
| 889 | cd.invalidate_domains, |
| 890 | cd.flush_domains, |
| 891 | cd.flush_rings); |
| 892 | if (ret) |
| 893 | return ret; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 894 | } |
| 895 | |
Chris Wilson | c59a333 | 2011-03-06 13:51:29 +0000 | [diff] [blame] | 896 | if (cd.flips) { |
| 897 | ret = i915_gem_execbuffer_wait_for_flips(ring, cd.flips); |
| 898 | if (ret) |
| 899 | return ret; |
| 900 | } |
| 901 | |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 902 | list_for_each_entry(obj, objects, exec_list) { |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 903 | ret = i915_gem_object_sync(obj, ring); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 904 | if (ret) |
| 905 | return ret; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 906 | } |
| 907 | |
| 908 | return 0; |
| 909 | } |
| 910 | |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 911 | static bool |
| 912 | i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec) |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 913 | { |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 914 | return ((exec->batch_start_offset | exec->batch_len) & 0x7) == 0; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 915 | } |
| 916 | |
| 917 | static int |
| 918 | validate_exec_list(struct drm_i915_gem_exec_object2 *exec, |
| 919 | int count) |
| 920 | { |
| 921 | int i; |
| 922 | |
| 923 | for (i = 0; i < count; i++) { |
| 924 | char __user *ptr = (char __user *)(uintptr_t)exec[i].relocs_ptr; |
| 925 | int length; /* limited by fault_in_pages_readable() */ |
| 926 | |
| 927 | /* First check for malicious input causing overflow */ |
| 928 | if (exec[i].relocation_count > |
| 929 | INT_MAX / sizeof(struct drm_i915_gem_relocation_entry)) |
| 930 | return -EINVAL; |
| 931 | |
| 932 | length = exec[i].relocation_count * |
| 933 | sizeof(struct drm_i915_gem_relocation_entry); |
| 934 | if (!access_ok(VERIFY_READ, ptr, length)) |
| 935 | return -EFAULT; |
| 936 | |
| 937 | /* we may also need to update the presumed offsets */ |
| 938 | if (!access_ok(VERIFY_WRITE, ptr, length)) |
| 939 | return -EFAULT; |
| 940 | |
Daniel Vetter | f56f821 | 2012-03-25 19:47:41 +0200 | [diff] [blame] | 941 | if (fault_in_multipages_readable(ptr, length)) |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 942 | return -EFAULT; |
| 943 | } |
| 944 | |
| 945 | return 0; |
| 946 | } |
| 947 | |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 948 | static void |
| 949 | i915_gem_execbuffer_move_to_active(struct list_head *objects, |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 950 | struct intel_ring_buffer *ring, |
| 951 | u32 seqno) |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 952 | { |
| 953 | struct drm_i915_gem_object *obj; |
| 954 | |
| 955 | list_for_each_entry(obj, objects, exec_list) { |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 956 | u32 old_read = obj->base.read_domains; |
| 957 | u32 old_write = obj->base.write_domain; |
| 958 | |
| 959 | |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 960 | obj->base.read_domains = obj->base.pending_read_domains; |
| 961 | obj->base.write_domain = obj->base.pending_write_domain; |
| 962 | obj->fenced_gpu_access = obj->pending_fenced_gpu_access; |
| 963 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 964 | i915_gem_object_move_to_active(obj, ring, seqno); |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 965 | if (obj->base.write_domain) { |
| 966 | obj->dirty = 1; |
Chris Wilson | 87ca9c8 | 2010-12-02 09:42:56 +0000 | [diff] [blame] | 967 | obj->pending_gpu_write = true; |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 968 | list_move_tail(&obj->gpu_write_list, |
| 969 | &ring->gpu_write_list); |
| 970 | intel_mark_busy(ring->dev, obj); |
| 971 | } |
| 972 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 973 | trace_i915_gem_object_change_domain(obj, old_read, old_write); |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 974 | } |
| 975 | } |
| 976 | |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 977 | static void |
| 978 | i915_gem_execbuffer_retire_commands(struct drm_device *dev, |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 979 | struct drm_file *file, |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 980 | struct intel_ring_buffer *ring) |
| 981 | { |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 982 | struct drm_i915_gem_request *request; |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 983 | u32 invalidate; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 984 | |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 985 | /* |
| 986 | * Ensure that the commands in the batch buffer are |
| 987 | * finished before the interrupt fires. |
| 988 | * |
| 989 | * The sampler always gets flushed on i965 (sigh). |
| 990 | */ |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 991 | invalidate = I915_GEM_DOMAIN_COMMAND; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 992 | if (INTEL_INFO(dev)->gen >= 4) |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 993 | invalidate |= I915_GEM_DOMAIN_SAMPLER; |
| 994 | if (ring->flush(ring, invalidate, 0)) { |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 995 | i915_gem_next_request_seqno(ring); |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 996 | return; |
| 997 | } |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 998 | |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 999 | /* Add a breadcrumb for the completion of the batch buffer */ |
| 1000 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1001 | if (request == NULL || i915_add_request(ring, file, request)) { |
| 1002 | i915_gem_next_request_seqno(ring); |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 1003 | kfree(request); |
| 1004 | } |
| 1005 | } |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1006 | |
| 1007 | static int |
Eric Anholt | ae662d3 | 2012-01-03 09:23:29 -0800 | [diff] [blame] | 1008 | i915_reset_gen7_sol_offsets(struct drm_device *dev, |
| 1009 | struct intel_ring_buffer *ring) |
| 1010 | { |
| 1011 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1012 | int ret, i; |
| 1013 | |
| 1014 | if (!IS_GEN7(dev) || ring != &dev_priv->ring[RCS]) |
| 1015 | return 0; |
| 1016 | |
| 1017 | ret = intel_ring_begin(ring, 4 * 3); |
| 1018 | if (ret) |
| 1019 | return ret; |
| 1020 | |
| 1021 | for (i = 0; i < 4; i++) { |
| 1022 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
| 1023 | intel_ring_emit(ring, GEN7_SO_WRITE_OFFSET(i)); |
| 1024 | intel_ring_emit(ring, 0); |
| 1025 | } |
| 1026 | |
| 1027 | intel_ring_advance(ring); |
| 1028 | |
| 1029 | return 0; |
| 1030 | } |
| 1031 | |
| 1032 | static int |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1033 | i915_gem_do_execbuffer(struct drm_device *dev, void *data, |
| 1034 | struct drm_file *file, |
| 1035 | struct drm_i915_gem_execbuffer2 *args, |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 1036 | struct drm_i915_gem_exec_object2 *exec) |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1037 | { |
| 1038 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 1039 | struct list_head objects; |
Chris Wilson | 67731b8 | 2010-12-08 10:38:14 +0000 | [diff] [blame] | 1040 | struct eb_objects *eb; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1041 | struct drm_i915_gem_object *batch_obj; |
| 1042 | struct drm_clip_rect *cliprects = NULL; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1043 | struct intel_ring_buffer *ring; |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 1044 | u32 exec_start, exec_len; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1045 | u32 seqno; |
Ben Widawsky | 84f9f93 | 2011-12-12 19:21:58 -0800 | [diff] [blame] | 1046 | u32 mask; |
Chris Wilson | 72bfa19 | 2010-12-19 11:42:05 +0000 | [diff] [blame] | 1047 | int ret, mode, i; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1048 | |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 1049 | if (!i915_gem_check_execbuffer(args)) { |
Daniel Vetter | ff24019 | 2012-01-31 21:08:14 +0100 | [diff] [blame] | 1050 | DRM_DEBUG("execbuf with invalid offset/length\n"); |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 1051 | return -EINVAL; |
| 1052 | } |
| 1053 | |
| 1054 | ret = validate_exec_list(exec, args->buffer_count); |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1055 | if (ret) |
| 1056 | return ret; |
| 1057 | |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1058 | switch (args->flags & I915_EXEC_RING_MASK) { |
| 1059 | case I915_EXEC_DEFAULT: |
| 1060 | case I915_EXEC_RENDER: |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1061 | ring = &dev_priv->ring[RCS]; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1062 | break; |
| 1063 | case I915_EXEC_BSD: |
| 1064 | if (!HAS_BSD(dev)) { |
Daniel Vetter | ff24019 | 2012-01-31 21:08:14 +0100 | [diff] [blame] | 1065 | DRM_DEBUG("execbuf with invalid ring (BSD)\n"); |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1066 | return -EINVAL; |
| 1067 | } |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1068 | ring = &dev_priv->ring[VCS]; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1069 | break; |
| 1070 | case I915_EXEC_BLT: |
| 1071 | if (!HAS_BLT(dev)) { |
Daniel Vetter | ff24019 | 2012-01-31 21:08:14 +0100 | [diff] [blame] | 1072 | DRM_DEBUG("execbuf with invalid ring (BLT)\n"); |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1073 | return -EINVAL; |
| 1074 | } |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1075 | ring = &dev_priv->ring[BCS]; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1076 | break; |
| 1077 | default: |
Daniel Vetter | ff24019 | 2012-01-31 21:08:14 +0100 | [diff] [blame] | 1078 | DRM_DEBUG("execbuf with unknown ring: %d\n", |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1079 | (int)(args->flags & I915_EXEC_RING_MASK)); |
| 1080 | return -EINVAL; |
| 1081 | } |
| 1082 | |
Chris Wilson | 72bfa19 | 2010-12-19 11:42:05 +0000 | [diff] [blame] | 1083 | mode = args->flags & I915_EXEC_CONSTANTS_MASK; |
Ben Widawsky | 84f9f93 | 2011-12-12 19:21:58 -0800 | [diff] [blame] | 1084 | mask = I915_EXEC_CONSTANTS_MASK; |
Chris Wilson | 72bfa19 | 2010-12-19 11:42:05 +0000 | [diff] [blame] | 1085 | switch (mode) { |
| 1086 | case I915_EXEC_CONSTANTS_REL_GENERAL: |
| 1087 | case I915_EXEC_CONSTANTS_ABSOLUTE: |
| 1088 | case I915_EXEC_CONSTANTS_REL_SURFACE: |
| 1089 | if (ring == &dev_priv->ring[RCS] && |
| 1090 | mode != dev_priv->relative_constants_mode) { |
| 1091 | if (INTEL_INFO(dev)->gen < 4) |
| 1092 | return -EINVAL; |
| 1093 | |
| 1094 | if (INTEL_INFO(dev)->gen > 5 && |
| 1095 | mode == I915_EXEC_CONSTANTS_REL_SURFACE) |
| 1096 | return -EINVAL; |
Ben Widawsky | 84f9f93 | 2011-12-12 19:21:58 -0800 | [diff] [blame] | 1097 | |
| 1098 | /* The HW changed the meaning on this bit on gen6 */ |
| 1099 | if (INTEL_INFO(dev)->gen >= 6) |
| 1100 | mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE; |
Chris Wilson | 72bfa19 | 2010-12-19 11:42:05 +0000 | [diff] [blame] | 1101 | } |
| 1102 | break; |
| 1103 | default: |
Daniel Vetter | ff24019 | 2012-01-31 21:08:14 +0100 | [diff] [blame] | 1104 | DRM_DEBUG("execbuf with unknown constants: %d\n", mode); |
Chris Wilson | 72bfa19 | 2010-12-19 11:42:05 +0000 | [diff] [blame] | 1105 | return -EINVAL; |
| 1106 | } |
| 1107 | |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1108 | if (args->buffer_count < 1) { |
Daniel Vetter | ff24019 | 2012-01-31 21:08:14 +0100 | [diff] [blame] | 1109 | DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count); |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1110 | return -EINVAL; |
| 1111 | } |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1112 | |
| 1113 | if (args->num_cliprects != 0) { |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1114 | if (ring != &dev_priv->ring[RCS]) { |
Daniel Vetter | ff24019 | 2012-01-31 21:08:14 +0100 | [diff] [blame] | 1115 | DRM_DEBUG("clip rectangles are only valid with the render ring\n"); |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 1116 | return -EINVAL; |
| 1117 | } |
| 1118 | |
Daniel Vetter | 6ebebc9 | 2012-04-26 23:28:11 +0200 | [diff] [blame] | 1119 | if (INTEL_INFO(dev)->gen >= 5) { |
| 1120 | DRM_DEBUG("clip rectangles are only valid on pre-gen5\n"); |
| 1121 | return -EINVAL; |
| 1122 | } |
| 1123 | |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 1124 | cliprects = kmalloc(args->num_cliprects * sizeof(*cliprects), |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1125 | GFP_KERNEL); |
| 1126 | if (cliprects == NULL) { |
| 1127 | ret = -ENOMEM; |
| 1128 | goto pre_mutex_err; |
| 1129 | } |
| 1130 | |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 1131 | if (copy_from_user(cliprects, |
| 1132 | (struct drm_clip_rect __user *)(uintptr_t) |
| 1133 | args->cliprects_ptr, |
| 1134 | sizeof(*cliprects)*args->num_cliprects)) { |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1135 | ret = -EFAULT; |
| 1136 | goto pre_mutex_err; |
| 1137 | } |
| 1138 | } |
| 1139 | |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1140 | ret = i915_mutex_lock_interruptible(dev); |
| 1141 | if (ret) |
| 1142 | goto pre_mutex_err; |
| 1143 | |
| 1144 | if (dev_priv->mm.suspended) { |
| 1145 | mutex_unlock(&dev->struct_mutex); |
| 1146 | ret = -EBUSY; |
| 1147 | goto pre_mutex_err; |
| 1148 | } |
| 1149 | |
Chris Wilson | 67731b8 | 2010-12-08 10:38:14 +0000 | [diff] [blame] | 1150 | eb = eb_create(args->buffer_count); |
| 1151 | if (eb == NULL) { |
| 1152 | mutex_unlock(&dev->struct_mutex); |
| 1153 | ret = -ENOMEM; |
| 1154 | goto pre_mutex_err; |
| 1155 | } |
| 1156 | |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1157 | /* Look up object handles */ |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 1158 | INIT_LIST_HEAD(&objects); |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1159 | for (i = 0; i < args->buffer_count; i++) { |
| 1160 | struct drm_i915_gem_object *obj; |
| 1161 | |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 1162 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, |
| 1163 | exec[i].handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 1164 | if (&obj->base == NULL) { |
Daniel Vetter | ff24019 | 2012-01-31 21:08:14 +0100 | [diff] [blame] | 1165 | DRM_DEBUG("Invalid object handle %d at index %d\n", |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 1166 | exec[i].handle, i); |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1167 | /* prevent error path from reading uninitialized data */ |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1168 | ret = -ENOENT; |
| 1169 | goto err; |
| 1170 | } |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1171 | |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 1172 | if (!list_empty(&obj->exec_list)) { |
Daniel Vetter | ff24019 | 2012-01-31 21:08:14 +0100 | [diff] [blame] | 1173 | DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n", |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 1174 | obj, exec[i].handle, i); |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1175 | ret = -EINVAL; |
| 1176 | goto err; |
| 1177 | } |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 1178 | |
| 1179 | list_add_tail(&obj->exec_list, &objects); |
Chris Wilson | 67731b8 | 2010-12-08 10:38:14 +0000 | [diff] [blame] | 1180 | obj->exec_handle = exec[i].handle; |
Chris Wilson | 6fe4f14 | 2011-01-10 17:35:37 +0000 | [diff] [blame] | 1181 | obj->exec_entry = &exec[i]; |
Chris Wilson | 67731b8 | 2010-12-08 10:38:14 +0000 | [diff] [blame] | 1182 | eb_add_object(eb, obj); |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1183 | } |
| 1184 | |
Chris Wilson | 6fe4f14 | 2011-01-10 17:35:37 +0000 | [diff] [blame] | 1185 | /* take note of the batch buffer before we might reorder the lists */ |
| 1186 | batch_obj = list_entry(objects.prev, |
| 1187 | struct drm_i915_gem_object, |
| 1188 | exec_list); |
| 1189 | |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1190 | /* Move the objects en-masse into the GTT, evicting if necessary. */ |
Chris Wilson | 6fe4f14 | 2011-01-10 17:35:37 +0000 | [diff] [blame] | 1191 | ret = i915_gem_execbuffer_reserve(ring, file, &objects); |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1192 | if (ret) |
| 1193 | goto err; |
| 1194 | |
| 1195 | /* The objects are in their final locations, apply the relocations. */ |
Chris Wilson | 6fe4f14 | 2011-01-10 17:35:37 +0000 | [diff] [blame] | 1196 | ret = i915_gem_execbuffer_relocate(dev, eb, &objects); |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1197 | if (ret) { |
| 1198 | if (ret == -EFAULT) { |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 1199 | ret = i915_gem_execbuffer_relocate_slow(dev, file, ring, |
Chris Wilson | 67731b8 | 2010-12-08 10:38:14 +0000 | [diff] [blame] | 1200 | &objects, eb, |
| 1201 | exec, |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1202 | args->buffer_count); |
| 1203 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
| 1204 | } |
| 1205 | if (ret) |
| 1206 | goto err; |
| 1207 | } |
| 1208 | |
| 1209 | /* Set the pending read domains for the batch buffer to COMMAND */ |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1210 | if (batch_obj->base.pending_write_domain) { |
Daniel Vetter | ff24019 | 2012-01-31 21:08:14 +0100 | [diff] [blame] | 1211 | DRM_DEBUG("Attempting to use self-modifying batch buffer\n"); |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1212 | ret = -EINVAL; |
| 1213 | goto err; |
| 1214 | } |
| 1215 | batch_obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND; |
| 1216 | |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 1217 | ret = i915_gem_execbuffer_move_to_gpu(ring, &objects); |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1218 | if (ret) |
| 1219 | goto err; |
| 1220 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1221 | seqno = i915_gem_next_request_seqno(ring); |
Chris Wilson | 076e2c0 | 2011-01-21 10:07:18 +0000 | [diff] [blame] | 1222 | for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++) { |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1223 | if (seqno < ring->sync_seqno[i]) { |
| 1224 | /* The GPU can not handle its semaphore value wrapping, |
| 1225 | * so every billion or so execbuffers, we need to stall |
| 1226 | * the GPU in order to reset the counters. |
| 1227 | */ |
Ben Widawsky | b2da9fe | 2012-04-26 16:02:58 -0700 | [diff] [blame] | 1228 | ret = i915_gpu_idle(dev); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1229 | if (ret) |
| 1230 | goto err; |
Ben Widawsky | b2da9fe | 2012-04-26 16:02:58 -0700 | [diff] [blame] | 1231 | i915_gem_retire_requests(dev); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1232 | |
| 1233 | BUG_ON(ring->sync_seqno[i]); |
| 1234 | } |
| 1235 | } |
| 1236 | |
Ben Widawsky | e2971bd | 2011-12-12 19:21:57 -0800 | [diff] [blame] | 1237 | if (ring == &dev_priv->ring[RCS] && |
| 1238 | mode != dev_priv->relative_constants_mode) { |
| 1239 | ret = intel_ring_begin(ring, 4); |
| 1240 | if (ret) |
| 1241 | goto err; |
| 1242 | |
| 1243 | intel_ring_emit(ring, MI_NOOP); |
| 1244 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
| 1245 | intel_ring_emit(ring, INSTPM); |
Ben Widawsky | 84f9f93 | 2011-12-12 19:21:58 -0800 | [diff] [blame] | 1246 | intel_ring_emit(ring, mask << 16 | mode); |
Ben Widawsky | e2971bd | 2011-12-12 19:21:57 -0800 | [diff] [blame] | 1247 | intel_ring_advance(ring); |
| 1248 | |
| 1249 | dev_priv->relative_constants_mode = mode; |
| 1250 | } |
| 1251 | |
Eric Anholt | ae662d3 | 2012-01-03 09:23:29 -0800 | [diff] [blame] | 1252 | if (args->flags & I915_EXEC_GEN7_SOL_RESET) { |
| 1253 | ret = i915_reset_gen7_sol_offsets(dev, ring); |
| 1254 | if (ret) |
| 1255 | goto err; |
| 1256 | } |
| 1257 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1258 | trace_i915_gem_ring_dispatch(ring, seqno); |
| 1259 | |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 1260 | exec_start = batch_obj->gtt_offset + args->batch_start_offset; |
| 1261 | exec_len = args->batch_len; |
| 1262 | if (cliprects) { |
| 1263 | for (i = 0; i < args->num_cliprects; i++) { |
| 1264 | ret = i915_emit_box(dev, &cliprects[i], |
| 1265 | args->DR1, args->DR4); |
| 1266 | if (ret) |
| 1267 | goto err; |
| 1268 | |
| 1269 | ret = ring->dispatch_execbuffer(ring, |
| 1270 | exec_start, exec_len); |
| 1271 | if (ret) |
| 1272 | goto err; |
| 1273 | } |
| 1274 | } else { |
| 1275 | ret = ring->dispatch_execbuffer(ring, exec_start, exec_len); |
| 1276 | if (ret) |
| 1277 | goto err; |
| 1278 | } |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1279 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1280 | i915_gem_execbuffer_move_to_active(&objects, ring, seqno); |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 1281 | i915_gem_execbuffer_retire_commands(dev, file, ring); |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1282 | |
| 1283 | err: |
Chris Wilson | 67731b8 | 2010-12-08 10:38:14 +0000 | [diff] [blame] | 1284 | eb_destroy(eb); |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 1285 | while (!list_empty(&objects)) { |
| 1286 | struct drm_i915_gem_object *obj; |
| 1287 | |
| 1288 | obj = list_first_entry(&objects, |
| 1289 | struct drm_i915_gem_object, |
| 1290 | exec_list); |
| 1291 | list_del_init(&obj->exec_list); |
| 1292 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1293 | } |
| 1294 | |
| 1295 | mutex_unlock(&dev->struct_mutex); |
| 1296 | |
| 1297 | pre_mutex_err: |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1298 | kfree(cliprects); |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1299 | return ret; |
| 1300 | } |
| 1301 | |
| 1302 | /* |
| 1303 | * Legacy execbuffer just creates an exec2 list from the original exec object |
| 1304 | * list array and passes it to the real function. |
| 1305 | */ |
| 1306 | int |
| 1307 | i915_gem_execbuffer(struct drm_device *dev, void *data, |
| 1308 | struct drm_file *file) |
| 1309 | { |
| 1310 | struct drm_i915_gem_execbuffer *args = data; |
| 1311 | struct drm_i915_gem_execbuffer2 exec2; |
| 1312 | struct drm_i915_gem_exec_object *exec_list = NULL; |
| 1313 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; |
| 1314 | int ret, i; |
| 1315 | |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1316 | if (args->buffer_count < 1) { |
Daniel Vetter | ff24019 | 2012-01-31 21:08:14 +0100 | [diff] [blame] | 1317 | DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count); |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1318 | return -EINVAL; |
| 1319 | } |
| 1320 | |
| 1321 | /* Copy in the exec list from userland */ |
| 1322 | exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count); |
| 1323 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); |
| 1324 | if (exec_list == NULL || exec2_list == NULL) { |
Daniel Vetter | ff24019 | 2012-01-31 21:08:14 +0100 | [diff] [blame] | 1325 | DRM_DEBUG("Failed to allocate exec list for %d buffers\n", |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1326 | args->buffer_count); |
| 1327 | drm_free_large(exec_list); |
| 1328 | drm_free_large(exec2_list); |
| 1329 | return -ENOMEM; |
| 1330 | } |
| 1331 | ret = copy_from_user(exec_list, |
| 1332 | (struct drm_i915_relocation_entry __user *) |
| 1333 | (uintptr_t) args->buffers_ptr, |
| 1334 | sizeof(*exec_list) * args->buffer_count); |
| 1335 | if (ret != 0) { |
Daniel Vetter | ff24019 | 2012-01-31 21:08:14 +0100 | [diff] [blame] | 1336 | DRM_DEBUG("copy %d exec entries failed %d\n", |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1337 | args->buffer_count, ret); |
| 1338 | drm_free_large(exec_list); |
| 1339 | drm_free_large(exec2_list); |
| 1340 | return -EFAULT; |
| 1341 | } |
| 1342 | |
| 1343 | for (i = 0; i < args->buffer_count; i++) { |
| 1344 | exec2_list[i].handle = exec_list[i].handle; |
| 1345 | exec2_list[i].relocation_count = exec_list[i].relocation_count; |
| 1346 | exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr; |
| 1347 | exec2_list[i].alignment = exec_list[i].alignment; |
| 1348 | exec2_list[i].offset = exec_list[i].offset; |
| 1349 | if (INTEL_INFO(dev)->gen < 4) |
| 1350 | exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE; |
| 1351 | else |
| 1352 | exec2_list[i].flags = 0; |
| 1353 | } |
| 1354 | |
| 1355 | exec2.buffers_ptr = args->buffers_ptr; |
| 1356 | exec2.buffer_count = args->buffer_count; |
| 1357 | exec2.batch_start_offset = args->batch_start_offset; |
| 1358 | exec2.batch_len = args->batch_len; |
| 1359 | exec2.DR1 = args->DR1; |
| 1360 | exec2.DR4 = args->DR4; |
| 1361 | exec2.num_cliprects = args->num_cliprects; |
| 1362 | exec2.cliprects_ptr = args->cliprects_ptr; |
| 1363 | exec2.flags = I915_EXEC_RENDER; |
| 1364 | |
| 1365 | ret = i915_gem_do_execbuffer(dev, data, file, &exec2, exec2_list); |
| 1366 | if (!ret) { |
| 1367 | /* Copy the new buffer offsets back to the user's exec list. */ |
| 1368 | for (i = 0; i < args->buffer_count; i++) |
| 1369 | exec_list[i].offset = exec2_list[i].offset; |
| 1370 | /* ... and back out to userspace */ |
| 1371 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) |
| 1372 | (uintptr_t) args->buffers_ptr, |
| 1373 | exec_list, |
| 1374 | sizeof(*exec_list) * args->buffer_count); |
| 1375 | if (ret) { |
| 1376 | ret = -EFAULT; |
Daniel Vetter | ff24019 | 2012-01-31 21:08:14 +0100 | [diff] [blame] | 1377 | DRM_DEBUG("failed to copy %d exec entries " |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1378 | "back to user (%d)\n", |
| 1379 | args->buffer_count, ret); |
| 1380 | } |
| 1381 | } |
| 1382 | |
| 1383 | drm_free_large(exec_list); |
| 1384 | drm_free_large(exec2_list); |
| 1385 | return ret; |
| 1386 | } |
| 1387 | |
| 1388 | int |
| 1389 | i915_gem_execbuffer2(struct drm_device *dev, void *data, |
| 1390 | struct drm_file *file) |
| 1391 | { |
| 1392 | struct drm_i915_gem_execbuffer2 *args = data; |
| 1393 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; |
| 1394 | int ret; |
| 1395 | |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1396 | if (args->buffer_count < 1) { |
Daniel Vetter | ff24019 | 2012-01-31 21:08:14 +0100 | [diff] [blame] | 1397 | DRM_DEBUG("execbuf2 with %d buffers\n", args->buffer_count); |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1398 | return -EINVAL; |
| 1399 | } |
| 1400 | |
Chris Wilson | 8408c28 | 2011-02-21 12:54:48 +0000 | [diff] [blame] | 1401 | exec2_list = kmalloc(sizeof(*exec2_list)*args->buffer_count, |
| 1402 | GFP_KERNEL | __GFP_NOWARN | __GFP_NORETRY); |
| 1403 | if (exec2_list == NULL) |
| 1404 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), |
| 1405 | args->buffer_count); |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1406 | if (exec2_list == NULL) { |
Daniel Vetter | ff24019 | 2012-01-31 21:08:14 +0100 | [diff] [blame] | 1407 | DRM_DEBUG("Failed to allocate exec list for %d buffers\n", |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1408 | args->buffer_count); |
| 1409 | return -ENOMEM; |
| 1410 | } |
| 1411 | ret = copy_from_user(exec2_list, |
| 1412 | (struct drm_i915_relocation_entry __user *) |
| 1413 | (uintptr_t) args->buffers_ptr, |
| 1414 | sizeof(*exec2_list) * args->buffer_count); |
| 1415 | if (ret != 0) { |
Daniel Vetter | ff24019 | 2012-01-31 21:08:14 +0100 | [diff] [blame] | 1416 | DRM_DEBUG("copy %d exec entries failed %d\n", |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1417 | args->buffer_count, ret); |
| 1418 | drm_free_large(exec2_list); |
| 1419 | return -EFAULT; |
| 1420 | } |
| 1421 | |
| 1422 | ret = i915_gem_do_execbuffer(dev, data, file, args, exec2_list); |
| 1423 | if (!ret) { |
| 1424 | /* Copy the new buffer offsets back to the user's exec list. */ |
| 1425 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) |
| 1426 | (uintptr_t) args->buffers_ptr, |
| 1427 | exec2_list, |
| 1428 | sizeof(*exec2_list) * args->buffer_count); |
| 1429 | if (ret) { |
| 1430 | ret = -EFAULT; |
Daniel Vetter | ff24019 | 2012-01-31 21:08:14 +0100 | [diff] [blame] | 1431 | DRM_DEBUG("failed to copy %d exec entries " |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1432 | "back to user (%d)\n", |
| 1433 | args->buffer_count, ret); |
| 1434 | } |
| 1435 | } |
| 1436 | |
| 1437 | drm_free_large(exec2_list); |
| 1438 | return ret; |
| 1439 | } |