Manuel Lauss | 9bdcf33 | 2009-10-04 14:55:24 +0200 | [diff] [blame] | 1 | /* |
| 2 | * bcsr.h -- Db1xxx/Pb1xxx Devboard CPLD registers ("BCSR") abstraction. |
| 3 | * |
| 4 | * All Alchemy development boards (except, of course, the weird PB1000) |
| 5 | * have a few registers in a CPLD with standardised layout; they mostly |
| 6 | * only differ in base address. |
| 7 | * All registers are 16bits wide with 32bit spacing. |
| 8 | */ |
| 9 | |
Manuel Lauss | 95a4379 | 2009-10-04 14:55:25 +0200 | [diff] [blame] | 10 | #include <linux/interrupt.h> |
Thomas Gleixner | e0288a0a | 2015-07-13 20:46:04 +0000 | [diff] [blame] | 11 | #include <linux/irqchip/chained_irq.h> |
Manuel Lauss | 9bdcf33 | 2009-10-04 14:55:24 +0200 | [diff] [blame] | 12 | #include <linux/module.h> |
| 13 | #include <linux/spinlock.h> |
David Howells | ca4d3e67 | 2010-10-07 14:08:54 +0100 | [diff] [blame] | 14 | #include <linux/irq.h> |
Manuel Lauss | 9bdcf33 | 2009-10-04 14:55:24 +0200 | [diff] [blame] | 15 | #include <asm/addrspace.h> |
| 16 | #include <asm/io.h> |
| 17 | #include <asm/mach-db1x00/bcsr.h> |
| 18 | |
| 19 | static struct bcsr_reg { |
| 20 | void __iomem *raddr; |
| 21 | spinlock_t lock; |
| 22 | } bcsr_regs[BCSR_CNT]; |
| 23 | |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 24 | static void __iomem *bcsr_virt; /* KSEG1 addr of BCSR base */ |
Manuel Lauss | 95a4379 | 2009-10-04 14:55:25 +0200 | [diff] [blame] | 25 | static int bcsr_csc_base; /* linux-irq of first cascaded irq */ |
| 26 | |
Manuel Lauss | 9bdcf33 | 2009-10-04 14:55:24 +0200 | [diff] [blame] | 27 | void __init bcsr_init(unsigned long bcsr1_phys, unsigned long bcsr2_phys) |
| 28 | { |
| 29 | int i; |
| 30 | |
| 31 | bcsr1_phys = KSEG1ADDR(CPHYSADDR(bcsr1_phys)); |
| 32 | bcsr2_phys = KSEG1ADDR(CPHYSADDR(bcsr2_phys)); |
| 33 | |
Manuel Lauss | 95a4379 | 2009-10-04 14:55:25 +0200 | [diff] [blame] | 34 | bcsr_virt = (void __iomem *)bcsr1_phys; |
| 35 | |
Manuel Lauss | 9bdcf33 | 2009-10-04 14:55:24 +0200 | [diff] [blame] | 36 | for (i = 0; i < BCSR_CNT; i++) { |
| 37 | if (i >= BCSR_HEXLEDS) |
| 38 | bcsr_regs[i].raddr = (void __iomem *)bcsr2_phys + |
| 39 | (0x04 * (i - BCSR_HEXLEDS)); |
| 40 | else |
| 41 | bcsr_regs[i].raddr = (void __iomem *)bcsr1_phys + |
| 42 | (0x04 * i); |
| 43 | |
| 44 | spin_lock_init(&bcsr_regs[i].lock); |
| 45 | } |
| 46 | } |
| 47 | |
| 48 | unsigned short bcsr_read(enum bcsr_id reg) |
| 49 | { |
| 50 | unsigned short r; |
| 51 | unsigned long flags; |
| 52 | |
| 53 | spin_lock_irqsave(&bcsr_regs[reg].lock, flags); |
| 54 | r = __raw_readw(bcsr_regs[reg].raddr); |
| 55 | spin_unlock_irqrestore(&bcsr_regs[reg].lock, flags); |
| 56 | return r; |
| 57 | } |
| 58 | EXPORT_SYMBOL_GPL(bcsr_read); |
| 59 | |
| 60 | void bcsr_write(enum bcsr_id reg, unsigned short val) |
| 61 | { |
| 62 | unsigned long flags; |
| 63 | |
| 64 | spin_lock_irqsave(&bcsr_regs[reg].lock, flags); |
| 65 | __raw_writew(val, bcsr_regs[reg].raddr); |
| 66 | wmb(); |
| 67 | spin_unlock_irqrestore(&bcsr_regs[reg].lock, flags); |
| 68 | } |
| 69 | EXPORT_SYMBOL_GPL(bcsr_write); |
| 70 | |
| 71 | void bcsr_mod(enum bcsr_id reg, unsigned short clr, unsigned short set) |
| 72 | { |
| 73 | unsigned short r; |
| 74 | unsigned long flags; |
| 75 | |
| 76 | spin_lock_irqsave(&bcsr_regs[reg].lock, flags); |
| 77 | r = __raw_readw(bcsr_regs[reg].raddr); |
| 78 | r &= ~clr; |
| 79 | r |= set; |
| 80 | __raw_writew(r, bcsr_regs[reg].raddr); |
| 81 | wmb(); |
| 82 | spin_unlock_irqrestore(&bcsr_regs[reg].lock, flags); |
| 83 | } |
| 84 | EXPORT_SYMBOL_GPL(bcsr_mod); |
Manuel Lauss | 95a4379 | 2009-10-04 14:55:25 +0200 | [diff] [blame] | 85 | |
| 86 | /* |
| 87 | * DB1200/PB1200 CPLD IRQ muxer |
| 88 | */ |
Thomas Gleixner | bd0b9ac | 2015-09-14 10:42:37 +0200 | [diff] [blame] | 89 | static void bcsr_csc_handler(struct irq_desc *d) |
Manuel Lauss | 95a4379 | 2009-10-04 14:55:25 +0200 | [diff] [blame] | 90 | { |
| 91 | unsigned short bisr = __raw_readw(bcsr_virt + BCSR_REG_INTSTAT); |
Thomas Gleixner | e0288a0a | 2015-07-13 20:46:04 +0000 | [diff] [blame] | 92 | struct irq_chip *chip = irq_desc_get_chip(d); |
Manuel Lauss | 95a4379 | 2009-10-04 14:55:25 +0200 | [diff] [blame] | 93 | |
Thomas Gleixner | e0288a0a | 2015-07-13 20:46:04 +0000 | [diff] [blame] | 94 | chained_irq_enter(chip, d); |
Manuel Lauss | 6c2be5c | 2012-01-21 18:13:15 +0100 | [diff] [blame] | 95 | generic_handle_irq(bcsr_csc_base + __ffs(bisr)); |
Thomas Gleixner | e0288a0a | 2015-07-13 20:46:04 +0000 | [diff] [blame] | 96 | chained_irq_exit(chip, d); |
Manuel Lauss | 95a4379 | 2009-10-04 14:55:25 +0200 | [diff] [blame] | 97 | } |
| 98 | |
Thomas Gleixner | d24c1a2 | 2011-03-23 21:08:44 +0000 | [diff] [blame] | 99 | static void bcsr_irq_mask(struct irq_data *d) |
Manuel Lauss | 95a4379 | 2009-10-04 14:55:25 +0200 | [diff] [blame] | 100 | { |
Thomas Gleixner | d24c1a2 | 2011-03-23 21:08:44 +0000 | [diff] [blame] | 101 | unsigned short v = 1 << (d->irq - bcsr_csc_base); |
Manuel Lauss | 95a4379 | 2009-10-04 14:55:25 +0200 | [diff] [blame] | 102 | __raw_writew(v, bcsr_virt + BCSR_REG_MASKCLR); |
| 103 | wmb(); |
| 104 | } |
| 105 | |
Thomas Gleixner | d24c1a2 | 2011-03-23 21:08:44 +0000 | [diff] [blame] | 106 | static void bcsr_irq_maskack(struct irq_data *d) |
Manuel Lauss | 95a4379 | 2009-10-04 14:55:25 +0200 | [diff] [blame] | 107 | { |
Thomas Gleixner | d24c1a2 | 2011-03-23 21:08:44 +0000 | [diff] [blame] | 108 | unsigned short v = 1 << (d->irq - bcsr_csc_base); |
Manuel Lauss | 95a4379 | 2009-10-04 14:55:25 +0200 | [diff] [blame] | 109 | __raw_writew(v, bcsr_virt + BCSR_REG_MASKCLR); |
| 110 | __raw_writew(v, bcsr_virt + BCSR_REG_INTSTAT); /* ack */ |
| 111 | wmb(); |
| 112 | } |
| 113 | |
Thomas Gleixner | d24c1a2 | 2011-03-23 21:08:44 +0000 | [diff] [blame] | 114 | static void bcsr_irq_unmask(struct irq_data *d) |
Manuel Lauss | 95a4379 | 2009-10-04 14:55:25 +0200 | [diff] [blame] | 115 | { |
Thomas Gleixner | d24c1a2 | 2011-03-23 21:08:44 +0000 | [diff] [blame] | 116 | unsigned short v = 1 << (d->irq - bcsr_csc_base); |
Manuel Lauss | 95a4379 | 2009-10-04 14:55:25 +0200 | [diff] [blame] | 117 | __raw_writew(v, bcsr_virt + BCSR_REG_MASKSET); |
| 118 | wmb(); |
| 119 | } |
| 120 | |
| 121 | static struct irq_chip bcsr_irq_type = { |
| 122 | .name = "CPLD", |
Thomas Gleixner | d24c1a2 | 2011-03-23 21:08:44 +0000 | [diff] [blame] | 123 | .irq_mask = bcsr_irq_mask, |
| 124 | .irq_mask_ack = bcsr_irq_maskack, |
| 125 | .irq_unmask = bcsr_irq_unmask, |
Manuel Lauss | 95a4379 | 2009-10-04 14:55:25 +0200 | [diff] [blame] | 126 | }; |
| 127 | |
| 128 | void __init bcsr_init_irq(int csc_start, int csc_end, int hook_irq) |
| 129 | { |
| 130 | unsigned int irq; |
| 131 | |
Manuel Lauss | fb469f0 | 2011-11-01 20:03:29 +0100 | [diff] [blame] | 132 | /* mask & enable & ack all */ |
Manuel Lauss | 95a4379 | 2009-10-04 14:55:25 +0200 | [diff] [blame] | 133 | __raw_writew(0xffff, bcsr_virt + BCSR_REG_MASKCLR); |
Manuel Lauss | fb469f0 | 2011-11-01 20:03:29 +0100 | [diff] [blame] | 134 | __raw_writew(0xffff, bcsr_virt + BCSR_REG_INTSET); |
Manuel Lauss | 95a4379 | 2009-10-04 14:55:25 +0200 | [diff] [blame] | 135 | __raw_writew(0xffff, bcsr_virt + BCSR_REG_INTSTAT); |
| 136 | wmb(); |
| 137 | |
| 138 | bcsr_csc_base = csc_start; |
| 139 | |
| 140 | for (irq = csc_start; irq <= csc_end; irq++) |
Thomas Gleixner | e4ec798 | 2011-03-27 15:19:28 +0200 | [diff] [blame] | 141 | irq_set_chip_and_handler_name(irq, &bcsr_irq_type, |
| 142 | handle_level_irq, "level"); |
Manuel Lauss | 95a4379 | 2009-10-04 14:55:25 +0200 | [diff] [blame] | 143 | |
Thomas Gleixner | e4ec798 | 2011-03-27 15:19:28 +0200 | [diff] [blame] | 144 | irq_set_chained_handler(hook_irq, bcsr_csc_handler); |
Manuel Lauss | 95a4379 | 2009-10-04 14:55:25 +0200 | [diff] [blame] | 145 | } |