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Laurent Pinchartb98d32f2011-08-12 19:09:34 +02001/*
2 * omap3isp.h
3 *
4 * TI OMAP3 ISP - Platform data
5 *
6 * Copyright (C) 2011 Nokia Corporation
7 *
8 * Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
9 * Sakari Ailus <sakari.ailus@iki.fi>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 *
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
23 * 02110-1301 USA
24 */
25
26#ifndef __MEDIA_OMAP3ISP_H__
27#define __MEDIA_OMAP3ISP_H__
28
29struct i2c_board_info;
30struct isp_device;
31
32enum isp_interface_type {
33 ISP_INTERFACE_PARALLEL,
34 ISP_INTERFACE_CSI2A_PHY2,
35 ISP_INTERFACE_CCP2B_PHY1,
36 ISP_INTERFACE_CCP2B_PHY2,
37 ISP_INTERFACE_CSI2C_PHY1,
38};
39
40enum {
Laurent Pinchartb98d32f2011-08-12 19:09:34 +020041 ISP_LANE_SHIFT_0 = 0,
42 ISP_LANE_SHIFT_2 = 1,
43 ISP_LANE_SHIFT_4 = 2,
44 ISP_LANE_SHIFT_6 = 3,
45};
46
47/**
48 * struct isp_parallel_platform_data - Parallel interface platform data
49 * @data_lane_shift: Data lane shifter
50 * ISP_LANE_SHIFT_0 - CAMEXT[13:0] -> CAM[13:0]
51 * ISP_LANE_SHIFT_2 - CAMEXT[13:2] -> CAM[11:0]
52 * ISP_LANE_SHIFT_4 - CAMEXT[13:4] -> CAM[9:0]
53 * ISP_LANE_SHIFT_6 - CAMEXT[13:6] -> CAM[7:0]
54 * @clk_pol: Pixel clock polarity
Laurent Pinchartc1026c582011-11-16 16:59:05 -030055 * 0 - Sample on rising edge, 1 - Sample on falling edge
Laurent Pinchartb98d32f2011-08-12 19:09:34 +020056 * @hs_pol: Horizontal synchronization polarity
57 * 0 - Active high, 1 - Active low
58 * @vs_pol: Vertical synchronization polarity
59 * 0 - Active high, 1 - Active low
Laurent Pinchart9a36d8e2014-05-19 16:37:38 -030060 * @fld_pol: Field signal polarity
61 * 0 - Positive, 1 - Negative
Laurent Pinchart73ea57e2011-08-31 10:53:41 -030062 * @data_pol: Data polarity
63 * 0 - Normal, 1 - One's complement
Laurent Pinchartb98d32f2011-08-12 19:09:34 +020064 */
65struct isp_parallel_platform_data {
66 unsigned int data_lane_shift:2;
67 unsigned int clk_pol:1;
68 unsigned int hs_pol:1;
69 unsigned int vs_pol:1;
Laurent Pinchart9a36d8e2014-05-19 16:37:38 -030070 unsigned int fld_pol:1;
Laurent Pinchart73ea57e2011-08-31 10:53:41 -030071 unsigned int data_pol:1;
Laurent Pinchartb98d32f2011-08-12 19:09:34 +020072};
73
74enum {
75 ISP_CCP2_PHY_DATA_CLOCK = 0,
76 ISP_CCP2_PHY_DATA_STROBE = 1,
77};
78
79enum {
80 ISP_CCP2_MODE_MIPI = 0,
81 ISP_CCP2_MODE_CCP2 = 1,
82};
83
84/**
Sakari Ailusfe6adc12011-10-10 14:13:26 -030085 * struct isp_csiphy_lane: CCP2/CSI2 lane position and polarity
86 * @pos: position of the lane
87 * @pol: polarity of the lane
88 */
89struct isp_csiphy_lane {
90 u8 pos;
91 u8 pol;
92};
93
94#define ISP_CSIPHY1_NUM_DATA_LANES 1
95#define ISP_CSIPHY2_NUM_DATA_LANES 2
96
97/**
98 * struct isp_csiphy_lanes_cfg - CCP2/CSI2 lane configuration
99 * @data: Configuration of one or two data lanes
100 * @clk: Clock lane configuration
101 */
102struct isp_csiphy_lanes_cfg {
103 struct isp_csiphy_lane data[ISP_CSIPHY2_NUM_DATA_LANES];
104 struct isp_csiphy_lane clk;
105};
106
107/**
Laurent Pinchartb98d32f2011-08-12 19:09:34 +0200108 * struct isp_ccp2_platform_data - CCP2 interface platform data
109 * @strobe_clk_pol: Strobe/clock polarity
110 * 0 - Non Inverted, 1 - Inverted
111 * @crc: Enable the cyclic redundancy check
112 * @ccp2_mode: Enable CCP2 compatibility mode
113 * ISP_CCP2_MODE_MIPI - MIPI-CSI1 mode
114 * ISP_CCP2_MODE_CCP2 - CCP2 mode
115 * @phy_layer: Physical layer selection
116 * ISP_CCP2_PHY_DATA_CLOCK - Data/clock physical layer
117 * ISP_CCP2_PHY_DATA_STROBE - Data/strobe physical layer
118 * @vpclk_div: Video port output clock control
119 */
120struct isp_ccp2_platform_data {
121 unsigned int strobe_clk_pol:1;
122 unsigned int crc:1;
123 unsigned int ccp2_mode:1;
124 unsigned int phy_layer:1;
125 unsigned int vpclk_div:2;
Sakari Ailusfe6adc12011-10-10 14:13:26 -0300126 struct isp_csiphy_lanes_cfg lanecfg;
Laurent Pinchartb98d32f2011-08-12 19:09:34 +0200127};
128
129/**
130 * struct isp_csi2_platform_data - CSI2 interface platform data
131 * @crc: Enable the cyclic redundancy check
132 * @vpclk_div: Video port output clock control
133 */
134struct isp_csi2_platform_data {
135 unsigned crc:1;
136 unsigned vpclk_div:2;
Sakari Ailusfe6adc12011-10-10 14:13:26 -0300137 struct isp_csiphy_lanes_cfg lanecfg;
Laurent Pinchartb98d32f2011-08-12 19:09:34 +0200138};
139
140struct isp_subdev_i2c_board_info {
141 struct i2c_board_info *board_info;
142 int i2c_adapter_id;
143};
144
145struct isp_v4l2_subdevs_group {
146 struct isp_subdev_i2c_board_info *subdevs;
147 enum isp_interface_type interface;
148 union {
149 struct isp_parallel_platform_data parallel;
150 struct isp_ccp2_platform_data ccp2;
151 struct isp_csi2_platform_data csi2;
152 } bus; /* gcc < 4.6.0 chokes on anonymous union initializers */
153};
154
Laurent Pinchart9b28ee32012-10-22 10:43:00 -0300155struct isp_platform_xclk {
156 const char *dev_id;
157 const char *con_id;
158};
159
Laurent Pinchartb98d32f2011-08-12 19:09:34 +0200160struct isp_platform_data {
Laurent Pinchart9b28ee32012-10-22 10:43:00 -0300161 struct isp_platform_xclk xclks[2];
Laurent Pinchartb98d32f2011-08-12 19:09:34 +0200162 struct isp_v4l2_subdevs_group *subdevs;
163 void (*set_constraints)(struct isp_device *isp, bool enable);
164};
165
166#endif /* __MEDIA_OMAP3ISP_H__ */