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Saeed Bisharaff7b0472008-07-08 11:58:36 -07001/*
2 * Copyright (C) 2007, 2008, Marvell International Ltd.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
11 * for more details.
Saeed Bisharaff7b0472008-07-08 11:58:36 -070012 */
13
14#ifndef MV_XOR_H
15#define MV_XOR_H
16
17#include <linux/types.h>
18#include <linux/io.h>
19#include <linux/dmaengine.h>
20#include <linux/interrupt.h>
21
Lior Amsalemf1d25e02015-05-26 15:07:35 +020022#define MV_XOR_POOL_SIZE (MV_XOR_SLOT_SIZE * 3072)
Saeed Bisharaff7b0472008-07-08 11:58:36 -070023#define MV_XOR_SLOT_SIZE 64
24#define MV_XOR_THRESHOLD 1
Thomas Petazzoni60d151f2012-10-29 16:54:49 +010025#define MV_XOR_MAX_CHANNELS 2
Saeed Bisharaff7b0472008-07-08 11:58:36 -070026
Lior Amsalem22843542014-08-27 10:52:55 -030027#define MV_XOR_MIN_BYTE_COUNT SZ_128
28#define MV_XOR_MAX_BYTE_COUNT (SZ_16M - 1)
29
Thomas Petazzonie03bc652013-07-29 17:42:14 +020030/* Values for the XOR_CONFIG register */
Saeed Bisharaff7b0472008-07-08 11:58:36 -070031#define XOR_OPERATION_MODE_XOR 0
32#define XOR_OPERATION_MODE_MEMCPY 2
Lior Amsalem6f166312015-05-26 15:07:34 +020033#define XOR_OPERATION_MODE_IN_DESC 7
Thomas Petazzonie03bc652013-07-29 17:42:14 +020034#define XOR_DESCRIPTOR_SWAP BIT(14)
Lior Amsalem91362912015-05-26 15:07:32 +020035#define XOR_DESC_SUCCESS 0x40000000
Saeed Bisharaff7b0472008-07-08 11:58:36 -070036
Lior Amsalem6f166312015-05-26 15:07:34 +020037#define XOR_DESC_OPERATION_XOR (0 << 24)
38#define XOR_DESC_OPERATION_CRC32C (1 << 24)
39#define XOR_DESC_OPERATION_MEMCPY (2 << 24)
40
Ezequiel Garcia0e7488e2014-08-27 10:52:52 -030041#define XOR_DESC_DMA_OWNED BIT(31)
42#define XOR_DESC_EOD_INT_EN BIT(31)
43
Ezequiel Garcia82a14022013-10-30 12:01:43 -030044#define XOR_CURR_DESC(chan) (chan->mmr_high_base + 0x10 + (chan->idx * 4))
45#define XOR_NEXT_DESC(chan) (chan->mmr_high_base + 0x00 + (chan->idx * 4))
46#define XOR_BYTE_COUNT(chan) (chan->mmr_high_base + 0x20 + (chan->idx * 4))
47#define XOR_DEST_POINTER(chan) (chan->mmr_high_base + 0xB0 + (chan->idx * 4))
48#define XOR_BLOCK_SIZE(chan) (chan->mmr_high_base + 0xC0 + (chan->idx * 4))
49#define XOR_INIT_VALUE_LOW(chan) (chan->mmr_high_base + 0xE0)
50#define XOR_INIT_VALUE_HIGH(chan) (chan->mmr_high_base + 0xE4)
Saeed Bisharaff7b0472008-07-08 11:58:36 -070051
52#define XOR_CONFIG(chan) (chan->mmr_base + 0x10 + (chan->idx * 4))
53#define XOR_ACTIVATION(chan) (chan->mmr_base + 0x20 + (chan->idx * 4))
54#define XOR_INTR_CAUSE(chan) (chan->mmr_base + 0x30)
55#define XOR_INTR_MASK(chan) (chan->mmr_base + 0x40)
56#define XOR_ERROR_CAUSE(chan) (chan->mmr_base + 0x50)
57#define XOR_ERROR_ADDR(chan) (chan->mmr_base + 0x60)
Ezequiel Garcia0e7488e2014-08-27 10:52:52 -030058
59#define XOR_INT_END_OF_DESC BIT(0)
60#define XOR_INT_END_OF_CHAIN BIT(1)
61#define XOR_INT_STOPPED BIT(2)
62#define XOR_INT_PAUSED BIT(3)
63#define XOR_INT_ERR_DECODE BIT(4)
64#define XOR_INT_ERR_RDPROT BIT(5)
65#define XOR_INT_ERR_WRPROT BIT(6)
66#define XOR_INT_ERR_OWN BIT(7)
67#define XOR_INT_ERR_PAR BIT(8)
68#define XOR_INT_ERR_MBUS BIT(9)
69
70#define XOR_INTR_ERRORS (XOR_INT_ERR_DECODE | XOR_INT_ERR_RDPROT | \
71 XOR_INT_ERR_WRPROT | XOR_INT_ERR_OWN | \
72 XOR_INT_ERR_PAR | XOR_INT_ERR_MBUS)
73
Lior Amsalemba87d132014-08-27 10:52:53 -030074#define XOR_INTR_MASK_VALUE (XOR_INT_END_OF_DESC | XOR_INT_END_OF_CHAIN | \
Ezequiel Garcia0e7488e2014-08-27 10:52:52 -030075 XOR_INT_STOPPED | XOR_INTR_ERRORS)
Saeed Bisharaff7b0472008-07-08 11:58:36 -070076
Ezequiel Garcia82a14022013-10-30 12:01:43 -030077#define WINDOW_BASE(w) (0x50 + ((w) << 2))
78#define WINDOW_SIZE(w) (0x70 + ((w) << 2))
79#define WINDOW_REMAP_HIGH(w) (0x90 + ((w) << 2))
80#define WINDOW_BAR_ENABLE(chan) (0x40 + ((chan) << 2))
81#define WINDOW_OVERRIDE_CTRL(chan) (0xA0 + ((chan) << 2))
Saeed Bisharaff7b0472008-07-08 11:58:36 -070082
Thomas Petazzoni297eedb2012-11-15 15:29:53 +010083struct mv_xor_device {
Thomas Petazzoni60d151f2012-10-29 16:54:49 +010084 void __iomem *xor_base;
85 void __iomem *xor_high_base;
86 struct clk *clk;
Thomas Petazzoni1ef48a22012-11-15 15:17:05 +010087 struct mv_xor_chan *channels[MV_XOR_MAX_CHANNELS];
Saeed Bisharaff7b0472008-07-08 11:58:36 -070088};
89
90/**
91 * struct mv_xor_chan - internal representation of a XOR channel
92 * @pending: allows batching of hardware operations
Saeed Bisharaff7b0472008-07-08 11:58:36 -070093 * @lock: serializes enqueue/dequeue operations to the descriptors pool
94 * @mmr_base: memory mapped register base
95 * @idx: the index of the xor channel
96 * @chain: device chain view of the descriptors
Lior Amsalemfbea28a2015-05-26 15:07:36 +020097 * @free_slots: free slots usable by the channel
98 * @allocated_slots: slots allocated by the driver
Saeed Bisharaff7b0472008-07-08 11:58:36 -070099 * @completed_slots: slots completed by HW but still need to be acked
100 * @device: parent device
101 * @common: common dmaengine channel object members
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700102 * @slots_allocated: records the actual size of the descriptor slot pool
103 * @irq_tasklet: bottom half where mv_xor_slot_cleanup runs
Lior Amsalem6f166312015-05-26 15:07:34 +0200104 * @op_in_desc: new mode of driver, each op is writen to descriptor.
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700105 */
106struct mv_xor_chan {
107 int pending;
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700108 spinlock_t lock; /* protects the descriptor slot pool */
109 void __iomem *mmr_base;
Ezequiel Garcia82a14022013-10-30 12:01:43 -0300110 void __iomem *mmr_high_base;
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700111 unsigned int idx;
Thomas Petazzoni88eb92c2012-11-15 16:11:18 +0100112 int irq;
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700113 struct list_head chain;
Lior Amsalemfbea28a2015-05-26 15:07:36 +0200114 struct list_head free_slots;
115 struct list_head allocated_slots;
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700116 struct list_head completed_slots;
Thomas Petazzoni1ef48a22012-11-15 15:17:05 +0100117 dma_addr_t dma_desc_pool;
118 void *dma_desc_pool_virt;
119 size_t pool_size;
120 struct dma_device dmadev;
Thomas Petazzoni98817b92012-11-15 14:57:44 +0100121 struct dma_chan dmachan;
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700122 int slots_allocated;
123 struct tasklet_struct irq_tasklet;
Lior Amsalem6f166312015-05-26 15:07:34 +0200124 int op_in_desc;
Lior Amsalem22843542014-08-27 10:52:55 -0300125 char dummy_src[MV_XOR_MIN_BYTE_COUNT];
126 char dummy_dst[MV_XOR_MIN_BYTE_COUNT];
127 dma_addr_t dummy_src_addr, dummy_dst_addr;
Thomas Petazzoni8b648432015-12-22 11:43:29 +0100128 u32 saved_config_reg, saved_int_mask_reg;
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700129};
130
131/**
132 * struct mv_xor_desc_slot - software descriptor
Lior Amsalemfbea28a2015-05-26 15:07:36 +0200133 * @node: node on the mv_xor_chan lists
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700134 * @hw_desc: virtual address of the hardware descriptor chain
135 * @phys: hardware address of the hardware descriptor chain
Lior Amsalemdfc97662014-08-27 10:52:51 -0300136 * @slot_used: slot in use or not
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700137 * @idx: pool index
Dan Williams64203b62009-09-08 17:53:03 -0700138 * @tx_list: list of slots that make up a multi-descriptor transaction
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700139 * @async_tx: support for the async_tx api
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700140 */
141struct mv_xor_desc_slot {
Lior Amsalemfbea28a2015-05-26 15:07:36 +0200142 struct list_head node;
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700143 enum dma_transaction_type type;
144 void *hw_desc;
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700145 u16 idx;
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700146 struct dma_async_tx_descriptor async_tx;
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700147};
148
Thomas Petazzonie03bc652013-07-29 17:42:14 +0200149/*
150 * This structure describes XOR descriptor size 64bytes. The
151 * mv_phy_src_idx() macro must be used when indexing the values of the
152 * phy_src_addr[] array. This is due to the fact that the 'descriptor
153 * swap' feature, used on big endian systems, swaps descriptors data
154 * within blocks of 8 bytes. So two consecutive values of the
155 * phy_src_addr[] array are actually swapped in big-endian, which
156 * explains the different mv_phy_src_idx() implementation.
157 */
158#if defined(__LITTLE_ENDIAN)
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700159struct mv_xor_desc {
160 u32 status; /* descriptor execution status */
161 u32 crc32_result; /* result of CRC-32 calculation */
162 u32 desc_command; /* type of operation to be carried out */
163 u32 phy_next_desc; /* next descriptor address pointer */
164 u32 byte_count; /* size of src/dst blocks in bytes */
165 u32 phy_dest_addr; /* destination block address */
166 u32 phy_src_addr[8]; /* source block addresses */
167 u32 reserved0;
168 u32 reserved1;
169};
Thomas Petazzonie03bc652013-07-29 17:42:14 +0200170#define mv_phy_src_idx(src_idx) (src_idx)
171#else
172struct mv_xor_desc {
173 u32 crc32_result; /* result of CRC-32 calculation */
174 u32 status; /* descriptor execution status */
175 u32 phy_next_desc; /* next descriptor address pointer */
176 u32 desc_command; /* type of operation to be carried out */
177 u32 phy_dest_addr; /* destination block address */
178 u32 byte_count; /* size of src/dst blocks in bytes */
179 u32 phy_src_addr[8]; /* source block addresses */
180 u32 reserved1;
181 u32 reserved0;
182};
183#define mv_phy_src_idx(src_idx) (src_idx ^ 1)
184#endif
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700185
186#define to_mv_sw_desc(addr_hw_desc) \
187 container_of(addr_hw_desc, struct mv_xor_desc_slot, hw_desc)
188
189#define mv_hw_desc_slot_idx(hw_desc, idx) \
190 ((void *)(((unsigned long)hw_desc) + ((idx) << 5)))
191
Saeed Bisharaff7b0472008-07-08 11:58:36 -0700192#endif