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gerrit-public.fairphone.software / kernel / msm-4.9 / 0b51b02edff2417deff98d8bbf294fa56b765bc6 / . / include / asm-powerpc / immap_qe.h
blob: 924aefbd6a8ed952956a1fdeaafb60412d237a2f [file] [log] [blame]
Li Yang98658532006-10-03 23:10:46 -0500[diff] [blame]1/*
2 * include/asm-powerpc/immap_qe.h
3 *
4 * QUICC Engine (QE) Internal Memory Map.
5 * The Internal Memory Map for devices with QE on them. This
6 * is the superset of all QE devices (8360, etc.).
7
8 * Copyright (C) 2006. Freescale Semicondutor, Inc. All rights reserved.
9 *
10 * Authors: Shlomi Gridish <gridish@freescale.com>
11 * Li Yang <leoli@freescale.com>
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 */
18#ifndef _ASM_POWERPC_IMMAP_QE_H
19#define _ASM_POWERPC_IMMAP_QE_H
20#ifdef __KERNEL__
21
22#include <linux/kernel.h>
23
24#define QE_IMMAP_SIZE (1024 * 1024) /* 1MB from 1MB+IMMR */
25
26/* QE I-RAM */
27struct qe_iram {
28 __be32 iadd; /* I-RAM Address Register */
29 __be32 idata; /* I-RAM Data Register */
30 u8 res0[0x78];
31} __attribute__ ((packed));
32
33/* QE Interrupt Controller */
34struct qe_ic_regs {
35 __be32 qicr;
36 __be32 qivec;
37 __be32 qripnr;
38 __be32 qipnr;
39 __be32 qipxcc;
40 __be32 qipycc;
41 __be32 qipwcc;
42 __be32 qipzcc;
43 __be32 qimr;
44 __be32 qrimr;
45 __be32 qicnr;
46 u8 res0[0x4];
47 __be32 qiprta;
48 __be32 qiprtb;
49 u8 res1[0x4];
50 __be32 qricr;
51 u8 res2[0x20];
52 __be32 qhivec;
53 u8 res3[0x1C];
54} __attribute__ ((packed));
55
56/* Communications Processor */
57struct cp_qe {
58 __be32 cecr; /* QE command register */
59 __be32 ceccr; /* QE controller configuration register */
60 __be32 cecdr; /* QE command data register */
61 u8 res0[0xA];
62 __be16 ceter; /* QE timer event register */
63 u8 res1[0x2];
64 __be16 cetmr; /* QE timers mask register */
65 __be32 cetscr; /* QE time-stamp timer control register */
66 __be32 cetsr1; /* QE time-stamp register 1 */
67 __be32 cetsr2; /* QE time-stamp register 2 */
68 u8 res2[0x8];
69 __be32 cevter; /* QE virtual tasks event register */
70 __be32 cevtmr; /* QE virtual tasks mask register */
71 __be16 cercr; /* QE RAM control register */
72 u8 res3[0x2];
73 u8 res4[0x24];
74 __be16 ceexe1; /* QE external request 1 event register */
75 u8 res5[0x2];
76 __be16 ceexm1; /* QE external request 1 mask register */
77 u8 res6[0x2];
78 __be16 ceexe2; /* QE external request 2 event register */
79 u8 res7[0x2];
80 __be16 ceexm2; /* QE external request 2 mask register */
81 u8 res8[0x2];
82 __be16 ceexe3; /* QE external request 3 event register */
83 u8 res9[0x2];
84 __be16 ceexm3; /* QE external request 3 mask register */
85 u8 res10[0x2];
86 __be16 ceexe4; /* QE external request 4 event register */
87 u8 res11[0x2];
88 __be16 ceexm4; /* QE external request 4 mask register */
Emil Medveb6927bc2007-09-26 12:03:40 -0500[diff] [blame]89 u8 res12[0x3A];
90 __be32 ceurnr; /* QE microcode revision number register */
91 u8 res13[0x244];
Li Yang98658532006-10-03 23:10:46 -0500[diff] [blame]92} __attribute__ ((packed));
93
94/* QE Multiplexer */
95struct qe_mux {
96 __be32 cmxgcr; /* CMX general clock route register */
97 __be32 cmxsi1cr_l; /* CMX SI1 clock route low register */
98 __be32 cmxsi1cr_h; /* CMX SI1 clock route high register */
99 __be32 cmxsi1syr; /* CMX SI1 SYNC route register */
Timur Tabi6b0b5942007-10-03 11:34:59 -0500[diff] [blame]100 __be32 cmxucr[4]; /* CMX UCCx clock route registers */
Li Yang98658532006-10-03 23:10:46 -0500[diff] [blame]101 __be32 cmxupcr; /* CMX UPC clock route register */
102 u8 res0[0x1C];
103} __attribute__ ((packed));
104
105/* QE Timers */
106struct qe_timers {
107 u8 gtcfr1; /* Timer 1 and Timer 2 global config register*/
108 u8 res0[0x3];
109 u8 gtcfr2; /* Timer 3 and timer 4 global config register*/
110 u8 res1[0xB];
111 __be16 gtmdr1; /* Timer 1 mode register */
112 __be16 gtmdr2; /* Timer 2 mode register */
113 __be16 gtrfr1; /* Timer 1 reference register */
114 __be16 gtrfr2; /* Timer 2 reference register */
115 __be16 gtcpr1; /* Timer 1 capture register */
116 __be16 gtcpr2; /* Timer 2 capture register */
117 __be16 gtcnr1; /* Timer 1 counter */
118 __be16 gtcnr2; /* Timer 2 counter */
119 __be16 gtmdr3; /* Timer 3 mode register */
120 __be16 gtmdr4; /* Timer 4 mode register */
121 __be16 gtrfr3; /* Timer 3 reference register */
122 __be16 gtrfr4; /* Timer 4 reference register */
123 __be16 gtcpr3; /* Timer 3 capture register */
124 __be16 gtcpr4; /* Timer 4 capture register */
125 __be16 gtcnr3; /* Timer 3 counter */
126 __be16 gtcnr4; /* Timer 4 counter */
127 __be16 gtevr1; /* Timer 1 event register */
128 __be16 gtevr2; /* Timer 2 event register */
129 __be16 gtevr3; /* Timer 3 event register */
130 __be16 gtevr4; /* Timer 4 event register */
131 __be16 gtps; /* Timer 1 prescale register */
132 u8 res2[0x46];
133} __attribute__ ((packed));
134
135/* BRG */
136struct qe_brg {
Timur Tabifc9e8b42006-11-09 15:42:44 -0600[diff] [blame]137 __be32 brgc[16]; /* BRG configuration registers */
Li Yang98658532006-10-03 23:10:46 -0500[diff] [blame]138 u8 res0[0x40];
139} __attribute__ ((packed));
140
141/* SPI */
142struct spi {
143 u8 res0[0x20];
144 __be32 spmode; /* SPI mode register */
145 u8 res1[0x2];
146 u8 spie; /* SPI event register */
147 u8 res2[0x1];
148 u8 res3[0x2];
149 u8 spim; /* SPI mask register */
150 u8 res4[0x1];
151 u8 res5[0x1];
152 u8 spcom; /* SPI command register */
153 u8 res6[0x2];
154 __be32 spitd; /* SPI transmit data register (cpu mode) */
155 __be32 spird; /* SPI receive data register (cpu mode) */
156 u8 res7[0x8];
157} __attribute__ ((packed));
158
159/* SI */
160struct si1 {
161 __be16 siamr1; /* SI1 TDMA mode register */
162 __be16 sibmr1; /* SI1 TDMB mode register */
163 __be16 sicmr1; /* SI1 TDMC mode register */
164 __be16 sidmr1; /* SI1 TDMD mode register */
165 u8 siglmr1_h; /* SI1 global mode register high */
166 u8 res0[0x1];
167 u8 sicmdr1_h; /* SI1 command register high */
168 u8 res2[0x1];
169 u8 sistr1_h; /* SI1 status register high */
170 u8 res3[0x1];
171 __be16 sirsr1_h; /* SI1 RAM shadow address register high */
172 u8 sitarc1; /* SI1 RAM counter Tx TDMA */
173 u8 sitbrc1; /* SI1 RAM counter Tx TDMB */
174 u8 sitcrc1; /* SI1 RAM counter Tx TDMC */
175 u8 sitdrc1; /* SI1 RAM counter Tx TDMD */
176 u8 sirarc1; /* SI1 RAM counter Rx TDMA */
177 u8 sirbrc1; /* SI1 RAM counter Rx TDMB */
178 u8 sircrc1; /* SI1 RAM counter Rx TDMC */
179 u8 sirdrc1; /* SI1 RAM counter Rx TDMD */
180 u8 res4[0x8];
181 __be16 siemr1; /* SI1 TDME mode register 16 bits */
182 __be16 sifmr1; /* SI1 TDMF mode register 16 bits */
183 __be16 sigmr1; /* SI1 TDMG mode register 16 bits */
184 __be16 sihmr1; /* SI1 TDMH mode register 16 bits */
185 u8 siglmg1_l; /* SI1 global mode register low 8 bits */
186 u8 res5[0x1];
187 u8 sicmdr1_l; /* SI1 command register low 8 bits */
188 u8 res6[0x1];
189 u8 sistr1_l; /* SI1 status register low 8 bits */
190 u8 res7[0x1];
191 __be16 sirsr1_l; /* SI1 RAM shadow address register low 16 bits*/
192 u8 siterc1; /* SI1 RAM counter Tx TDME 8 bits */
193 u8 sitfrc1; /* SI1 RAM counter Tx TDMF 8 bits */
194 u8 sitgrc1; /* SI1 RAM counter Tx TDMG 8 bits */
195 u8 sithrc1; /* SI1 RAM counter Tx TDMH 8 bits */
196 u8 sirerc1; /* SI1 RAM counter Rx TDME 8 bits */
197 u8 sirfrc1; /* SI1 RAM counter Rx TDMF 8 bits */
198 u8 sirgrc1; /* SI1 RAM counter Rx TDMG 8 bits */
199 u8 sirhrc1; /* SI1 RAM counter Rx TDMH 8 bits */
200 u8 res8[0x8];
201 __be32 siml1; /* SI1 multiframe limit register */
202 u8 siedm1; /* SI1 extended diagnostic mode register */
203 u8 res9[0xBB];
204} __attribute__ ((packed));
205
206/* SI Routing Tables */
207struct sir {
208 u8 tx[0x400];
209 u8 rx[0x400];
210 u8 res0[0x800];
211} __attribute__ ((packed));
212
213/* USB Controller */
214struct usb_ctlr {
215 u8 usb_usmod;
216 u8 usb_usadr;
217 u8 usb_uscom;
218 u8 res1[1];
219 __be16 usb_usep1;
220 __be16 usb_usep2;
221 __be16 usb_usep3;
222 __be16 usb_usep4;
223 u8 res2[4];
224 __be16 usb_usber;
225 u8 res3[2];
226 __be16 usb_usbmr;
227 u8 res4[1];
228 u8 usb_usbs;
229 __be16 usb_ussft;
230 u8 res5[2];
231 __be16 usb_usfrn;
232 u8 res6[0x22];
233} __attribute__ ((packed));
234
235/* MCC */
236struct mcc {
237 __be32 mcce; /* MCC event register */
238 __be32 mccm; /* MCC mask register */
239 __be32 mccf; /* MCC configuration register */
240 __be32 merl; /* MCC emergency request level register */
241 u8 res0[0xF0];
242} __attribute__ ((packed));
243
244/* QE UCC Slow */
245struct ucc_slow {
246 __be32 gumr_l; /* UCCx general mode register (low) */
247 __be32 gumr_h; /* UCCx general mode register (high) */
248 __be16 upsmr; /* UCCx protocol-specific mode register */
249 u8 res0[0x2];
250 __be16 utodr; /* UCCx transmit on demand register */
251 __be16 udsr; /* UCCx data synchronization register */
252 __be16 ucce; /* UCCx event register */
253 u8 res1[0x2];
254 __be16 uccm; /* UCCx mask register */
255 u8 res2[0x1];
256 u8 uccs; /* UCCx status register */
257 u8 res3[0x24];
258 __be16 utpt;
Timur Tabi297640e2007-03-26 14:25:42 -0500[diff] [blame]259 u8 res4[0x52];
Li Yang98658532006-10-03 23:10:46 -0500[diff] [blame]260 u8 guemr; /* UCC general extended mode register */
Li Yang98658532006-10-03 23:10:46 -0500[diff] [blame]261} __attribute__ ((packed));
262
263/* QE UCC Fast */
264struct ucc_fast {
265 __be32 gumr; /* UCCx general mode register */
266 __be32 upsmr; /* UCCx protocol-specific mode register */
267 __be16 utodr; /* UCCx transmit on demand register */
268 u8 res0[0x2];
269 __be16 udsr; /* UCCx data synchronization register */
270 u8 res1[0x2];
271 __be32 ucce; /* UCCx event register */
272 __be32 uccm; /* UCCx mask register */
273 u8 uccs; /* UCCx status register */
274 u8 res2[0x7];
275 __be32 urfb; /* UCC receive FIFO base */
276 __be16 urfs; /* UCC receive FIFO size */
277 u8 res3[0x2];
278 __be16 urfet; /* UCC receive FIFO emergency threshold */
279 __be16 urfset; /* UCC receive FIFO special emergency
280 threshold */
281 __be32 utfb; /* UCC transmit FIFO base */
282 __be16 utfs; /* UCC transmit FIFO size */
283 u8 res4[0x2];
284 __be16 utfet; /* UCC transmit FIFO emergency threshold */
285 u8 res5[0x2];
286 __be16 utftt; /* UCC transmit FIFO transmit threshold */
287 u8 res6[0x2];
288 __be16 utpt; /* UCC transmit polling timer */
289 u8 res7[0x2];
290 __be32 urtry; /* UCC retry counter register */
291 u8 res8[0x4C];
292 u8 guemr; /* UCC general extended mode register */
Li Yang98658532006-10-03 23:10:46 -0500[diff] [blame]293} __attribute__ ((packed));
294
295struct ucc {
296 union {
297 struct ucc_slow slow;
298 struct ucc_fast fast;
Timur Tabi6b0b5942007-10-03 11:34:59 -0500[diff] [blame]299 u8 res[0x200]; /* UCC blocks are 512 bytes each */
Li Yang98658532006-10-03 23:10:46 -0500[diff] [blame]300 };
301} __attribute__ ((packed));
302
303/* MultiPHY UTOPIA POS Controllers (UPC) */
304struct upc {
305 __be32 upgcr; /* UTOPIA/POS general configuration register */
306 __be32 uplpa; /* UTOPIA/POS last PHY address */
307 __be32 uphec; /* ATM HEC register */
308 __be32 upuc; /* UTOPIA/POS UCC configuration */
309 __be32 updc1; /* UTOPIA/POS device 1 configuration */
310 __be32 updc2; /* UTOPIA/POS device 2 configuration */
311 __be32 updc3; /* UTOPIA/POS device 3 configuration */
312 __be32 updc4; /* UTOPIA/POS device 4 configuration */
313 __be32 upstpa; /* UTOPIA/POS STPA threshold */
314 u8 res0[0xC];
315 __be32 updrs1_h; /* UTOPIA/POS device 1 rate select */
316 __be32 updrs1_l; /* UTOPIA/POS device 1 rate select */
317 __be32 updrs2_h; /* UTOPIA/POS device 2 rate select */
318 __be32 updrs2_l; /* UTOPIA/POS device 2 rate select */
319 __be32 updrs3_h; /* UTOPIA/POS device 3 rate select */
320 __be32 updrs3_l; /* UTOPIA/POS device 3 rate select */
321 __be32 updrs4_h; /* UTOPIA/POS device 4 rate select */
322 __be32 updrs4_l; /* UTOPIA/POS device 4 rate select */
323 __be32 updrp1; /* UTOPIA/POS device 1 receive priority low */
324 __be32 updrp2; /* UTOPIA/POS device 2 receive priority low */
325 __be32 updrp3; /* UTOPIA/POS device 3 receive priority low */
326 __be32 updrp4; /* UTOPIA/POS device 4 receive priority low */
327 __be32 upde1; /* UTOPIA/POS device 1 event */
328 __be32 upde2; /* UTOPIA/POS device 2 event */
329 __be32 upde3; /* UTOPIA/POS device 3 event */
330 __be32 upde4; /* UTOPIA/POS device 4 event */
331 __be16 uprp1;
332 __be16 uprp2;
333 __be16 uprp3;
334 __be16 uprp4;
335 u8 res1[0x8];
336 __be16 uptirr1_0; /* Device 1 transmit internal rate 0 */
337 __be16 uptirr1_1; /* Device 1 transmit internal rate 1 */
338 __be16 uptirr1_2; /* Device 1 transmit internal rate 2 */
339 __be16 uptirr1_3; /* Device 1 transmit internal rate 3 */
340 __be16 uptirr2_0; /* Device 2 transmit internal rate 0 */
341 __be16 uptirr2_1; /* Device 2 transmit internal rate 1 */
342 __be16 uptirr2_2; /* Device 2 transmit internal rate 2 */
343 __be16 uptirr2_3; /* Device 2 transmit internal rate 3 */
344 __be16 uptirr3_0; /* Device 3 transmit internal rate 0 */
345 __be16 uptirr3_1; /* Device 3 transmit internal rate 1 */
346 __be16 uptirr3_2; /* Device 3 transmit internal rate 2 */
347 __be16 uptirr3_3; /* Device 3 transmit internal rate 3 */
348 __be16 uptirr4_0; /* Device 4 transmit internal rate 0 */
349 __be16 uptirr4_1; /* Device 4 transmit internal rate 1 */
350 __be16 uptirr4_2; /* Device 4 transmit internal rate 2 */
351 __be16 uptirr4_3; /* Device 4 transmit internal rate 3 */
352 __be32 uper1; /* Device 1 port enable register */
353 __be32 uper2; /* Device 2 port enable register */
354 __be32 uper3; /* Device 3 port enable register */
355 __be32 uper4; /* Device 4 port enable register */
356 u8 res2[0x150];
357} __attribute__ ((packed));
358
359/* SDMA */
360struct sdma {
361 __be32 sdsr; /* Serial DMA status register */
362 __be32 sdmr; /* Serial DMA mode register */
363 __be32 sdtr1; /* SDMA system bus threshold register */
364 __be32 sdtr2; /* SDMA secondary bus threshold register */
365 __be32 sdhy1; /* SDMA system bus hysteresis register */
366 __be32 sdhy2; /* SDMA secondary bus hysteresis register */
367 __be32 sdta1; /* SDMA system bus address register */
368 __be32 sdta2; /* SDMA secondary bus address register */
369 __be32 sdtm1; /* SDMA system bus MSNUM register */
370 __be32 sdtm2; /* SDMA secondary bus MSNUM register */
371 u8 res0[0x10];
372 __be32 sdaqr; /* SDMA address bus qualify register */
373 __be32 sdaqmr; /* SDMA address bus qualify mask register */
374 u8 res1[0x4];
375 __be32 sdebcr; /* SDMA CAM entries base register */
376 u8 res2[0x38];
377} __attribute__ ((packed));
378
379/* Debug Space */
380struct dbg {
381 __be32 bpdcr; /* Breakpoint debug command register */
382 __be32 bpdsr; /* Breakpoint debug status register */
383 __be32 bpdmr; /* Breakpoint debug mask register */
384 __be32 bprmrr0; /* Breakpoint request mode risc register 0 */
385 __be32 bprmrr1; /* Breakpoint request mode risc register 1 */
386 u8 res0[0x8];
387 __be32 bprmtr0; /* Breakpoint request mode trb register 0 */
388 __be32 bprmtr1; /* Breakpoint request mode trb register 1 */
389 u8 res1[0x8];
390 __be32 bprmir; /* Breakpoint request mode immediate register */
391 __be32 bprmsr; /* Breakpoint request mode serial register */
392 __be32 bpemr; /* Breakpoint exit mode register */
393 u8 res2[0x48];
394} __attribute__ ((packed));
395
Timur Tabibc556ba2008-01-08 10:30:58 -0600[diff] [blame]396/*
397 * RISC Special Registers (Trap and Breakpoint). These are described in
398 * the QE Developer's Handbook.
399 */
Li Yang98658532006-10-03 23:10:46 -0500[diff] [blame]400struct rsp {
Timur Tabibc556ba2008-01-08 10:30:58 -0600[diff] [blame]401 __be32 tibcr[16]; /* Trap/instruction breakpoint control regs */
402 u8 res0[64];
403 __be32 ibcr0;
404 __be32 ibs0;
405 __be32 ibcnr0;
406 u8 res1[4];
407 __be32 ibcr1;
408 __be32 ibs1;
409 __be32 ibcnr1;
410 __be32 npcr;
411 __be32 dbcr;
412 __be32 dbar;
413 __be32 dbamr;
414 __be32 dbsr;
415 __be32 dbcnr;
416 u8 res2[12];
417 __be32 dbdr_h;
418 __be32 dbdr_l;
419 __be32 dbdmr_h;
420 __be32 dbdmr_l;
421 __be32 bsr;
422 __be32 bor;
423 __be32 bior;
424 u8 res3[4];
425 __be32 iatr[4];
426 __be32 eccr; /* Exception control configuration register */
427 __be32 eicr;
428 u8 res4[0x100-0xf8];
Li Yang98658532006-10-03 23:10:46 -0500[diff] [blame]429} __attribute__ ((packed));
430
431struct qe_immap {
432 struct qe_iram iram; /* I-RAM */
433 struct qe_ic_regs ic; /* Interrupt Controller */
434 struct cp_qe cp; /* Communications Processor */
435 struct qe_mux qmx; /* QE Multiplexer */
436 struct qe_timers qet; /* QE Timers */
437 struct spi spi[0x2]; /* spi */
438 struct mcc mcc; /* mcc */
439 struct qe_brg brg; /* brg */
440 struct usb_ctlr usb; /* USB */
441 struct si1 si1; /* SI */
442 u8 res11[0x800];
443 struct sir sir; /* SI Routing Tables */
444 struct ucc ucc1; /* ucc1 */
445 struct ucc ucc3; /* ucc3 */
446 struct ucc ucc5; /* ucc5 */
447 struct ucc ucc7; /* ucc7 */
448 u8 res12[0x600];
449 struct upc upc1; /* MultiPHY UTOPIA POS Ctrlr 1*/
450 struct ucc ucc2; /* ucc2 */
451 struct ucc ucc4; /* ucc4 */
452 struct ucc ucc6; /* ucc6 */
453 struct ucc ucc8; /* ucc8 */
454 u8 res13[0x600];
455 struct upc upc2; /* MultiPHY UTOPIA POS Ctrlr 2*/
456 struct sdma sdma; /* SDMA */
Timur Tabi6b0b5942007-10-03 11:34:59 -0500[diff] [blame]457 struct dbg dbg; /* 0x104080 - 0x1040FF
458 Debug Space */
459 struct rsp rsp[0x2]; /* 0x104100 - 0x1042FF
460 RISC Special Registers
Li Yang98658532006-10-03 23:10:46 -0500[diff] [blame]461 (Trap and Breakpoint) */
Timur Tabi6b0b5942007-10-03 11:34:59 -0500[diff] [blame]462 u8 res14[0x300]; /* 0x104300 - 0x1045FF */
463 u8 res15[0x3A00]; /* 0x104600 - 0x107FFF */
Li Yang98658532006-10-03 23:10:46 -0500[diff] [blame]464 u8 res16[0x8000]; /* 0x108000 - 0x110000 */
465 u8 muram[0xC000]; /* 0x110000 - 0x11C000
466 Multi-user RAM */
467 u8 res17[0x24000]; /* 0x11C000 - 0x140000 */
468 u8 res18[0xC0000]; /* 0x140000 - 0x200000 */
469} __attribute__ ((packed));
470
Anton Vorontsov0b51b022008-03-11 20:24:13 +0300[diff] [blame^]471extern struct qe_immap __iomem *qe_immr;
Li Yang98658532006-10-03 23:10:46 -0500[diff] [blame]472extern phys_addr_t get_qe_base(void);
473
Timur Tabi6b0b5942007-10-03 11:34:59 -0500[diff] [blame]474static inline unsigned long immrbar_virt_to_phys(void *address)
Li Yang98658532006-10-03 23:10:46 -0500[diff] [blame]475{
476 if ( ((u32)address >= (u32)qe_immr) &&
477 ((u32)address < ((u32)qe_immr + QE_IMMAP_SIZE)) )
478 return (unsigned long)(address - (u32)qe_immr +
479 (u32)get_qe_base());
480 return (unsigned long)virt_to_phys(address);
481}
482
483#endif /* __KERNEL__ */
484#endif /* _ASM_POWERPC_IMMAP_QE_H */