blob: 79d6edf446d513d22702ad093b7382ca8ab57b7d [file] [log] [blame]
Lorenzo Pieralisied69bdd2012-07-13 15:55:52 +01001/*
2 * CCI cache coherent interconnect support
3 *
4 * Copyright (C) 2013 ARM Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#ifndef __LINUX_ARM_CCI_H
22#define __LINUX_ARM_CCI_H
23
24#include <linux/errno.h>
25#include <linux/types.h>
26
27struct device_node;
28
29#ifdef CONFIG_ARM_CCI
30extern bool cci_probed(void);
31extern int cci_ace_get_port(struct device_node *dn);
32extern int cci_disable_port_by_cpu(u64 mpidr);
33extern int __cci_control_port_by_device(struct device_node *dn, bool enable);
34extern int __cci_control_port_by_index(u32 port, bool enable);
35#else
36static inline bool cci_probed(void) { return false; }
37static inline int cci_ace_get_port(struct device_node *dn)
38{
39 return -ENODEV;
40}
41static inline int cci_disable_port_by_cpu(u64 mpidr) { return -ENODEV; }
42static inline int __cci_control_port_by_device(struct device_node *dn,
43 bool enable)
44{
45 return -ENODEV;
46}
47static inline int __cci_control_port_by_index(u32 port, bool enable)
48{
49 return -ENODEV;
50}
51#endif
52#define cci_disable_port_by_device(dev) \
53 __cci_control_port_by_device(dev, false)
54#define cci_enable_port_by_device(dev) \
55 __cci_control_port_by_device(dev, true)
56#define cci_disable_port_by_index(dev) \
57 __cci_control_port_by_index(dev, false)
58#define cci_enable_port_by_index(dev) \
59 __cci_control_port_by_index(dev, true)
60
61#endif