| Sonic Zhang | 22a8262 | 2012-05-16 17:24:33 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2011 Analog Devices Inc. |
| 3 | * |
| 4 | * Licensed under the GPL-2 or later. |
| 5 | */ |
| 6 | |
| 7 | #ifndef _CDEF_BF60X_H |
| 8 | #define _CDEF_BF60X_H |
| 9 | |
| 10 | /* ************************************************************** */ |
| 11 | /* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF60x */ |
| 12 | /* ************************************************************** */ |
| 13 | |
| 14 | /* Debug/MP/Emulation Registers (0xFFC00014 - 0xFFC00014) */ |
| 15 | |
| 16 | #define bfin_read_CHIPID() bfin_read32(CHIPID) |
| 17 | #define bfin_write_CHIPID(val) bfin_write32(CHIPID, val) |
| 18 | |
| 19 | /* System Reset and Interrubfin_read_()t Controller (0xFFC00100 - 0xFFC00104) */ |
| 20 | |
| 21 | /* SEC0 Registers */ |
| 22 | #define bfin_read_SEC0_CCTL() bfin_read32(SEC0_CCTL) |
| 23 | #define bfin_write_SEC0_CCTL(val) bfin_write32(SEC0_CCTL, val) |
| 24 | #define bfin_read_SEC0_CSID() bfin_read32(SEC0_CSID) |
| 25 | #define bfin_write_SEC0_CSID(val) bfin_write32(SEC0_CSID, val) |
| 26 | #define bfin_read_SEC_GCTL() bfin_read32(SEC_GCTL) |
| 27 | #define bfin_write_SEC_GCTL(val) bfin_write32(SEC_GCTL, val) |
| 28 | |
| 29 | #define bfin_read_SEC_FCTL() bfin_read32(SEC_FCTL) |
| 30 | #define bfin_write_SEC_FCTL(val) bfin_write32(SEC_FCTL, val) |
| 31 | |
| 32 | #define bfin_read_SEC_SCTL(sid) bfin_read32((SEC_SCTL0 + (sid) * 8)) |
| 33 | #define bfin_write_SEC_SCTL(sid, val) bfin_write32((SEC_SCTL0 + (sid) * 8), val) |
| 34 | |
| 35 | #define bfin_read_SEC_SSTAT(sid) bfin_read32((SEC_SSTAT0 + (sid) * 8)) |
| 36 | #define bfin_write_SEC_SSTAT(sid, val) bfin_write32((SEC_SSTAT0 + (sid) * 8), val) |
| 37 | |
| 38 | /* RCU0 Registers */ |
| 39 | #define bfin_read_RCU0_CTL() bfin_read32(RCU0_CTL) |
| 40 | #define bfin_write_RCU0_CTL(val) bfin_write32(RCU0_CTL, val) |
| 41 | |
| 42 | /* Watchdog Timer Registers */ |
| 43 | #define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL) |
| 44 | #define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val) |
| 45 | #define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT) |
| 46 | #define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val) |
| 47 | #define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT) |
| 48 | #define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val) |
| 49 | |
| 50 | /* RTC Registers */ |
| 51 | |
| 52 | /* UART0 Registers */ |
| 53 | |
| 54 | #define bfin_read_UART0_REVID() bfin_read32(UART0_REVID) |
| 55 | #define bfin_write_UART0_REVID(val) bfin_write32(UART0_REVID, val) |
| 56 | #define bfin_read_UART0_GCTL() bfin_read32(UART0_GCTL) |
| 57 | #define bfin_write_UART0_GCTL(val) bfin_write32(UART0_GCTL, val) |
| 58 | #define bfin_read_UART0_STAT() bfin_read32(UART0_STAT) |
| 59 | #define bfin_write_UART0_STAT(val) bfin_write32(UART0_STAT, val) |
| 60 | #define bfin_read_UART0_SCR() bfin_read32(UART0_SCR) |
| 61 | #define bfin_write_UART0_SCR(val) bfin_write32(UART0_SCR, val) |
| 62 | #define bfin_read_UART0_CLK() bfin_read32(UART0_CLK) |
| 63 | #define bfin_write_UART0_CLK(val) bfin_write32(UART0_CLK, val) |
| 64 | #define bfin_read_UART0_IER() bfin_read32(UART0_IER) |
| 65 | #define bfin_write_UART0_IER(val) bfin_write32(UART0_IER, val) |
| 66 | #define bfin_read_UART0_IER_SET() bfin_read32(UART0_IER_SET) |
| 67 | #define bfin_write_UART0_IER_SET(val) bfin_write32(UART0_IER_SET, val) |
| 68 | #define bfin_read_UART0_IER_CLEAR() bfin_read32(UART0_IER_CLEAR) |
| 69 | #define bfin_write_UART0_IER_CLEAR(val) bfin_write32(UART0_IER_CLEAR, val) |
| 70 | #define bfin_read_UART0_RBR() bfin_read32(UART0_RBR) |
| 71 | #define bfin_write_UART0_RBR(val) bfin_write32(UART0_RBR, val) |
| 72 | #define bfin_read_UART0_THR() bfin_read32(UART0_THR) |
| 73 | #define bfin_write_UART0_THR(val) bfin_write32(UART0_THR, val) |
| 74 | #define bfin_read_UART0_TAIP() bfin_read32(UART0_TAIP) |
| 75 | #define bfin_write_UART0_TAIP(val) bfin_write32(UART0_TAIP, val) |
| 76 | #define bfin_read_UART0_TSR() bfin_read32(UART0_TSR) |
| 77 | #define bfin_write_UART0_TSR(val) bfin_write32(UART0_TSR, val) |
| 78 | #define bfin_read_UART0_RSR() bfin_read32(UART0_RSR) |
| 79 | #define bfin_write_UART0_RSR(val) bfin_write32(UART0_RSR, val) |
| 80 | #define bfin_read_UART0_TXCNT() bfin_read32(UART0_TXCNT) |
| 81 | #define bfin_write_UART0_TXCNT(val) bfin_write32(UART0_TXCNT, val) |
| 82 | #define bfin_read_UART0_RXCNT() bfin_read32(UART0_RXCNT) |
| 83 | #define bfin_write_UART0_RXCNT(val) bfin_write32(UART0_RXCNT, val) |
| 84 | |
| 85 | /* UART1 Registers */ |
| 86 | |
| 87 | #define bfin_read_UART1_REVID() bfin_read32(UART1_REVID) |
| 88 | #define bfin_write_UART1_REVID(val) bfin_write32(UART1_REVID, val) |
| 89 | #define bfin_read_UART1_GCTL() bfin_read32(UART1_GCTL) |
| 90 | #define bfin_write_UART1_GCTL(val) bfin_write32(UART1_GCTL, val) |
| 91 | #define bfin_read_UART1_STAT() bfin_read32(UART1_STAT) |
| 92 | #define bfin_write_UART1_STAT(val) bfin_write32(UART1_STAT, val) |
| 93 | #define bfin_read_UART1_SCR() bfin_read32(UART1_SCR) |
| 94 | #define bfin_write_UART1_SCR(val) bfin_write32(UART1_SCR, val) |
| 95 | #define bfin_read_UART1_CLK() bfin_read32(UART1_CLK) |
| 96 | #define bfin_write_UART1_CLK(val) bfin_write32(UART1_CLK, val) |
| 97 | #define bfin_read_UART1_IER() bfin_read32(UART1_IER) |
| 98 | #define bfin_write_UART1_IER(val) bfin_write32(UART1_IER, val) |
| 99 | #define bfin_read_UART1_IER_SET() bfin_read32(UART1_IER_SET) |
| 100 | #define bfin_write_UART1_IER_SET(val) bfin_write32(UART1_IER_SET, val) |
| 101 | #define bfin_read_UART1_IER_CLEAR() bfin_read32(UART1_IER_CLEAR) |
| 102 | #define bfin_write_UART1_IER_CLEAR(val) bfin_write32(UART1_IER_CLEAR, val) |
| 103 | #define bfin_read_UART1_RBR() bfin_read32(UART1_RBR) |
| 104 | #define bfin_write_UART1_RBR(val) bfin_write32(UART1_RBR, val) |
| 105 | #define bfin_read_UART1_THR() bfin_read32(UART1_THR) |
| 106 | #define bfin_write_UART1_THR(val) bfin_write32(UART1_THR, val) |
| 107 | #define bfin_read_UART1_TAIP() bfin_read32(UART1_TAIP) |
| 108 | #define bfin_write_UART1_TAIP(val) bfin_write32(UART1_TAIP, val) |
| 109 | #define bfin_read_UART1_TSR() bfin_read32(UART1_TSR) |
| 110 | #define bfin_write_UART1_TSR(val) bfin_write32(UART1_TSR, val) |
| 111 | #define bfin_read_UART1_RSR() bfin_read32(UART1_RSR) |
| 112 | #define bfin_write_UART1_RSR(val) bfin_write32(UART1_RSR, val) |
| 113 | #define bfin_read_UART1_TXCNT() bfin_read32(UART1_TXCNT) |
| 114 | #define bfin_write_UART1_TXCNT(val) bfin_write32(UART1_TXCNT, val) |
| 115 | #define bfin_read_UART1_RXCNT() bfin_read32(UART1_RXCNT) |
| 116 | #define bfin_write_UART1_RXCNT(val) bfin_write32(UART1_RXCNT, val) |
| 117 | |
| 118 | |
| 119 | /* SPI0 Registers */ |
| 120 | |
| 121 | #define bfin_read_SPI0_CTL() bfin_read32(SPI0_CTL) |
| 122 | #define bfin_write_SPI0_CTL(val) bfin_write32(SPI0_CTL, val) |
| 123 | #define bfin_read_SPI0_RXCTL() bfin_read32(SPI0_RXCTL) |
| 124 | #define bfin_write_SPI0_RXCTL(val) bfin_write32(SPI0_RXCTL, val) |
| 125 | #define bfin_read_SPI0_TXCTL() bfin_read32(SPI0_TXCTL) |
| 126 | #define bfin_write_SPI0_TXCTL(val) bfin_write32(SPI0_TXCTL, val) |
| 127 | #define bfin_read_SPI0_CLK() bfin_read32(SPI0_CLK) |
| 128 | #define bfin_write_SPI0_CLK(val) bfin_write32(SPI0_CLK, val) |
| 129 | #define bfin_read_SPI0_DLY() bfin_read32(SPI0_DLY) |
| 130 | #define bfin_write_SPI0_DLY(val) bfin_write32(SPI0_DLY, val) |
| 131 | #define bfin_read_SPI0_SLVSEL() bfin_read32(SPI0_SLVSEL) |
| 132 | #define bfin_write_SPI0_SLVSEL(val) bfin_write32(SPI0_SLVSEL, val) |
| 133 | #define bfin_read_SPI0_RWC() bfin_read32(SPI0_RWC) |
| 134 | #define bfin_write_SPI0_RWC(val) bfin_write32(SPI0_RWC, val) |
| 135 | #define bfin_read_SPI0_RWCR() bfin_read32(SPI0_RWCR) |
| 136 | #define bfin_write_SPI0_RWCR(val) bfin_write32(SPI0_RWCR, val) |
| 137 | #define bfin_read_SPI0_TWC() bfin_read32(SPI0_TWC) |
| 138 | #define bfin_write_SPI0_TWC(val) bfin_write32(SPI0_TWC, val) |
| 139 | #define bfin_read_SPI0_TWCR() bfin_read32(SPI0_TWCR) |
| 140 | #define bfin_write_SPI0_TWCR(val) bfin_write32(SPI0_TWCR, val) |
| 141 | #define bfin_read_SPI0_IMSK() bfin_read32(SPI0_IMSK) |
| 142 | #define bfin_write_SPI0_IMSK(val) bfin_write32(SPI0_IMSK, val) |
| 143 | #define bfin_read_SPI0_IMSK_CLR() bfin_read32(SPI0_IMSK_CLR) |
| 144 | #define bfin_write_SPI0_IMSK_CLR(val) bfin_write32(SPI0_IMSK_CLR, val) |
| 145 | #define bfin_read_SPI0_IMSK_SET() bfin_read32(SPI0_IMSK_SET) |
| 146 | #define bfin_write_SPI0_IMSK_SET(val) bfin_write32(SPI0_IMSK_SET, val) |
| 147 | #define bfin_read_SPI0_STAT() bfin_read32(SPI0_STAT) |
| 148 | #define bfin_write_SPI0_STAT(val) bfin_write32(SPI0_STAT, val) |
| 149 | #define bfin_read_SPI0_ILAT() bfin_read32(SPI0_ILAT) |
| 150 | #define bfin_write_SPI0_ILAT(val) bfin_write32(SPI0_ILAT, val) |
| 151 | #define bfin_read_SPI0_ILAT_CLR() bfin_read32(SPI0_ILAT_CLR) |
| 152 | #define bfin_write_SPI0_ILAT_CLR(val) bfin_write32(SPI0_ILAT_CLR, val) |
| 153 | #define bfin_read_SPI0_RFIFO() bfin_read32(SPI0_RFIFO) |
| 154 | #define bfin_write_SPI0_RFIFO(val) bfin_write32(SPI0_RFIFO, val) |
| 155 | #define bfin_read_SPI0_TFIFO() bfin_read32(SPI0_TFIFO) |
| 156 | #define bfin_write_SPI0_TFIFO(val) bfin_write32(SPI0_TFIFO, val) |
| 157 | |
| 158 | /* SPI1 Registers */ |
| 159 | |
| 160 | #define bfin_read_SPI1_CTL() bfin_read32(SPI1_CTL) |
| 161 | #define bfin_write_SPI1_CTL(val) bfin_write32(SPI1_CTL, val) |
| 162 | #define bfin_read_SPI1_RXCTL() bfin_read32(SPI1_RXCTL) |
| 163 | #define bfin_write_SPI1_RXCTL(val) bfin_write32(SPI1_RXCTL, val) |
| 164 | #define bfin_read_SPI1_TXCTL() bfin_read32(SPI1_TXCTL) |
| 165 | #define bfin_write_SPI1_TXCTL(val) bfin_write32(SPI1_TXCTL, val) |
| 166 | #define bfin_read_SPI1_CLK() bfin_read32(SPI1_CLK) |
| 167 | #define bfin_write_SPI1_CLK(val) bfin_write32(SPI1_CLK, val) |
| 168 | #define bfin_read_SPI1_DLY() bfin_read32(SPI1_DLY) |
| 169 | #define bfin_write_SPI1_DLY(val) bfin_write32(SPI1_DLY, val) |
| 170 | #define bfin_read_SPI1_SLVSEL() bfin_read32(SPI1_SLVSEL) |
| 171 | #define bfin_write_SPI1_SLVSEL(val) bfin_write32(SPI1_SLVSEL, val) |
| 172 | #define bfin_read_SPI1_RWC() bfin_read32(SPI1_RWC) |
| 173 | #define bfin_write_SPI1_RWC(val) bfin_write32(SPI1_RWC, val) |
| 174 | #define bfin_read_SPI1_RWCR() bfin_read32(SPI1_RWCR) |
| 175 | #define bfin_write_SPI1_RWCR(val) bfin_write32(SPI1_RWCR, val) |
| 176 | #define bfin_read_SPI1_TWC() bfin_read32(SPI1_TWC) |
| 177 | #define bfin_write_SPI1_TWC(val) bfin_write32(SPI1_TWC, val) |
| 178 | #define bfin_read_SPI1_TWCR() bfin_read32(SPI1_TWCR) |
| 179 | #define bfin_write_SPI1_TWCR(val) bfin_write32(SPI1_TWCR, val) |
| 180 | #define bfin_read_SPI1_IMSK() bfin_read32(SPI1_IMSK) |
| 181 | #define bfin_write_SPI1_IMSK(val) bfin_write32(SPI1_IMSK, val) |
| 182 | #define bfin_read_SPI1_IMSK_CLR() bfin_read32(SPI1_IMSK_CLR) |
| 183 | #define bfin_write_SPI1_IMSK_CLR(val) bfin_write32(SPI1_IMSK_CLR, val) |
| 184 | #define bfin_read_SPI1_IMSK_SET() bfin_read32(SPI1_IMSK_SET) |
| 185 | #define bfin_write_SPI1_IMSK_SET(val) bfin_write32(SPI1_IMSK_SET, val) |
| 186 | #define bfin_read_SPI1_STAT() bfin_read32(SPI1_STAT) |
| 187 | #define bfin_write_SPI1_STAT(val) bfin_write32(SPI1_STAT, val) |
| 188 | #define bfin_read_SPI1_ILAT() bfin_read32(SPI1_ILAT) |
| 189 | #define bfin_write_SPI1_ILAT(val) bfin_write32(SPI1_ILAT, val) |
| 190 | #define bfin_read_SPI1_ILAT_CLR() bfin_read32(SPI1_ILAT_CLR) |
| 191 | #define bfin_write_SPI1_ILAT_CLR(val) bfin_write32(SPI1_ILAT_CLR, val) |
| 192 | #define bfin_read_SPI1_RFIFO() bfin_read32(SPI1_RFIFO) |
| 193 | #define bfin_write_SPI1_RFIFO(val) bfin_write32(SPI1_RFIFO, val) |
| 194 | #define bfin_read_SPI1_TFIFO() bfin_read32(SPI1_TFIFO) |
| 195 | #define bfin_write_SPI1_TFIFO(val) bfin_write32(SPI1_TFIFO, val) |
| 196 | |
| 197 | /* Timer 0-7 registers */ |
| 198 | #define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG) |
| 199 | #define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val) |
| 200 | #define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER) |
| 201 | #define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val) |
| 202 | #define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD) |
| 203 | #define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val) |
| 204 | #define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH) |
| 205 | #define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val) |
| 206 | #define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG) |
| 207 | #define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val) |
| 208 | #define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER) |
| 209 | #define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val) |
| 210 | #define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD) |
| 211 | #define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val) |
| 212 | #define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH) |
| 213 | #define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val) |
| 214 | #define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG) |
| 215 | #define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val) |
| 216 | #define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER) |
| 217 | #define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val) |
| 218 | #define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD) |
| 219 | #define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val) |
| 220 | #define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH) |
| 221 | #define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val) |
| 222 | #define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG) |
| 223 | #define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val) |
| 224 | #define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER) |
| 225 | #define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val) |
| 226 | #define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD) |
| 227 | #define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val) |
| 228 | #define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH) |
| 229 | #define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val) |
| 230 | #define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG) |
| 231 | #define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val) |
| 232 | #define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER) |
| 233 | #define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val) |
| 234 | #define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD) |
| 235 | #define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val) |
| 236 | #define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH) |
| 237 | #define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val) |
| 238 | #define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG) |
| 239 | #define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val) |
| 240 | #define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER) |
| 241 | #define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val) |
| 242 | #define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD) |
| 243 | #define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val) |
| 244 | #define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH) |
| 245 | #define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val) |
| 246 | #define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG) |
| 247 | #define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val) |
| 248 | #define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER) |
| 249 | #define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val) |
| 250 | #define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD) |
| 251 | #define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val) |
| 252 | #define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH) |
| 253 | #define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val) |
| 254 | #define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG) |
| 255 | #define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val) |
| 256 | #define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER) |
| 257 | #define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val) |
| 258 | #define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD) |
| 259 | #define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val) |
| 260 | #define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH) |
| 261 | #define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val) |
| 262 | |
| 263 | |
| 264 | |
| 265 | |
| 266 | /* Two Wire Interface Registers (TWI0) */ |
| 267 | |
| 268 | /* SPORT1 Registers */ |
| 269 | |
| 270 | |
| 271 | /* SMC Registers */ |
| 272 | #define bfin_read_SMC_GCTL() bfin_read32(SMC_GCTL) |
| 273 | #define bfin_write_SMC_GCTL(val) bfin_write32(SMC_GCTL, val) |
| 274 | #define bfin_read_SMC_GSTAT() bfin_read32(SMC_GSTAT) |
| 275 | #define bfin_read_SMC_B0CTL() bfin_read32(SMC_B0CTL) |
| 276 | #define bfin_write_SMC_B0CTL(val) bfin_write32(SMC_B0CTL, val) |
| 277 | #define bfin_read_SMC_B0TIM() bfin_read32(SMC_B0TIM) |
| 278 | #define bfin_write_SMC_B0TIM(val) bfin_write32(SMC_B0TIM, val) |
| 279 | #define bfin_read_SMC_B0ETIM() bfin_read32(SMC_B0ETIM) |
| 280 | #define bfin_write_SMC_B0ETIM(val) bfin_write32(SMC_B0ETIM, val) |
| 281 | #define bfin_read_SMC_B1CTL() bfin_read32(SMC_B1CTL) |
| 282 | #define bfin_write_SMC_B1CTL(val) bfin_write32(SMC_B1CTL, val) |
| 283 | #define bfin_read_SMC_B1TIM() bfin_read32(SMC_B1TIM) |
| 284 | #define bfin_write_SMC_B1TIM(val) bfin_write32(SMC_B1TIM, val) |
| 285 | #define bfin_read_SMC_B1ETIM() bfin_read32(SMC_B1ETIM) |
| 286 | #define bfin_write_SMC_B1ETIM(val) bfin_write32(SMC_B1ETIM, val) |
| 287 | #define bfin_read_SMC_B2CTL() bfin_read32(SMC_B2CTL) |
| 288 | #define bfin_write_SMC_B2CTL(val) bfin_write32(SMC_B2CTL, val) |
| 289 | #define bfin_read_SMC_B2TIM() bfin_read32(SMC_B2TIM) |
| 290 | #define bfin_write_SMC_B2TIM(val) bfin_write32(SMC_B2TIM, val) |
| 291 | #define bfin_read_SMC_B2ETIM() bfin_read32(SMC_B2ETIM) |
| 292 | #define bfin_write_SMC_B2ETIM(val) bfin_write32(SMC_B2ETIM, val) |
| 293 | #define bfin_read_SMC_B3CTL() bfin_read32(SMC_B3CTL) |
| 294 | #define bfin_write_SMC_B3CTL(val) bfin_write32(SMC_B3CTL, val) |
| 295 | #define bfin_read_SMC_B3TIM() bfin_read32(SMC_B3TIM) |
| 296 | #define bfin_write_SMC_B3TIM(val) bfin_write32(SMC_B3TIM, val) |
| 297 | #define bfin_read_SMC_B3ETIM() bfin_read32(SMC_B3ETIM) |
| 298 | #define bfin_write_SMC_B3ETIM(val) bfin_write32(SMC_B3ETIM, val) |
| 299 | |
| 300 | /* DDR2 Memory Control Registers */ |
| Sonic Zhang | 8bf7135 | 2012-05-15 13:04:24 +0800 | [diff] [blame] | 301 | #define bfin_read_DMC0_CFG() bfin_read32(DMC0_CFG) |
| 302 | #define bfin_write_DMC0_CFG(val) bfin_write32(DMC0_CFG, val) |
| 303 | #define bfin_read_DMC0_TR0() bfin_read32(DMC0_TR0) |
| 304 | #define bfin_write_DMC0_TR0(val) bfin_write32(DMC0_TR0, val) |
| 305 | #define bfin_read_DMC0_TR1() bfin_read32(DMC0_TR1) |
| 306 | #define bfin_write_DMC0_TR1(val) bfin_write32(DMC0_TR1, val) |
| 307 | #define bfin_read_DMC0_TR2() bfin_read32(DMC0_TR2) |
| 308 | #define bfin_write_DMC0_TR2(val) bfin_write32(DMC0_TR2, val) |
| 309 | #define bfin_read_DMC0_MR() bfin_read32(DMC0_MR) |
| 310 | #define bfin_write_DMC0_MR(val) bfin_write32(DMC0_MR, val) |
| 311 | #define bfin_read_DMC0_EMR1() bfin_read32(DMC0_EMR1) |
| 312 | #define bfin_write_DMC0_EMR1(val) bfin_write32(DMC0_EMR1, val) |
| 313 | #define bfin_read_DMC0_CTL() bfin_read32(DMC0_CTL) |
| 314 | #define bfin_write_DMC0_CTL(val) bfin_write32(DMC0_CTL, val) |
| Sonic Zhang | c83a917 | 2012-11-29 11:41:17 +0800 | [diff] [blame] | 315 | #define bfin_read_DMC0_EFFCTL() bfin_read32(DMC0_EFFCTL) |
| 316 | #define bfin_write_DMC0_EFFCTL(val) bfin_write32(DMC0_EFFCTL, val) |
| Sonic Zhang | 8bf7135 | 2012-05-15 13:04:24 +0800 | [diff] [blame] | 317 | #define bfin_read_DMC0_STAT() bfin_read32(DMC0_STAT) |
| 318 | #define bfin_write_DMC0_STAT(val) bfin_write32(DMC0_STAT, val) |
| 319 | #define bfin_read_DMC0_DLLCTL() bfin_read32(DMC0_DLLCTL) |
| 320 | #define bfin_write_DMC0_DLLCTL(val) bfin_write32(DMC0_DLLCTL, val) |
| Sonic Zhang | 22a8262 | 2012-05-16 17:24:33 +0800 | [diff] [blame] | 321 | |
| 322 | /* DDR BankRead and Write Count Registers */ |
| 323 | |
| 324 | |
| 325 | /* DMA Channel 0 Registers */ |
| 326 | |
| 327 | #define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR) |
| 328 | #define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR, val) |
| 329 | #define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR) |
| 330 | #define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val) |
| 331 | #define bfin_read_DMA0_CONFIG() bfin_read32(DMA0_CONFIG) |
| 332 | #define bfin_write_DMA0_CONFIG(val) bfin_write32(DMA0_CONFIG, val) |
| 333 | #define bfin_read_DMA0_X_COUNT() bfin_read32(DMA0_X_COUNT) |
| 334 | #define bfin_write_DMA0_X_COUNT(val) bfin_write32(DMA0_X_COUNT, val) |
| 335 | #define bfin_read_DMA0_X_MODIFY() bfin_read32(DMA0_X_MODIFY) |
| 336 | #define bfin_write_DMA0_X_MODIFY(val) bfin_write32(DMA0_X_MODIFY, val) |
| 337 | #define bfin_read_DMA0_Y_COUNT() bfin_read32(DMA0_Y_COUNT) |
| 338 | #define bfin_write_DMA0_Y_COUNT(val) bfin_write32(DMA0_Y_COUNT, val) |
| 339 | #define bfin_read_DMA0_Y_MODIFY() bfin_read32(DMA0_Y_MODIFY) |
| 340 | #define bfin_write_DMA0_Y_MODIFY(val) bfin_write32(DMA0_Y_MODIFY, val) |
| 341 | #define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR) |
| 342 | #define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR, val) |
| 343 | #define bfin_read_DMA0_PREV_DESC_PTR() bfin_read32(DMA0_PREV_DESC_PTR) |
| 344 | #define bfin_write_DMA0_PREV_DESC_PTR(val) bfin_write32(DMA0_PREV_DESC_PTR, val) |
| 345 | #define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR) |
| 346 | #define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val) |
| 347 | #define bfin_read_DMA0_IRQ_STATUS() bfin_read32(DMA0_IRQ_STATUS) |
| 348 | #define bfin_write_DMA0_IRQ_STATUS(val) bfin_write32(DMA0_IRQ_STATUS, val) |
| 349 | #define bfin_read_DMA0_CURR_X_COUNT() bfin_read32(DMA0_CURR_X_COUNT) |
| 350 | #define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write32(DMA0_CURR_X_COUNT, val) |
| 351 | #define bfin_read_DMA0_CURR_Y_COUNT() bfin_read32(DMA0_CURR_Y_COUNT) |
| 352 | #define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write32(DMA0_CURR_Y_COUNT, val) |
| 353 | #define bfin_read_DMA0_BWL_COUNT() bfin_read32(DMA0_BWL_COUNT) |
| 354 | #define bfin_write_DMA0_BWL_COUNT(val) bfin_write32(DMA0_BWL_COUNT, val) |
| 355 | #define bfin_read_DMA0_CURR_BWL_COUNT() bfin_read32(DMA0_CURR_BWL_COUNT) |
| 356 | #define bfin_write_DMA0_CURR_BWL_COUNT(val) bfin_write32(DMA0_CURR_BWL_COUNT, val) |
| 357 | #define bfin_read_DMA0_BWM_COUNT() bfin_read32(DMA0_BWM_COUNT) |
| 358 | #define bfin_write_DMA0_BWM_COUNT(val) bfin_write32(DMA0_BWM_COUNT, val) |
| 359 | #define bfin_read_DMA0_CURR_BWM_COUNT() bfin_read32(DMA0_CURR_BWM_COUNT) |
| 360 | #define bfin_write_DMA0_CURR_BWM_COUNT(val) bfin_write32(DMA0_CURR_BWM_COUNT, val) |
| 361 | |
| 362 | /* DMA Channel 1 Registers */ |
| 363 | |
| 364 | #define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR) |
| 365 | #define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR, val) |
| 366 | #define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR) |
| 367 | #define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val) |
| 368 | #define bfin_read_DMA1_CONFIG() bfin_read32(DMA1_CONFIG) |
| 369 | #define bfin_write_DMA1_CONFIG(val) bfin_write32(DMA1_CONFIG, val) |
| 370 | #define bfin_read_DMA1_X_COUNT() bfin_read32(DMA1_X_COUNT) |
| 371 | #define bfin_write_DMA1_X_COUNT(val) bfin_write32(DMA1_X_COUNT, val) |
| 372 | #define bfin_read_DMA1_X_MODIFY() bfin_read32(DMA1_X_MODIFY) |
| 373 | #define bfin_write_DMA1_X_MODIFY(val) bfin_write32(DMA1_X_MODIFY, val) |
| 374 | #define bfin_read_DMA1_Y_COUNT() bfin_read32(DMA1_Y_COUNT) |
| 375 | #define bfin_write_DMA1_Y_COUNT(val) bfin_write32(DMA1_Y_COUNT, val) |
| 376 | #define bfin_read_DMA1_Y_MODIFY() bfin_read32(DMA1_Y_MODIFY) |
| 377 | #define bfin_write_DMA1_Y_MODIFY(val) bfin_write32(DMA1_Y_MODIFY, val) |
| 378 | #define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR) |
| 379 | #define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR, val) |
| 380 | #define bfin_read_DMA1_PREV_DESC_PTR() bfin_read32(DMA1_PREV_DESC_PTR) |
| 381 | #define bfin_write_DMA1_PREV_DESC_PTR(val) bfin_write32(DMA1_PREV_DESC_PTR, val) |
| 382 | #define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR) |
| 383 | #define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR, val) |
| 384 | #define bfin_read_DMA1_IRQ_STATUS() bfin_read32(DMA1_IRQ_STATUS) |
| 385 | #define bfin_write_DMA1_IRQ_STATUS(val) bfin_write32(DMA1_IRQ_STATUS, val) |
| 386 | #define bfin_read_DMA1_CURR_X_COUNT() bfin_read32(DMA1_CURR_X_COUNT) |
| 387 | #define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write32(DMA1_CURR_X_COUNT, val) |
| 388 | #define bfin_read_DMA1_CURR_Y_COUNT() bfin_read32(DMA1_CURR_Y_COUNT) |
| 389 | #define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write32(DMA1_CURR_Y_COUNT, val) |
| 390 | #define bfin_read_DMA1_BWL_COUNT() bfin_read32(DMA1_BWL_COUNT) |
| 391 | #define bfin_write_DMA1_BWL_COUNT(val) bfin_write32(DMA1_BWL_COUNT, val) |
| 392 | #define bfin_read_DMA1_CURR_BWL_COUNT() bfin_read32(DMA1_CURR_BWL_COUNT) |
| 393 | #define bfin_write_DMA1_CURR_BWL_COUNT(val) bfin_write32(DMA1_CURR_BWL_COUNT, val) |
| 394 | #define bfin_read_DMA1_BWM_COUNT() bfin_read32(DMA1_BWM_COUNT) |
| 395 | #define bfin_write_DMA1_BWM_COUNT(val) bfin_write32(DMA1_BWM_COUNT, val) |
| 396 | #define bfin_read_DMA1_CURR_BWM_COUNT() bfin_read32(DMA1_CURR_BWM_COUNT) |
| 397 | #define bfin_write_DMA1_CURR_BWM_COUNT(val) bfin_write32(DMA1_CURR_BWM_COUNT, val) |
| 398 | |
| 399 | /* DMA Channel 2 Registers */ |
| 400 | |
| 401 | #define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR) |
| 402 | #define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR, val) |
| 403 | #define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR) |
| 404 | #define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR, val) |
| 405 | #define bfin_read_DMA2_CONFIG() bfin_read32(DMA2_CONFIG) |
| 406 | #define bfin_write_DMA2_CONFIG(val) bfin_write32(DMA2_CONFIG, val) |
| 407 | #define bfin_read_DMA2_X_COUNT() bfin_read32(DMA2_X_COUNT) |
| 408 | #define bfin_write_DMA2_X_COUNT(val) bfin_write32(DMA2_X_COUNT, val) |
| 409 | #define bfin_read_DMA2_X_MODIFY() bfin_read32(DMA2_X_MODIFY) |
| 410 | #define bfin_write_DMA2_X_MODIFY(val) bfin_write32(DMA2_X_MODIFY, val) |
| 411 | #define bfin_read_DMA2_Y_COUNT() bfin_read32(DMA2_Y_COUNT) |
| 412 | #define bfin_write_DMA2_Y_COUNT(val) bfin_write32(DMA2_Y_COUNT, val) |
| 413 | #define bfin_read_DMA2_Y_MODIFY() bfin_read32(DMA2_Y_MODIFY) |
| 414 | #define bfin_write_DMA2_Y_MODIFY(val) bfin_write32(DMA2_Y_MODIFY, val) |
| 415 | #define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR) |
| 416 | #define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR, val) |
| 417 | #define bfin_read_DMA2_PREV_DESC_PTR() bfin_read32(DMA2_PREV_DESC_PTR) |
| 418 | #define bfin_write_DMA2_PREV_DESC_PTR(val) bfin_write32(DMA2_PREV_DESC_PTR, val) |
| 419 | #define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR) |
| 420 | #define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR, val) |
| 421 | #define bfin_read_DMA2_IRQ_STATUS() bfin_read32(DMA2_IRQ_STATUS) |
| 422 | #define bfin_write_DMA2_IRQ_STATUS(val) bfin_write32(DMA2_IRQ_STATUS, val) |
| 423 | #define bfin_read_DMA2_CURR_X_COUNT() bfin_read32(DMA2_CURR_X_COUNT) |
| 424 | #define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write32(DMA2_CURR_X_COUNT, val) |
| 425 | #define bfin_read_DMA2_CURR_Y_COUNT() bfin_read32(DMA2_CURR_Y_COUNT) |
| 426 | #define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write32(DMA2_CURR_Y_COUNT, val) |
| 427 | #define bfin_read_DMA2_BWL_COUNT() bfin_read32(DMA2_BWL_COUNT) |
| 428 | #define bfin_write_DMA2_BWL_COUNT(val) bfin_write32(DMA2_BWL_COUNT, val) |
| 429 | #define bfin_read_DMA2_CURR_BWL_COUNT() bfin_read32(DMA2_CURR_BWL_COUNT) |
| 430 | #define bfin_write_DMA2_CURR_BWL_COUNT(val) bfin_write32(DMA2_CURR_BWL_COUNT, val) |
| 431 | #define bfin_read_DMA2_BWM_COUNT() bfin_read32(DMA2_BWM_COUNT) |
| 432 | #define bfin_write_DMA2_BWM_COUNT(val) bfin_write32(DMA2_BWM_COUNT, val) |
| 433 | #define bfin_read_DMA2_CURR_BWM_COUNT() bfin_read32(DMA2_CURR_BWM_COUNT) |
| 434 | #define bfin_write_DMA2_CURR_BWM_COUNT(val) bfin_write32(DMA2_CURR_BWM_COUNT, val) |
| 435 | |
| 436 | /* DMA Channel 3 Registers */ |
| 437 | |
| 438 | #define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR) |
| 439 | #define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR, val) |
| 440 | #define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR) |
| 441 | #define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val) |
| 442 | #define bfin_read_DMA3_CONFIG() bfin_read32(DMA3_CONFIG) |
| 443 | #define bfin_write_DMA3_CONFIG(val) bfin_write32(DMA3_CONFIG, val) |
| 444 | #define bfin_read_DMA3_X_COUNT() bfin_read32(DMA3_X_COUNT) |
| 445 | #define bfin_write_DMA3_X_COUNT(val) bfin_write32(DMA3_X_COUNT, val) |
| 446 | #define bfin_read_DMA3_X_MODIFY() bfin_read32(DMA3_X_MODIFY) |
| 447 | #define bfin_write_DMA3_X_MODIFY(val) bfin_write32(DMA3_X_MODIFY, val) |
| 448 | #define bfin_read_DMA3_Y_COUNT() bfin_read32(DMA3_Y_COUNT) |
| 449 | #define bfin_write_DMA3_Y_COUNT(val) bfin_write32(DMA3_Y_COUNT, val) |
| 450 | #define bfin_read_DMA3_Y_MODIFY() bfin_read32(DMA3_Y_MODIFY) |
| 451 | #define bfin_write_DMA3_Y_MODIFY(val) bfin_write32(DMA3_Y_MODIFY, val) |
| 452 | #define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR) |
| 453 | #define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR, val) |
| 454 | #define bfin_read_DMA3_PREV_DESC_PTR() bfin_read32(DMA3_PREV_DESC_PTR) |
| 455 | #define bfin_write_DMA3_PREV_DESC_PTR(val) bfin_write32(DMA3_PREV_DESC_PTR, val) |
| 456 | #define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR) |
| 457 | #define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR, val) |
| 458 | #define bfin_read_DMA3_IRQ_STATUS() bfin_read32(DMA3_IRQ_STATUS) |
| 459 | #define bfin_write_DMA3_IRQ_STATUS(val) bfin_write32(DMA3_IRQ_STATUS, val) |
| 460 | #define bfin_read_DMA3_CURR_X_COUNT() bfin_read32(DMA3_CURR_X_COUNT) |
| 461 | #define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write32(DMA3_CURR_X_COUNT, val) |
| 462 | #define bfin_read_DMA3_CURR_Y_COUNT() bfin_read32(DMA3_CURR_Y_COUNT) |
| 463 | #define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write32(DMA3_CURR_Y_COUNT, val) |
| 464 | #define bfin_read_DMA3_BWL_COUNT() bfin_read32(DMA3_BWL_COUNT) |
| 465 | #define bfin_write_DMA3_BWL_COUNT(val) bfin_write32(DMA3_BWL_COUNT, val) |
| 466 | #define bfin_read_DMA3_CURR_BWL_COUNT() bfin_read32(DMA3_CURR_BWL_COUNT) |
| 467 | #define bfin_write_DMA3_CURR_BWL_COUNT(val) bfin_write32(DMA3_CURR_BWL_COUNT, val) |
| 468 | #define bfin_read_DMA3_BWM_COUNT() bfin_read32(DMA3_BWM_COUNT) |
| 469 | #define bfin_write_DMA3_BWM_COUNT(val) bfin_write32(DMA3_BWM_COUNT, val) |
| 470 | #define bfin_read_DMA3_CURR_BWM_COUNT() bfin_read32(DMA3_CURR_BWM_COUNT) |
| 471 | #define bfin_write_DMA3_CURR_BWM_COUNT(val) bfin_write32(DMA3_CURR_BWM_COUNT, val) |
| 472 | |
| 473 | /* DMA Channel 4 Registers */ |
| 474 | |
| 475 | #define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR) |
| 476 | #define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR, val) |
| 477 | #define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR) |
| 478 | #define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val) |
| 479 | #define bfin_read_DMA4_CONFIG() bfin_read32(DMA4_CONFIG) |
| 480 | #define bfin_write_DMA4_CONFIG(val) bfin_write32(DMA4_CONFIG, val) |
| 481 | #define bfin_read_DMA4_X_COUNT() bfin_read32(DMA4_X_COUNT) |
| 482 | #define bfin_write_DMA4_X_COUNT(val) bfin_write32(DMA4_X_COUNT, val) |
| 483 | #define bfin_read_DMA4_X_MODIFY() bfin_read32(DMA4_X_MODIFY) |
| 484 | #define bfin_write_DMA4_X_MODIFY(val) bfin_write32(DMA4_X_MODIFY, val) |
| 485 | #define bfin_read_DMA4_Y_COUNT() bfin_read32(DMA4_Y_COUNT) |
| 486 | #define bfin_write_DMA4_Y_COUNT(val) bfin_write32(DMA4_Y_COUNT, val) |
| 487 | #define bfin_read_DMA4_Y_MODIFY() bfin_read32(DMA4_Y_MODIFY) |
| 488 | #define bfin_write_DMA4_Y_MODIFY(val) bfin_write32(DMA4_Y_MODIFY, val) |
| 489 | #define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR) |
| 490 | #define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR, val) |
| 491 | #define bfin_read_DMA4_PREV_DESC_PTR() bfin_read32(DMA4_PREV_DESC_PTR) |
| 492 | #define bfin_write_DMA4_PREV_DESC_PTR(val) bfin_write32(DMA4_PREV_DESC_PTR, val) |
| 493 | #define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR) |
| 494 | #define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR, val) |
| 495 | #define bfin_read_DMA4_IRQ_STATUS() bfin_read32(DMA4_IRQ_STATUS) |
| 496 | #define bfin_write_DMA4_IRQ_STATUS(val) bfin_write32(DMA4_IRQ_STATUS, val) |
| 497 | #define bfin_read_DMA4_CURR_X_COUNT() bfin_read32(DMA4_CURR_X_COUNT) |
| 498 | #define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write32(DMA4_CURR_X_COUNT, val) |
| 499 | #define bfin_read_DMA4_CURR_Y_COUNT() bfin_read32(DMA4_CURR_Y_COUNT) |
| 500 | #define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write32(DMA4_CURR_Y_COUNT, val) |
| 501 | #define bfin_read_DMA4_BWL_COUNT() bfin_read32(DMA4_BWL_COUNT) |
| 502 | #define bfin_write_DMA4_BWL_COUNT(val) bfin_write32(DMA4_BWL_COUNT, val) |
| 503 | #define bfin_read_DMA4_CURR_BWL_COUNT() bfin_read32(DMA4_CURR_BWL_COUNT) |
| 504 | #define bfin_write_DMA4_CURR_BWL_COUNT(val) bfin_write32(DMA4_CURR_BWL_COUNT, val) |
| 505 | #define bfin_read_DMA4_BWM_COUNT() bfin_read32(DMA4_BWM_COUNT) |
| 506 | #define bfin_write_DMA4_BWM_COUNT(val) bfin_write32(DMA4_BWM_COUNT, val) |
| 507 | #define bfin_read_DMA4_CURR_BWM_COUNT() bfin_read32(DMA4_CURR_BWM_COUNT) |
| 508 | #define bfin_write_DMA4_CURR_BWM_COUNT(val) bfin_write32(DMA4_CURR_BWM_COUNT, val) |
| 509 | |
| 510 | /* DMA Channel 5 Registers */ |
| 511 | |
| 512 | #define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR) |
| 513 | #define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val) |
| 514 | #define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR) |
| 515 | #define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val) |
| 516 | #define bfin_read_DMA5_CONFIG() bfin_read32(DMA5_CONFIG) |
| 517 | #define bfin_write_DMA5_CONFIG(val) bfin_write32(DMA5_CONFIG, val) |
| 518 | #define bfin_read_DMA5_X_COUNT() bfin_read32(DMA5_X_COUNT) |
| 519 | #define bfin_write_DMA5_X_COUNT(val) bfin_write32(DMA5_X_COUNT, val) |
| 520 | #define bfin_read_DMA5_X_MODIFY() bfin_read32(DMA5_X_MODIFY) |
| 521 | #define bfin_write_DMA5_X_MODIFY(val) bfin_write32(DMA5_X_MODIFY, val) |
| 522 | #define bfin_read_DMA5_Y_COUNT() bfin_read32(DMA5_Y_COUNT) |
| 523 | #define bfin_write_DMA5_Y_COUNT(val) bfin_write32(DMA5_Y_COUNT, val) |
| 524 | #define bfin_read_DMA5_Y_MODIFY() bfin_read32(DMA5_Y_MODIFY) |
| 525 | #define bfin_write_DMA5_Y_MODIFY(val) bfin_write32(DMA5_Y_MODIFY, val) |
| 526 | #define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR) |
| 527 | #define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR, val) |
| 528 | #define bfin_read_DMA5_PREV_DESC_PTR() bfin_read32(DMA5_PREV_DESC_PTR) |
| 529 | #define bfin_write_DMA5_PREV_DESC_PTR(val) bfin_write32(DMA5_PREV_DESC_PTR, val) |
| 530 | #define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR) |
| 531 | #define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR, val) |
| 532 | #define bfin_read_DMA5_IRQ_STATUS() bfin_read32(DMA5_IRQ_STATUS) |
| 533 | #define bfin_write_DMA5_IRQ_STATUS(val) bfin_write32(DMA5_IRQ_STATUS, val) |
| 534 | #define bfin_read_DMA5_CURR_X_COUNT() bfin_read32(DMA5_CURR_X_COUNT) |
| 535 | #define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write32(DMA5_CURR_X_COUNT, val) |
| 536 | #define bfin_read_DMA5_CURR_Y_COUNT() bfin_read32(DMA5_CURR_Y_COUNT) |
| 537 | #define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write32(DMA5_CURR_Y_COUNT, val) |
| 538 | #define bfin_read_DMA5_BWL_COUNT() bfin_read32(DMA5_BWL_COUNT) |
| 539 | #define bfin_write_DMA5_BWL_COUNT(val) bfin_write32(DMA5_BWL_COUNT, val) |
| 540 | #define bfin_read_DMA5_CURR_BWL_COUNT() bfin_read32(DMA5_CURR_BWL_COUNT) |
| 541 | #define bfin_write_DMA5_CURR_BWL_COUNT(val) bfin_write32(DMA5_CURR_BWL_COUNT, val) |
| 542 | #define bfin_read_DMA5_BWM_COUNT() bfin_read32(DMA5_BWM_COUNT) |
| 543 | #define bfin_write_DMA5_BWM_COUNT(val) bfin_write32(DMA5_BWM_COUNT, val) |
| 544 | #define bfin_read_DMA5_CURR_BWM_COUNT() bfin_read32(DMA5_CURR_BWM_COUNT) |
| 545 | #define bfin_write_DMA5_CURR_BWM_COUNT(val) bfin_write32(DMA5_CURR_BWM_COUNT, val) |
| 546 | |
| 547 | /* DMA Channel 6 Registers */ |
| 548 | |
| 549 | #define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR) |
| 550 | #define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val) |
| 551 | #define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR) |
| 552 | #define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR, val) |
| 553 | #define bfin_read_DMA6_CONFIG() bfin_read32(DMA6_CONFIG) |
| 554 | #define bfin_write_DMA6_CONFIG(val) bfin_write32(DMA6_CONFIG, val) |
| 555 | #define bfin_read_DMA6_X_COUNT() bfin_read32(DMA6_X_COUNT) |
| 556 | #define bfin_write_DMA6_X_COUNT(val) bfin_write32(DMA6_X_COUNT, val) |
| 557 | #define bfin_read_DMA6_X_MODIFY() bfin_read32(DMA6_X_MODIFY) |
| 558 | #define bfin_write_DMA6_X_MODIFY(val) bfin_write32(DMA6_X_MODIFY, val) |
| 559 | #define bfin_read_DMA6_Y_COUNT() bfin_read32(DMA6_Y_COUNT) |
| 560 | #define bfin_write_DMA6_Y_COUNT(val) bfin_write32(DMA6_Y_COUNT, val) |
| 561 | #define bfin_read_DMA6_Y_MODIFY() bfin_read32(DMA6_Y_MODIFY) |
| 562 | #define bfin_write_DMA6_Y_MODIFY(val) bfin_write32(DMA6_Y_MODIFY, val) |
| 563 | #define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR) |
| 564 | #define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR, val) |
| 565 | #define bfin_read_DMA6_PREV_DESC_PTR() bfin_read32(DMA6_PREV_DESC_PTR) |
| 566 | #define bfin_write_DMA6_PREV_DESC_PTR(val) bfin_write32(DMA6_PREV_DESC_PTR, val) |
| 567 | #define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR) |
| 568 | #define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR, val) |
| 569 | #define bfin_read_DMA6_IRQ_STATUS() bfin_read32(DMA6_IRQ_STATUS) |
| 570 | #define bfin_write_DMA6_IRQ_STATUS(val) bfin_write32(DMA6_IRQ_STATUS, val) |
| 571 | #define bfin_read_DMA6_CURR_X_COUNT() bfin_read32(DMA6_CURR_X_COUNT) |
| 572 | #define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write32(DMA6_CURR_X_COUNT, val) |
| 573 | #define bfin_read_DMA6_CURR_Y_COUNT() bfin_read32(DMA6_CURR_Y_COUNT) |
| 574 | #define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write32(DMA6_CURR_Y_COUNT, val) |
| 575 | #define bfin_read_DMA6_BWL_COUNT() bfin_read32(DMA6_BWL_COUNT) |
| 576 | #define bfin_write_DMA6_BWL_COUNT(val) bfin_write32(DMA6_BWL_COUNT, val) |
| 577 | #define bfin_read_DMA6_CURR_BWL_COUNT() bfin_read32(DMA6_CURR_BWL_COUNT) |
| 578 | #define bfin_write_DMA6_CURR_BWL_COUNT(val) bfin_write32(DMA6_CURR_BWL_COUNT, val) |
| 579 | #define bfin_read_DMA6_BWM_COUNT() bfin_read32(DMA6_BWM_COUNT) |
| 580 | #define bfin_write_DMA6_BWM_COUNT(val) bfin_write32(DMA6_BWM_COUNT, val) |
| 581 | #define bfin_read_DMA6_CURR_BWM_COUNT() bfin_read32(DMA6_CURR_BWM_COUNT) |
| 582 | #define bfin_write_DMA6_CURR_BWM_COUNT(val) bfin_write32(DMA6_CURR_BWM_COUNT, val) |
| 583 | |
| 584 | /* DMA Channel 7 Registers */ |
| 585 | |
| 586 | #define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR) |
| 587 | #define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR, val) |
| 588 | #define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR) |
| 589 | #define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR, val) |
| 590 | #define bfin_read_DMA7_CONFIG() bfin_read32(DMA7_CONFIG) |
| 591 | #define bfin_write_DMA7_CONFIG(val) bfin_write32(DMA7_CONFIG, val) |
| 592 | #define bfin_read_DMA7_X_COUNT() bfin_read32(DMA7_X_COUNT) |
| 593 | #define bfin_write_DMA7_X_COUNT(val) bfin_write32(DMA7_X_COUNT, val) |
| 594 | #define bfin_read_DMA7_X_MODIFY() bfin_read32(DMA7_X_MODIFY) |
| 595 | #define bfin_write_DMA7_X_MODIFY(val) bfin_write32(DMA7_X_MODIFY, val) |
| 596 | #define bfin_read_DMA7_Y_COUNT() bfin_read32(DMA7_Y_COUNT) |
| 597 | #define bfin_write_DMA7_Y_COUNT(val) bfin_write32(DMA7_Y_COUNT, val) |
| 598 | #define bfin_read_DMA7_Y_MODIFY() bfin_read32(DMA7_Y_MODIFY) |
| 599 | #define bfin_write_DMA7_Y_MODIFY(val) bfin_write32(DMA7_Y_MODIFY, val) |
| 600 | #define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR) |
| 601 | #define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR, val) |
| 602 | #define bfin_read_DMA7_PREV_DESC_PTR() bfin_read32(DMA7_PREV_DESC_PTR) |
| 603 | #define bfin_write_DMA7_PREV_DESC_PTR(val) bfin_write32(DMA7_PREV_DESC_PTR, val) |
| 604 | #define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR) |
| 605 | #define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR, val) |
| 606 | #define bfin_read_DMA7_IRQ_STATUS() bfin_read32(DMA7_IRQ_STATUS) |
| 607 | #define bfin_write_DMA7_IRQ_STATUS(val) bfin_write32(DMA7_IRQ_STATUS, val) |
| 608 | #define bfin_read_DMA7_CURR_X_COUNT() bfin_read32(DMA7_CURR_X_COUNT) |
| 609 | #define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write32(DMA7_CURR_X_COUNT, val) |
| 610 | #define bfin_read_DMA7_CURR_Y_COUNT() bfin_read32(DMA7_CURR_Y_COUNT) |
| 611 | #define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write32(DMA7_CURR_Y_COUNT, val) |
| 612 | #define bfin_read_DMA7_BWL_COUNT() bfin_read32(DMA7_BWL_COUNT) |
| 613 | #define bfin_write_DMA7_BWL_COUNT(val) bfin_write32(DMA7_BWL_COUNT, val) |
| 614 | #define bfin_read_DMA7_CURR_BWL_COUNT() bfin_read32(DMA7_CURR_BWL_COUNT) |
| 615 | #define bfin_write_DMA7_CURR_BWL_COUNT(val) bfin_write32(DMA7_CURR_BWL_COUNT, val) |
| 616 | #define bfin_read_DMA7_BWM_COUNT() bfin_read32(DMA7_BWM_COUNT) |
| 617 | #define bfin_write_DMA7_BWM_COUNT(val) bfin_write32(DMA7_BWM_COUNT, val) |
| 618 | #define bfin_read_DMA7_CURR_BWM_COUNT() bfin_read32(DMA7_CURR_BWM_COUNT) |
| 619 | #define bfin_write_DMA7_CURR_BWM_COUNT(val) bfin_write32(DMA7_CURR_BWM_COUNT, val) |
| 620 | |
| 621 | /* DMA Channel 8 Registers */ |
| 622 | |
| 623 | #define bfin_read_DMA8_NEXT_DESC_PTR() bfin_read32(DMA8_NEXT_DESC_PTR) |
| 624 | #define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR, val) |
| 625 | #define bfin_read_DMA8_START_ADDR() bfin_read32(DMA8_START_ADDR) |
| 626 | #define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR, val) |
| 627 | #define bfin_read_DMA8_CONFIG() bfin_read32(DMA8_CONFIG) |
| 628 | #define bfin_write_DMA8_CONFIG(val) bfin_write32(DMA8_CONFIG, val) |
| 629 | #define bfin_read_DMA8_X_COUNT() bfin_read32(DMA8_X_COUNT) |
| 630 | #define bfin_write_DMA8_X_COUNT(val) bfin_write32(DMA8_X_COUNT, val) |
| 631 | #define bfin_read_DMA8_X_MODIFY() bfin_read32(DMA8_X_MODIFY) |
| 632 | #define bfin_write_DMA8_X_MODIFY(val) bfin_write32(DMA8_X_MODIFY, val) |
| 633 | #define bfin_read_DMA8_Y_COUNT() bfin_read32(DMA8_Y_COUNT) |
| 634 | #define bfin_write_DMA8_Y_COUNT(val) bfin_write32(DMA8_Y_COUNT, val) |
| 635 | #define bfin_read_DMA8_Y_MODIFY() bfin_read32(DMA8_Y_MODIFY) |
| 636 | #define bfin_write_DMA8_Y_MODIFY(val) bfin_write32(DMA8_Y_MODIFY, val) |
| 637 | #define bfin_read_DMA8_CURR_DESC_PTR() bfin_read32(DMA8_CURR_DESC_PTR) |
| 638 | #define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR, val) |
| 639 | #define bfin_read_DMA8_PREV_DESC_PTR() bfin_read32(DMA8_PREV_DESC_PTR) |
| 640 | #define bfin_write_DMA8_PREV_DESC_PTR(val) bfin_write32(DMA8_PREV_DESC_PTR, val) |
| 641 | #define bfin_read_DMA8_CURR_ADDR() bfin_read32(DMA8_CURR_ADDR) |
| 642 | #define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR, val) |
| 643 | #define bfin_read_DMA8_IRQ_STATUS() bfin_read32(DMA8_IRQ_STATUS) |
| 644 | #define bfin_write_DMA8_IRQ_STATUS(val) bfin_write32(DMA8_IRQ_STATUS, val) |
| 645 | #define bfin_read_DMA8_CURR_X_COUNT() bfin_read32(DMA8_CURR_X_COUNT) |
| 646 | #define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write32(DMA8_CURR_X_COUNT, val) |
| 647 | #define bfin_read_DMA8_CURR_Y_COUNT() bfin_read32(DMA8_CURR_Y_COUNT) |
| 648 | #define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write32(DMA8_CURR_Y_COUNT, val) |
| 649 | #define bfin_read_DMA8_BWL_COUNT() bfin_read32(DMA8_BWL_COUNT) |
| 650 | #define bfin_write_DMA8_BWL_COUNT(val) bfin_write32(DMA8_BWL_COUNT, val) |
| 651 | #define bfin_read_DMA8_CURR_BWL_COUNT() bfin_read32(DMA8_CURR_BWL_COUNT) |
| 652 | #define bfin_write_DMA8_CURR_BWL_COUNT(val) bfin_write32(DMA8_CURR_BWL_COUNT, val) |
| 653 | #define bfin_read_DMA8_BWM_COUNT() bfin_read32(DMA8_BWM_COUNT) |
| 654 | #define bfin_write_DMA8_BWM_COUNT(val) bfin_write32(DMA8_BWM_COUNT, val) |
| 655 | #define bfin_read_DMA8_CURR_BWM_COUNT() bfin_read32(DMA8_CURR_BWM_COUNT) |
| 656 | #define bfin_write_DMA8_CURR_BWM_COUNT(val) bfin_write32(DMA8_CURR_BWM_COUNT, val) |
| 657 | |
| 658 | /* DMA Channel 9 Registers */ |
| 659 | |
| 660 | #define bfin_read_DMA9_NEXT_DESC_PTR() bfin_read32(DMA9_NEXT_DESC_PTR) |
| 661 | #define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR, val) |
| 662 | #define bfin_read_DMA9_START_ADDR() bfin_read32(DMA9_START_ADDR) |
| 663 | #define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR, val) |
| 664 | #define bfin_read_DMA9_CONFIG() bfin_read32(DMA9_CONFIG) |
| 665 | #define bfin_write_DMA9_CONFIG(val) bfin_write32(DMA9_CONFIG, val) |
| 666 | #define bfin_read_DMA9_X_COUNT() bfin_read32(DMA9_X_COUNT) |
| 667 | #define bfin_write_DMA9_X_COUNT(val) bfin_write32(DMA9_X_COUNT, val) |
| 668 | #define bfin_read_DMA9_X_MODIFY() bfin_read32(DMA9_X_MODIFY) |
| 669 | #define bfin_write_DMA9_X_MODIFY(val) bfin_write32(DMA9_X_MODIFY, val) |
| 670 | #define bfin_read_DMA9_Y_COUNT() bfin_read32(DMA9_Y_COUNT) |
| 671 | #define bfin_write_DMA9_Y_COUNT(val) bfin_write32(DMA9_Y_COUNT, val) |
| 672 | #define bfin_read_DMA9_Y_MODIFY() bfin_read32(DMA9_Y_MODIFY) |
| 673 | #define bfin_write_DMA9_Y_MODIFY(val) bfin_write32(DMA9_Y_MODIFY, val) |
| 674 | #define bfin_read_DMA9_CURR_DESC_PTR() bfin_read32(DMA9_CURR_DESC_PTR) |
| 675 | #define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR, val) |
| 676 | #define bfin_read_DMA9_PREV_DESC_PTR() bfin_read32(DMA9_PREV_DESC_PTR) |
| 677 | #define bfin_write_DMA9_PREV_DESC_PTR(val) bfin_write32(DMA9_PREV_DESC_PTR, val) |
| 678 | #define bfin_read_DMA9_CURR_ADDR() bfin_read32(DMA9_CURR_ADDR) |
| 679 | #define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR, val) |
| 680 | #define bfin_read_DMA9_IRQ_STATUS() bfin_read32(DMA9_IRQ_STATUS) |
| 681 | #define bfin_write_DMA9_IRQ_STATUS(val) bfin_write32(DMA9_IRQ_STATUS, val) |
| 682 | #define bfin_read_DMA9_CURR_X_COUNT() bfin_read32(DMA9_CURR_X_COUNT) |
| 683 | #define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write32(DMA9_CURR_X_COUNT, val) |
| 684 | #define bfin_read_DMA9_CURR_Y_COUNT() bfin_read32(DMA9_CURR_Y_COUNT) |
| 685 | #define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write32(DMA9_CURR_Y_COUNT, val) |
| 686 | #define bfin_read_DMA9_BWL_COUNT() bfin_read32(DMA9_BWL_COUNT) |
| 687 | #define bfin_write_DMA9_BWL_COUNT(val) bfin_write32(DMA9_BWL_COUNT, val) |
| 688 | #define bfin_read_DMA9_CURR_BWL_COUNT() bfin_read32(DMA9_CURR_BWL_COUNT) |
| 689 | #define bfin_write_DMA9_CURR_BWL_COUNT(val) bfin_write32(DMA9_CURR_BWL_COUNT, val) |
| 690 | #define bfin_read_DMA9_BWM_COUNT() bfin_read32(DMA9_BWM_COUNT) |
| 691 | #define bfin_write_DMA9_BWM_COUNT(val) bfin_write32(DMA9_BWM_COUNT, val) |
| 692 | #define bfin_read_DMA9_CURR_BWM_COUNT() bfin_read32(DMA9_CURR_BWM_COUNT) |
| 693 | #define bfin_write_DMA9_CURR_BWM_COUNT(val) bfin_write32(DMA9_CURR_BWM_COUNT, val) |
| 694 | |
| 695 | /* DMA Channel 10 Registers */ |
| 696 | |
| 697 | #define bfin_read_DMA10_NEXT_DESC_PTR() bfin_read32(DMA10_NEXT_DESC_PTR) |
| 698 | #define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR, val) |
| 699 | #define bfin_read_DMA10_START_ADDR() bfin_read32(DMA10_START_ADDR) |
| 700 | #define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR, val) |
| 701 | #define bfin_read_DMA10_CONFIG() bfin_read32(DMA10_CONFIG) |
| 702 | #define bfin_write_DMA10_CONFIG(val) bfin_write32(DMA10_CONFIG, val) |
| 703 | #define bfin_read_DMA10_X_COUNT() bfin_read32(DMA10_X_COUNT) |
| 704 | #define bfin_write_DMA10_X_COUNT(val) bfin_write32(DMA10_X_COUNT, val) |
| 705 | #define bfin_read_DMA10_X_MODIFY() bfin_read32(DMA10_X_MODIFY) |
| 706 | #define bfin_write_DMA10_X_MODIFY(val) bfin_write32(DMA10_X_MODIFY, val) |
| 707 | #define bfin_read_DMA10_Y_COUNT() bfin_read32(DMA10_Y_COUNT) |
| 708 | #define bfin_write_DMA10_Y_COUNT(val) bfin_write32(DMA10_Y_COUNT, val) |
| 709 | #define bfin_read_DMA10_Y_MODIFY() bfin_read32(DMA10_Y_MODIFY) |
| 710 | #define bfin_write_DMA10_Y_MODIFY(val) bfin_write32(DMA10_Y_MODIFY, val) |
| 711 | #define bfin_read_DMA10_CURR_DESC_PTR() bfin_read32(DMA10_CURR_DESC_PTR) |
| 712 | #define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR, val) |
| 713 | #define bfin_read_DMA10_PREV_DESC_PTR() bfin_read32(DMA10_PREV_DESC_PTR) |
| 714 | #define bfin_write_DMA10_PREV_DESC_PTR(val) bfin_write32(DMA10_PREV_DESC_PTR, val) |
| 715 | #define bfin_read_DMA10_CURR_ADDR() bfin_read32(DMA10_CURR_ADDR) |
| 716 | #define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR, val) |
| 717 | #define bfin_read_DMA10_IRQ_STATUS() bfin_read32(DMA10_IRQ_STATUS) |
| 718 | #define bfin_write_DMA10_IRQ_STATUS(val) bfin_write32(DMA10_IRQ_STATUS, val) |
| 719 | #define bfin_read_DMA10_CURR_X_COUNT() bfin_read32(DMA10_CURR_X_COUNT) |
| 720 | #define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write32(DMA10_CURR_X_COUNT, val) |
| 721 | #define bfin_read_DMA10_CURR_Y_COUNT() bfin_read32(DMA10_CURR_Y_COUNT) |
| 722 | #define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write32(DMA10_CURR_Y_COUNT, val) |
| 723 | #define bfin_read_DMA10_BWL_COUNT() bfin_read32(DMA10_BWL_COUNT) |
| 724 | #define bfin_write_DMA10_BWL_COUNT(val) bfin_write32(DMA10_BWL_COUNT, val) |
| 725 | #define bfin_read_DMA10_CURR_BWL_COUNT() bfin_read32(DMA10_CURR_BWL_COUNT) |
| 726 | #define bfin_write_DMA10_CURR_BWL_COUNT(val) bfin_write32(DMA10_CURR_BWL_COUNT, val) |
| 727 | #define bfin_read_DMA10_BWM_COUNT() bfin_read32(DMA10_BWM_COUNT) |
| 728 | #define bfin_write_DMA10_BWM_COUNT(val) bfin_write32(DMA10_BWM_COUNT, val) |
| 729 | #define bfin_read_DMA10_CURR_BWM_COUNT() bfin_read32(DMA10_CURR_BWM_COUNT) |
| 730 | #define bfin_write_DMA10_CURR_BWM_COUNT(val) bfin_write32(DMA10_CURR_BWM_COUNT, val) |
| 731 | |
| 732 | /* DMA Channel 11 Registers */ |
| 733 | |
| 734 | #define bfin_read_DMA11_NEXT_DESC_PTR() bfin_read32(DMA11_NEXT_DESC_PTR) |
| 735 | #define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR, val) |
| 736 | #define bfin_read_DMA11_START_ADDR() bfin_read32(DMA11_START_ADDR) |
| 737 | #define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR, val) |
| 738 | #define bfin_read_DMA11_CONFIG() bfin_read32(DMA11_CONFIG) |
| 739 | #define bfin_write_DMA11_CONFIG(val) bfin_write32(DMA11_CONFIG, val) |
| 740 | #define bfin_read_DMA11_X_COUNT() bfin_read32(DMA11_X_COUNT) |
| 741 | #define bfin_write_DMA11_X_COUNT(val) bfin_write32(DMA11_X_COUNT, val) |
| 742 | #define bfin_read_DMA11_X_MODIFY() bfin_read32(DMA11_X_MODIFY) |
| 743 | #define bfin_write_DMA11_X_MODIFY(val) bfin_write32(DMA11_X_MODIFY, val) |
| 744 | #define bfin_read_DMA11_Y_COUNT() bfin_read32(DMA11_Y_COUNT) |
| 745 | #define bfin_write_DMA11_Y_COUNT(val) bfin_write32(DMA11_Y_COUNT, val) |
| 746 | #define bfin_read_DMA11_Y_MODIFY() bfin_read32(DMA11_Y_MODIFY) |
| 747 | #define bfin_write_DMA11_Y_MODIFY(val) bfin_write32(DMA11_Y_MODIFY, val) |
| 748 | #define bfin_read_DMA11_CURR_DESC_PTR() bfin_read32(DMA11_CURR_DESC_PTR) |
| 749 | #define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR, val) |
| 750 | #define bfin_read_DMA11_PREV_DESC_PTR() bfin_read32(DMA11_PREV_DESC_PTR) |
| 751 | #define bfin_write_DMA11_PREV_DESC_PTR(val) bfin_write32(DMA11_PREV_DESC_PTR, val) |
| 752 | #define bfin_read_DMA11_CURR_ADDR() bfin_read32(DMA11_CURR_ADDR) |
| 753 | #define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR, val) |
| 754 | #define bfin_read_DMA11_IRQ_STATUS() bfin_read32(DMA11_IRQ_STATUS) |
| 755 | #define bfin_write_DMA11_IRQ_STATUS(val) bfin_write32(DMA11_IRQ_STATUS, val) |
| 756 | #define bfin_read_DMA11_CURR_X_COUNT() bfin_read32(DMA11_CURR_X_COUNT) |
| 757 | #define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write32(DMA11_CURR_X_COUNT, val) |
| 758 | #define bfin_read_DMA11_CURR_Y_COUNT() bfin_read32(DMA11_CURR_Y_COUNT) |
| 759 | #define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write32(DMA11_CURR_Y_COUNT, val) |
| 760 | #define bfin_read_DMA11_BWL_COUNT() bfin_read32(DMA11_BWL_COUNT) |
| 761 | #define bfin_write_DMA11_BWL_COUNT(val) bfin_write32(DMA11_BWL_COUNT, val) |
| 762 | #define bfin_read_DMA11_CURR_BWL_COUNT() bfin_read32(DMA11_CURR_BWL_COUNT) |
| 763 | #define bfin_write_DMA11_CURR_BWL_COUNT(val) bfin_write32(DMA11_CURR_BWL_COUNT, val) |
| 764 | #define bfin_read_DMA11_BWM_COUNT() bfin_read32(DMA11_BWM_COUNT) |
| 765 | #define bfin_write_DMA11_BWM_COUNT(val) bfin_write32(DMA11_BWM_COUNT, val) |
| 766 | #define bfin_read_DMA11_CURR_BWM_COUNT() bfin_read32(DMA11_CURR_BWM_COUNT) |
| 767 | #define bfin_write_DMA11_CURR_BWM_COUNT(val) bfin_write32(DMA11_CURR_BWM_COUNT, val) |
| 768 | |
| 769 | /* DMA Channel 12 Registers */ |
| 770 | |
| 771 | #define bfin_read_DMA12_NEXT_DESC_PTR() bfin_read32(DMA12_NEXT_DESC_PTR) |
| 772 | #define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_write32(DMA12_NEXT_DESC_PTR, val) |
| 773 | #define bfin_read_DMA12_START_ADDR() bfin_read32(DMA12_START_ADDR) |
| 774 | #define bfin_write_DMA12_START_ADDR(val) bfin_write32(DMA12_START_ADDR, val) |
| 775 | #define bfin_read_DMA12_CONFIG() bfin_read32(DMA12_CONFIG) |
| 776 | #define bfin_write_DMA12_CONFIG(val) bfin_write32(DMA12_CONFIG, val) |
| 777 | #define bfin_read_DMA12_X_COUNT() bfin_read32(DMA12_X_COUNT) |
| 778 | #define bfin_write_DMA12_X_COUNT(val) bfin_write32(DMA12_X_COUNT, val) |
| 779 | #define bfin_read_DMA12_X_MODIFY() bfin_read32(DMA12_X_MODIFY) |
| 780 | #define bfin_write_DMA12_X_MODIFY(val) bfin_write32(DMA12_X_MODIFY, val) |
| 781 | #define bfin_read_DMA12_Y_COUNT() bfin_read32(DMA12_Y_COUNT) |
| 782 | #define bfin_write_DMA12_Y_COUNT(val) bfin_write32(DMA12_Y_COUNT, val) |
| 783 | #define bfin_read_DMA12_Y_MODIFY() bfin_read32(DMA12_Y_MODIFY) |
| 784 | #define bfin_write_DMA12_Y_MODIFY(val) bfin_write32(DMA12_Y_MODIFY, val) |
| 785 | #define bfin_read_DMA12_CURR_DESC_PTR() bfin_read32(DMA12_CURR_DESC_PTR) |
| 786 | #define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_write32(DMA12_CURR_DESC_PTR, val) |
| 787 | #define bfin_read_DMA12_PREV_DESC_PTR() bfin_read32(DMA12_PREV_DESC_PTR) |
| 788 | #define bfin_write_DMA12_PREV_DESC_PTR(val) bfin_write32(DMA12_PREV_DESC_PTR, val) |
| 789 | #define bfin_read_DMA12_CURR_ADDR() bfin_read32(DMA12_CURR_ADDR) |
| 790 | #define bfin_write_DMA12_CURR_ADDR(val) bfin_write32(DMA12_CURR_ADDR, val) |
| 791 | #define bfin_read_DMA12_IRQ_STATUS() bfin_read32(DMA12_IRQ_STATUS) |
| 792 | #define bfin_write_DMA12_IRQ_STATUS(val) bfin_write32(DMA12_IRQ_STATUS, val) |
| 793 | #define bfin_read_DMA12_CURR_X_COUNT() bfin_read32(DMA12_CURR_X_COUNT) |
| 794 | #define bfin_write_DMA12_CURR_X_COUNT(val) bfin_write32(DMA12_CURR_X_COUNT, val) |
| 795 | #define bfin_read_DMA12_CURR_Y_COUNT() bfin_read32(DMA12_CURR_Y_COUNT) |
| 796 | #define bfin_write_DMA12_CURR_Y_COUNT(val) bfin_write32(DMA12_CURR_Y_COUNT, val) |
| 797 | #define bfin_read_DMA12_BWL_COUNT() bfin_read32(DMA12_BWL_COUNT) |
| 798 | #define bfin_write_DMA12_BWL_COUNT(val) bfin_write32(DMA12_BWL_COUNT, val) |
| 799 | #define bfin_read_DMA12_CURR_BWL_COUNT() bfin_read32(DMA12_CURR_BWL_COUNT) |
| 800 | #define bfin_write_DMA12_CURR_BWL_COUNT(val) bfin_write32(DMA12_CURR_BWL_COUNT, val) |
| 801 | #define bfin_read_DMA12_BWM_COUNT() bfin_read32(DMA12_BWM_COUNT) |
| 802 | #define bfin_write_DMA12_BWM_COUNT(val) bfin_write32(DMA12_BWM_COUNT, val) |
| 803 | #define bfin_read_DMA12_CURR_BWM_COUNT() bfin_read32(DMA12_CURR_BWM_COUNT) |
| 804 | #define bfin_write_DMA12_CURR_BWM_COUNT(val) bfin_write32(DMA12_CURR_BWM_COUNT, val) |
| 805 | |
| 806 | /* DMA Channel 13 Registers */ |
| 807 | |
| 808 | #define bfin_read_DMA13_NEXT_DESC_PTR() bfin_read32(DMA13_NEXT_DESC_PTR) |
| 809 | #define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_write32(DMA13_NEXT_DESC_PTR, val) |
| 810 | #define bfin_read_DMA13_START_ADDR() bfin_read32(DMA13_START_ADDR) |
| 811 | #define bfin_write_DMA13_START_ADDR(val) bfin_write32(DMA13_START_ADDR, val) |
| 812 | #define bfin_read_DMA13_CONFIG() bfin_read32(DMA13_CONFIG) |
| 813 | #define bfin_write_DMA13_CONFIG(val) bfin_write32(DMA13_CONFIG, val) |
| 814 | #define bfin_read_DMA13_X_COUNT() bfin_read32(DMA13_X_COUNT) |
| 815 | #define bfin_write_DMA13_X_COUNT(val) bfin_write32(DMA13_X_COUNT, val) |
| 816 | #define bfin_read_DMA13_X_MODIFY() bfin_read32(DMA13_X_MODIFY) |
| 817 | #define bfin_write_DMA13_X_MODIFY(val) bfin_write32(DMA13_X_MODIFY, val) |
| 818 | #define bfin_read_DMA13_Y_COUNT() bfin_read32(DMA13_Y_COUNT) |
| 819 | #define bfin_write_DMA13_Y_COUNT(val) bfin_write32(DMA13_Y_COUNT, val) |
| 820 | #define bfin_read_DMA13_Y_MODIFY() bfin_read32(DMA13_Y_MODIFY) |
| 821 | #define bfin_write_DMA13_Y_MODIFY(val) bfin_write32(DMA13_Y_MODIFY, val) |
| 822 | #define bfin_read_DMA13_CURR_DESC_PTR() bfin_read32(DMA13_CURR_DESC_PTR) |
| 823 | #define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_write32(DMA13_CURR_DESC_PTR, val) |
| 824 | #define bfin_read_DMA13_PREV_DESC_PTR() bfin_read32(DMA13_PREV_DESC_PTR) |
| 825 | #define bfin_write_DMA13_PREV_DESC_PTR(val) bfin_write32(DMA13_PREV_DESC_PTR, val) |
| 826 | #define bfin_read_DMA13_CURR_ADDR() bfin_read32(DMA13_CURR_ADDR) |
| 827 | #define bfin_write_DMA13_CURR_ADDR(val) bfin_write32(DMA13_CURR_ADDR, val) |
| 828 | #define bfin_read_DMA13_IRQ_STATUS() bfin_read32(DMA13_IRQ_STATUS) |
| 829 | #define bfin_write_DMA13_IRQ_STATUS(val) bfin_write32(DMA13_IRQ_STATUS, val) |
| 830 | #define bfin_read_DMA13_CURR_X_COUNT() bfin_read32(DMA13_CURR_X_COUNT) |
| 831 | #define bfin_write_DMA13_CURR_X_COUNT(val) bfin_write32(DMA13_CURR_X_COUNT, val) |
| 832 | #define bfin_read_DMA13_CURR_Y_COUNT() bfin_read32(DMA13_CURR_Y_COUNT) |
| 833 | #define bfin_write_DMA13_CURR_Y_COUNT(val) bfin_write32(DMA13_CURR_Y_COUNT, val) |
| 834 | #define bfin_read_DMA13_BWL_COUNT() bfin_read32(DMA13_BWL_COUNT) |
| 835 | #define bfin_write_DMA13_BWL_COUNT(val) bfin_write32(DMA13_BWL_COUNT, val) |
| 836 | #define bfin_read_DMA13_CURR_BWL_COUNT() bfin_read32(DMA13_CURR_BWL_COUNT) |
| 837 | #define bfin_write_DMA13_CURR_BWL_COUNT(val) bfin_write32(DMA13_CURR_BWL_COUNT, val) |
| 838 | #define bfin_read_DMA13_BWM_COUNT() bfin_read32(DMA13_BWM_COUNT) |
| 839 | #define bfin_write_DMA13_BWM_COUNT(val) bfin_write32(DMA13_BWM_COUNT, val) |
| 840 | #define bfin_read_DMA13_CURR_BWM_COUNT() bfin_read32(DMA13_CURR_BWM_COUNT) |
| 841 | #define bfin_write_DMA13_CURR_BWM_COUNT(val) bfin_write32(DMA13_CURR_BWM_COUNT, val) |
| 842 | |
| 843 | /* DMA Channel 14 Registers */ |
| 844 | |
| 845 | #define bfin_read_DMA14_NEXT_DESC_PTR() bfin_read32(DMA14_NEXT_DESC_PTR) |
| 846 | #define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_write32(DMA14_NEXT_DESC_PTR, val) |
| 847 | #define bfin_read_DMA14_START_ADDR() bfin_read32(DMA14_START_ADDR) |
| 848 | #define bfin_write_DMA14_START_ADDR(val) bfin_write32(DMA14_START_ADDR, val) |
| 849 | #define bfin_read_DMA14_CONFIG() bfin_read32(DMA14_CONFIG) |
| 850 | #define bfin_write_DMA14_CONFIG(val) bfin_write32(DMA14_CONFIG, val) |
| 851 | #define bfin_read_DMA14_X_COUNT() bfin_read32(DMA14_X_COUNT) |
| 852 | #define bfin_write_DMA14_X_COUNT(val) bfin_write32(DMA14_X_COUNT, val) |
| 853 | #define bfin_read_DMA14_X_MODIFY() bfin_read32(DMA14_X_MODIFY) |
| 854 | #define bfin_write_DMA14_X_MODIFY(val) bfin_write32(DMA14_X_MODIFY, val) |
| 855 | #define bfin_read_DMA14_Y_COUNT() bfin_read32(DMA14_Y_COUNT) |
| 856 | #define bfin_write_DMA14_Y_COUNT(val) bfin_write32(DMA14_Y_COUNT, val) |
| 857 | #define bfin_read_DMA14_Y_MODIFY() bfin_read32(DMA14_Y_MODIFY) |
| 858 | #define bfin_write_DMA14_Y_MODIFY(val) bfin_write32(DMA14_Y_MODIFY, val) |
| 859 | #define bfin_read_DMA14_CURR_DESC_PTR() bfin_read32(DMA14_CURR_DESC_PTR) |
| 860 | #define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_write32(DMA14_CURR_DESC_PTR, val) |
| 861 | #define bfin_read_DMA14_PREV_DESC_PTR() bfin_read32(DMA14_PREV_DESC_PTR) |
| 862 | #define bfin_write_DMA14_PREV_DESC_PTR(val) bfin_write32(DMA14_PREV_DESC_PTR, val) |
| 863 | #define bfin_read_DMA14_CURR_ADDR() bfin_read32(DMA14_CURR_ADDR) |
| 864 | #define bfin_write_DMA14_CURR_ADDR(val) bfin_write32(DMA14_CURR_ADDR, val) |
| 865 | #define bfin_read_DMA14_IRQ_STATUS() bfin_read32(DMA14_IRQ_STATUS) |
| 866 | #define bfin_write_DMA14_IRQ_STATUS(val) bfin_write32(DMA14_IRQ_STATUS, val) |
| 867 | #define bfin_read_DMA14_CURR_X_COUNT() bfin_read32(DMA14_CURR_X_COUNT) |
| 868 | #define bfin_write_DMA14_CURR_X_COUNT(val) bfin_write32(DMA14_CURR_X_COUNT, val) |
| 869 | #define bfin_read_DMA14_CURR_Y_COUNT() bfin_read32(DMA14_CURR_Y_COUNT) |
| 870 | #define bfin_write_DMA14_CURR_Y_COUNT(val) bfin_write32(DMA14_CURR_Y_COUNT, val) |
| 871 | #define bfin_read_DMA14_BWL_COUNT() bfin_read32(DMA14_BWL_COUNT) |
| 872 | #define bfin_write_DMA14_BWL_COUNT(val) bfin_write32(DMA14_BWL_COUNT, val) |
| 873 | #define bfin_read_DMA14_CURR_BWL_COUNT() bfin_read32(DMA14_CURR_BWL_COUNT) |
| 874 | #define bfin_write_DMA14_CURR_BWL_COUNT(val) bfin_write32(DMA14_CURR_BWL_COUNT, val) |
| 875 | #define bfin_read_DMA14_BWM_COUNT() bfin_read32(DMA14_BWM_COUNT) |
| 876 | #define bfin_write_DMA14_BWM_COUNT(val) bfin_write32(DMA14_BWM_COUNT, val) |
| 877 | #define bfin_read_DMA14_CURR_BWM_COUNT() bfin_read32(DMA14_CURR_BWM_COUNT) |
| 878 | #define bfin_write_DMA14_CURR_BWM_COUNT(val) bfin_write32(DMA14_CURR_BWM_COUNT, val) |
| 879 | |
| 880 | /* DMA Channel 15 Registers */ |
| 881 | |
| 882 | #define bfin_read_DMA15_NEXT_DESC_PTR() bfin_read32(DMA15_NEXT_DESC_PTR) |
| 883 | #define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_write32(DMA15_NEXT_DESC_PTR, val) |
| 884 | #define bfin_read_DMA15_START_ADDR() bfin_read32(DMA15_START_ADDR) |
| 885 | #define bfin_write_DMA15_START_ADDR(val) bfin_write32(DMA15_START_ADDR, val) |
| 886 | #define bfin_read_DMA15_CONFIG() bfin_read32(DMA15_CONFIG) |
| 887 | #define bfin_write_DMA15_CONFIG(val) bfin_write32(DMA15_CONFIG, val) |
| 888 | #define bfin_read_DMA15_X_COUNT() bfin_read32(DMA15_X_COUNT) |
| 889 | #define bfin_write_DMA15_X_COUNT(val) bfin_write32(DMA15_X_COUNT, val) |
| 890 | #define bfin_read_DMA15_X_MODIFY() bfin_read32(DMA15_X_MODIFY) |
| 891 | #define bfin_write_DMA15_X_MODIFY(val) bfin_write32(DMA15_X_MODIFY, val) |
| 892 | #define bfin_read_DMA15_Y_COUNT() bfin_read32(DMA15_Y_COUNT) |
| 893 | #define bfin_write_DMA15_Y_COUNT(val) bfin_write32(DMA15_Y_COUNT, val) |
| 894 | #define bfin_read_DMA15_Y_MODIFY() bfin_read32(DMA15_Y_MODIFY) |
| 895 | #define bfin_write_DMA15_Y_MODIFY(val) bfin_write32(DMA15_Y_MODIFY, val) |
| 896 | #define bfin_read_DMA15_CURR_DESC_PTR() bfin_read32(DMA15_CURR_DESC_PTR) |
| 897 | #define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_write32(DMA15_CURR_DESC_PTR, val) |
| 898 | #define bfin_read_DMA15_PREV_DESC_PTR() bfin_read32(DMA15_PREV_DESC_PTR) |
| 899 | #define bfin_write_DMA15_PREV_DESC_PTR(val) bfin_write32(DMA15_PREV_DESC_PTR, val) |
| 900 | #define bfin_read_DMA15_CURR_ADDR() bfin_read32(DMA15_CURR_ADDR) |
| 901 | #define bfin_write_DMA15_CURR_ADDR(val) bfin_write32(DMA15_CURR_ADDR, val) |
| 902 | #define bfin_read_DMA15_IRQ_STATUS() bfin_read32(DMA15_IRQ_STATUS) |
| 903 | #define bfin_write_DMA15_IRQ_STATUS(val) bfin_write32(DMA15_IRQ_STATUS, val) |
| 904 | #define bfin_read_DMA15_CURR_X_COUNT() bfin_read32(DMA15_CURR_X_COUNT) |
| 905 | #define bfin_write_DMA15_CURR_X_COUNT(val) bfin_write32(DMA15_CURR_X_COUNT, val) |
| 906 | #define bfin_read_DMA15_CURR_Y_COUNT() bfin_read32(DMA15_CURR_Y_COUNT) |
| 907 | #define bfin_write_DMA15_CURR_Y_COUNT(val) bfin_write32(DMA15_CURR_Y_COUNT, val) |
| 908 | #define bfin_read_DMA15_BWL_COUNT() bfin_read32(DMA15_BWL_COUNT) |
| 909 | #define bfin_write_DMA15_BWL_COUNT(val) bfin_write32(DMA15_BWL_COUNT, val) |
| 910 | #define bfin_read_DMA15_CURR_BWL_COUNT() bfin_read32(DMA15_CURR_BWL_COUNT) |
| 911 | #define bfin_write_DMA15_CURR_BWL_COUNT(val) bfin_write32(DMA15_CURR_BWL_COUNT, val) |
| 912 | #define bfin_read_DMA15_BWM_COUNT() bfin_read32(DMA15_BWM_COUNT) |
| 913 | #define bfin_write_DMA15_BWM_COUNT(val) bfin_write32(DMA15_BWM_COUNT, val) |
| 914 | #define bfin_read_DMA15_CURR_BWM_COUNT() bfin_read32(DMA15_CURR_BWM_COUNT) |
| 915 | #define bfin_write_DMA15_CURR_BWM_COUNT(val) bfin_write32(DMA15_CURR_BWM_COUNT, val) |
| 916 | |
| 917 | /* DMA Channel 16 Registers */ |
| 918 | |
| 919 | #define bfin_read_DMA16_NEXT_DESC_PTR() bfin_read32(DMA16_NEXT_DESC_PTR) |
| 920 | #define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_write32(DMA16_NEXT_DESC_PTR, val) |
| 921 | #define bfin_read_DMA16_START_ADDR() bfin_read32(DMA16_START_ADDR) |
| 922 | #define bfin_write_DMA16_START_ADDR(val) bfin_write32(DMA16_START_ADDR, val) |
| 923 | #define bfin_read_DMA16_CONFIG() bfin_read32(DMA16_CONFIG) |
| 924 | #define bfin_write_DMA16_CONFIG(val) bfin_write32(DMA16_CONFIG, val) |
| 925 | #define bfin_read_DMA16_X_COUNT() bfin_read32(DMA16_X_COUNT) |
| 926 | #define bfin_write_DMA16_X_COUNT(val) bfin_write32(DMA16_X_COUNT, val) |
| 927 | #define bfin_read_DMA16_X_MODIFY() bfin_read32(DMA16_X_MODIFY) |
| 928 | #define bfin_write_DMA16_X_MODIFY(val) bfin_write32(DMA16_X_MODIFY, val) |
| 929 | #define bfin_read_DMA16_Y_COUNT() bfin_read32(DMA16_Y_COUNT) |
| 930 | #define bfin_write_DMA16_Y_COUNT(val) bfin_write32(DMA16_Y_COUNT, val) |
| 931 | #define bfin_read_DMA16_Y_MODIFY() bfin_read32(DMA16_Y_MODIFY) |
| 932 | #define bfin_write_DMA16_Y_MODIFY(val) bfin_write32(DMA16_Y_MODIFY, val) |
| 933 | #define bfin_read_DMA16_CURR_DESC_PTR() bfin_read32(DMA16_CURR_DESC_PTR) |
| 934 | #define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_write32(DMA16_CURR_DESC_PTR, val) |
| 935 | #define bfin_read_DMA16_PREV_DESC_PTR() bfin_read32(DMA16_PREV_DESC_PTR) |
| 936 | #define bfin_write_DMA16_PREV_DESC_PTR(val) bfin_write32(DMA16_PREV_DESC_PTR, val) |
| 937 | #define bfin_read_DMA16_CURR_ADDR() bfin_read32(DMA16_CURR_ADDR) |
| 938 | #define bfin_write_DMA16_CURR_ADDR(val) bfin_write32(DMA16_CURR_ADDR, val) |
| 939 | #define bfin_read_DMA16_IRQ_STATUS() bfin_read32(DMA16_IRQ_STATUS) |
| 940 | #define bfin_write_DMA16_IRQ_STATUS(val) bfin_write32(DMA16_IRQ_STATUS, val) |
| 941 | #define bfin_read_DMA16_CURR_X_COUNT() bfin_read32(DMA16_CURR_X_COUNT) |
| 942 | #define bfin_write_DMA16_CURR_X_COUNT(val) bfin_write32(DMA16_CURR_X_COUNT, val) |
| 943 | #define bfin_read_DMA16_CURR_Y_COUNT() bfin_read32(DMA16_CURR_Y_COUNT) |
| 944 | #define bfin_write_DMA16_CURR_Y_COUNT(val) bfin_write32(DMA16_CURR_Y_COUNT, val) |
| 945 | #define bfin_read_DMA16_BWL_COUNT() bfin_read32(DMA16_BWL_COUNT) |
| 946 | #define bfin_write_DMA16_BWL_COUNT(val) bfin_write32(DMA16_BWL_COUNT, val) |
| 947 | #define bfin_read_DMA16_CURR_BWL_COUNT() bfin_read32(DMA16_CURR_BWL_COUNT) |
| 948 | #define bfin_write_DMA16_CURR_BWL_COUNT(val) bfin_write32(DMA16_CURR_BWL_COUNT, val) |
| 949 | #define bfin_read_DMA16_BWM_COUNT() bfin_read32(DMA16_BWM_COUNT) |
| 950 | #define bfin_write_DMA16_BWM_COUNT(val) bfin_write32(DMA16_BWM_COUNT, val) |
| 951 | #define bfin_read_DMA16_CURR_BWM_COUNT() bfin_read32(DMA16_CURR_BWM_COUNT) |
| 952 | #define bfin_write_DMA16_CURR_BWM_COUNT(val) bfin_write32(DMA16_CURR_BWM_COUNT, val) |
| 953 | |
| 954 | /* DMA Channel 17 Registers */ |
| 955 | |
| 956 | #define bfin_read_DMA17_NEXT_DESC_PTR() bfin_read32(DMA17_NEXT_DESC_PTR) |
| 957 | #define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_write32(DMA17_NEXT_DESC_PTR, val) |
| 958 | #define bfin_read_DMA17_START_ADDR() bfin_read32(DMA17_START_ADDR) |
| 959 | #define bfin_write_DMA17_START_ADDR(val) bfin_write32(DMA17_START_ADDR, val) |
| 960 | #define bfin_read_DMA17_CONFIG() bfin_read32(DMA17_CONFIG) |
| 961 | #define bfin_write_DMA17_CONFIG(val) bfin_write32(DMA17_CONFIG, val) |
| 962 | #define bfin_read_DMA17_X_COUNT() bfin_read32(DMA17_X_COUNT) |
| 963 | #define bfin_write_DMA17_X_COUNT(val) bfin_write32(DMA17_X_COUNT, val) |
| 964 | #define bfin_read_DMA17_X_MODIFY() bfin_read32(DMA17_X_MODIFY) |
| 965 | #define bfin_write_DMA17_X_MODIFY(val) bfin_write32(DMA17_X_MODIFY, val) |
| 966 | #define bfin_read_DMA17_Y_COUNT() bfin_read32(DMA17_Y_COUNT) |
| 967 | #define bfin_write_DMA17_Y_COUNT(val) bfin_write32(DMA17_Y_COUNT, val) |
| 968 | #define bfin_read_DMA17_Y_MODIFY() bfin_read32(DMA17_Y_MODIFY) |
| 969 | #define bfin_write_DMA17_Y_MODIFY(val) bfin_write32(DMA17_Y_MODIFY, val) |
| 970 | #define bfin_read_DMA17_CURR_DESC_PTR() bfin_read32(DMA17_CURR_DESC_PTR) |
| 971 | #define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_write32(DMA17_CURR_DESC_PTR, val) |
| 972 | #define bfin_read_DMA17_PREV_DESC_PTR() bfin_read32(DMA17_PREV_DESC_PTR) |
| 973 | #define bfin_write_DMA17_PREV_DESC_PTR(val) bfin_write32(DMA17_PREV_DESC_PTR, val) |
| 974 | #define bfin_read_DMA17_CURR_ADDR() bfin_read32(DMA17_CURR_ADDR) |
| 975 | #define bfin_write_DMA17_CURR_ADDR(val) bfin_write32(DMA17_CURR_ADDR, val) |
| 976 | #define bfin_read_DMA17_IRQ_STATUS() bfin_read32(DMA17_IRQ_STATUS) |
| 977 | #define bfin_write_DMA17_IRQ_STATUS(val) bfin_write32(DMA17_IRQ_STATUS, val) |
| 978 | #define bfin_read_DMA17_CURR_X_COUNT() bfin_read32(DMA17_CURR_X_COUNT) |
| 979 | #define bfin_write_DMA17_CURR_X_COUNT(val) bfin_write32(DMA17_CURR_X_COUNT, val) |
| 980 | #define bfin_read_DMA17_CURR_Y_COUNT() bfin_read32(DMA17_CURR_Y_COUNT) |
| 981 | #define bfin_write_DMA17_CURR_Y_COUNT(val) bfin_write32(DMA17_CURR_Y_COUNT, val) |
| 982 | #define bfin_read_DMA17_BWL_COUNT() bfin_read32(DMA17_BWL_COUNT) |
| 983 | #define bfin_write_DMA17_BWL_COUNT(val) bfin_write32(DMA17_BWL_COUNT, val) |
| 984 | #define bfin_read_DMA17_CURR_BWL_COUNT() bfin_read32(DMA17_CURR_BWL_COUNT) |
| 985 | #define bfin_write_DMA17_CURR_BWL_COUNT(val) bfin_write32(DMA17_CURR_BWL_COUNT, val) |
| 986 | #define bfin_read_DMA17_BWM_COUNT() bfin_read32(DMA17_BWM_COUNT) |
| 987 | #define bfin_write_DMA17_BWM_COUNT(val) bfin_write32(DMA17_BWM_COUNT, val) |
| 988 | #define bfin_read_DMA17_CURR_BWM_COUNT() bfin_read32(DMA17_CURR_BWM_COUNT) |
| 989 | #define bfin_write_DMA17_CURR_BWM_COUNT(val) bfin_write32(DMA17_CURR_BWM_COUNT, val) |
| 990 | |
| 991 | /* DMA Channel 18 Registers */ |
| 992 | |
| 993 | #define bfin_read_DMA18_NEXT_DESC_PTR() bfin_read32(DMA18_NEXT_DESC_PTR) |
| 994 | #define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_write32(DMA18_NEXT_DESC_PTR, val) |
| 995 | #define bfin_read_DMA18_START_ADDR() bfin_read32(DMA18_START_ADDR) |
| 996 | #define bfin_write_DMA18_START_ADDR(val) bfin_write32(DMA18_START_ADDR, val) |
| 997 | #define bfin_read_DMA18_CONFIG() bfin_read32(DMA18_CONFIG) |
| 998 | #define bfin_write_DMA18_CONFIG(val) bfin_write32(DMA18_CONFIG, val) |
| 999 | #define bfin_read_DMA18_X_COUNT() bfin_read32(DMA18_X_COUNT) |
| 1000 | #define bfin_write_DMA18_X_COUNT(val) bfin_write32(DMA18_X_COUNT, val) |
| 1001 | #define bfin_read_DMA18_X_MODIFY() bfin_read32(DMA18_X_MODIFY) |
| 1002 | #define bfin_write_DMA18_X_MODIFY(val) bfin_write32(DMA18_X_MODIFY, val) |
| 1003 | #define bfin_read_DMA18_Y_COUNT() bfin_read32(DMA18_Y_COUNT) |
| 1004 | #define bfin_write_DMA18_Y_COUNT(val) bfin_write32(DMA18_Y_COUNT, val) |
| 1005 | #define bfin_read_DMA18_Y_MODIFY() bfin_read32(DMA18_Y_MODIFY) |
| 1006 | #define bfin_write_DMA18_Y_MODIFY(val) bfin_write32(DMA18_Y_MODIFY, val) |
| 1007 | #define bfin_read_DMA18_CURR_DESC_PTR() bfin_read32(DMA18_CURR_DESC_PTR) |
| 1008 | #define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_write32(DMA18_CURR_DESC_PTR, val) |
| 1009 | #define bfin_read_DMA18_PREV_DESC_PTR() bfin_read32(DMA18_PREV_DESC_PTR) |
| 1010 | #define bfin_write_DMA18_PREV_DESC_PTR(val) bfin_write32(DMA18_PREV_DESC_PTR, val) |
| 1011 | #define bfin_read_DMA18_CURR_ADDR() bfin_read32(DMA18_CURR_ADDR) |
| 1012 | #define bfin_write_DMA18_CURR_ADDR(val) bfin_write32(DMA18_CURR_ADDR, val) |
| 1013 | #define bfin_read_DMA18_IRQ_STATUS() bfin_read32(DMA18_IRQ_STATUS) |
| 1014 | #define bfin_write_DMA18_IRQ_STATUS(val) bfin_write32(DMA18_IRQ_STATUS, val) |
| 1015 | #define bfin_read_DMA18_CURR_X_COUNT() bfin_read32(DMA18_CURR_X_COUNT) |
| 1016 | #define bfin_write_DMA18_CURR_X_COUNT(val) bfin_write32(DMA18_CURR_X_COUNT, val) |
| 1017 | #define bfin_read_DMA18_CURR_Y_COUNT() bfin_read32(DMA18_CURR_Y_COUNT) |
| 1018 | #define bfin_write_DMA18_CURR_Y_COUNT(val) bfin_write32(DMA18_CURR_Y_COUNT, val) |
| 1019 | #define bfin_read_DMA18_BWL_COUNT() bfin_read32(DMA18_BWL_COUNT) |
| 1020 | #define bfin_write_DMA18_BWL_COUNT(val) bfin_write32(DMA18_BWL_COUNT, val) |
| 1021 | #define bfin_read_DMA18_CURR_BWL_COUNT() bfin_read32(DMA18_CURR_BWL_COUNT) |
| 1022 | #define bfin_write_DMA18_CURR_BWL_COUNT(val) bfin_write32(DMA18_CURR_BWL_COUNT, val) |
| 1023 | #define bfin_read_DMA18_BWM_COUNT() bfin_read32(DMA18_BWM_COUNT) |
| 1024 | #define bfin_write_DMA18_BWM_COUNT(val) bfin_write32(DMA18_BWM_COUNT, val) |
| 1025 | #define bfin_read_DMA18_CURR_BWM_COUNT() bfin_read32(DMA18_CURR_BWM_COUNT) |
| 1026 | #define bfin_write_DMA18_CURR_BWM_COUNT(val) bfin_write32(DMA18_CURR_BWM_COUNT, val) |
| 1027 | |
| 1028 | /* DMA Channel 19 Registers */ |
| 1029 | |
| 1030 | #define bfin_read_DMA19_NEXT_DESC_PTR() bfin_read32(DMA19_NEXT_DESC_PTR) |
| 1031 | #define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_write32(DMA19_NEXT_DESC_PTR, val) |
| 1032 | #define bfin_read_DMA19_START_ADDR() bfin_read32(DMA19_START_ADDR) |
| 1033 | #define bfin_write_DMA19_START_ADDR(val) bfin_write32(DMA19_START_ADDR, val) |
| 1034 | #define bfin_read_DMA19_CONFIG() bfin_read32(DMA19_CONFIG) |
| 1035 | #define bfin_write_DMA19_CONFIG(val) bfin_write32(DMA19_CONFIG, val) |
| 1036 | #define bfin_read_DMA19_X_COUNT() bfin_read32(DMA19_X_COUNT) |
| 1037 | #define bfin_write_DMA19_X_COUNT(val) bfin_write32(DMA19_X_COUNT, val) |
| 1038 | #define bfin_read_DMA19_X_MODIFY() bfin_read32(DMA19_X_MODIFY) |
| 1039 | #define bfin_write_DMA19_X_MODIFY(val) bfin_write32(DMA19_X_MODIFY, val) |
| 1040 | #define bfin_read_DMA19_Y_COUNT() bfin_read32(DMA19_Y_COUNT) |
| 1041 | #define bfin_write_DMA19_Y_COUNT(val) bfin_write32(DMA19_Y_COUNT, val) |
| 1042 | #define bfin_read_DMA19_Y_MODIFY() bfin_read32(DMA19_Y_MODIFY) |
| 1043 | #define bfin_write_DMA19_Y_MODIFY(val) bfin_write32(DMA19_Y_MODIFY, val) |
| 1044 | #define bfin_read_DMA19_CURR_DESC_PTR() bfin_read32(DMA19_CURR_DESC_PTR) |
| 1045 | #define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_write32(DMA19_CURR_DESC_PTR, val) |
| 1046 | #define bfin_read_DMA19_PREV_DESC_PTR() bfin_read32(DMA19_PREV_DESC_PTR) |
| 1047 | #define bfin_write_DMA19_PREV_DESC_PTR(val) bfin_write32(DMA19_PREV_DESC_PTR, val) |
| 1048 | #define bfin_read_DMA19_CURR_ADDR() bfin_read32(DMA19_CURR_ADDR) |
| 1049 | #define bfin_write_DMA19_CURR_ADDR(val) bfin_write32(DMA19_CURR_ADDR, val) |
| 1050 | #define bfin_read_DMA19_IRQ_STATUS() bfin_read32(DMA19_IRQ_STATUS) |
| 1051 | #define bfin_write_DMA19_IRQ_STATUS(val) bfin_write32(DMA19_IRQ_STATUS, val) |
| 1052 | #define bfin_read_DMA19_CURR_X_COUNT() bfin_read32(DMA19_CURR_X_COUNT) |
| 1053 | #define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write32(DMA19_CURR_X_COUNT, val) |
| 1054 | #define bfin_read_DMA19_CURR_Y_COUNT() bfin_read32(DMA19_CURR_Y_COUNT) |
| 1055 | #define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write32(DMA19_CURR_Y_COUNT, val) |
| 1056 | #define bfin_read_DMA19_BWL_COUNT() bfin_read32(DMA19_BWL_COUNT) |
| 1057 | #define bfin_write_DMA19_BWL_COUNT(val) bfin_write32(DMA19_BWL_COUNT, val) |
| 1058 | #define bfin_read_DMA19_CURR_BWL_COUNT() bfin_read32(DMA19_CURR_BWL_COUNT) |
| 1059 | #define bfin_write_DMA19_CURR_BWL_COUNT(val) bfin_write32(DMA19_CURR_BWL_COUNT, val) |
| 1060 | #define bfin_read_DMA19_BWM_COUNT() bfin_read32(DMA19_BWM_COUNT) |
| 1061 | #define bfin_write_DMA19_BWM_COUNT(val) bfin_write32(DMA19_BWM_COUNT, val) |
| 1062 | #define bfin_read_DMA19_CURR_BWM_COUNT() bfin_read32(DMA19_CURR_BWM_COUNT) |
| 1063 | #define bfin_write_DMA19_CURR_BWM_COUNT(val) bfin_write32(DMA19_CURR_BWM_COUNT, val) |
| 1064 | |
| 1065 | /* DMA Channel 20 Registers */ |
| 1066 | |
| 1067 | #define bfin_read_DMA20_NEXT_DESC_PTR() bfin_read32(DMA20_NEXT_DESC_PTR) |
| 1068 | #define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_write32(DMA20_NEXT_DESC_PTR, val) |
| 1069 | #define bfin_read_DMA20_START_ADDR() bfin_read32(DMA20_START_ADDR) |
| 1070 | #define bfin_write_DMA20_START_ADDR(val) bfin_write32(DMA20_START_ADDR, val) |
| 1071 | #define bfin_read_DMA20_CONFIG() bfin_read32(DMA20_CONFIG) |
| 1072 | #define bfin_write_DMA20_CONFIG(val) bfin_write32(DMA20_CONFIG, val) |
| 1073 | #define bfin_read_DMA20_X_COUNT() bfin_read32(DMA20_X_COUNT) |
| 1074 | #define bfin_write_DMA20_X_COUNT(val) bfin_write32(DMA20_X_COUNT, val) |
| 1075 | #define bfin_read_DMA20_X_MODIFY() bfin_read32(DMA20_X_MODIFY) |
| 1076 | #define bfin_write_DMA20_X_MODIFY(val) bfin_write32(DMA20_X_MODIFY, val) |
| 1077 | #define bfin_read_DMA20_Y_COUNT() bfin_read32(DMA20_Y_COUNT) |
| 1078 | #define bfin_write_DMA20_Y_COUNT(val) bfin_write32(DMA20_Y_COUNT, val) |
| 1079 | #define bfin_read_DMA20_Y_MODIFY() bfin_read32(DMA20_Y_MODIFY) |
| 1080 | #define bfin_write_DMA20_Y_MODIFY(val) bfin_write32(DMA20_Y_MODIFY, val) |
| 1081 | #define bfin_read_DMA20_CURR_DESC_PTR() bfin_read32(DMA20_CURR_DESC_PTR) |
| 1082 | #define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_write32(DMA20_CURR_DESC_PTR, val) |
| 1083 | #define bfin_read_DMA20_PREV_DESC_PTR() bfin_read32(DMA20_PREV_DESC_PTR) |
| 1084 | #define bfin_write_DMA20_PREV_DESC_PTR(val) bfin_write32(DMA20_PREV_DESC_PTR, val) |
| 1085 | #define bfin_read_DMA20_CURR_ADDR() bfin_read32(DMA20_CURR_ADDR) |
| 1086 | #define bfin_write_DMA20_CURR_ADDR(val) bfin_write32(DMA20_CURR_ADDR, val) |
| 1087 | #define bfin_read_DMA20_IRQ_STATUS() bfin_read32(DMA20_IRQ_STATUS) |
| 1088 | #define bfin_write_DMA20_IRQ_STATUS(val) bfin_write32(DMA20_IRQ_STATUS, val) |
| 1089 | #define bfin_read_DMA20_CURR_X_COUNT() bfin_read32(DMA20_CURR_X_COUNT) |
| 1090 | #define bfin_write_DMA20_CURR_X_COUNT(val) bfin_write32(DMA20_CURR_X_COUNT, val) |
| 1091 | #define bfin_read_DMA20_CURR_Y_COUNT() bfin_read32(DMA20_CURR_Y_COUNT) |
| 1092 | #define bfin_write_DMA20_CURR_Y_COUNT(val) bfin_write32(DMA20_CURR_Y_COUNT, val) |
| 1093 | #define bfin_read_DMA20_BWL_COUNT() bfin_read32(DMA20_BWL_COUNT) |
| 1094 | #define bfin_write_DMA20_BWL_COUNT(val) bfin_write32(DMA20_BWL_COUNT, val) |
| 1095 | #define bfin_read_DMA20_CURR_BWL_COUNT() bfin_read32(DMA20_CURR_BWL_COUNT) |
| 1096 | #define bfin_write_DMA20_CURR_BWL_COUNT(val) bfin_write32(DMA20_CURR_BWL_COUNT, val) |
| 1097 | #define bfin_read_DMA20_BWM_COUNT() bfin_read32(DMA20_BWM_COUNT) |
| 1098 | #define bfin_write_DMA20_BWM_COUNT(val) bfin_write32(DMA20_BWM_COUNT, val) |
| 1099 | #define bfin_read_DMA20_CURR_BWM_COUNT() bfin_read32(DMA20_CURR_BWM_COUNT) |
| 1100 | #define bfin_write_DMA20_CURR_BWM_COUNT(val) bfin_write32(DMA20_CURR_BWM_COUNT, val) |
| 1101 | |
| 1102 | |
| 1103 | /* MDMA Stream 0 Registers (DMA Channel 21 and 22) */ |
| 1104 | |
| 1105 | #define bfin_read_MDMA0_DEST_CRC0_NEXT_DESC_PTR() bfin_read32(MDMA0_DEST_CRC0_NEXT_DESC_PTR) |
| 1106 | #define bfin_write_MDMA0_DEST_CRC0_NEXT_DESC_PTR(val) bfin_write32(MDMA0_DEST_CRC0_NEXT_DESC_PTR, val) |
| 1107 | #define bfin_read_MDMA0_DEST_CRC0_START_ADDR() bfin_read32(MDMA0_DEST_CRC0_START_ADDR) |
| 1108 | #define bfin_write_MDMA0_DEST_CRC0_START_ADDR(val) bfin_write32(MDMA0_DEST_CRC0_START_ADDR, val) |
| 1109 | #define bfin_read_MDMA0_DEST_CRC0_CONFIG() bfin_read32(MDMA0_DEST_CRC0_CONFIG) |
| 1110 | #define bfin_write_MDMA0_DEST_CRC0_CONFIG(val) bfin_write32(MDMA0_DEST_CRC0_CONFIG, val) |
| 1111 | #define bfin_read_MDMA0_DEST_CRC0_X_COUNT() bfin_read32(MDMA0_DEST_CRC0_X_COUNT) |
| 1112 | #define bfin_write_MDMA0_DEST_CRC0_X_COUNT(val) bfin_write32(MDMA0_DEST_CRC0_X_COUNT, val) |
| 1113 | #define bfin_read_MDMA0_DEST_CRC0_X_MODIFY() bfin_read32(MDMA0_DEST_CRC0_X_MODIFY) |
| 1114 | #define bfin_write_MDMA0_DEST_CRC0_X_MODIFY(val) bfin_write32(MDMA0_DEST_CRC0_X_MODIFY, val) |
| 1115 | #define bfin_read_MDMA0_DEST_CRC0_Y_COUNT() bfin_read32(MDMA0_DEST_CRC0_Y_COUNT) |
| 1116 | #define bfin_write_MDMA0_DEST_CRC0_Y_COUNT(val) bfin_write32(MDMA0_DEST_CRC0_Y_COUNT, val) |
| 1117 | #define bfin_read_MDMA0_DEST_CRC0_Y_MODIFY() bfin_read32(MDMA0_DEST_CRC0_Y_MODIFY) |
| 1118 | #define bfin_write_MDMA0_DEST_CRC0_Y_MODIFY(val) bfin_write32(MDMA0_DEST_CRC0_Y_MODIFY, val) |
| 1119 | #define bfin_read_MDMA0_DEST_CRC0_CURR_DESC_PTR() bfin_read32(MDMA0_DEST_CRC0_CURR_DESC_PTR) |
| 1120 | #define bfin_write_MDMA0_DEST_CRC0_CURR_DESC_PTR(val) bfin_write32(MDMA0_DEST_CRC0_CURR_DESC_PTR, val) |
| 1121 | #define bfin_read_MDMA0_DEST_CRC0_PREV_DESC_PTR() bfin_read32(MDMA0_DEST_CRC0_PREV_DESC_PTR) |
| 1122 | #define bfin_write_MDMA0_DEST_CRC0_PREV_DESC_PTR(val) bfin_write32(MDMA0_DEST_CRC0_PREV_DESC_PTR, val) |
| 1123 | #define bfin_read_MDMA0_DEST_CRC0_CURR_ADDR() bfin_read32(MDMA0_DEST_CRC0_CURR_ADDR) |
| 1124 | #define bfin_write_MDMA0_DEST_CRC0_CURR_ADDR(val) bfin_write32(MDMA0_DEST_CRC0_CURR_ADDR, val) |
| 1125 | #define bfin_read_MDMA0_DEST_CRC0_IRQ_STATUS() bfin_read32(MDMA0_DEST_CRC0_IRQ_STATUS) |
| 1126 | #define bfin_write_MDMA0_DEST_CRC0_IRQ_STATUS(val) bfin_write32(MDMA0_DEST_CRC0_IRQ_STATUS, val) |
| 1127 | #define bfin_read_MDMA0_DEST_CRC0_CURR_X_COUNT() bfin_read32(MDMA0_DEST_CRC0_CURR_X_COUNT) |
| 1128 | #define bfin_write_MDMA0_DEST_CRC0_CURR_X_COUNT(val) bfin_write32(MDMA0_DEST_CRC0_CURR_X_COUNT, val) |
| 1129 | #define bfin_read_MDMA0_DEST_CRC0_CURR_Y_COUNT() bfin_read32(MDMA0_DEST_CRC0_CURR_Y_COUNT) |
| 1130 | #define bfin_write_MDMA0_DEST_CRC0_CURR_Y_COUNT(val) bfin_write32(MDMA0_DEST_CRC0_CURR_Y_COUNT, val) |
| 1131 | #define bfin_read_MDMA0_SRC_CRC0_NEXT_DESC_PTR() bfin_read32(MDMA0_SRC_CRC0_NEXT_DESC_PTR) |
| 1132 | #define bfin_write_MDMA0_SRC_CRC0_NEXT_DESC_PTR(val) bfin_write32(MDMA0_SRC_CRC0_NEXT_DESC_PTR, val) |
| 1133 | #define bfin_read_MDMA0_SRC_CRC0_START_ADDR() bfin_read32(MDMA0_SRC_CRC0_START_ADDR) |
| 1134 | #define bfin_write_MDMA0_SRC_CRC0_START_ADDR(val) bfin_write32(MDMA0_SRC_CRC0_START_ADDR, val) |
| 1135 | #define bfin_read_MDMA0_SRC_CRC0_CONFIG() bfin_read32(MDMA0_SRC_CRC0_CONFIG) |
| 1136 | #define bfin_write_MDMA0_SRC_CRC0_CONFIG(val) bfin_write32(MDMA0_SRC_CRC0_CONFIG, val) |
| 1137 | #define bfin_read_MDMA0_SRC_CRC0_X_COUNT() bfin_read32(MDMA0_SRC_CRC0_X_COUNT) |
| 1138 | #define bfin_write_MDMA0_SRC_CRC0_X_COUNT(val) bfin_write32(MDMA0_SRC_CRC0_X_COUNT, val) |
| 1139 | #define bfin_read_MDMA0_SRC_CRC0_X_MODIFY() bfin_read32(MDMA0_SRC_CRC0_X_MODIFY) |
| 1140 | #define bfin_write_MDMA0_SRC_CRC0_X_MODIFY(val) bfin_write32(MDMA0_SRC_CRC0_X_MODIFY, val) |
| 1141 | #define bfin_read_MDMA0_SRC_CRC0_Y_COUNT() bfin_read32(MDMA0_SRC_CRC0_Y_COUNT) |
| 1142 | #define bfin_write_MDMA0_SRC_CRC0_Y_COUNT(val) bfin_write32(MDMA0_SRC_CRC0_Y_COUNT, val) |
| 1143 | #define bfin_read_MDMA0_SRC_CRC0_Y_MODIFY() bfin_read32(MDMA0_SRC_CRC0_Y_MODIFY) |
| 1144 | #define bfin_write_MDMA0_SRC_CRC0_Y_MODIFY(val) bfin_write32(MDMA0_SRC_CRC0_Y_MODIFY, val) |
| 1145 | #define bfin_read_MDMA0_SRC_CRC0_CURR_DESC_PTR() bfin_read32(MDMA0_SRC_CRC0_CURR_DESC_PTR) |
| 1146 | #define bfin_write_MDMA0_SRC_CRC0_CURR_DESC_PTR(val) bfin_write32(MDMA0_SRC_CRC0_CURR_DESC_PTR, val) |
| 1147 | #define bfin_read_MDMA0_SRC_CRC0_PREV_DESC_PTR() bfin_read32(MDMA0_SRC_CRC0_PREV_DESC_PTR) |
| 1148 | #define bfin_write_MDMA0_SRC_CRC0_PREV_DESC_PTR(val) bfin_write32(MDMA0_SRC_CRC0_PREV_DESC_PTR, val) |
| 1149 | #define bfin_read_MDMA0_SRC_CRC0_CURR_ADDR() bfin_read32(MDMA0_SRC_CRC0_CURR_ADDR) |
| 1150 | #define bfin_write_MDMA0_SRC_CRC0_CURR_ADDR(val) bfin_write32(MDMA0_SRC_CRC0_CURR_ADDR, val) |
| 1151 | #define bfin_read_MDMA0_SRC_CRC0_IRQ_STATUS() bfin_read32(MDMA0_SRC_CRC0_IRQ_STATUS) |
| 1152 | #define bfin_write_MDMA0_SRC_CRC0_IRQ_STATUS(val) bfin_write32(MDMA0_SRC_CRC0_IRQ_STATUS, val) |
| 1153 | #define bfin_read_MDMA0_SRC_CRC0_CURR_X_COUNT() bfin_read32(MDMA0_SRC_CRC0_CURR_X_COUNT) |
| 1154 | #define bfin_write_MDMA0_SRC_CRC0_CURR_X_COUNT(val) bfin_write32(MDMA0_SRC_CRC0_CURR_X_COUNT, val) |
| 1155 | #define bfin_read_MDMA0_SRC_CRC0_CURR_Y_COUNT() bfin_read32(MDMA0_SRC_CRC0_CURR_Y_COUNT) |
| 1156 | #define bfin_write_MDMA0_SRC_CRC0_CURR_Y_COUNT(val) bfin_write32(MDMA0_SRC_CRC0_CURR_Y_COUNT, val) |
| 1157 | |
| 1158 | /* MDMA Stream 1 Registers (DMA Channel 23 and 24) */ |
| 1159 | |
| 1160 | #define bfin_read_MDMA1_DEST_CRC1_NEXT_DESC_PTR() bfin_read32(MDMA1_DEST_CRC1_NEXT_DESC_PTR) |
| 1161 | #define bfin_write_MDMA1_DEST_CRC1_NEXT_DESC_PTR(val) bfin_write32(MDMA1_DEST_CRC1_NEXT_DESC_PTR, val) |
| 1162 | #define bfin_read_MDMA1_DEST_CRC1_START_ADDR() bfin_read32(MDMA1_DEST_CRC1_START_ADDR) |
| 1163 | #define bfin_write_MDMA1_DEST_CRC1_START_ADDR(val) bfin_write32(MDMA1_DEST_CRC1_START_ADDR, val) |
| 1164 | #define bfin_read_MDMA1_DEST_CRC1_CONFIG() bfin_read32(MDMA1_DEST_CRC1_CONFIG) |
| 1165 | #define bfin_write_MDMA1_DEST_CRC1_CONFIG(val) bfin_write32(MDMA1_DEST_CRC1_CONFIG, val) |
| 1166 | #define bfin_read_MDMA1_DEST_CRC1_X_COUNT() bfin_read32(MDMA1_DEST_CRC1_X_COUNT) |
| 1167 | #define bfin_write_MDMA1_DEST_CRC1_X_COUNT(val) bfin_write32(MDMA1_DEST_CRC1_X_COUNT, val) |
| 1168 | #define bfin_read_MDMA1_DEST_CRC1_X_MODIFY() bfin_read32(MDMA1_DEST_CRC1_X_MODIFY) |
| 1169 | #define bfin_write_MDMA1_DEST_CRC1_X_MODIFY(val) bfin_write32(MDMA1_DEST_CRC1_X_MODIFY, val) |
| 1170 | #define bfin_read_MDMA1_DEST_CRC1_Y_COUNT() bfin_read32(MDMA1_DEST_CRC1_Y_COUNT) |
| 1171 | #define bfin_write_MDMA1_DEST_CRC1_Y_COUNT(val) bfin_write32(MDMA1_DEST_CRC1_Y_COUNT, val) |
| 1172 | #define bfin_read_MDMA1_DEST_CRC1_Y_MODIFY() bfin_read32(MDMA1_DEST_CRC1_Y_MODIFY) |
| 1173 | #define bfin_write_MDMA1_DEST_CRC1_Y_MODIFY(val) bfin_write32(MDMA1_DEST_CRC1_Y_MODIFY, val) |
| 1174 | #define bfin_read_MDMA1_DEST_CRC1_CURR_DESC_PTR() bfin_read32(MDMA1_DEST_CRC1_CURR_DESC_PTR) |
| 1175 | #define bfin_write_MDMA1_DEST_CRC1_CURR_DESC_PTR(val) bfin_write32(MDMA1_DEST_CRC1_CURR_DESC_PTR, val) |
| 1176 | #define bfin_read_MDMA1_DEST_CRC1_PREV_DESC_PTR() bfin_read32(MDMA1_DEST_CRC1_PREV_DESC_PTR) |
| 1177 | #define bfin_write_MDMA1_DEST_CRC1_PREV_DESC_PTR(val) bfin_write32(MDMA1_DEST_CRC1_PREV_DESC_PTR, val) |
| 1178 | #define bfin_read_MDMA1_DEST_CRC1_CURR_ADDR() bfin_read32(MDMA1_DEST_CRC1_CURR_ADDR) |
| 1179 | #define bfin_write_MDMA1_DEST_CRC1_CURR_ADDR(val) bfin_write32(MDMA1_DEST_CRC1_CURR_ADDR, val) |
| 1180 | #define bfin_read_MDMA1_DEST_CRC1_IRQ_STATUS() bfin_read32(MDMA1_DEST_CRC1_IRQ_STATUS) |
| 1181 | #define bfin_write_MDMA1_DEST_CRC1_IRQ_STATUS(val) bfin_write32(MDMA1_DEST_CRC1_IRQ_STATUS, val) |
| 1182 | #define bfin_read_MDMA1_DEST_CRC1_CURR_X_COUNT() bfin_read32(MDMA1_DEST_CRC1_CURR_X_COUNT) |
| 1183 | #define bfin_write_MDMA1_DEST_CRC1_CURR_X_COUNT(val) bfin_write32(MDMA1_DEST_CRC1_CURR_X_COUNT, val) |
| 1184 | #define bfin_read_MDMA1_DEST_CRC1_CURR_Y_COUNT() bfin_read32(MDMA1_DEST_CRC1_CURR_Y_COUNT) |
| 1185 | #define bfin_write_MDMA1_DEST_CRC1_CURR_Y_COUNT(val) bfin_write32(MDMA1_DEST_CRC1_CURR_Y_COUNT, val) |
| 1186 | #define bfin_read_MDMA1_SRC_CRC1_NEXT_DESC_PTR() bfin_read32(MDMA1_SRC_CRC1_NEXT_DESC_PTR) |
| 1187 | #define bfin_write_MDMA1_SRC_CRC1_NEXT_DESC_PTR(val) bfin_write32(MDMA1_SRC_CRC1_NEXT_DESC_PTR, val) |
| 1188 | #define bfin_read_MDMA1_SRC_CRC1_START_ADDR() bfin_read32(MDMA1_SRC_CRC1_START_ADDR) |
| 1189 | #define bfin_write_MDMA1_SRC_CRC1_START_ADDR(val) bfin_write32(MDMA1_SRC_CRC1_START_ADDR, val) |
| 1190 | #define bfin_read_MDMA1_SRC_CRC1_CONFIG() bfin_read32(MDMA1_SRC_CRC1_CONFIG) |
| 1191 | #define bfin_write_MDMA1_SRC_CRC1_CONFIG(val) bfin_write32(MDMA1_SRC_CRC1_CONFIG, val) |
| 1192 | #define bfin_read_MDMA1_SRC_CRC1_X_COUNT() bfin_read32(MDMA1_SRC_CRC1_X_COUNT) |
| 1193 | #define bfin_write_MDMA1_SRC_CRC1_X_COUNT(val) bfin_write32(MDMA1_SRC_CRC1_X_COUNT, val) |
| 1194 | #define bfin_read_MDMA1_SRC_CRC1_X_MODIFY() bfin_read32(MDMA1_SRC_CRC1_X_MODIFY) |
| 1195 | #define bfin_write_MDMA1_SRC_CRC1_X_MODIFY(val) bfin_write32(MDMA1_SRC_CRC1_X_MODIFY, val) |
| 1196 | #define bfin_read_MDMA1_SRC_CRC1_Y_COUNT() bfin_read32(MDMA1_SRC_CRC1_Y_COUNT) |
| 1197 | #define bfin_write_MDMA1_SRC_CRC1_Y_COUNT(val) bfin_write32(MDMA1_SRC_CRC1_Y_COUNT, val) |
| 1198 | #define bfin_read_MDMA1_SRC_CRC1_Y_MODIFY() bfin_read32(MDMA1_SRC_CRC1_Y_MODIFY) |
| 1199 | #define bfin_write_MDMA1_SRC_CRC1_Y_MODIFY(val) bfin_write32(MDMA1_SRC_CRC1_Y_MODIFY, val) |
| 1200 | #define bfin_read_MDMA1_SRC_CRC1_CURR_DESC_PTR() bfin_read32(MDMA1_SRC_CRC1_CURR_DESC_PTR) |
| 1201 | #define bfin_write_MDMA1_SRC_CRC1_CURR_DESC_PTR(val) bfin_write32(MDMA1_SRC_CRC1_CURR_DESC_PTR, val) |
| 1202 | #define bfin_read_MDMA1_SRC_CRC1_PREV_DESC_PTR() bfin_read32(MDMA1_SRC_CRC1_PREV_DESC_PTR) |
| 1203 | #define bfin_write_MDMA1_SRC_CRC1_PREV_DESC_PTR(val) bfin_write32(MDMA1_SRC_CRC1_PREV_DESC_PTR, val) |
| 1204 | #define bfin_read_MDMA1_SRC_CRC1_CURR_ADDR() bfin_read32(MDMA1_SRC_CRC1_CURR_ADDR) |
| 1205 | #define bfin_write_MDMA1_SRC_CRC1_CURR_ADDR(val) bfin_write32(MDMA1_SRC_CRC1_CURR_ADDR, val) |
| 1206 | #define bfin_read_MDMA1_SRC_CRC1_IRQ_STATUS() bfin_read32(MDMA1_SRC_CRC1_IRQ_STATUS) |
| 1207 | #define bfin_write_MDMA1_SRC_CRC1_IRQ_STATUS(val) bfin_write32(MDMA1_SRC_CRC1_IRQ_STATUS, val) |
| 1208 | #define bfin_read_MDMA1_SRC_CRC1_CURR_X_COUNT() bfin_read32(MDMA1_SRC_CRC1_CURR_X_COUNT) |
| 1209 | #define bfin_write_MDMA1_SRC_CRC1_CURR_X_COUNT(val) bfin_write32(MDMA1_SRC_CRC1_CURR_X_COUNT, val) |
| 1210 | #define bfin_read_MDMA1_SRC_CRC1_CURR_Y_COUNT() bfin_read32(MDMA1_SRC_CRC1_CURR_Y_COUNT) |
| 1211 | #define bfin_write_MDMA1_SRC_CRC1_CURR_Y_COUNT(val) bfin_write32(MDMA1_SRC_CRC1_CURR_Y_COUNT, val) |
| 1212 | |
| 1213 | |
| 1214 | /* MDMA Stream 2 Registers (DMA Channel 25 and 26) */ |
| 1215 | |
| 1216 | #define bfin_read_MDMA2_DEST_NEXT_DESC_PTR() bfin_read32(MDMA2_DEST_NEXT_DESC_PTR) |
| 1217 | #define bfin_write_MDMA2_DEST_NEXT_DESC_PTR(val) bfin_write32(MDMA2_DEST_NEXT_DESC_PTR, val) |
| 1218 | #define bfin_read_MDMA2_DEST_START_ADDR() bfin_read32(MDMA2_DEST_START_ADDR) |
| 1219 | #define bfin_write_MDMA2_DEST_START_ADDR(val) bfin_write32(MDMA2_DEST_START_ADDR, val) |
| 1220 | #define bfin_read_MDMA2_DEST_CONFIG() bfin_read32(MDMA2_DEST_CONFIG) |
| 1221 | #define bfin_write_MDMA2_DEST_CONFIG(val) bfin_write32(MDMA2_DEST_CONFIG, val) |
| 1222 | #define bfin_read_MDMA2_DEST_X_COUNT() bfin_read32(MDMA2_DEST_X_COUNT) |
| 1223 | #define bfin_write_MDMA2_DEST_X_COUNT(val) bfin_write32(MDMA2_DEST_X_COUNT, val) |
| 1224 | #define bfin_read_MDMA2_DEST_X_MODIFY() bfin_read32(MDMA2_DEST_X_MODIFY) |
| 1225 | #define bfin_write_MDMA2_DEST_X_MODIFY(val) bfin_write32(MDMA2_DEST_X_MODIFY, val) |
| 1226 | #define bfin_read_MDMA2_DEST_Y_COUNT() bfin_read32(MDMA2_DEST_Y_COUNT) |
| 1227 | #define bfin_write_MDMA2_DEST_Y_COUNT(val) bfin_write32(MDMA2_DEST_Y_COUNT, val) |
| 1228 | #define bfin_read_MDMA2_DEST_Y_MODIFY() bfin_read32(MDMA2_DEST_Y_MODIFY) |
| 1229 | #define bfin_write_MDMA2_DEST_Y_MODIFY(val) bfin_write32(MDMA2_DEST_Y_MODIFY, val) |
| 1230 | #define bfin_read_MDMA2_DEST_CURR_DESC_PTR() bfin_read32(MDMA2_DEST_CURR_DESC_PTR) |
| 1231 | #define bfin_write_MDMA2_DEST_CURR_DESC_PTR(val) bfin_write32(MDMA2_DEST_CURR_DESC_PTR, val) |
| 1232 | #define bfin_read_MDMA2_DEST_PREV_DESC_PTR() bfin_read32(MDMA2_DEST_PREV_DESC_PTR) |
| 1233 | #define bfin_write_MDMA2_DEST_PREV_DESC_PTR(val) bfin_write32(MDMA2_DEST_PREV_DESC_PTR, val) |
| 1234 | #define bfin_read_MDMA2_DEST_CURR_ADDR() bfin_read32(MDMA2_DEST_CURR_ADDR) |
| 1235 | #define bfin_write_MDMA2_DEST_CURR_ADDR(val) bfin_write32(MDMA2_DEST_CURR_ADDR, val) |
| 1236 | #define bfin_read_MDMA2_DEST_IRQ_STATUS() bfin_read32(MDMA2_DEST_IRQ_STATUS) |
| 1237 | #define bfin_write_MDMA2_DEST_IRQ_STATUS(val) bfin_write32(MDMA2_DEST_IRQ_STATUS, val) |
| 1238 | #define bfin_read_MDMA2_DEST_CURR_X_COUNT() bfin_read32(MDMA2_DEST_CURR_X_COUNT) |
| 1239 | #define bfin_write_MDMA2_DEST_CURR_X_COUNT(val) bfin_write32(MDMA2_DEST_CURR_X_COUNT, val) |
| 1240 | #define bfin_read_MDMA2_DEST_CURR_Y_COUNT() bfin_read32(MDMA2_DEST_CURR_Y_COUNT) |
| 1241 | #define bfin_write_MDMA2_DEST_CURR_Y_COUNT(val) bfin_write32(MDMA2_DEST_CURR_Y_COUNT, val) |
| 1242 | #define bfin_read_MDMA2_SRC_NEXT_DESC_PTR() bfin_read32(MDMA2_SRC_NEXT_DESC_PTR) |
| 1243 | #define bfin_write_MDMA2_SRC_NEXT_DESC_PTR(val) bfin_write32(MDMA2_SRC_NEXT_DESC_PTR, val) |
| 1244 | #define bfin_read_MDMA2_SRC_START_ADDR() bfin_read32(MDMA2_SRC_START_ADDR) |
| 1245 | #define bfin_write_MDMA2_SRC_START_ADDR(val) bfin_write32(MDMA2_SRC_START_ADDR, val) |
| 1246 | #define bfin_read_MDMA2_SRC_CONFIG() bfin_read32(MDMA2_SRC_CONFIG) |
| 1247 | #define bfin_write_MDMA2_SRC_CONFIG(val) bfin_write32(MDMA2_SRC_CONFIG, val) |
| 1248 | #define bfin_read_MDMA2_SRC_X_COUNT() bfin_read32(MDMA2_SRC_X_COUNT) |
| 1249 | #define bfin_write_MDMA2_SRC_X_COUNT(val) bfin_write32(MDMA2_SRC_X_COUNT, val) |
| 1250 | #define bfin_read_MDMA2_SRC_X_MODIFY() bfin_read32(MDMA2_SRC_X_MODIFY) |
| 1251 | #define bfin_write_MDMA2_SRC_X_MODIFY(val) bfin_write32(MDMA2_SRC_X_MODIFY, val) |
| 1252 | #define bfin_read_MDMA2_SRC_Y_COUNT() bfin_read32(MDMA2_SRC_Y_COUNT) |
| 1253 | #define bfin_write_MDMA2_SRC_Y_COUNT(val) bfin_write32(MDMA2_SRC_Y_COUNT, val) |
| 1254 | #define bfin_read_MDMA2_SRC_Y_MODIFY() bfin_read32(MDMA2_SRC_Y_MODIFY) |
| 1255 | #define bfin_write_MDMA2_SRC_Y_MODIFY(val) bfin_write32(MDMA2_SRC_Y_MODIFY, val) |
| 1256 | #define bfin_read_MDMA2_SRC_CURR_DESC_PTR() bfin_read32(MDMA2_SRC_CURR_DESC_PTR) |
| 1257 | #define bfin_write_MDMA2_SRC_CURR_DESC_PTR(val) bfin_write32(MDMA2_SRC_CURR_DESC_PTR, val) |
| 1258 | #define bfin_read_MDMA2_SRC_PREV_DESC_PTR() bfin_read32(MDMA2_SRC_PREV_DESC_PTR) |
| 1259 | #define bfin_write_MDMA2_SRC_PREV_DESC_PTR(val) bfin_write32(MDMA2_SRC_PREV_DESC_PTR, val) |
| 1260 | #define bfin_read_MDMA2_SRC_CURR_ADDR() bfin_read32(MDMA2_SRC_CURR_ADDR) |
| 1261 | #define bfin_write_MDMA2_SRC_CURR_ADDR(val) bfin_write32(MDMA2_SRC_CURR_ADDR, val) |
| 1262 | #define bfin_read_MDMA2_SRC_IRQ_STATUS() bfin_read32(MDMA2_SRC_IRQ_STATUS) |
| 1263 | #define bfin_write_MDMA2_SRC_IRQ_STATUS(val) bfin_write32(MDMA2_SRC_IRQ_STATUS, val) |
| 1264 | #define bfin_read_MDMA2_SRC_CURR_X_COUNT() bfin_read32(MDMA2_SRC_CURR_X_COUNT) |
| 1265 | #define bfin_write_MDMA2_SRC_CURR_X_COUNT(val) bfin_write32(MDMA2_SRC_CURR_X_COUNT, val) |
| 1266 | #define bfin_read_MDMA2_SRC_CURR_Y_COUNT() bfin_read32(MDMA2_SRC_CURR_Y_COUNT) |
| 1267 | #define bfin_write_MDMA2_SRC_CURR_Y_COUNT(val) bfin_write32(MDMA2_SRC_CURR_Y_COUNT, val) |
| 1268 | |
| 1269 | /* MDMA Stream 3 Registers (DMA Channel 27 and 28) */ |
| 1270 | |
| 1271 | #define bfin_read_MDMA3_DEST_NEXT_DESC_PTR() bfin_read32(MDMA3_DEST_NEXT_DESC_PTR) |
| 1272 | #define bfin_write_MDMA3_DEST_NEXT_DESC_PTR(val) bfin_write32(MDMA3_DEST_NEXT_DESC_PTR, val) |
| 1273 | #define bfin_read_MDMA3_DEST_START_ADDR() bfin_read32(MDMA3_DEST_START_ADDR) |
| 1274 | #define bfin_write_MDMA3_DEST_START_ADDR(val) bfin_write32(MDMA3_DEST_START_ADDR, val) |
| 1275 | #define bfin_read_MDMA3_DEST_CONFIG() bfin_read32(MDMA3_DEST_CONFIG) |
| 1276 | #define bfin_write_MDMA3_DEST_CONFIG(val) bfin_write32(MDMA3_DEST_CONFIG, val) |
| 1277 | #define bfin_read_MDMA3_DEST_X_COUNT() bfin_read32(MDMA3_DEST_X_COUNT) |
| 1278 | #define bfin_write_MDMA3_DEST_X_COUNT(val) bfin_write32(MDMA3_DEST_X_COUNT, val) |
| 1279 | #define bfin_read_MDMA3_DEST_X_MODIFY() bfin_read32(MDMA3_DEST_X_MODIFY) |
| 1280 | #define bfin_write_MDMA3_DEST_X_MODIFY(val) bfin_write32(MDMA3_DEST_X_MODIFY, val) |
| 1281 | #define bfin_read_MDMA3_DEST_Y_COUNT() bfin_read32(MDMA3_DEST_Y_COUNT) |
| 1282 | #define bfin_write_MDMA3_DEST_Y_COUNT(val) bfin_write32(MDMA3_DEST_Y_COUNT, val) |
| 1283 | #define bfin_read_MDMA3_DEST_Y_MODIFY() bfin_read32(MDMA3_DEST_Y_MODIFY) |
| 1284 | #define bfin_write_MDMA3_DEST_Y_MODIFY(val) bfin_write32(MDMA3_DEST_Y_MODIFY, val) |
| 1285 | #define bfin_read_MDMA3_DEST_CURR_DESC_PTR() bfin_read32(MDMA3_DEST_CURR_DESC_PTR) |
| 1286 | #define bfin_write_MDMA3_DEST_CURR_DESC_PTR(val) bfin_write32(MDMA3_DEST_CURR_DESC_PTR, val) |
| 1287 | #define bfin_read_MDMA3_DEST_PREV_DESC_PTR() bfin_read32(MDMA3_DEST_PREV_DESC_PTR) |
| 1288 | #define bfin_write_MDMA3_DEST_PREV_DESC_PTR(val) bfin_write32(MDMA3_DEST_PREV_DESC_PTR, val) |
| 1289 | #define bfin_read_MDMA3_DEST_CURR_ADDR() bfin_read32(MDMA3_DEST_CURR_ADDR) |
| 1290 | #define bfin_write_MDMA3_DEST_CURR_ADDR(val) bfin_write32(MDMA3_DEST_CURR_ADDR, val) |
| 1291 | #define bfin_read_MDMA3_DEST_IRQ_STATUS() bfin_read32(MDMA3_DEST_IRQ_STATUS) |
| 1292 | #define bfin_write_MDMA3_DEST_IRQ_STATUS(val) bfin_write32(MDMA3_DEST_IRQ_STATUS, val) |
| 1293 | #define bfin_read_MDMA3_DEST_CURR_X_COUNT() bfin_read32(MDMA3_DEST_CURR_X_COUNT) |
| 1294 | #define bfin_write_MDMA3_DEST_CURR_X_COUNT(val) bfin_write32(MDMA3_DEST_CURR_X_COUNT, val) |
| 1295 | #define bfin_read_MDMA3_DEST_CURR_Y_COUNT() bfin_read32(MDMA3_DEST_CURR_Y_COUNT) |
| 1296 | #define bfin_write_MDMA3_DEST_CURR_Y_COUNT(val) bfin_write32(MDMA3_DEST_CURR_Y_COUNT, val) |
| 1297 | #define bfin_read_MDMA3_SRC_NEXT_DESC_PTR() bfin_read32(MDMA3_SRC_NEXT_DESC_PTR) |
| 1298 | #define bfin_write_MDMA3_SRC_NEXT_DESC_PTR(val) bfin_write32(MDMA3_SRC_NEXT_DESC_PTR, val) |
| 1299 | #define bfin_read_MDMA3_SRC_START_ADDR() bfin_read32(MDMA3_SRC_START_ADDR) |
| 1300 | #define bfin_write_MDMA3_SRC_START_ADDR(val) bfin_write32(MDMA3_SRC_START_ADDR, val) |
| 1301 | #define bfin_read_MDMA3_SRC_CONFIG() bfin_read32(MDMA3_SRC_CONFIG) |
| 1302 | #define bfin_write_MDMA3_SRC_CONFIG(val) bfin_write32(MDMA3_SRC_CONFIG, val) |
| 1303 | #define bfin_read_MDMA3_SRC_X_COUNT() bfin_read32(MDMA3_SRC_X_COUNT) |
| 1304 | #define bfin_write_MDMA3_SRC_X_COUNT(val) bfin_write32(MDMA3_SRC_X_COUNT, val) |
| 1305 | #define bfin_read_MDMA3_SRC_X_MODIFY() bfin_read32(MDMA3_SRC_X_MODIFY) |
| 1306 | #define bfin_write_MDMA3_SRC_X_MODIFY(val) bfin_write32(MDMA3_SRC_X_MODIFY, val) |
| 1307 | #define bfin_read_MDMA3_SRC_Y_COUNT() bfin_read32(MDMA3_SRC_Y_COUNT) |
| 1308 | #define bfin_write_MDMA3_SRC_Y_COUNT(val) bfin_write32(MDMA3_SRC_Y_COUNT, val) |
| 1309 | #define bfin_read_MDMA3_SRC_Y_MODIFY() bfin_read32(MDMA3_SRC_Y_MODIFY) |
| 1310 | #define bfin_write_MDMA3_SRC_Y_MODIFY(val) bfin_write32(MDMA3_SRC_Y_MODIFY, val) |
| 1311 | #define bfin_read_MDMA3_SRC_CURR_DESC_PTR() bfin_read32(MDMA3_SRC_CURR_DESC_PTR) |
| 1312 | #define bfin_write_MDMA3_SRC_CURR_DESC_PTR(val) bfin_write32(MDMA3_SRC_CURR_DESC_PTR, val) |
| 1313 | #define bfin_read_MDMA3_SRC_PREV_DESC_PTR() bfin_read32(MDMA3_SRC_PREV_DESC_PTR) |
| 1314 | #define bfin_write_MDMA3_SRC_PREV_DESC_PTR(val) bfin_write32(MDMA3_SRC_PREV_DESC_PTR, val) |
| 1315 | #define bfin_read_MDMA3_SRC_CURR_ADDR() bfin_read32(MDMA3_SRC_CURR_ADDR) |
| 1316 | #define bfin_write_MDMA3_SRC_CURR_ADDR(val) bfin_write32(MDMA3_SRC_CURR_ADDR, val) |
| 1317 | #define bfin_read_MDMA3_SRC_IRQ_STATUS() bfin_read32(MDMA3_SRC_IRQ_STATUS) |
| 1318 | #define bfin_write_MDMA3_SRC_IRQ_STATUS(val) bfin_write32(MDMA3_SRC_IRQ_STATUS, val) |
| 1319 | #define bfin_read_MDMA3_SRC_CURR_X_COUNT() bfin_read32(MDMA3_SRC_CURR_X_COUNT) |
| 1320 | #define bfin_write_MDMA3_SRC_CURR_X_COUNT(val) bfin_write32(MDMA3_SRC_CURR_X_COUNT, val) |
| 1321 | #define bfin_read_MDMA3_SRC_CURR_Y_COUNT() bfin_read32(MDMA3_SRC_CURR_Y_COUNT) |
| 1322 | #define bfin_write_MDMA3_SRC_CURR_Y_COUNT(val) bfin_write32(MDMA3_SRC_CURR_Y_COUNT, val) |
| 1323 | |
| 1324 | |
| 1325 | /* DMA Channel 29 Registers */ |
| 1326 | |
| 1327 | #define bfin_read_DMA29_NEXT_DESC_PTR() bfin_read32(DMA29_NEXT_DESC_PTR) |
| 1328 | #define bfin_write_DMA29_NEXT_DESC_PTR(val) bfin_write32(DMA29_NEXT_DESC_PTR, val) |
| 1329 | #define bfin_read_DMA29_START_ADDR() bfin_read32(DMA29_START_ADDR) |
| 1330 | #define bfin_write_DMA29_START_ADDR(val) bfin_write32(DMA29_START_ADDR, val) |
| 1331 | #define bfin_read_DMA29_CONFIG() bfin_read32(DMA29_CONFIG) |
| 1332 | #define bfin_write_DMA29_CONFIG(val) bfin_write32(DMA29_CONFIG, val) |
| 1333 | #define bfin_read_DMA29_X_COUNT() bfin_read32(DMA29_X_COUNT) |
| 1334 | #define bfin_write_DMA29_X_COUNT(val) bfin_write32(DMA29_X_COUNT, val) |
| 1335 | #define bfin_read_DMA29_X_MODIFY() bfin_read32(DMA29_X_MODIFY) |
| 1336 | #define bfin_write_DMA29_X_MODIFY(val) bfin_write32(DMA29_X_MODIFY, val) |
| 1337 | #define bfin_read_DMA29_Y_COUNT() bfin_read32(DMA29_Y_COUNT) |
| 1338 | #define bfin_write_DMA29_Y_COUNT(val) bfin_write32(DMA29_Y_COUNT, val) |
| 1339 | #define bfin_read_DMA29_Y_MODIFY() bfin_read32(DMA29_Y_MODIFY) |
| 1340 | #define bfin_write_DMA29_Y_MODIFY(val) bfin_write32(DMA29_Y_MODIFY, val) |
| 1341 | #define bfin_read_DMA29_CURR_DESC_PTR() bfin_read32(DMA29_CURR_DESC_PTR) |
| 1342 | #define bfin_write_DMA29_CURR_DESC_PTR(val) bfin_write32(DMA29_CURR_DESC_PTR, val) |
| 1343 | #define bfin_read_DMA29_PREV_DESC_PTR() bfin_read32(DMA29_PREV_DESC_PTR) |
| 1344 | #define bfin_write_DMA29_PREV_DESC_PTR(val) bfin_write32(DMA29_PREV_DESC_PTR, val) |
| 1345 | #define bfin_read_DMA29_CURR_ADDR() bfin_read32(DMA29_CURR_ADDR) |
| 1346 | #define bfin_write_DMA29_CURR_ADDR(val) bfin_write32(DMA29_CURR_ADDR, val) |
| 1347 | #define bfin_read_DMA29_IRQ_STATUS() bfin_read32(DMA29_IRQ_STATUS) |
| 1348 | #define bfin_write_DMA29_IRQ_STATUS(val) bfin_write32(DMA29_IRQ_STATUS, val) |
| 1349 | #define bfin_read_DMA29_CURR_X_COUNT() bfin_read32(DMA29_CURR_X_COUNT) |
| 1350 | #define bfin_write_DMA29_CURR_X_COUNT(val) bfin_write32(DMA29_CURR_X_COUNT, val) |
| 1351 | #define bfin_read_DMA29_CURR_Y_COUNT() bfin_read32(DMA29_CURR_Y_COUNT) |
| 1352 | #define bfin_write_DMA29_CURR_Y_COUNT(val) bfin_write32(DMA29_CURR_Y_COUNT, val) |
| 1353 | #define bfin_read_DMA29_BWL_COUNT() bfin_read32(DMA29_BWL_COUNT) |
| 1354 | #define bfin_write_DMA29_BWL_COUNT(val) bfin_write32(DMA29_BWL_COUNT, val) |
| 1355 | #define bfin_read_DMA29_CURR_BWL_COUNT() bfin_read32(DMA29_CURR_BWL_COUNT) |
| 1356 | #define bfin_write_DMA29_CURR_BWL_COUNT(val) bfin_write32(DMA29_CURR_BWL_COUNT, val) |
| 1357 | #define bfin_read_DMA29_BWM_COUNT() bfin_read32(DMA29_BWM_COUNT) |
| 1358 | #define bfin_write_DMA29_BWM_COUNT(val) bfin_write32(DMA29_BWM_COUNT, val) |
| 1359 | #define bfin_read_DMA29_CURR_BWM_COUNT() bfin_read32(DMA29_CURR_BWM_COUNT) |
| 1360 | #define bfin_write_DMA29_CURR_BWM_COUNT(val) bfin_write32(DMA29_CURR_BWM_COUNT, val) |
| 1361 | |
| 1362 | /* DMA Channel 30 Registers */ |
| 1363 | |
| 1364 | #define bfin_read_DMA30_NEXT_DESC_PTR() bfin_read32(DMA30_NEXT_DESC_PTR) |
| 1365 | #define bfin_write_DMA30_NEXT_DESC_PTR(val) bfin_write32(DMA30_NEXT_DESC_PTR, val) |
| 1366 | #define bfin_read_DMA30_START_ADDR() bfin_read32(DMA30_START_ADDR) |
| 1367 | #define bfin_write_DMA30_START_ADDR(val) bfin_write32(DMA30_START_ADDR, val) |
| 1368 | #define bfin_read_DMA30_CONFIG() bfin_read32(DMA30_CONFIG) |
| 1369 | #define bfin_write_DMA30_CONFIG(val) bfin_write32(DMA30_CONFIG, val) |
| 1370 | #define bfin_read_DMA30_X_COUNT() bfin_read32(DMA30_X_COUNT) |
| 1371 | #define bfin_write_DMA30_X_COUNT(val) bfin_write32(DMA30_X_COUNT, val) |
| 1372 | #define bfin_read_DMA30_X_MODIFY() bfin_read32(DMA30_X_MODIFY) |
| 1373 | #define bfin_write_DMA30_X_MODIFY(val) bfin_write32(DMA30_X_MODIFY, val) |
| 1374 | #define bfin_read_DMA30_Y_COUNT() bfin_read32(DMA30_Y_COUNT) |
| 1375 | #define bfin_write_DMA30_Y_COUNT(val) bfin_write32(DMA30_Y_COUNT, val) |
| 1376 | #define bfin_read_DMA30_Y_MODIFY() bfin_read32(DMA30_Y_MODIFY) |
| 1377 | #define bfin_write_DMA30_Y_MODIFY(val) bfin_write32(DMA30_Y_MODIFY, val) |
| 1378 | #define bfin_read_DMA30_CURR_DESC_PTR() bfin_read32(DMA30_CURR_DESC_PTR) |
| 1379 | #define bfin_write_DMA30_CURR_DESC_PTR(val) bfin_write32(DMA30_CURR_DESC_PTR, val) |
| 1380 | #define bfin_read_DMA30_PREV_DESC_PTR() bfin_read32(DMA30_PREV_DESC_PTR) |
| 1381 | #define bfin_write_DMA30_PREV_DESC_PTR(val) bfin_write32(DMA30_PREV_DESC_PTR, val) |
| 1382 | #define bfin_read_DMA30_CURR_ADDR() bfin_read32(DMA30_CURR_ADDR) |
| 1383 | #define bfin_write_DMA30_CURR_ADDR(val) bfin_write32(DMA30_CURR_ADDR, val) |
| 1384 | #define bfin_read_DMA30_IRQ_STATUS() bfin_read32(DMA30_IRQ_STATUS) |
| 1385 | #define bfin_write_DMA30_IRQ_STATUS(val) bfin_write32(DMA30_IRQ_STATUS, val) |
| 1386 | #define bfin_read_DMA30_CURR_X_COUNT() bfin_read32(DMA30_CURR_X_COUNT) |
| 1387 | #define bfin_write_DMA30_CURR_X_COUNT(val) bfin_write32(DMA30_CURR_X_COUNT, val) |
| 1388 | #define bfin_read_DMA30_CURR_Y_COUNT() bfin_read32(DMA30_CURR_Y_COUNT) |
| 1389 | #define bfin_write_DMA30_CURR_Y_COUNT(val) bfin_write32(DMA30_CURR_Y_COUNT, val) |
| 1390 | #define bfin_read_DMA30_BWL_COUNT() bfin_read32(DMA30_BWL_COUNT) |
| 1391 | #define bfin_write_DMA30_BWL_COUNT(val) bfin_write32(DMA30_BWL_COUNT, val) |
| 1392 | #define bfin_read_DMA30_CURR_BWL_COUNT() bfin_read32(DMA30_CURR_BWL_COUNT) |
| 1393 | #define bfin_write_DMA30_CURR_BWL_COUNT(val) bfin_write32(DMA30_CURR_BWL_COUNT, val) |
| 1394 | #define bfin_read_DMA30_BWM_COUNT() bfin_read32(DMA30_BWM_COUNT) |
| 1395 | #define bfin_write_DMA30_BWM_COUNT(val) bfin_write32(DMA30_BWM_COUNT, val) |
| 1396 | #define bfin_read_DMA30_CURR_BWM_COUNT() bfin_read32(DMA30_CURR_BWM_COUNT) |
| 1397 | #define bfin_write_DMA30_CURR_BWM_COUNT(val) bfin_write32(DMA30_CURR_BWM_COUNT, val) |
| 1398 | |
| 1399 | /* DMA Channel 31 Registers */ |
| 1400 | |
| 1401 | #define bfin_read_DMA31_NEXT_DESC_PTR() bfin_read32(DMA31_NEXT_DESC_PTR) |
| 1402 | #define bfin_write_DMA31_NEXT_DESC_PTR(val) bfin_write32(DMA31_NEXT_DESC_PTR, val) |
| 1403 | #define bfin_read_DMA31_START_ADDR() bfin_read32(DMA31_START_ADDR) |
| 1404 | #define bfin_write_DMA31_START_ADDR(val) bfin_write32(DMA31_START_ADDR, val) |
| 1405 | #define bfin_read_DMA31_CONFIG() bfin_read32(DMA31_CONFIG) |
| 1406 | #define bfin_write_DMA31_CONFIG(val) bfin_write32(DMA31_CONFIG, val) |
| 1407 | #define bfin_read_DMA31_X_COUNT() bfin_read32(DMA31_X_COUNT) |
| 1408 | #define bfin_write_DMA31_X_COUNT(val) bfin_write32(DMA31_X_COUNT, val) |
| 1409 | #define bfin_read_DMA31_X_MODIFY() bfin_read32(DMA31_X_MODIFY) |
| 1410 | #define bfin_write_DMA31_X_MODIFY(val) bfin_write32(DMA31_X_MODIFY, val) |
| 1411 | #define bfin_read_DMA31_Y_COUNT() bfin_read32(DMA31_Y_COUNT) |
| 1412 | #define bfin_write_DMA31_Y_COUNT(val) bfin_write32(DMA31_Y_COUNT, val) |
| 1413 | #define bfin_read_DMA31_Y_MODIFY() bfin_read32(DMA31_Y_MODIFY) |
| 1414 | #define bfin_write_DMA31_Y_MODIFY(val) bfin_write32(DMA31_Y_MODIFY, val) |
| 1415 | #define bfin_read_DMA31_CURR_DESC_PTR() bfin_read32(DMA31_CURR_DESC_PTR) |
| 1416 | #define bfin_write_DMA31_CURR_DESC_PTR(val) bfin_write32(DMA31_CURR_DESC_PTR, val) |
| 1417 | #define bfin_read_DMA31_PREV_DESC_PTR() bfin_read32(DMA31_PREV_DESC_PTR) |
| 1418 | #define bfin_write_DMA31_PREV_DESC_PTR(val) bfin_write32(DMA31_PREV_DESC_PTR, val) |
| 1419 | #define bfin_read_DMA31_CURR_ADDR() bfin_read32(DMA31_CURR_ADDR) |
| 1420 | #define bfin_write_DMA31_CURR_ADDR(val) bfin_write32(DMA31_CURR_ADDR, val) |
| 1421 | #define bfin_read_DMA31_IRQ_STATUS() bfin_read32(DMA31_IRQ_STATUS) |
| 1422 | #define bfin_write_DMA31_IRQ_STATUS(val) bfin_write32(DMA31_IRQ_STATUS, val) |
| 1423 | #define bfin_read_DMA31_CURR_X_COUNT() bfin_read32(DMA31_CURR_X_COUNT) |
| 1424 | #define bfin_write_DMA31_CURR_X_COUNT(val) bfin_write32(DMA31_CURR_X_COUNT, val) |
| 1425 | #define bfin_read_DMA31_CURR_Y_COUNT() bfin_read32(DMA31_CURR_Y_COUNT) |
| 1426 | #define bfin_write_DMA31_CURR_Y_COUNT(val) bfin_write32(DMA31_CURR_Y_COUNT, val) |
| 1427 | #define bfin_read_DMA31_BWL_COUNT() bfin_read32(DMA31_BWL_COUNT) |
| 1428 | #define bfin_write_DMA31_BWL_COUNT(val) bfin_write32(DMA31_BWL_COUNT, val) |
| 1429 | #define bfin_read_DMA31_CURR_BWL_COUNT() bfin_read32(DMA31_CURR_BWL_COUNT) |
| 1430 | #define bfin_write_DMA31_CURR_BWL_COUNT(val) bfin_write32(DMA31_CURR_BWL_COUNT, val) |
| 1431 | #define bfin_read_DMA31_BWM_COUNT() bfin_read32(DMA31_BWM_COUNT) |
| 1432 | #define bfin_write_DMA31_BWM_COUNT(val) bfin_write32(DMA31_BWM_COUNT, val) |
| 1433 | #define bfin_read_DMA31_CURR_BWM_COUNT() bfin_read32(DMA31_CURR_BWM_COUNT) |
| 1434 | #define bfin_write_DMA31_CURR_BWM_COUNT(val) bfin_write32(DMA31_CURR_BWM_COUNT, val) |
| 1435 | |
| 1436 | /* DMA Channel 32 Registers */ |
| 1437 | |
| 1438 | #define bfin_read_DMA32_NEXT_DESC_PTR() bfin_read32(DMA32_NEXT_DESC_PTR) |
| 1439 | #define bfin_write_DMA32_NEXT_DESC_PTR(val) bfin_write32(DMA32_NEXT_DESC_PTR, val) |
| 1440 | #define bfin_read_DMA32_START_ADDR() bfin_read32(DMA32_START_ADDR) |
| 1441 | #define bfin_write_DMA32_START_ADDR(val) bfin_write32(DMA32_START_ADDR, val) |
| 1442 | #define bfin_read_DMA32_CONFIG() bfin_read32(DMA32_CONFIG) |
| 1443 | #define bfin_write_DMA32_CONFIG(val) bfin_write32(DMA32_CONFIG, val) |
| 1444 | #define bfin_read_DMA32_X_COUNT() bfin_read32(DMA32_X_COUNT) |
| 1445 | #define bfin_write_DMA32_X_COUNT(val) bfin_write32(DMA32_X_COUNT, val) |
| 1446 | #define bfin_read_DMA32_X_MODIFY() bfin_read32(DMA32_X_MODIFY) |
| 1447 | #define bfin_write_DMA32_X_MODIFY(val) bfin_write32(DMA32_X_MODIFY, val) |
| 1448 | #define bfin_read_DMA32_Y_COUNT() bfin_read32(DMA32_Y_COUNT) |
| 1449 | #define bfin_write_DMA32_Y_COUNT(val) bfin_write32(DMA32_Y_COUNT, val) |
| 1450 | #define bfin_read_DMA32_Y_MODIFY() bfin_read32(DMA32_Y_MODIFY) |
| 1451 | #define bfin_write_DMA32_Y_MODIFY(val) bfin_write32(DMA32_Y_MODIFY, val) |
| 1452 | #define bfin_read_DMA32_CURR_DESC_PTR() bfin_read32(DMA32_CURR_DESC_PTR) |
| 1453 | #define bfin_write_DMA32_CURR_DESC_PTR(val) bfin_write32(DMA32_CURR_DESC_PTR, val) |
| 1454 | #define bfin_read_DMA32_PREV_DESC_PTR() bfin_read32(DMA32_PREV_DESC_PTR) |
| 1455 | #define bfin_write_DMA32_PREV_DESC_PTR(val) bfin_write32(DMA32_PREV_DESC_PTR, val) |
| 1456 | #define bfin_read_DMA32_CURR_ADDR() bfin_read32(DMA32_CURR_ADDR) |
| 1457 | #define bfin_write_DMA32_CURR_ADDR(val) bfin_write32(DMA32_CURR_ADDR, val) |
| 1458 | #define bfin_read_DMA32_IRQ_STATUS() bfin_read32(DMA32_IRQ_STATUS) |
| 1459 | #define bfin_write_DMA32_IRQ_STATUS(val) bfin_write32(DMA32_IRQ_STATUS, val) |
| 1460 | #define bfin_read_DMA32_CURR_X_COUNT() bfin_read32(DMA32_CURR_X_COUNT) |
| 1461 | #define bfin_write_DMA32_CURR_X_COUNT(val) bfin_write32(DMA32_CURR_X_COUNT, val) |
| 1462 | #define bfin_read_DMA32_CURR_Y_COUNT() bfin_read32(DMA32_CURR_Y_COUNT) |
| 1463 | #define bfin_write_DMA32_CURR_Y_COUNT(val) bfin_write32(DMA32_CURR_Y_COUNT, val) |
| 1464 | #define bfin_read_DMA32_BWL_COUNT() bfin_read32(DMA32_BWL_COUNT) |
| 1465 | #define bfin_write_DMA32_BWL_COUNT(val) bfin_write32(DMA32_BWL_COUNT, val) |
| 1466 | #define bfin_read_DMA32_CURR_BWL_COUNT() bfin_read32(DMA32_CURR_BWL_COUNT) |
| 1467 | #define bfin_write_DMA32_CURR_BWL_COUNT(val) bfin_write32(DMA32_CURR_BWL_COUNT, val) |
| 1468 | #define bfin_read_DMA32_BWM_COUNT() bfin_read32(DMA32_BWM_COUNT) |
| 1469 | #define bfin_write_DMA32_BWM_COUNT(val) bfin_write32(DMA32_BWM_COUNT, val) |
| 1470 | #define bfin_read_DMA32_CURR_BWM_COUNT() bfin_read32(DMA32_CURR_BWM_COUNT) |
| 1471 | #define bfin_write_DMA32_CURR_BWM_COUNT(val) bfin_write32(DMA32_CURR_BWM_COUNT, val) |
| 1472 | |
| 1473 | /* DMA Channel 33 Registers */ |
| 1474 | |
| 1475 | #define bfin_read_DMA33_NEXT_DESC_PTR() bfin_read32(DMA33_NEXT_DESC_PTR) |
| 1476 | #define bfin_write_DMA33_NEXT_DESC_PTR(val) bfin_write32(DMA33_NEXT_DESC_PTR, val) |
| 1477 | #define bfin_read_DMA33_START_ADDR() bfin_read32(DMA33_START_ADDR) |
| 1478 | #define bfin_write_DMA33_START_ADDR(val) bfin_write32(DMA33_START_ADDR, val) |
| 1479 | #define bfin_read_DMA33_CONFIG() bfin_read32(DMA33_CONFIG) |
| 1480 | #define bfin_write_DMA33_CONFIG(val) bfin_write32(DMA33_CONFIG, val) |
| 1481 | #define bfin_read_DMA33_X_COUNT() bfin_read32(DMA33_X_COUNT) |
| 1482 | #define bfin_write_DMA33_X_COUNT(val) bfin_write32(DMA33_X_COUNT, val) |
| 1483 | #define bfin_read_DMA33_X_MODIFY() bfin_read32(DMA33_X_MODIFY) |
| 1484 | #define bfin_write_DMA33_X_MODIFY(val) bfin_write32(DMA33_X_MODIFY, val) |
| 1485 | #define bfin_read_DMA33_Y_COUNT() bfin_read32(DMA33_Y_COUNT) |
| 1486 | #define bfin_write_DMA33_Y_COUNT(val) bfin_write32(DMA33_Y_COUNT, val) |
| 1487 | #define bfin_read_DMA33_Y_MODIFY() bfin_read32(DMA33_Y_MODIFY) |
| 1488 | #define bfin_write_DMA33_Y_MODIFY(val) bfin_write32(DMA33_Y_MODIFY, val) |
| 1489 | #define bfin_read_DMA33_CURR_DESC_PTR() bfin_read32(DMA33_CURR_DESC_PTR) |
| 1490 | #define bfin_write_DMA33_CURR_DESC_PTR(val) bfin_write32(DMA33_CURR_DESC_PTR, val) |
| 1491 | #define bfin_read_DMA33_PREV_DESC_PTR() bfin_read32(DMA33_PREV_DESC_PTR) |
| 1492 | #define bfin_write_DMA33_PREV_DESC_PTR(val) bfin_write32(DMA33_PREV_DESC_PTR, val) |
| 1493 | #define bfin_read_DMA33_CURR_ADDR() bfin_read32(DMA33_CURR_ADDR) |
| 1494 | #define bfin_write_DMA33_CURR_ADDR(val) bfin_write32(DMA33_CURR_ADDR, val) |
| 1495 | #define bfin_read_DMA33_IRQ_STATUS() bfin_read32(DMA33_IRQ_STATUS) |
| 1496 | #define bfin_write_DMA33_IRQ_STATUS(val) bfin_write32(DMA33_IRQ_STATUS, val) |
| 1497 | #define bfin_read_DMA33_CURR_X_COUNT() bfin_read32(DMA33_CURR_X_COUNT) |
| 1498 | #define bfin_write_DMA33_CURR_X_COUNT(val) bfin_write32(DMA33_CURR_X_COUNT, val) |
| 1499 | #define bfin_read_DMA33_CURR_Y_COUNT() bfin_read32(DMA33_CURR_Y_COUNT) |
| 1500 | #define bfin_write_DMA33_CURR_Y_COUNT(val) bfin_write32(DMA33_CURR_Y_COUNT, val) |
| 1501 | #define bfin_read_DMA33_BWL_COUNT() bfin_read32(DMA33_BWL_COUNT) |
| 1502 | #define bfin_write_DMA33_BWL_COUNT(val) bfin_write32(DMA33_BWL_COUNT, val) |
| 1503 | #define bfin_read_DMA33_CURR_BWL_COUNT() bfin_read32(DMA33_CURR_BWL_COUNT) |
| 1504 | #define bfin_write_DMA33_CURR_BWL_COUNT(val) bfin_write32(DMA33_CURR_BWL_COUNT, val) |
| 1505 | #define bfin_read_DMA33_BWM_COUNT() bfin_read32(DMA33_BWM_COUNT) |
| 1506 | #define bfin_write_DMA33_BWM_COUNT(val) bfin_write32(DMA33_BWM_COUNT, val) |
| 1507 | #define bfin_read_DMA33_CURR_BWM_COUNT() bfin_read32(DMA33_CURR_BWM_COUNT) |
| 1508 | #define bfin_write_DMA33_CURR_BWM_COUNT(val) bfin_write32(DMA33_CURR_BWM_COUNT, val) |
| 1509 | |
| 1510 | /* DMA Channel 34 Registers */ |
| 1511 | |
| 1512 | #define bfin_read_DMA34_NEXT_DESC_PTR() bfin_read32(DMA34_NEXT_DESC_PTR) |
| 1513 | #define bfin_write_DMA34_NEXT_DESC_PTR(val) bfin_write32(DMA34_NEXT_DESC_PTR, val) |
| 1514 | #define bfin_read_DMA34_START_ADDR() bfin_read32(DMA34_START_ADDR) |
| 1515 | #define bfin_write_DMA34_START_ADDR(val) bfin_write32(DMA34_START_ADDR, val) |
| 1516 | #define bfin_read_DMA34_CONFIG() bfin_read32(DMA34_CONFIG) |
| 1517 | #define bfin_write_DMA34_CONFIG(val) bfin_write32(DMA34_CONFIG, val) |
| 1518 | #define bfin_read_DMA34_X_COUNT() bfin_read32(DMA34_X_COUNT) |
| 1519 | #define bfin_write_DMA34_X_COUNT(val) bfin_write32(DMA34_X_COUNT, val) |
| 1520 | #define bfin_read_DMA34_X_MODIFY() bfin_read32(DMA34_X_MODIFY) |
| 1521 | #define bfin_write_DMA34_X_MODIFY(val) bfin_write32(DMA34_X_MODIFY, val) |
| 1522 | #define bfin_read_DMA34_Y_COUNT() bfin_read32(DMA34_Y_COUNT) |
| 1523 | #define bfin_write_DMA34_Y_COUNT(val) bfin_write32(DMA34_Y_COUNT, val) |
| 1524 | #define bfin_read_DMA34_Y_MODIFY() bfin_read32(DMA34_Y_MODIFY) |
| 1525 | #define bfin_write_DMA34_Y_MODIFY(val) bfin_write32(DMA34_Y_MODIFY, val) |
| 1526 | #define bfin_read_DMA34_CURR_DESC_PTR() bfin_read32(DMA34_CURR_DESC_PTR) |
| 1527 | #define bfin_write_DMA34_CURR_DESC_PTR(val) bfin_write32(DMA34_CURR_DESC_PTR, val) |
| 1528 | #define bfin_read_DMA34_PREV_DESC_PTR() bfin_read32(DMA34_PREV_DESC_PTR) |
| 1529 | #define bfin_write_DMA34_PREV_DESC_PTR(val) bfin_write32(DMA34_PREV_DESC_PTR, val) |
| 1530 | #define bfin_read_DMA34_CURR_ADDR() bfin_read32(DMA34_CURR_ADDR) |
| 1531 | #define bfin_write_DMA34_CURR_ADDR(val) bfin_write32(DMA34_CURR_ADDR, val) |
| 1532 | #define bfin_read_DMA34_IRQ_STATUS() bfin_read32(DMA34_IRQ_STATUS) |
| 1533 | #define bfin_write_DMA34_IRQ_STATUS(val) bfin_write32(DMA34_IRQ_STATUS, val) |
| 1534 | #define bfin_read_DMA34_CURR_X_COUNT() bfin_read32(DMA34_CURR_X_COUNT) |
| 1535 | #define bfin_write_DMA34_CURR_X_COUNT(val) bfin_write32(DMA34_CURR_X_COUNT, val) |
| 1536 | #define bfin_read_DMA34_CURR_Y_COUNT() bfin_read32(DMA34_CURR_Y_COUNT) |
| 1537 | #define bfin_write_DMA34_CURR_Y_COUNT(val) bfin_write32(DMA34_CURR_Y_COUNT, val) |
| 1538 | #define bfin_read_DMA34_BWL_COUNT() bfin_read32(DMA34_BWL_COUNT) |
| 1539 | #define bfin_write_DMA34_BWL_COUNT(val) bfin_write32(DMA34_BWL_COUNT, val) |
| 1540 | #define bfin_read_DMA34_CURR_BWL_COUNT() bfin_read32(DMA34_CURR_BWL_COUNT) |
| 1541 | #define bfin_write_DMA34_CURR_BWL_COUNT(val) bfin_write32(DMA34_CURR_BWL_COUNT, val) |
| 1542 | #define bfin_read_DMA34_BWM_COUNT() bfin_read32(DMA34_BWM_COUNT) |
| 1543 | #define bfin_write_DMA34_BWM_COUNT(val) bfin_write32(DMA34_BWM_COUNT, val) |
| 1544 | #define bfin_read_DMA34_CURR_BWM_COUNT() bfin_read32(DMA34_CURR_BWM_COUNT) |
| 1545 | #define bfin_write_DMA34_CURR_BWM_COUNT(val) bfin_write32(DMA34_CURR_BWM_COUNT, val) |
| 1546 | |
| 1547 | /* DMA Channel 35 Registers */ |
| 1548 | |
| 1549 | #define bfin_read_DMA35_NEXT_DESC_PTR() bfin_read32(DMA35_NEXT_DESC_PTR) |
| 1550 | #define bfin_write_DMA35_NEXT_DESC_PTR(val) bfin_write32(DMA35_NEXT_DESC_PTR, val) |
| 1551 | #define bfin_read_DMA35_START_ADDR() bfin_read32(DMA35_START_ADDR) |
| 1552 | #define bfin_write_DMA35_START_ADDR(val) bfin_write32(DMA35_START_ADDR, val) |
| 1553 | #define bfin_read_DMA35_CONFIG() bfin_read32(DMA35_CONFIG) |
| 1554 | #define bfin_write_DMA35_CONFIG(val) bfin_write32(DMA35_CONFIG, val) |
| 1555 | #define bfin_read_DMA35_X_COUNT() bfin_read32(DMA35_X_COUNT) |
| 1556 | #define bfin_write_DMA35_X_COUNT(val) bfin_write32(DMA35_X_COUNT, val) |
| 1557 | #define bfin_read_DMA35_X_MODIFY() bfin_read32(DMA35_X_MODIFY) |
| 1558 | #define bfin_write_DMA35_X_MODIFY(val) bfin_write32(DMA35_X_MODIFY, val) |
| 1559 | #define bfin_read_DMA35_Y_COUNT() bfin_read32(DMA35_Y_COUNT) |
| 1560 | #define bfin_write_DMA35_Y_COUNT(val) bfin_write32(DMA35_Y_COUNT, val) |
| 1561 | #define bfin_read_DMA35_Y_MODIFY() bfin_read32(DMA35_Y_MODIFY) |
| 1562 | #define bfin_write_DMA35_Y_MODIFY(val) bfin_write32(DMA35_Y_MODIFY, val) |
| 1563 | #define bfin_read_DMA35_CURR_DESC_PTR() bfin_read32(DMA35_CURR_DESC_PTR) |
| 1564 | #define bfin_write_DMA35_CURR_DESC_PTR(val) bfin_write32(DMA35_CURR_DESC_PTR, val) |
| 1565 | #define bfin_read_DMA35_PREV_DESC_PTR() bfin_read32(DMA35_PREV_DESC_PTR) |
| 1566 | #define bfin_write_DMA35_PREV_DESC_PTR(val) bfin_write32(DMA35_PREV_DESC_PTR, val) |
| 1567 | #define bfin_read_DMA35_CURR_ADDR() bfin_read32(DMA35_CURR_ADDR) |
| 1568 | #define bfin_write_DMA35_CURR_ADDR(val) bfin_write32(DMA35_CURR_ADDR, val) |
| 1569 | #define bfin_read_DMA35_IRQ_STATUS() bfin_read32(DMA35_IRQ_STATUS) |
| 1570 | #define bfin_write_DMA35_IRQ_STATUS(val) bfin_write32(DMA35_IRQ_STATUS, val) |
| 1571 | #define bfin_read_DMA35_CURR_X_COUNT() bfin_read32(DMA35_CURR_X_COUNT) |
| 1572 | #define bfin_write_DMA35_CURR_X_COUNT(val) bfin_write32(DMA35_CURR_X_COUNT, val) |
| 1573 | #define bfin_read_DMA35_CURR_Y_COUNT() bfin_read32(DMA35_CURR_Y_COUNT) |
| 1574 | #define bfin_write_DMA35_CURR_Y_COUNT(val) bfin_write32(DMA35_CURR_Y_COUNT, val) |
| 1575 | #define bfin_read_DMA35_BWL_COUNT() bfin_read32(DMA35_BWL_COUNT) |
| 1576 | #define bfin_write_DMA35_BWL_COUNT(val) bfin_write32(DMA35_BWL_COUNT, val) |
| 1577 | #define bfin_read_DMA35_CURR_BWL_COUNT() bfin_read32(DMA35_CURR_BWL_COUNT) |
| 1578 | #define bfin_write_DMA35_CURR_BWL_COUNT(val) bfin_write32(DMA35_CURR_BWL_COUNT, val) |
| 1579 | #define bfin_read_DMA35_BWM_COUNT() bfin_read32(DMA35_BWM_COUNT) |
| 1580 | #define bfin_write_DMA35_BWM_COUNT(val) bfin_write32(DMA35_BWM_COUNT, val) |
| 1581 | #define bfin_read_DMA35_CURR_BWM_COUNT() bfin_read32(DMA35_CURR_BWM_COUNT) |
| 1582 | #define bfin_write_DMA35_CURR_BWM_COUNT(val) bfin_write32(DMA35_CURR_BWM_COUNT, val) |
| 1583 | |
| 1584 | /* DMA Channel 36 Registers */ |
| 1585 | |
| 1586 | #define bfin_read_DMA36_NEXT_DESC_PTR() bfin_read32(DMA36_NEXT_DESC_PTR) |
| 1587 | #define bfin_write_DMA36_NEXT_DESC_PTR(val) bfin_write32(DMA36_NEXT_DESC_PTR, val) |
| 1588 | #define bfin_read_DMA36_START_ADDR() bfin_read32(DMA36_START_ADDR) |
| 1589 | #define bfin_write_DMA36_START_ADDR(val) bfin_write32(DMA36_START_ADDR, val) |
| 1590 | #define bfin_read_DMA36_CONFIG() bfin_read32(DMA36_CONFIG) |
| 1591 | #define bfin_write_DMA36_CONFIG(val) bfin_write32(DMA36_CONFIG, val) |
| 1592 | #define bfin_read_DMA36_X_COUNT() bfin_read32(DMA36_X_COUNT) |
| 1593 | #define bfin_write_DMA36_X_COUNT(val) bfin_write32(DMA36_X_COUNT, val) |
| 1594 | #define bfin_read_DMA36_X_MODIFY() bfin_read32(DMA36_X_MODIFY) |
| 1595 | #define bfin_write_DMA36_X_MODIFY(val) bfin_write32(DMA36_X_MODIFY, val) |
| 1596 | #define bfin_read_DMA36_Y_COUNT() bfin_read32(DMA36_Y_COUNT) |
| 1597 | #define bfin_write_DMA36_Y_COUNT(val) bfin_write32(DMA36_Y_COUNT, val) |
| 1598 | #define bfin_read_DMA36_Y_MODIFY() bfin_read32(DMA36_Y_MODIFY) |
| 1599 | #define bfin_write_DMA36_Y_MODIFY(val) bfin_write32(DMA36_Y_MODIFY, val) |
| 1600 | #define bfin_read_DMA36_CURR_DESC_PTR() bfin_read32(DMA36_CURR_DESC_PTR) |
| 1601 | #define bfin_write_DMA36_CURR_DESC_PTR(val) bfin_write32(DMA36_CURR_DESC_PTR, val) |
| 1602 | #define bfin_read_DMA36_PREV_DESC_PTR() bfin_read32(DMA36_PREV_DESC_PTR) |
| 1603 | #define bfin_write_DMA36_PREV_DESC_PTR(val) bfin_write32(DMA36_PREV_DESC_PTR, val) |
| 1604 | #define bfin_read_DMA36_CURR_ADDR() bfin_read32(DMA36_CURR_ADDR) |
| 1605 | #define bfin_write_DMA36_CURR_ADDR(val) bfin_write32(DMA36_CURR_ADDR, val) |
| 1606 | #define bfin_read_DMA36_IRQ_STATUS() bfin_read32(DMA36_IRQ_STATUS) |
| 1607 | #define bfin_write_DMA36_IRQ_STATUS(val) bfin_write32(DMA36_IRQ_STATUS, val) |
| 1608 | #define bfin_read_DMA36_CURR_X_COUNT() bfin_read32(DMA36_CURR_X_COUNT) |
| 1609 | #define bfin_write_DMA36_CURR_X_COUNT(val) bfin_write32(DMA36_CURR_X_COUNT, val) |
| 1610 | #define bfin_read_DMA36_CURR_Y_COUNT() bfin_read32(DMA36_CURR_Y_COUNT) |
| 1611 | #define bfin_write_DMA36_CURR_Y_COUNT(val) bfin_write32(DMA36_CURR_Y_COUNT, val) |
| 1612 | #define bfin_read_DMA36_BWL_COUNT() bfin_read32(DMA36_BWL_COUNT) |
| 1613 | #define bfin_write_DMA36_BWL_COUNT(val) bfin_write32(DMA36_BWL_COUNT, val) |
| 1614 | #define bfin_read_DMA36_CURR_BWL_COUNT() bfin_read32(DMA36_CURR_BWL_COUNT) |
| 1615 | #define bfin_write_DMA36_CURR_BWL_COUNT(val) bfin_write32(DMA36_CURR_BWL_COUNT, val) |
| 1616 | #define bfin_read_DMA36_BWM_COUNT() bfin_read32(DMA36_BWM_COUNT) |
| 1617 | #define bfin_write_DMA36_BWM_COUNT(val) bfin_write32(DMA36_BWM_COUNT, val) |
| 1618 | #define bfin_read_DMA36_CURR_BWM_COUNT() bfin_read32(DMA36_CURR_BWM_COUNT) |
| 1619 | #define bfin_write_DMA36_CURR_BWM_COUNT(val) bfin_write32(DMA36_CURR_BWM_COUNT, val) |
| 1620 | |
| 1621 | /* DMA Channel 37 Registers */ |
| 1622 | |
| 1623 | #define bfin_read_DMA37_NEXT_DESC_PTR() bfin_read32(DMA37_NEXT_DESC_PTR) |
| 1624 | #define bfin_write_DMA37_NEXT_DESC_PTR(val) bfin_write32(DMA37_NEXT_DESC_PTR, val) |
| 1625 | #define bfin_read_DMA37_START_ADDR() bfin_read32(DMA37_START_ADDR) |
| 1626 | #define bfin_write_DMA37_START_ADDR(val) bfin_write32(DMA37_START_ADDR, val) |
| 1627 | #define bfin_read_DMA37_CONFIG() bfin_read32(DMA37_CONFIG) |
| 1628 | #define bfin_write_DMA37_CONFIG(val) bfin_write32(DMA37_CONFIG, val) |
| 1629 | #define bfin_read_DMA37_X_COUNT() bfin_read32(DMA37_X_COUNT) |
| 1630 | #define bfin_write_DMA37_X_COUNT(val) bfin_write32(DMA37_X_COUNT, val) |
| 1631 | #define bfin_read_DMA37_X_MODIFY() bfin_read32(DMA37_X_MODIFY) |
| 1632 | #define bfin_write_DMA37_X_MODIFY(val) bfin_write32(DMA37_X_MODIFY, val) |
| 1633 | #define bfin_read_DMA37_Y_COUNT() bfin_read32(DMA37_Y_COUNT) |
| 1634 | #define bfin_write_DMA37_Y_COUNT(val) bfin_write32(DMA37_Y_COUNT, val) |
| 1635 | #define bfin_read_DMA37_Y_MODIFY() bfin_read32(DMA37_Y_MODIFY) |
| 1636 | #define bfin_write_DMA37_Y_MODIFY(val) bfin_write32(DMA37_Y_MODIFY, val) |
| 1637 | #define bfin_read_DMA37_CURR_DESC_PTR() bfin_read32(DMA37_CURR_DESC_PTR) |
| 1638 | #define bfin_write_DMA37_CURR_DESC_PTR(val) bfin_write32(DMA37_CURR_DESC_PTR, val) |
| 1639 | #define bfin_read_DMA37_PREV_DESC_PTR() bfin_read32(DMA37_PREV_DESC_PTR) |
| 1640 | #define bfin_write_DMA37_PREV_DESC_PTR(val) bfin_write32(DMA37_PREV_DESC_PTR, val) |
| 1641 | #define bfin_read_DMA37_CURR_ADDR() bfin_read32(DMA37_CURR_ADDR) |
| 1642 | #define bfin_write_DMA37_CURR_ADDR(val) bfin_write32(DMA37_CURR_ADDR, val) |
| 1643 | #define bfin_read_DMA37_IRQ_STATUS() bfin_read32(DMA37_IRQ_STATUS) |
| 1644 | #define bfin_write_DMA37_IRQ_STATUS(val) bfin_write32(DMA37_IRQ_STATUS, val) |
| 1645 | #define bfin_read_DMA37_CURR_X_COUNT() bfin_read32(DMA37_CURR_X_COUNT) |
| 1646 | #define bfin_write_DMA37_CURR_X_COUNT(val) bfin_write32(DMA37_CURR_X_COUNT, val) |
| 1647 | #define bfin_read_DMA37_CURR_Y_COUNT() bfin_read32(DMA37_CURR_Y_COUNT) |
| 1648 | #define bfin_write_DMA37_CURR_Y_COUNT(val) bfin_write32(DMA37_CURR_Y_COUNT, val) |
| 1649 | #define bfin_read_DMA37_BWL_COUNT() bfin_read32(DMA37_BWL_COUNT) |
| 1650 | #define bfin_write_DMA37_BWL_COUNT(val) bfin_write32(DMA37_BWL_COUNT, val) |
| 1651 | #define bfin_read_DMA37_CURR_BWL_COUNT() bfin_read32(DMA37_CURR_BWL_COUNT) |
| 1652 | #define bfin_write_DMA37_CURR_BWL_COUNT(val) bfin_write32(DMA37_CURR_BWL_COUNT, val) |
| 1653 | #define bfin_read_DMA37_BWM_COUNT() bfin_read32(DMA37_BWM_COUNT) |
| 1654 | #define bfin_write_DMA37_BWM_COUNT(val) bfin_write32(DMA37_BWM_COUNT, val) |
| 1655 | #define bfin_read_DMA37_CURR_BWM_COUNT() bfin_read32(DMA37_CURR_BWM_COUNT) |
| 1656 | #define bfin_write_DMA37_CURR_BWM_COUNT(val) bfin_write32(DMA37_CURR_BWM_COUNT, val) |
| 1657 | |
| 1658 | /* DMA Channel 38 Registers */ |
| 1659 | |
| 1660 | #define bfin_read_DMA38_NEXT_DESC_PTR() bfin_read32(DMA38_NEXT_DESC_PTR) |
| 1661 | #define bfin_write_DMA38_NEXT_DESC_PTR(val) bfin_write32(DMA38_NEXT_DESC_PTR, val) |
| 1662 | #define bfin_read_DMA38_START_ADDR() bfin_read32(DMA38_START_ADDR) |
| 1663 | #define bfin_write_DMA38_START_ADDR(val) bfin_write32(DMA38_START_ADDR, val) |
| 1664 | #define bfin_read_DMA38_CONFIG() bfin_read32(DMA38_CONFIG) |
| 1665 | #define bfin_write_DMA38_CONFIG(val) bfin_write32(DMA38_CONFIG, val) |
| 1666 | #define bfin_read_DMA38_X_COUNT() bfin_read32(DMA38_X_COUNT) |
| 1667 | #define bfin_write_DMA38_X_COUNT(val) bfin_write32(DMA38_X_COUNT, val) |
| 1668 | #define bfin_read_DMA38_X_MODIFY() bfin_read32(DMA38_X_MODIFY) |
| 1669 | #define bfin_write_DMA38_X_MODIFY(val) bfin_write32(DMA38_X_MODIFY, val) |
| 1670 | #define bfin_read_DMA38_Y_COUNT() bfin_read32(DMA38_Y_COUNT) |
| 1671 | #define bfin_write_DMA38_Y_COUNT(val) bfin_write32(DMA38_Y_COUNT, val) |
| 1672 | #define bfin_read_DMA38_Y_MODIFY() bfin_read32(DMA38_Y_MODIFY) |
| 1673 | #define bfin_write_DMA38_Y_MODIFY(val) bfin_write32(DMA38_Y_MODIFY, val) |
| 1674 | #define bfin_read_DMA38_CURR_DESC_PTR() bfin_read32(DMA38_CURR_DESC_PTR) |
| 1675 | #define bfin_write_DMA38_CURR_DESC_PTR(val) bfin_write32(DMA38_CURR_DESC_PTR, val) |
| 1676 | #define bfin_read_DMA38_PREV_DESC_PTR() bfin_read32(DMA38_PREV_DESC_PTR) |
| 1677 | #define bfin_write_DMA38_PREV_DESC_PTR(val) bfin_write32(DMA38_PREV_DESC_PTR, val) |
| 1678 | #define bfin_read_DMA38_CURR_ADDR() bfin_read32(DMA38_CURR_ADDR) |
| 1679 | #define bfin_write_DMA38_CURR_ADDR(val) bfin_write32(DMA38_CURR_ADDR, val) |
| 1680 | #define bfin_read_DMA38_IRQ_STATUS() bfin_read32(DMA38_IRQ_STATUS) |
| 1681 | #define bfin_write_DMA38_IRQ_STATUS(val) bfin_write32(DMA38_IRQ_STATUS, val) |
| 1682 | #define bfin_read_DMA38_CURR_X_COUNT() bfin_read32(DMA38_CURR_X_COUNT) |
| 1683 | #define bfin_write_DMA38_CURR_X_COUNT(val) bfin_write32(DMA38_CURR_X_COUNT, val) |
| 1684 | #define bfin_read_DMA38_CURR_Y_COUNT() bfin_read32(DMA38_CURR_Y_COUNT) |
| 1685 | #define bfin_write_DMA38_CURR_Y_COUNT(val) bfin_write32(DMA38_CURR_Y_COUNT, val) |
| 1686 | #define bfin_read_DMA38_BWL_COUNT() bfin_read32(DMA38_BWL_COUNT) |
| 1687 | #define bfin_write_DMA38_BWL_COUNT(val) bfin_write32(DMA38_BWL_COUNT, val) |
| 1688 | #define bfin_read_DMA38_CURR_BWL_COUNT() bfin_read32(DMA38_CURR_BWL_COUNT) |
| 1689 | #define bfin_write_DMA38_CURR_BWL_COUNT(val) bfin_write32(DMA38_CURR_BWL_COUNT, val) |
| 1690 | #define bfin_read_DMA38_BWM_COUNT() bfin_read32(DMA38_BWM_COUNT) |
| 1691 | #define bfin_write_DMA38_BWM_COUNT(val) bfin_write32(DMA38_BWM_COUNT, val) |
| 1692 | #define bfin_read_DMA38_CURR_BWM_COUNT() bfin_read32(DMA38_CURR_BWM_COUNT) |
| 1693 | #define bfin_write_DMA38_CURR_BWM_COUNT(val) bfin_write32(DMA38_CURR_BWM_COUNT, val) |
| 1694 | |
| 1695 | /* DMA Channel 39 Registers */ |
| 1696 | |
| 1697 | #define bfin_read_DMA39_NEXT_DESC_PTR() bfin_read32(DMA39_NEXT_DESC_PTR) |
| 1698 | #define bfin_write_DMA39_NEXT_DESC_PTR(val) bfin_write32(DMA39_NEXT_DESC_PTR, val) |
| 1699 | #define bfin_read_DMA39_START_ADDR() bfin_read32(DMA39_START_ADDR) |
| 1700 | #define bfin_write_DMA39_START_ADDR(val) bfin_write32(DMA39_START_ADDR, val) |
| 1701 | #define bfin_read_DMA39_CONFIG() bfin_read32(DMA39_CONFIG) |
| 1702 | #define bfin_write_DMA39_CONFIG(val) bfin_write32(DMA39_CONFIG, val) |
| 1703 | #define bfin_read_DMA39_X_COUNT() bfin_read32(DMA39_X_COUNT) |
| 1704 | #define bfin_write_DMA39_X_COUNT(val) bfin_write32(DMA39_X_COUNT, val) |
| 1705 | #define bfin_read_DMA39_X_MODIFY() bfin_read32(DMA39_X_MODIFY) |
| 1706 | #define bfin_write_DMA39_X_MODIFY(val) bfin_write32(DMA39_X_MODIFY, val) |
| 1707 | #define bfin_read_DMA39_Y_COUNT() bfin_read32(DMA39_Y_COUNT) |
| 1708 | #define bfin_write_DMA39_Y_COUNT(val) bfin_write32(DMA39_Y_COUNT, val) |
| 1709 | #define bfin_read_DMA39_Y_MODIFY() bfin_read32(DMA39_Y_MODIFY) |
| 1710 | #define bfin_write_DMA39_Y_MODIFY(val) bfin_write32(DMA39_Y_MODIFY, val) |
| 1711 | #define bfin_read_DMA39_CURR_DESC_PTR() bfin_read32(DMA39_CURR_DESC_PTR) |
| 1712 | #define bfin_write_DMA39_CURR_DESC_PTR(val) bfin_write32(DMA39_CURR_DESC_PTR, val) |
| 1713 | #define bfin_read_DMA39_PREV_DESC_PTR() bfin_read32(DMA39_PREV_DESC_PTR) |
| 1714 | #define bfin_write_DMA39_PREV_DESC_PTR(val) bfin_write32(DMA39_PREV_DESC_PTR, val) |
| 1715 | #define bfin_read_DMA39_CURR_ADDR() bfin_read32(DMA39_CURR_ADDR) |
| 1716 | #define bfin_write_DMA39_CURR_ADDR(val) bfin_write32(DMA39_CURR_ADDR, val) |
| 1717 | #define bfin_read_DMA39_IRQ_STATUS() bfin_read32(DMA39_IRQ_STATUS) |
| 1718 | #define bfin_write_DMA39_IRQ_STATUS(val) bfin_write32(DMA39_IRQ_STATUS, val) |
| 1719 | #define bfin_read_DMA39_CURR_X_COUNT() bfin_read32(DMA39_CURR_X_COUNT) |
| 1720 | #define bfin_write_DMA39_CURR_X_COUNT(val) bfin_write32(DMA39_CURR_X_COUNT, val) |
| 1721 | #define bfin_read_DMA39_CURR_Y_COUNT() bfin_read32(DMA39_CURR_Y_COUNT) |
| 1722 | #define bfin_write_DMA39_CURR_Y_COUNT(val) bfin_write32(DMA39_CURR_Y_COUNT, val) |
| 1723 | #define bfin_read_DMA39_BWL_COUNT() bfin_read32(DMA39_BWL_COUNT) |
| 1724 | #define bfin_write_DMA39_BWL_COUNT(val) bfin_write32(DMA39_BWL_COUNT, val) |
| 1725 | #define bfin_read_DMA39_CURR_BWL_COUNT() bfin_read32(DMA39_CURR_BWL_COUNT) |
| 1726 | #define bfin_write_DMA39_CURR_BWL_COUNT(val) bfin_write32(DMA39_CURR_BWL_COUNT, val) |
| 1727 | #define bfin_read_DMA39_BWM_COUNT() bfin_read32(DMA39_BWM_COUNT) |
| 1728 | #define bfin_write_DMA39_BWM_COUNT(val) bfin_write32(DMA39_BWM_COUNT, val) |
| 1729 | #define bfin_read_DMA39_CURR_BWM_COUNT() bfin_read32(DMA39_CURR_BWM_COUNT) |
| 1730 | #define bfin_write_DMA39_CURR_BWM_COUNT(val) bfin_write32(DMA39_CURR_BWM_COUNT, val) |
| 1731 | |
| 1732 | /* DMA Channel 40 Registers */ |
| 1733 | |
| 1734 | #define bfin_read_DMA40_NEXT_DESC_PTR() bfin_read32(DMA40_NEXT_DESC_PTR) |
| 1735 | #define bfin_write_DMA40_NEXT_DESC_PTR(val) bfin_write32(DMA40_NEXT_DESC_PTR, val) |
| 1736 | #define bfin_read_DMA40_START_ADDR() bfin_read32(DMA40_START_ADDR) |
| 1737 | #define bfin_write_DMA40_START_ADDR(val) bfin_write32(DMA40_START_ADDR, val) |
| 1738 | #define bfin_read_DMA40_CONFIG() bfin_read32(DMA40_CONFIG) |
| 1739 | #define bfin_write_DMA40_CONFIG(val) bfin_write32(DMA40_CONFIG, val) |
| 1740 | #define bfin_read_DMA40_X_COUNT() bfin_read32(DMA40_X_COUNT) |
| 1741 | #define bfin_write_DMA40_X_COUNT(val) bfin_write32(DMA40_X_COUNT, val) |
| 1742 | #define bfin_read_DMA40_X_MODIFY() bfin_read32(DMA40_X_MODIFY) |
| 1743 | #define bfin_write_DMA40_X_MODIFY(val) bfin_write32(DMA40_X_MODIFY, val) |
| 1744 | #define bfin_read_DMA40_Y_COUNT() bfin_read32(DMA40_Y_COUNT) |
| 1745 | #define bfin_write_DMA40_Y_COUNT(val) bfin_write32(DMA40_Y_COUNT, val) |
| 1746 | #define bfin_read_DMA40_Y_MODIFY() bfin_read32(DMA40_Y_MODIFY) |
| 1747 | #define bfin_write_DMA40_Y_MODIFY(val) bfin_write32(DMA40_Y_MODIFY, val) |
| 1748 | #define bfin_read_DMA40_CURR_DESC_PTR() bfin_read32(DMA40_CURR_DESC_PTR) |
| 1749 | #define bfin_write_DMA40_CURR_DESC_PTR(val) bfin_write32(DMA40_CURR_DESC_PTR, val) |
| 1750 | #define bfin_read_DMA40_PREV_DESC_PTR() bfin_read32(DMA40_PREV_DESC_PTR) |
| 1751 | #define bfin_write_DMA40_PREV_DESC_PTR(val) bfin_write32(DMA40_PREV_DESC_PTR, val) |
| 1752 | #define bfin_read_DMA40_CURR_ADDR() bfin_read32(DMA40_CURR_ADDR) |
| 1753 | #define bfin_write_DMA40_CURR_ADDR(val) bfin_write32(DMA40_CURR_ADDR, val) |
| 1754 | #define bfin_read_DMA40_IRQ_STATUS() bfin_read32(DMA40_IRQ_STATUS) |
| 1755 | #define bfin_write_DMA40_IRQ_STATUS(val) bfin_write32(DMA40_IRQ_STATUS, val) |
| 1756 | #define bfin_read_DMA40_CURR_X_COUNT() bfin_read32(DMA40_CURR_X_COUNT) |
| 1757 | #define bfin_write_DMA40_CURR_X_COUNT(val) bfin_write32(DMA40_CURR_X_COUNT, val) |
| 1758 | #define bfin_read_DMA40_CURR_Y_COUNT() bfin_read32(DMA40_CURR_Y_COUNT) |
| 1759 | #define bfin_write_DMA40_CURR_Y_COUNT(val) bfin_write32(DMA40_CURR_Y_COUNT, val) |
| 1760 | #define bfin_read_DMA40_BWL_COUNT() bfin_read32(DMA40_BWL_COUNT) |
| 1761 | #define bfin_write_DMA40_BWL_COUNT(val) bfin_write32(DMA40_BWL_COUNT, val) |
| 1762 | #define bfin_read_DMA40_CURR_BWL_COUNT() bfin_read32(DMA40_CURR_BWL_COUNT) |
| 1763 | #define bfin_write_DMA40_CURR_BWL_COUNT(val) bfin_write32(DMA40_CURR_BWL_COUNT, val) |
| 1764 | #define bfin_read_DMA40_BWM_COUNT() bfin_read32(DMA40_BWM_COUNT) |
| 1765 | #define bfin_write_DMA40_BWM_COUNT(val) bfin_write32(DMA40_BWM_COUNT, val) |
| 1766 | #define bfin_read_DMA40_CURR_BWM_COUNT() bfin_read32(DMA40_CURR_BWM_COUNT) |
| 1767 | #define bfin_write_DMA40_CURR_BWM_COUNT(val) bfin_write32(DMA40_CURR_BWM_COUNT, val) |
| 1768 | |
| 1769 | /* DMA Channel 41 Registers */ |
| 1770 | |
| 1771 | #define bfin_read_DMA41_NEXT_DESC_PTR() bfin_read32(DMA41_NEXT_DESC_PTR) |
| 1772 | #define bfin_write_DMA41_NEXT_DESC_PTR(val) bfin_write32(DMA41_NEXT_DESC_PTR, val) |
| 1773 | #define bfin_read_DMA41_START_ADDR() bfin_read32(DMA41_START_ADDR) |
| 1774 | #define bfin_write_DMA41_START_ADDR(val) bfin_write32(DMA41_START_ADDR, val) |
| 1775 | #define bfin_read_DMA41_CONFIG() bfin_read32(DMA41_CONFIG) |
| 1776 | #define bfin_write_DMA41_CONFIG(val) bfin_write32(DMA41_CONFIG, val) |
| 1777 | #define bfin_read_DMA41_X_COUNT() bfin_read32(DMA41_X_COUNT) |
| 1778 | #define bfin_write_DMA41_X_COUNT(val) bfin_write32(DMA41_X_COUNT, val) |
| 1779 | #define bfin_read_DMA41_X_MODIFY() bfin_read32(DMA41_X_MODIFY) |
| 1780 | #define bfin_write_DMA41_X_MODIFY(val) bfin_write32(DMA41_X_MODIFY, val) |
| 1781 | #define bfin_read_DMA41_Y_COUNT() bfin_read32(DMA41_Y_COUNT) |
| 1782 | #define bfin_write_DMA41_Y_COUNT(val) bfin_write32(DMA41_Y_COUNT, val) |
| 1783 | #define bfin_read_DMA41_Y_MODIFY() bfin_read32(DMA41_Y_MODIFY) |
| 1784 | #define bfin_write_DMA41_Y_MODIFY(val) bfin_write32(DMA41_Y_MODIFY, val) |
| 1785 | #define bfin_read_DMA41_CURR_DESC_PTR() bfin_read32(DMA41_CURR_DESC_PTR) |
| 1786 | #define bfin_write_DMA41_CURR_DESC_PTR(val) bfin_write32(DMA41_CURR_DESC_PTR, val) |
| 1787 | #define bfin_read_DMA41_PREV_DESC_PTR() bfin_read32(DMA41_PREV_DESC_PTR) |
| 1788 | #define bfin_write_DMA41_PREV_DESC_PTR(val) bfin_write32(DMA41_PREV_DESC_PTR, val) |
| 1789 | #define bfin_read_DMA41_CURR_ADDR() bfin_read32(DMA41_CURR_ADDR) |
| 1790 | #define bfin_write_DMA41_CURR_ADDR(val) bfin_write32(DMA41_CURR_ADDR, val) |
| 1791 | #define bfin_read_DMA41_IRQ_STATUS() bfin_read32(DMA41_IRQ_STATUS) |
| 1792 | #define bfin_write_DMA41_IRQ_STATUS(val) bfin_write32(DMA41_IRQ_STATUS, val) |
| 1793 | #define bfin_read_DMA41_CURR_X_COUNT() bfin_read32(DMA41_CURR_X_COUNT) |
| 1794 | #define bfin_write_DMA41_CURR_X_COUNT(val) bfin_write32(DMA41_CURR_X_COUNT, val) |
| 1795 | #define bfin_read_DMA41_CURR_Y_COUNT() bfin_read32(DMA41_CURR_Y_COUNT) |
| 1796 | #define bfin_write_DMA41_CURR_Y_COUNT(val) bfin_write32(DMA41_CURR_Y_COUNT, val) |
| 1797 | #define bfin_read_DMA41_BWL_COUNT() bfin_read32(DMA41_BWL_COUNT) |
| 1798 | #define bfin_write_DMA41_BWL_COUNT(val) bfin_write32(DMA41_BWL_COUNT, val) |
| 1799 | #define bfin_read_DMA41_CURR_BWL_COUNT() bfin_read32(DMA41_CURR_BWL_COUNT) |
| 1800 | #define bfin_write_DMA41_CURR_BWL_COUNT(val) bfin_write32(DMA41_CURR_BWL_COUNT, val) |
| 1801 | #define bfin_read_DMA41_BWM_COUNT() bfin_read32(DMA41_BWM_COUNT) |
| 1802 | #define bfin_write_DMA41_BWM_COUNT(val) bfin_write32(DMA41_BWM_COUNT, val) |
| 1803 | #define bfin_read_DMA41_CURR_BWM_COUNT() bfin_read32(DMA41_CURR_BWM_COUNT) |
| 1804 | #define bfin_write_DMA41_CURR_BWM_COUNT(val) bfin_write32(DMA41_CURR_BWM_COUNT, val) |
| 1805 | |
| 1806 | /* DMA Channel 42 Registers */ |
| 1807 | |
| 1808 | #define bfin_read_DMA42_NEXT_DESC_PTR() bfin_read32(DMA42_NEXT_DESC_PTR) |
| 1809 | #define bfin_write_DMA42_NEXT_DESC_PTR(val) bfin_write32(DMA42_NEXT_DESC_PTR, val) |
| 1810 | #define bfin_read_DMA42_START_ADDR() bfin_read32(DMA42_START_ADDR) |
| 1811 | #define bfin_write_DMA42_START_ADDR(val) bfin_write32(DMA42_START_ADDR, val) |
| 1812 | #define bfin_read_DMA42_CONFIG() bfin_read32(DMA42_CONFIG) |
| 1813 | #define bfin_write_DMA42_CONFIG(val) bfin_write32(DMA42_CONFIG, val) |
| 1814 | #define bfin_read_DMA42_X_COUNT() bfin_read32(DMA42_X_COUNT) |
| 1815 | #define bfin_write_DMA42_X_COUNT(val) bfin_write32(DMA42_X_COUNT, val) |
| 1816 | #define bfin_read_DMA42_X_MODIFY() bfin_read32(DMA42_X_MODIFY) |
| 1817 | #define bfin_write_DMA42_X_MODIFY(val) bfin_write32(DMA42_X_MODIFY, val) |
| 1818 | #define bfin_read_DMA42_Y_COUNT() bfin_read32(DMA42_Y_COUNT) |
| 1819 | #define bfin_write_DMA42_Y_COUNT(val) bfin_write32(DMA42_Y_COUNT, val) |
| 1820 | #define bfin_read_DMA42_Y_MODIFY() bfin_read32(DMA42_Y_MODIFY) |
| 1821 | #define bfin_write_DMA42_Y_MODIFY(val) bfin_write32(DMA42_Y_MODIFY, val) |
| 1822 | #define bfin_read_DMA42_CURR_DESC_PTR() bfin_read32(DMA42_CURR_DESC_PTR) |
| 1823 | #define bfin_write_DMA42_CURR_DESC_PTR(val) bfin_write32(DMA42_CURR_DESC_PTR, val) |
| 1824 | #define bfin_read_DMA42_PREV_DESC_PTR() bfin_read32(DMA42_PREV_DESC_PTR) |
| 1825 | #define bfin_write_DMA42_PREV_DESC_PTR(val) bfin_write32(DMA42_PREV_DESC_PTR, val) |
| 1826 | #define bfin_read_DMA42_CURR_ADDR() bfin_read32(DMA42_CURR_ADDR) |
| 1827 | #define bfin_write_DMA42_CURR_ADDR(val) bfin_write32(DMA42_CURR_ADDR, val) |
| 1828 | #define bfin_read_DMA42_IRQ_STATUS() bfin_read32(DMA42_IRQ_STATUS) |
| 1829 | #define bfin_write_DMA42_IRQ_STATUS(val) bfin_write32(DMA42_IRQ_STATUS, val) |
| 1830 | #define bfin_read_DMA42_CURR_X_COUNT() bfin_read32(DMA42_CURR_X_COUNT) |
| 1831 | #define bfin_write_DMA42_CURR_X_COUNT(val) bfin_write32(DMA42_CURR_X_COUNT, val) |
| 1832 | #define bfin_read_DMA42_CURR_Y_COUNT() bfin_read32(DMA42_CURR_Y_COUNT) |
| 1833 | #define bfin_write_DMA42_CURR_Y_COUNT(val) bfin_write32(DMA42_CURR_Y_COUNT, val) |
| 1834 | #define bfin_read_DMA42_BWL_COUNT() bfin_read32(DMA42_BWL_COUNT) |
| 1835 | #define bfin_write_DMA42_BWL_COUNT(val) bfin_write32(DMA42_BWL_COUNT, val) |
| 1836 | #define bfin_read_DMA42_CURR_BWL_COUNT() bfin_read32(DMA42_CURR_BWL_COUNT) |
| 1837 | #define bfin_write_DMA42_CURR_BWL_COUNT(val) bfin_write32(DMA42_CURR_BWL_COUNT, val) |
| 1838 | #define bfin_read_DMA42_BWM_COUNT() bfin_read32(DMA42_BWM_COUNT) |
| 1839 | #define bfin_write_DMA42_BWM_COUNT(val) bfin_write32(DMA42_BWM_COUNT, val) |
| 1840 | #define bfin_read_DMA42_CURR_BWM_COUNT() bfin_read32(DMA42_CURR_BWM_COUNT) |
| 1841 | #define bfin_write_DMA42_CURR_BWM_COUNT(val) bfin_write32(DMA42_CURR_BWM_COUNT, val) |
| 1842 | |
| 1843 | /* DMA Channel 43 Registers */ |
| 1844 | |
| 1845 | #define bfin_read_DMA43_NEXT_DESC_PTR() bfin_read32(DMA43_NEXT_DESC_PTR) |
| 1846 | #define bfin_write_DMA43_NEXT_DESC_PTR(val) bfin_write32(DMA43_NEXT_DESC_PTR, val) |
| 1847 | #define bfin_read_DMA43_START_ADDR() bfin_read32(DMA43_START_ADDR) |
| 1848 | #define bfin_write_DMA43_START_ADDR(val) bfin_write32(DMA43_START_ADDR, val) |
| 1849 | #define bfin_read_DMA43_CONFIG() bfin_read32(DMA43_CONFIG) |
| 1850 | #define bfin_write_DMA43_CONFIG(val) bfin_write32(DMA43_CONFIG, val) |
| 1851 | #define bfin_read_DMA43_X_COUNT() bfin_read32(DMA43_X_COUNT) |
| 1852 | #define bfin_write_DMA43_X_COUNT(val) bfin_write32(DMA43_X_COUNT, val) |
| 1853 | #define bfin_read_DMA43_X_MODIFY() bfin_read32(DMA43_X_MODIFY) |
| 1854 | #define bfin_write_DMA43_X_MODIFY(val) bfin_write32(DMA43_X_MODIFY, val) |
| 1855 | #define bfin_read_DMA43_Y_COUNT() bfin_read32(DMA43_Y_COUNT) |
| 1856 | #define bfin_write_DMA43_Y_COUNT(val) bfin_write32(DMA43_Y_COUNT, val) |
| 1857 | #define bfin_read_DMA43_Y_MODIFY() bfin_read32(DMA43_Y_MODIFY) |
| 1858 | #define bfin_write_DMA43_Y_MODIFY(val) bfin_write32(DMA43_Y_MODIFY, val) |
| 1859 | #define bfin_read_DMA43_CURR_DESC_PTR() bfin_read32(DMA43_CURR_DESC_PTR) |
| 1860 | #define bfin_write_DMA43_CURR_DESC_PTR(val) bfin_write32(DMA43_CURR_DESC_PTR, val) |
| 1861 | #define bfin_read_DMA43_PREV_DESC_PTR() bfin_read32(DMA43_PREV_DESC_PTR) |
| 1862 | #define bfin_write_DMA43_PREV_DESC_PTR(val) bfin_write32(DMA43_PREV_DESC_PTR, val) |
| 1863 | #define bfin_read_DMA43_CURR_ADDR() bfin_read32(DMA43_CURR_ADDR) |
| 1864 | #define bfin_write_DMA43_CURR_ADDR(val) bfin_write32(DMA43_CURR_ADDR, val) |
| 1865 | #define bfin_read_DMA43_IRQ_STATUS() bfin_read32(DMA43_IRQ_STATUS) |
| 1866 | #define bfin_write_DMA43_IRQ_STATUS(val) bfin_write32(DMA43_IRQ_STATUS, val) |
| 1867 | #define bfin_read_DMA43_CURR_X_COUNT() bfin_read32(DMA43_CURR_X_COUNT) |
| 1868 | #define bfin_write_DMA43_CURR_X_COUNT(val) bfin_write32(DMA43_CURR_X_COUNT, val) |
| 1869 | #define bfin_read_DMA43_CURR_Y_COUNT() bfin_read32(DMA43_CURR_Y_COUNT) |
| 1870 | #define bfin_write_DMA43_CURR_Y_COUNT(val) bfin_write32(DMA43_CURR_Y_COUNT, val) |
| 1871 | #define bfin_read_DMA43_BWL_COUNT() bfin_read32(DMA43_BWL_COUNT) |
| 1872 | #define bfin_write_DMA43_BWL_COUNT(val) bfin_write32(DMA43_BWL_COUNT, val) |
| 1873 | #define bfin_read_DMA43_CURR_BWL_COUNT() bfin_read32(DMA43_CURR_BWL_COUNT) |
| 1874 | #define bfin_write_DMA43_CURR_BWL_COUNT(val) bfin_write32(DMA43_CURR_BWL_COUNT, val) |
| 1875 | #define bfin_read_DMA43_BWM_COUNT() bfin_read32(DMA43_BWM_COUNT) |
| 1876 | #define bfin_write_DMA43_BWM_COUNT(val) bfin_write32(DMA43_BWM_COUNT, val) |
| 1877 | #define bfin_read_DMA43_CURR_BWM_COUNT() bfin_read32(DMA43_CURR_BWM_COUNT) |
| 1878 | #define bfin_write_DMA43_CURR_BWM_COUNT(val) bfin_write32(DMA43_CURR_BWM_COUNT, val) |
| 1879 | |
| 1880 | /* DMA Channel 44 Registers */ |
| 1881 | |
| 1882 | #define bfin_read_DMA44_NEXT_DESC_PTR() bfin_read32(DMA44_NEXT_DESC_PTR) |
| 1883 | #define bfin_write_DMA44_NEXT_DESC_PTR(val) bfin_write32(DMA44_NEXT_DESC_PTR, val) |
| 1884 | #define bfin_read_DMA44_START_ADDR() bfin_read32(DMA44_START_ADDR) |
| 1885 | #define bfin_write_DMA44_START_ADDR(val) bfin_write32(DMA44_START_ADDR, val) |
| 1886 | #define bfin_read_DMA44_CONFIG() bfin_read32(DMA44_CONFIG) |
| 1887 | #define bfin_write_DMA44_CONFIG(val) bfin_write32(DMA44_CONFIG, val) |
| 1888 | #define bfin_read_DMA44_X_COUNT() bfin_read32(DMA44_X_COUNT) |
| 1889 | #define bfin_write_DMA44_X_COUNT(val) bfin_write32(DMA44_X_COUNT, val) |
| 1890 | #define bfin_read_DMA44_X_MODIFY() bfin_read32(DMA44_X_MODIFY) |
| 1891 | #define bfin_write_DMA44_X_MODIFY(val) bfin_write32(DMA44_X_MODIFY, val) |
| 1892 | #define bfin_read_DMA44_Y_COUNT() bfin_read32(DMA44_Y_COUNT) |
| 1893 | #define bfin_write_DMA44_Y_COUNT(val) bfin_write32(DMA44_Y_COUNT, val) |
| 1894 | #define bfin_read_DMA44_Y_MODIFY() bfin_read32(DMA44_Y_MODIFY) |
| 1895 | #define bfin_write_DMA44_Y_MODIFY(val) bfin_write32(DMA44_Y_MODIFY, val) |
| 1896 | #define bfin_read_DMA44_CURR_DESC_PTR() bfin_read32(DMA44_CURR_DESC_PTR) |
| 1897 | #define bfin_write_DMA44_CURR_DESC_PTR(val) bfin_write32(DMA44_CURR_DESC_PTR, val) |
| 1898 | #define bfin_read_DMA44_PREV_DESC_PTR() bfin_read32(DMA44_PREV_DESC_PTR) |
| 1899 | #define bfin_write_DMA44_PREV_DESC_PTR(val) bfin_write32(DMA44_PREV_DESC_PTR, val) |
| 1900 | #define bfin_read_DMA44_CURR_ADDR() bfin_read32(DMA44_CURR_ADDR) |
| 1901 | #define bfin_write_DMA44_CURR_ADDR(val) bfin_write32(DMA44_CURR_ADDR, val) |
| 1902 | #define bfin_read_DMA44_IRQ_STATUS() bfin_read32(DMA44_IRQ_STATUS) |
| 1903 | #define bfin_write_DMA44_IRQ_STATUS(val) bfin_write32(DMA44_IRQ_STATUS, val) |
| 1904 | #define bfin_read_DMA44_CURR_X_COUNT() bfin_read32(DMA44_CURR_X_COUNT) |
| 1905 | #define bfin_write_DMA44_CURR_X_COUNT(val) bfin_write32(DMA44_CURR_X_COUNT, val) |
| 1906 | #define bfin_read_DMA44_CURR_Y_COUNT() bfin_read32(DMA44_CURR_Y_COUNT) |
| 1907 | #define bfin_write_DMA44_CURR_Y_COUNT(val) bfin_write32(DMA44_CURR_Y_COUNT, val) |
| 1908 | #define bfin_read_DMA44_BWL_COUNT() bfin_read32(DMA44_BWL_COUNT) |
| 1909 | #define bfin_write_DMA44_BWL_COUNT(val) bfin_write32(DMA44_BWL_COUNT, val) |
| 1910 | #define bfin_read_DMA44_CURR_BWL_COUNT() bfin_read32(DMA44_CURR_BWL_COUNT) |
| 1911 | #define bfin_write_DMA44_CURR_BWL_COUNT(val) bfin_write32(DMA44_CURR_BWL_COUNT, val) |
| 1912 | #define bfin_read_DMA44_BWM_COUNT() bfin_read32(DMA44_BWM_COUNT) |
| 1913 | #define bfin_write_DMA44_BWM_COUNT(val) bfin_write32(DMA44_BWM_COUNT, val) |
| 1914 | #define bfin_read_DMA44_CURR_BWM_COUNT() bfin_read32(DMA44_CURR_BWM_COUNT) |
| 1915 | #define bfin_write_DMA44_CURR_BWM_COUNT(val) bfin_write32(DMA44_CURR_BWM_COUNT, val) |
| 1916 | |
| 1917 | /* DMA Channel 45 Registers */ |
| 1918 | |
| 1919 | #define bfin_read_DMA45_NEXT_DESC_PTR() bfin_read32(DMA45_NEXT_DESC_PTR) |
| 1920 | #define bfin_write_DMA45_NEXT_DESC_PTR(val) bfin_write32(DMA45_NEXT_DESC_PTR, val) |
| 1921 | #define bfin_read_DMA45_START_ADDR() bfin_read32(DMA45_START_ADDR) |
| 1922 | #define bfin_write_DMA45_START_ADDR(val) bfin_write32(DMA45_START_ADDR, val) |
| 1923 | #define bfin_read_DMA45_CONFIG() bfin_read32(DMA45_CONFIG) |
| 1924 | #define bfin_write_DMA45_CONFIG(val) bfin_write32(DMA45_CONFIG, val) |
| 1925 | #define bfin_read_DMA45_X_COUNT() bfin_read32(DMA45_X_COUNT) |
| 1926 | #define bfin_write_DMA45_X_COUNT(val) bfin_write32(DMA45_X_COUNT, val) |
| 1927 | #define bfin_read_DMA45_X_MODIFY() bfin_read32(DMA45_X_MODIFY) |
| 1928 | #define bfin_write_DMA45_X_MODIFY(val) bfin_write32(DMA45_X_MODIFY, val) |
| 1929 | #define bfin_read_DMA45_Y_COUNT() bfin_read32(DMA45_Y_COUNT) |
| 1930 | #define bfin_write_DMA45_Y_COUNT(val) bfin_write32(DMA45_Y_COUNT, val) |
| 1931 | #define bfin_read_DMA45_Y_MODIFY() bfin_read32(DMA45_Y_MODIFY) |
| 1932 | #define bfin_write_DMA45_Y_MODIFY(val) bfin_write32(DMA45_Y_MODIFY, val) |
| 1933 | #define bfin_read_DMA45_CURR_DESC_PTR() bfin_read32(DMA45_CURR_DESC_PTR) |
| 1934 | #define bfin_write_DMA45_CURR_DESC_PTR(val) bfin_write32(DMA45_CURR_DESC_PTR, val) |
| 1935 | #define bfin_read_DMA45_PREV_DESC_PTR() bfin_read32(DMA45_PREV_DESC_PTR) |
| 1936 | #define bfin_write_DMA45_PREV_DESC_PTR(val) bfin_write32(DMA45_PREV_DESC_PTR, val) |
| 1937 | #define bfin_read_DMA45_CURR_ADDR() bfin_read32(DMA45_CURR_ADDR) |
| 1938 | #define bfin_write_DMA45_CURR_ADDR(val) bfin_write32(DMA45_CURR_ADDR, val) |
| 1939 | #define bfin_read_DMA45_IRQ_STATUS() bfin_read32(DMA45_IRQ_STATUS) |
| 1940 | #define bfin_write_DMA45_IRQ_STATUS(val) bfin_write32(DMA45_IRQ_STATUS, val) |
| 1941 | #define bfin_read_DMA45_CURR_X_COUNT() bfin_read32(DMA45_CURR_X_COUNT) |
| 1942 | #define bfin_write_DMA45_CURR_X_COUNT(val) bfin_write32(DMA45_CURR_X_COUNT, val) |
| 1943 | #define bfin_read_DMA45_CURR_Y_COUNT() bfin_read32(DMA45_CURR_Y_COUNT) |
| 1944 | #define bfin_write_DMA45_CURR_Y_COUNT(val) bfin_write32(DMA45_CURR_Y_COUNT, val) |
| 1945 | #define bfin_read_DMA45_BWL_COUNT() bfin_read32(DMA45_BWL_COUNT) |
| 1946 | #define bfin_write_DMA45_BWL_COUNT(val) bfin_write32(DMA45_BWL_COUNT, val) |
| 1947 | #define bfin_read_DMA45_CURR_BWL_COUNT() bfin_read32(DMA45_CURR_BWL_COUNT) |
| 1948 | #define bfin_write_DMA45_CURR_BWL_COUNT(val) bfin_write32(DMA45_CURR_BWL_COUNT, val) |
| 1949 | #define bfin_read_DMA45_BWM_COUNT() bfin_read32(DMA45_BWM_COUNT) |
| 1950 | #define bfin_write_DMA45_BWM_COUNT(val) bfin_write32(DMA45_BWM_COUNT, val) |
| 1951 | #define bfin_read_DMA45_CURR_BWM_COUNT() bfin_read32(DMA45_CURR_BWM_COUNT) |
| 1952 | #define bfin_write_DMA45_CURR_BWM_COUNT(val) bfin_write32(DMA45_CURR_BWM_COUNT, val) |
| 1953 | |
| 1954 | /* DMA Channel 46 Registers */ |
| 1955 | |
| 1956 | #define bfin_read_DMA46_NEXT_DESC_PTR() bfin_read32(DMA46_NEXT_DESC_PTR) |
| 1957 | #define bfin_write_DMA46_NEXT_DESC_PTR(val) bfin_write32(DMA46_NEXT_DESC_PTR, val) |
| 1958 | #define bfin_read_DMA46_START_ADDR() bfin_read32(DMA46_START_ADDR) |
| 1959 | #define bfin_write_DMA46_START_ADDR(val) bfin_write32(DMA46_START_ADDR, val) |
| 1960 | #define bfin_read_DMA46_CONFIG() bfin_read32(DMA46_CONFIG) |
| 1961 | #define bfin_write_DMA46_CONFIG(val) bfin_write32(DMA46_CONFIG, val) |
| 1962 | #define bfin_read_DMA46_X_COUNT() bfin_read32(DMA46_X_COUNT) |
| 1963 | #define bfin_write_DMA46_X_COUNT(val) bfin_write32(DMA46_X_COUNT, val) |
| 1964 | #define bfin_read_DMA46_X_MODIFY() bfin_read32(DMA46_X_MODIFY) |
| 1965 | #define bfin_write_DMA46_X_MODIFY(val) bfin_write32(DMA46_X_MODIFY, val) |
| 1966 | #define bfin_read_DMA46_Y_COUNT() bfin_read32(DMA46_Y_COUNT) |
| 1967 | #define bfin_write_DMA46_Y_COUNT(val) bfin_write32(DMA46_Y_COUNT, val) |
| 1968 | #define bfin_read_DMA46_Y_MODIFY() bfin_read32(DMA46_Y_MODIFY) |
| 1969 | #define bfin_write_DMA46_Y_MODIFY(val) bfin_write32(DMA46_Y_MODIFY, val) |
| 1970 | #define bfin_read_DMA46_CURR_DESC_PTR() bfin_read32(DMA46_CURR_DESC_PTR) |
| 1971 | #define bfin_write_DMA46_CURR_DESC_PTR(val) bfin_write32(DMA46_CURR_DESC_PTR, val) |
| 1972 | #define bfin_read_DMA46_PREV_DESC_PTR() bfin_read32(DMA46_PREV_DESC_PTR) |
| 1973 | #define bfin_write_DMA46_PREV_DESC_PTR(val) bfin_write32(DMA46_PREV_DESC_PTR, val) |
| 1974 | #define bfin_read_DMA46_CURR_ADDR() bfin_read32(DMA46_CURR_ADDR) |
| 1975 | #define bfin_write_DMA46_CURR_ADDR(val) bfin_write32(DMA46_CURR_ADDR, val) |
| 1976 | #define bfin_read_DMA46_IRQ_STATUS() bfin_read32(DMA46_IRQ_STATUS) |
| 1977 | #define bfin_write_DMA46_IRQ_STATUS(val) bfin_write32(DMA46_IRQ_STATUS, val) |
| 1978 | #define bfin_read_DMA46_CURR_X_COUNT() bfin_read32(DMA46_CURR_X_COUNT) |
| 1979 | #define bfin_write_DMA46_CURR_X_COUNT(val) bfin_write32(DMA46_CURR_X_COUNT, val) |
| 1980 | #define bfin_read_DMA46_CURR_Y_COUNT() bfin_read32(DMA46_CURR_Y_COUNT) |
| 1981 | #define bfin_write_DMA46_CURR_Y_COUNT(val) bfin_write32(DMA46_CURR_Y_COUNT, val) |
| 1982 | #define bfin_read_DMA46_BWL_COUNT() bfin_read32(DMA46_BWL_COUNT) |
| 1983 | #define bfin_write_DMA46_BWL_COUNT(val) bfin_write32(DMA46_BWL_COUNT, val) |
| 1984 | #define bfin_read_DMA46_CURR_BWL_COUNT() bfin_read32(DMA46_CURR_BWL_COUNT) |
| 1985 | #define bfin_write_DMA46_CURR_BWL_COUNT(val) bfin_write32(DMA46_CURR_BWL_COUNT, val) |
| 1986 | #define bfin_read_DMA46_BWM_COUNT() bfin_read32(DMA46_BWM_COUNT) |
| 1987 | #define bfin_write_DMA46_BWM_COUNT(val) bfin_write32(DMA46_BWM_COUNT, val) |
| 1988 | #define bfin_read_DMA46_CURR_BWM_COUNT() bfin_read32(DMA46_CURR_BWM_COUNT) |
| 1989 | #define bfin_write_DMA46_CURR_BWM_COUNT(val) bfin_write32(DMA46_CURR_BWM_COUNT, val) |
| 1990 | |
| 1991 | |
| 1992 | /* EPPI1 Registers */ |
| 1993 | |
| 1994 | |
| 1995 | /* Port Interrubfin_read_()t 0 Registers (32-bit) */ |
| 1996 | |
| 1997 | #define bfin_read_PINT0_MASK_SET() bfin_read32(PINT0_MASK_SET) |
| 1998 | #define bfin_write_PINT0_MASK_SET(val) bfin_write32(PINT0_MASK_SET, val) |
| 1999 | #define bfin_read_PINT0_MASK_CLEAR() bfin_read32(PINT0_MASK_CLEAR) |
| 2000 | #define bfin_write_PINT0_MASK_CLEAR(val) bfin_write32(PINT0_MASK_CLEAR, val) |
| 2001 | #define bfin_read_PINT0_REQUEST() bfin_read32(PINT0_REQUEST) |
| 2002 | #define bfin_write_PINT0_REQUEST(val) bfin_write32(PINT0_REQUEST, val) |
| 2003 | #define bfin_read_PINT0_ASSIGN() bfin_read32(PINT0_ASSIGN) |
| 2004 | #define bfin_write_PINT0_ASSIGN(val) bfin_write32(PINT0_ASSIGN, val) |
| 2005 | #define bfin_read_PINT0_EDGE_SET() bfin_read32(PINT0_EDGE_SET) |
| 2006 | #define bfin_write_PINT0_EDGE_SET(val) bfin_write32(PINT0_EDGE_SET, val) |
| 2007 | #define bfin_read_PINT0_EDGE_CLEAR() bfin_read32(PINT0_EDGE_CLEAR) |
| 2008 | #define bfin_write_PINT0_EDGE_CLEAR(val) bfin_write32(PINT0_EDGE_CLEAR, val) |
| 2009 | #define bfin_read_PINT0_INVERT_SET() bfin_read32(PINT0_INVERT_SET) |
| 2010 | #define bfin_write_PINT0_INVERT_SET(val) bfin_write32(PINT0_INVERT_SET, val) |
| 2011 | #define bfin_read_PINT0_INVERT_CLEAR() bfin_read32(PINT0_INVERT_CLEAR) |
| 2012 | #define bfin_write_PINT0_INVERT_CLEAR(val) bfin_write32(PINT0_INVERT_CLEAR, val) |
| 2013 | #define bfin_read_PINT0_PINSTATE() bfin_read32(PINT0_PINSTATE) |
| 2014 | #define bfin_write_PINT0_PINSTATE(val) bfin_write32(PINT0_PINSTATE, val) |
| 2015 | #define bfin_read_PINT0_LATCH() bfin_read32(PINT0_LATCH) |
| 2016 | #define bfin_write_PINT0_LATCH(val) bfin_write32(PINT0_LATCH, val) |
| 2017 | |
| 2018 | /* Port Interrubfin_read_()t 1 Registers (32-bit) */ |
| 2019 | |
| 2020 | #define bfin_read_PINT1_MASK_SET() bfin_read32(PINT1_MASK_SET) |
| 2021 | #define bfin_write_PINT1_MASK_SET(val) bfin_write32(PINT1_MASK_SET, val) |
| 2022 | #define bfin_read_PINT1_MASK_CLEAR() bfin_read32(PINT1_MASK_CLEAR) |
| 2023 | #define bfin_write_PINT1_MASK_CLEAR(val) bfin_write32(PINT1_MASK_CLEAR, val) |
| 2024 | #define bfin_read_PINT1_REQUEST() bfin_read32(PINT1_REQUEST) |
| 2025 | #define bfin_write_PINT1_REQUEST(val) bfin_write32(PINT1_REQUEST, val) |
| 2026 | #define bfin_read_PINT1_ASSIGN() bfin_read32(PINT1_ASSIGN) |
| 2027 | #define bfin_write_PINT1_ASSIGN(val) bfin_write32(PINT1_ASSIGN, val) |
| 2028 | #define bfin_read_PINT1_EDGE_SET() bfin_read32(PINT1_EDGE_SET) |
| 2029 | #define bfin_write_PINT1_EDGE_SET(val) bfin_write32(PINT1_EDGE_SET, val) |
| 2030 | #define bfin_read_PINT1_EDGE_CLEAR() bfin_read32(PINT1_EDGE_CLEAR) |
| 2031 | #define bfin_write_PINT1_EDGE_CLEAR(val) bfin_write32(PINT1_EDGE_CLEAR, val) |
| 2032 | #define bfin_read_PINT1_INVERT_SET() bfin_read32(PINT1_INVERT_SET) |
| 2033 | #define bfin_write_PINT1_INVERT_SET(val) bfin_write32(PINT1_INVERT_SET, val) |
| 2034 | #define bfin_read_PINT1_INVERT_CLEAR() bfin_read32(PINT1_INVERT_CLEAR) |
| 2035 | #define bfin_write_PINT1_INVERT_CLEAR(val) bfin_write32(PINT1_INVERT_CLEAR, val) |
| 2036 | #define bfin_read_PINT1_PINSTATE() bfin_read32(PINT1_PINSTATE) |
| 2037 | #define bfin_write_PINT1_PINSTATE(val) bfin_write32(PINT1_PINSTATE, val) |
| 2038 | #define bfin_read_PINT1_LATCH() bfin_read32(PINT1_LATCH) |
| 2039 | #define bfin_write_PINT1_LATCH(val) bfin_write32(PINT1_LATCH, val) |
| 2040 | |
| 2041 | /* Port Interrubfin_read_()t 2 Registers (32-bit) */ |
| 2042 | |
| 2043 | #define bfin_read_PINT2_MASK_SET() bfin_read32(PINT2_MASK_SET) |
| 2044 | #define bfin_write_PINT2_MASK_SET(val) bfin_write32(PINT2_MASK_SET, val) |
| 2045 | #define bfin_read_PINT2_MASK_CLEAR() bfin_read32(PINT2_MASK_CLEAR) |
| 2046 | #define bfin_write_PINT2_MASK_CLEAR(val) bfin_write32(PINT2_MASK_CLEAR, val) |
| 2047 | #define bfin_read_PINT2_REQUEST() bfin_read32(PINT2_REQUEST) |
| 2048 | #define bfin_write_PINT2_REQUEST(val) bfin_write32(PINT2_REQUEST, val) |
| 2049 | #define bfin_read_PINT2_ASSIGN() bfin_read32(PINT2_ASSIGN) |
| 2050 | #define bfin_write_PINT2_ASSIGN(val) bfin_write32(PINT2_ASSIGN, val) |
| 2051 | #define bfin_read_PINT2_EDGE_SET() bfin_read32(PINT2_EDGE_SET) |
| 2052 | #define bfin_write_PINT2_EDGE_SET(val) bfin_write32(PINT2_EDGE_SET, val) |
| 2053 | #define bfin_read_PINT2_EDGE_CLEAR() bfin_read32(PINT2_EDGE_CLEAR) |
| 2054 | #define bfin_write_PINT2_EDGE_CLEAR(val) bfin_write32(PINT2_EDGE_CLEAR, val) |
| 2055 | #define bfin_read_PINT2_INVERT_SET() bfin_read32(PINT2_INVERT_SET) |
| 2056 | #define bfin_write_PINT2_INVERT_SET(val) bfin_write32(PINT2_INVERT_SET, val) |
| 2057 | #define bfin_read_PINT2_INVERT_CLEAR() bfin_read32(PINT2_INVERT_CLEAR) |
| 2058 | #define bfin_write_PINT2_INVERT_CLEAR(val) bfin_write32(PINT2_INVERT_CLEAR, val) |
| 2059 | #define bfin_read_PINT2_PINSTATE() bfin_read32(PINT2_PINSTATE) |
| 2060 | #define bfin_write_PINT2_PINSTATE(val) bfin_write32(PINT2_PINSTATE, val) |
| 2061 | #define bfin_read_PINT2_LATCH() bfin_read32(PINT2_LATCH) |
| 2062 | #define bfin_write_PINT2_LATCH(val) bfin_write32(PINT2_LATCH, val) |
| 2063 | |
| 2064 | /* Port Interrubfin_read_()t 3 Registers (32-bit) */ |
| 2065 | |
| 2066 | #define bfin_read_PINT3_MASK_SET() bfin_read32(PINT3_MASK_SET) |
| 2067 | #define bfin_write_PINT3_MASK_SET(val) bfin_write32(PINT3_MASK_SET, val) |
| 2068 | #define bfin_read_PINT3_MASK_CLEAR() bfin_read32(PINT3_MASK_CLEAR) |
| 2069 | #define bfin_write_PINT3_MASK_CLEAR(val) bfin_write32(PINT3_MASK_CLEAR, val) |
| 2070 | #define bfin_read_PINT3_REQUEST() bfin_read32(PINT3_REQUEST) |
| 2071 | #define bfin_write_PINT3_REQUEST(val) bfin_write32(PINT3_REQUEST, val) |
| 2072 | #define bfin_read_PINT3_ASSIGN() bfin_read32(PINT3_ASSIGN) |
| 2073 | #define bfin_write_PINT3_ASSIGN(val) bfin_write32(PINT3_ASSIGN, val) |
| 2074 | #define bfin_read_PINT3_EDGE_SET() bfin_read32(PINT3_EDGE_SET) |
| 2075 | #define bfin_write_PINT3_EDGE_SET(val) bfin_write32(PINT3_EDGE_SET, val) |
| 2076 | #define bfin_read_PINT3_EDGE_CLEAR() bfin_read32(PINT3_EDGE_CLEAR) |
| 2077 | #define bfin_write_PINT3_EDGE_CLEAR(val) bfin_write32(PINT3_EDGE_CLEAR, val) |
| 2078 | #define bfin_read_PINT3_INVERT_SET() bfin_read32(PINT3_INVERT_SET) |
| 2079 | #define bfin_write_PINT3_INVERT_SET(val) bfin_write32(PINT3_INVERT_SET, val) |
| 2080 | #define bfin_read_PINT3_INVERT_CLEAR() bfin_read32(PINT3_INVERT_CLEAR) |
| 2081 | #define bfin_write_PINT3_INVERT_CLEAR(val) bfin_write32(PINT3_INVERT_CLEAR, val) |
| 2082 | #define bfin_read_PINT3_PINSTATE() bfin_read32(PINT3_PINSTATE) |
| 2083 | #define bfin_write_PINT3_PINSTATE(val) bfin_write32(PINT3_PINSTATE, val) |
| 2084 | #define bfin_read_PINT3_LATCH() bfin_read32(PINT3_LATCH) |
| 2085 | #define bfin_write_PINT3_LATCH(val) bfin_write32(PINT3_LATCH, val) |
| 2086 | |
| 2087 | /* Port Interrubfin_read_()t 4 Registers (32-bit) */ |
| 2088 | |
| 2089 | #define bfin_read_PINT4_MASK_SET() bfin_read32(PINT4_MASK_SET) |
| 2090 | #define bfin_write_PINT4_MASK_SET(val) bfin_write32(PINT4_MASK_SET, val) |
| 2091 | #define bfin_read_PINT4_MASK_CLEAR() bfin_read32(PINT4_MASK_CLEAR) |
| 2092 | #define bfin_write_PINT4_MASK_CLEAR(val) bfin_write32(PINT4_MASK_CLEAR, val) |
| 2093 | #define bfin_read_PINT4_REQUEST() bfin_read32(PINT4_REQUEST) |
| 2094 | #define bfin_write_PINT4_REQUEST(val) bfin_write32(PINT4_REQUEST, val) |
| 2095 | #define bfin_read_PINT4_ASSIGN() bfin_read32(PINT4_ASSIGN) |
| 2096 | #define bfin_write_PINT4_ASSIGN(val) bfin_write32(PINT4_ASSIGN, val) |
| 2097 | #define bfin_read_PINT4_EDGE_SET() bfin_read32(PINT4_EDGE_SET) |
| 2098 | #define bfin_write_PINT4_EDGE_SET(val) bfin_write32(PINT4_EDGE_SET, val) |
| 2099 | #define bfin_read_PINT4_EDGE_CLEAR() bfin_read32(PINT4_EDGE_CLEAR) |
| 2100 | #define bfin_write_PINT4_EDGE_CLEAR(val) bfin_write32(PINT4_EDGE_CLEAR, val) |
| 2101 | #define bfin_read_PINT4_INVERT_SET() bfin_read32(PINT4_INVERT_SET) |
| 2102 | #define bfin_write_PINT4_INVERT_SET(val) bfin_write32(PINT4_INVERT_SET, val) |
| 2103 | #define bfin_read_PINT4_INVERT_CLEAR() bfin_read32(PINT4_INVERT_CLEAR) |
| 2104 | #define bfin_write_PINT4_INVERT_CLEAR(val) bfin_write32(PINT4_INVERT_CLEAR, val) |
| 2105 | #define bfin_read_PINT4_PINSTATE() bfin_read32(PINT4_PINSTATE) |
| 2106 | #define bfin_write_PINT4_PINSTATE(val) bfin_write32(PINT4_PINSTATE, val) |
| 2107 | #define bfin_read_PINT4_LATCH() bfin_read32(PINT4_LATCH) |
| 2108 | #define bfin_write_PINT4_LATCH(val) bfin_write32(PINT4_LATCH, val) |
| 2109 | |
| 2110 | /* Port Interrubfin_read_()t 5 Registers (32-bit) */ |
| 2111 | |
| 2112 | #define bfin_read_PINT5_MASK_SET() bfin_read32(PINT5_MASK_SET) |
| 2113 | #define bfin_write_PINT5_MASK_SET(val) bfin_write32(PINT5_MASK_SET, val) |
| 2114 | #define bfin_read_PINT5_MASK_CLEAR() bfin_read32(PINT5_MASK_CLEAR) |
| 2115 | #define bfin_write_PINT5_MASK_CLEAR(val) bfin_write32(PINT5_MASK_CLEAR, val) |
| 2116 | #define bfin_read_PINT5_REQUEST() bfin_read32(PINT5_REQUEST) |
| 2117 | #define bfin_write_PINT5_REQUEST(val) bfin_write32(PINT5_REQUEST, val) |
| 2118 | #define bfin_read_PINT5_ASSIGN() bfin_read32(PINT5_ASSIGN) |
| 2119 | #define bfin_write_PINT5_ASSIGN(val) bfin_write32(PINT5_ASSIGN, val) |
| 2120 | #define bfin_read_PINT5_EDGE_SET() bfin_read32(PINT5_EDGE_SET) |
| 2121 | #define bfin_write_PINT5_EDGE_SET(val) bfin_write32(PINT5_EDGE_SET, val) |
| 2122 | #define bfin_read_PINT5_EDGE_CLEAR() bfin_read32(PINT5_EDGE_CLEAR) |
| 2123 | #define bfin_write_PINT5_EDGE_CLEAR(val) bfin_write32(PINT5_EDGE_CLEAR, val) |
| 2124 | #define bfin_read_PINT5_INVERT_SET() bfin_read32(PINT5_INVERT_SET) |
| 2125 | #define bfin_write_PINT5_INVERT_SET(val) bfin_write32(PINT5_INVERT_SET, val) |
| 2126 | #define bfin_read_PINT5_INVERT_CLEAR() bfin_read32(PINT5_INVERT_CLEAR) |
| 2127 | #define bfin_write_PINT5_INVERT_CLEAR(val) bfin_write32(PINT5_INVERT_CLEAR, val) |
| 2128 | #define bfin_read_PINT5_PINSTATE() bfin_read32(PINT5_PINSTATE) |
| 2129 | #define bfin_write_PINT5_PINSTATE(val) bfin_write32(PINT5_PINSTATE, val) |
| 2130 | #define bfin_read_PINT5_LATCH() bfin_read32(PINT5_LATCH) |
| 2131 | #define bfin_write_PINT5_LATCH(val) bfin_write32(PINT5_LATCH, val) |
| 2132 | |
| 2133 | /* Port A Registers */ |
| 2134 | |
| 2135 | #define bfin_read_PORTA_FER() bfin_read32(PORTA_FER) |
| 2136 | #define bfin_write_PORTA_FER(val) bfin_write32(PORTA_FER, val) |
| 2137 | #define bfin_read_PORTA_FER_SET() bfin_read32(PORTA_FER_SET) |
| 2138 | #define bfin_write_PORTA_FER_SET(val) bfin_write32(PORTA_FER_SET, val) |
| 2139 | #define bfin_read_PORTA_FER_CLEAR() bfin_read32(PORTA_FER_CLEAR) |
| 2140 | #define bfin_write_PORTA_FER_CLEAR(val) bfin_write32(PORTA_FER_CLEAR, val) |
| 2141 | #define bfin_read_PORTA() bfin_read32(PORTA) |
| 2142 | #define bfin_write_PORTA(val) bfin_write32(PORTA, val) |
| 2143 | #define bfin_read_PORTA_SET() bfin_read32(PORTA_SET) |
| 2144 | #define bfin_write_PORTA_SET(val) bfin_write32(PORTA_SET, val) |
| 2145 | #define bfin_read_PORTA_CLEAR() bfin_read32(PORTA_CLEAR) |
| 2146 | #define bfin_write_PORTA_CLEAR(val) bfin_write32(PORTA_CLEAR, val) |
| 2147 | #define bfin_read_PORTA_DIR() bfin_read32(PORTA_DIR) |
| 2148 | #define bfin_write_PORTA_DIR(val) bfin_write32(PORTA_DIR, val) |
| 2149 | #define bfin_read_PORTA_DIR_SET() bfin_read32(PORTA_DIR_SET) |
| 2150 | #define bfin_write_PORTA_DIR_SET(val) bfin_write32(PORTA_DIR_SET, val) |
| 2151 | #define bfin_read_PORTA_DIR_CLEAR() bfin_read32(PORTA_DIR_CLEAR) |
| 2152 | #define bfin_write_PORTA_DIR_CLEAR(val) bfin_write32(PORTA_DIR_CLEAR, val) |
| 2153 | #define bfin_read_PORTA_INEN() bfin_read32(PORTA_INEN) |
| 2154 | #define bfin_write_PORTA_INEN(val) bfin_write32(PORTA_INEN, val) |
| 2155 | #define bfin_read_PORTA_INEN_SET() bfin_read32(PORTA_INEN_SET) |
| 2156 | #define bfin_write_PORTA_INEN_SET(val) bfin_write32(PORTA_INEN_SET, val) |
| 2157 | #define bfin_read_PORTA_INEN_CLEAR() bfin_read32(PORTA_INEN_CLEAR) |
| 2158 | #define bfin_write_PORTA_INEN_CLEAR(val) bfin_write32(PORTA_INEN_CLEAR, val) |
| 2159 | #define bfin_read_PORTA_MUX() bfin_read32(PORTA_MUX) |
| 2160 | #define bfin_write_PORTA_MUX(val) bfin_write32(PORTA_MUX, val) |
| 2161 | #define bfin_read_PORTA_DATA_TGL() bfin_read32(PORTA_DATA_TGL) |
| 2162 | #define bfin_write_PORTA_DATA_TGL(val) bfin_write32(PORTA_DATA_TGL, val) |
| 2163 | #define bfin_read_PORTA_POL() bfin_read32(PORTA_POL) |
| 2164 | #define bfin_write_PORTA_POL(val) bfin_write32(PORTA_POL, val) |
| 2165 | #define bfin_read_PORTA_POL_SET() bfin_read32(PORTA_POL_SET) |
| 2166 | #define bfin_write_PORTA_POL_SET(val) bfin_write32(PORTA_POL_SET, val) |
| 2167 | #define bfin_read_PORTA_POL_CLEAR() bfin_read32(PORTA_POL_CLEAR) |
| 2168 | #define bfin_write_PORTA_POL_CLEAR(val) bfin_write32(PORTA_POL_CLEAR, val) |
| 2169 | #define bfin_read_PORTA_LOCK() bfin_read32(PORTA_LOCK) |
| 2170 | #define bfin_write_PORTA_LOCK(val) bfin_write32(PORTA_LOCK, val) |
| 2171 | #define bfin_read_PORTA_REVID() bfin_read32(PORTA_REVID) |
| 2172 | #define bfin_write_PORTA_REVID(val) bfin_write32(PORTA_REVID, val) |
| 2173 | |
| 2174 | |
| 2175 | |
| 2176 | /* Port B Registers */ |
| 2177 | #define bfin_read_PORTB_FER() bfin_read32(PORTB_FER) |
| 2178 | #define bfin_write_PORTB_FER(val) bfin_write32(PORTB_FER, val) |
| 2179 | #define bfin_read_PORTB_FER_SET() bfin_read32(PORTB_FER_SET) |
| 2180 | #define bfin_write_PORTB_FER_SET(val) bfin_write32(PORTB_FER_SET, val) |
| 2181 | #define bfin_read_PORTB_FER_CLEAR() bfin_read32(PORTB_FER_CLEAR) |
| 2182 | #define bfin_write_PORTB_FER_CLEAR(val) bfin_write32(PORTB_FER_CLEAR, val) |
| 2183 | #define bfin_read_PORTB() bfin_read32(PORTB) |
| 2184 | #define bfin_write_PORTB(val) bfin_write32(PORTB, val) |
| 2185 | #define bfin_read_PORTB_SET() bfin_read32(PORTB_SET) |
| 2186 | #define bfin_write_PORTB_SET(val) bfin_write32(PORTB_SET, val) |
| 2187 | #define bfin_read_PORTB_CLEAR() bfin_read32(PORTB_CLEAR) |
| 2188 | #define bfin_write_PORTB_CLEAR(val) bfin_write32(PORTB_CLEAR, val) |
| 2189 | #define bfin_read_PORTB_DIR() bfin_read32(PORTB_DIR) |
| 2190 | #define bfin_write_PORTB_DIR(val) bfin_write32(PORTB_DIR, val) |
| 2191 | #define bfin_read_PORTB_DIR_SET() bfin_read32(PORTB_DIR_SET) |
| 2192 | #define bfin_write_PORTB_DIR_SET(val) bfin_write32(PORTB_DIR_SET, val) |
| 2193 | #define bfin_read_PORTB_DIR_CLEAR() bfin_read32(PORTB_DIR_CLEAR) |
| 2194 | #define bfin_write_PORTB_DIR_CLEAR(val) bfin_write32(PORTB_DIR_CLEAR, val) |
| 2195 | #define bfin_read_PORTB_INEN() bfin_read32(PORTB_INEN) |
| 2196 | #define bfin_write_PORTB_INEN(val) bfin_write32(PORTB_INEN, val) |
| 2197 | #define bfin_read_PORTB_INEN_SET() bfin_read32(PORTB_INEN_SET) |
| 2198 | #define bfin_write_PORTB_INEN_SET(val) bfin_write32(PORTB_INEN_SET, val) |
| 2199 | #define bfin_read_PORTB_INEN_CLEAR() bfin_read32(PORTB_INEN_CLEAR) |
| 2200 | #define bfin_write_PORTB_INEN_CLEAR(val) bfin_write32(PORTB_INEN_CLEAR, val) |
| 2201 | #define bfin_read_PORTB_MUX() bfin_read32(PORTB_MUX) |
| 2202 | #define bfin_write_PORTB_MUX(val) bfin_write32(PORTB_MUX, val) |
| 2203 | #define bfin_read_PORTB_DATA_TGL() bfin_read32(PORTB_DATA_TGL) |
| 2204 | #define bfin_write_PORTB_DATA_TGL(val) bfin_write32(PORTB_DATA_TGL, val) |
| 2205 | #define bfin_read_PORTB_POL() bfin_read32(PORTB_POL) |
| 2206 | #define bfin_write_PORTB_POL(val) bfin_write32(PORTB_POL, val) |
| 2207 | #define bfin_read_PORTB_POL_SET() bfin_read32(PORTB_POL_SET) |
| 2208 | #define bfin_write_PORTB_POL_SET(val) bfin_write32(PORTB_POL_SET, val) |
| 2209 | #define bfin_read_PORTB_POL_CLEAR() bfin_read32(PORTB_POL_CLEAR) |
| 2210 | #define bfin_write_PORTB_POL_CLEAR(val) bfin_write32(PORTB_POL_CLEAR, val) |
| 2211 | #define bfin_read_PORTB_LOCK() bfin_read32(PORTB_LOCK) |
| 2212 | #define bfin_write_PORTB_LOCK(val) bfin_write32(PORTB_LOCK, val) |
| 2213 | #define bfin_read_PORTB_REVID() bfin_read32(PORTB_REVID) |
| 2214 | #define bfin_write_PORTB_REVID(val) bfin_write32(PORTB_REVID, val) |
| 2215 | |
| 2216 | |
| 2217 | /* Port C Registers */ |
| 2218 | #define bfin_read_PORTC_FER() bfin_read32(PORTC_FER) |
| 2219 | #define bfin_write_PORTC_FER(val) bfin_write32(PORTC_FER, val) |
| 2220 | #define bfin_read_PORTC_FER_SET() bfin_read32(PORTC_FER_SET) |
| 2221 | #define bfin_write_PORTC_FER_SET(val) bfin_write32(PORTC_FER_SET, val) |
| 2222 | #define bfin_read_PORTC_FER_CLEAR() bfin_read32(PORTC_FER_CLEAR) |
| 2223 | #define bfin_write_PORTC_FER_CLEAR(val) bfin_write32(PORTC_FER_CLEAR, val) |
| 2224 | #define bfin_read_PORTC() bfin_read32(PORTC) |
| 2225 | #define bfin_write_PORTC(val) bfin_write32(PORTC, val) |
| 2226 | #define bfin_read_PORTC_SET() bfin_read32(PORTC_SET) |
| 2227 | #define bfin_write_PORTC_SET(val) bfin_write32(PORTC_SET, val) |
| 2228 | #define bfin_read_PORTC_CLEAR() bfin_read32(PORTC_CLEAR) |
| 2229 | #define bfin_write_PORTC_CLEAR(val) bfin_write32(PORTC_CLEAR, val) |
| 2230 | #define bfin_read_PORTC_DIR() bfin_read32(PORTC_DIR) |
| 2231 | #define bfin_write_PORTC_DIR(val) bfin_write32(PORTC_DIR, val) |
| 2232 | #define bfin_read_PORTC_DIR_SET() bfin_read32(PORTC_DIR_SET) |
| 2233 | #define bfin_write_PORTC_DIR_SET(val) bfin_write32(PORTC_DIR_SET, val) |
| 2234 | #define bfin_read_PORTC_DIR_CLEAR() bfin_read32(PORTC_DIR_CLEAR) |
| 2235 | #define bfin_write_PORTC_DIR_CLEAR(val) bfin_write32(PORTC_DIR_CLEAR, val) |
| 2236 | #define bfin_read_PORTC_INEN() bfin_read32(PORTC_INEN) |
| 2237 | #define bfin_write_PORTC_INEN(val) bfin_write32(PORTC_INEN, val) |
| 2238 | #define bfin_read_PORTC_INEN_SET() bfin_read32(PORTC_INEN_SET) |
| 2239 | #define bfin_write_PORTC_INEN_SET(val) bfin_write32(PORTC_INEN_SET, val) |
| 2240 | #define bfin_read_PORTC_INEN_CLEAR() bfin_read32(PORTC_INEN_CLEAR) |
| 2241 | #define bfin_write_PORTC_INEN_CLEAR(val) bfin_write32(PORTC_INEN_CLEAR, val) |
| 2242 | #define bfin_read_PORTC_MUX() bfin_read32(PORTC_MUX) |
| 2243 | #define bfin_write_PORTC_MUX(val) bfin_write32(PORTC_MUX, val) |
| 2244 | #define bfin_read_PORTC_DATA_TGL() bfin_read32(PORTC_DATA_TGL) |
| 2245 | #define bfin_write_PORTC_DATA_TGL(val) bfin_write32(PORTC_DATA_TGL, val) |
| 2246 | #define bfin_read_PORTC_POL() bfin_read32(PORTC_POL) |
| 2247 | #define bfin_write_PORTC_POL(val) bfin_write32(PORTC_POL, val) |
| 2248 | #define bfin_read_PORTC_POL_SET() bfin_read32(PORTC_POL_SET) |
| 2249 | #define bfin_write_PORTC_POL_SET(val) bfin_write32(PORTC_POL_SET, val) |
| 2250 | #define bfin_read_PORTC_POL_CLEAR() bfin_read32(PORTC_POL_CLEAR) |
| 2251 | #define bfin_write_PORTC_POL_CLEAR(val) bfin_write32(PORTC_POL_CLEAR, val) |
| 2252 | #define bfin_read_PORTC_LOCK() bfin_read32(PORTC_LOCK) |
| 2253 | #define bfin_write_PORTC_LOCK(val) bfin_write32(PORTC_LOCK, val) |
| 2254 | #define bfin_read_PORTC_REVID() bfin_read32(PORTC_REVID) |
| 2255 | #define bfin_write_PORTC_REVID(val) bfin_write32(PORTC_REVID, val) |
| 2256 | |
| 2257 | |
| 2258 | /* Port D Registers */ |
| 2259 | #define bfin_read_PORTD_FER() bfin_read32(PORTD_FER) |
| 2260 | #define bfin_write_PORTD_FER(val) bfin_write32(PORTD_FER, val) |
| 2261 | #define bfin_read_PORTD_FER_SET() bfin_read32(PORTD_FER_SET) |
| 2262 | #define bfin_write_PORTD_FER_SET(val) bfin_write32(PORTD_FER_SET, val) |
| 2263 | #define bfin_read_PORTD_FER_CLEAR() bfin_read32(PORTD_FER_CLEAR) |
| 2264 | #define bfin_write_PORTD_FER_CLEAR(val) bfin_write32(PORTD_FER_CLEAR, val) |
| 2265 | #define bfin_read_PORTD() bfin_read32(PORTD) |
| 2266 | #define bfin_write_PORTD(val) bfin_write32(PORTD, val) |
| 2267 | #define bfin_read_PORTD_SET() bfin_read32(PORTD_SET) |
| 2268 | #define bfin_write_PORTD_SET(val) bfin_write32(PORTD_SET, val) |
| 2269 | #define bfin_read_PORTD_CLEAR() bfin_read32(PORTD_CLEAR) |
| 2270 | #define bfin_write_PORTD_CLEAR(val) bfin_write32(PORTD_CLEAR, val) |
| 2271 | #define bfin_read_PORTD_DIR() bfin_read32(PORTD_DIR) |
| 2272 | #define bfin_write_PORTD_DIR(val) bfin_write32(PORTD_DIR, val) |
| 2273 | #define bfin_read_PORTD_DIR_SET() bfin_read32(PORTD_DIR_SET) |
| 2274 | #define bfin_write_PORTD_DIR_SET(val) bfin_write32(PORTD_DIR_SET, val) |
| 2275 | #define bfin_read_PORTD_DIR_CLEAR() bfin_read32(PORTD_DIR_CLEAR) |
| 2276 | #define bfin_write_PORTD_DIR_CLEAR(val) bfin_write32(PORTD_DIR_CLEAR, val) |
| 2277 | #define bfin_read_PORTD_INEN() bfin_read32(PORTD_INEN) |
| 2278 | #define bfin_write_PORTD_INEN(val) bfin_write32(PORTD_INEN, val) |
| 2279 | #define bfin_read_PORTD_INEN_SET() bfin_read32(PORTD_INEN_SET) |
| 2280 | #define bfin_write_PORTD_INEN_SET(val) bfin_write32(PORTD_INEN_SET, val) |
| 2281 | #define bfin_read_PORTD_INEN_CLEAR() bfin_read32(PORTD_INEN_CLEAR) |
| 2282 | #define bfin_write_PORTD_INEN_CLEAR(val) bfin_write32(PORTD_INEN_CLEAR, val) |
| 2283 | #define bfin_read_PORTD_MUX() bfin_read32(PORTD_MUX) |
| 2284 | #define bfin_write_PORTD_MUX(val) bfin_write32(PORTD_MUX, val) |
| 2285 | #define bfin_read_PORTD_DATA_TGL() bfin_read32(PORTD_DATA_TGL) |
| 2286 | #define bfin_write_PORTD_DATA_TGL(val) bfin_write32(PORTD_DATA_TGL, val) |
| 2287 | #define bfin_read_PORTD_POL() bfin_read32(PORTD_POL) |
| 2288 | #define bfin_write_PORTD_POL(val) bfin_write32(PORTD_POL, val) |
| 2289 | #define bfin_read_PORTD_POL_SET() bfin_read32(PORTD_POL_SET) |
| 2290 | #define bfin_write_PORTD_POL_SET(val) bfin_write32(PORTD_POL_SET, val) |
| 2291 | #define bfin_read_PORTD_POL_CLEAR() bfin_read32(PORTD_POL_CLEAR) |
| 2292 | #define bfin_write_PORTD_POL_CLEAR(val) bfin_write32(PORTD_POL_CLEAR, val) |
| 2293 | #define bfin_read_PORTD_LOCK() bfin_read32(PORTD_LOCK) |
| 2294 | #define bfin_write_PORTD_LOCK(val) bfin_write32(PORTD_LOCK, val) |
| 2295 | #define bfin_read_PORTD_REVID() bfin_read32(PORTD_REVID) |
| 2296 | #define bfin_write_PORTD_REVID(val) bfin_write32(PORTD_REVID, val) |
| 2297 | |
| 2298 | |
| 2299 | /* Port E Registers */ |
| 2300 | #define bfin_read_PORTE_FER() bfin_read32(PORTE_FER) |
| 2301 | #define bfin_write_PORTE_FER(val) bfin_write32(PORTE_FER, val) |
| 2302 | #define bfin_read_PORTE_FER_SET() bfin_read32(PORTE_FER_SET) |
| 2303 | #define bfin_write_PORTE_FER_SET(val) bfin_write32(PORTE_FER_SET, val) |
| 2304 | #define bfin_read_PORTE_FER_CLEAR() bfin_read32(PORTE_FER_CLEAR) |
| 2305 | #define bfin_write_PORTE_FER_CLEAR(val) bfin_write32(PORTE_FER_CLEAR, val) |
| 2306 | #define bfin_read_PORTE() bfin_read32(PORTE) |
| 2307 | #define bfin_write_PORTE(val) bfin_write32(PORTE, val) |
| 2308 | #define bfin_read_PORTE_SET() bfin_read32(PORTE_SET) |
| 2309 | #define bfin_write_PORTE_SET(val) bfin_write32(PORTE_SET, val) |
| 2310 | #define bfin_read_PORTE_CLEAR() bfin_read32(PORTE_CLEAR) |
| 2311 | #define bfin_write_PORTE_CLEAR(val) bfin_write32(PORTE_CLEAR, val) |
| 2312 | #define bfin_read_PORTE_DIR() bfin_read32(PORTE_DIR) |
| 2313 | #define bfin_write_PORTE_DIR(val) bfin_write32(PORTE_DIR, val) |
| 2314 | #define bfin_read_PORTE_DIR_SET() bfin_read32(PORTE_DIR_SET) |
| 2315 | #define bfin_write_PORTE_DIR_SET(val) bfin_write32(PORTE_DIR_SET, val) |
| 2316 | #define bfin_read_PORTE_DIR_CLEAR() bfin_read32(PORTE_DIR_CLEAR) |
| 2317 | #define bfin_write_PORTE_DIR_CLEAR(val) bfin_write32(PORTE_DIR_CLEAR, val) |
| 2318 | #define bfin_read_PORTE_INEN() bfin_read32(PORTE_INEN) |
| 2319 | #define bfin_write_PORTE_INEN(val) bfin_write32(PORTE_INEN, val) |
| 2320 | #define bfin_read_PORTE_INEN_SET() bfin_read32(PORTE_INEN_SET) |
| 2321 | #define bfin_write_PORTE_INEN_SET(val) bfin_write32(PORTE_INEN_SET, val) |
| 2322 | #define bfin_read_PORTE_INEN_CLEAR() bfin_read32(PORTE_INEN_CLEAR) |
| 2323 | #define bfin_write_PORTE_INEN_CLEAR(val) bfin_write32(PORTE_INEN_CLEAR, val) |
| 2324 | #define bfin_read_PORTE_MUX() bfin_read32(PORTE_MUX) |
| 2325 | #define bfin_write_PORTE_MUX(val) bfin_write32(PORTE_MUX, val) |
| 2326 | #define bfin_read_PORTE_DATA_TGL() bfin_read32(PORTE_DATA_TGL) |
| 2327 | #define bfin_write_PORTE_DATA_TGL(val) bfin_write32(PORTE_DATA_TGL, val) |
| 2328 | #define bfin_read_PORTE_POL() bfin_read32(PORTE_POL) |
| 2329 | #define bfin_write_PORTE_POL(val) bfin_write32(PORTE_POL, val) |
| 2330 | #define bfin_read_PORTE_POL_SET() bfin_read32(PORTE_POL_SET) |
| 2331 | #define bfin_write_PORTE_POL_SET(val) bfin_write32(PORTE_POL_SET, val) |
| 2332 | #define bfin_read_PORTE_POL_CLEAR() bfin_read32(PORTE_POL_CLEAR) |
| 2333 | #define bfin_write_PORTE_POL_CLEAR(val) bfin_write32(PORTE_POL_CLEAR, val) |
| 2334 | #define bfin_read_PORTE_LOCK() bfin_read32(PORTE_LOCK) |
| 2335 | #define bfin_write_PORTE_LOCK(val) bfin_write32(PORTE_LOCK, val) |
| 2336 | #define bfin_read_PORTE_REVID() bfin_read32(PORTE_REVID) |
| 2337 | #define bfin_write_PORTE_REVID(val) bfin_write32(PORTE_REVID, val) |
| 2338 | |
| 2339 | |
| 2340 | /* Port F Registers */ |
| 2341 | #define bfin_read_PORTF_FER() bfin_read32(PORTF_FER) |
| 2342 | #define bfin_write_PORTF_FER(val) bfin_write32(PORTF_FER, val) |
| 2343 | #define bfin_read_PORTF_FER_SET() bfin_read32(PORTF_FER_SET) |
| 2344 | #define bfin_write_PORTF_FER_SET(val) bfin_write32(PORTF_FER_SET, val) |
| 2345 | #define bfin_read_PORTF_FER_CLEAR() bfin_read32(PORTF_FER_CLEAR) |
| 2346 | #define bfin_write_PORTF_FER_CLEAR(val) bfin_write32(PORTF_FER_CLEAR, val) |
| 2347 | #define bfin_read_PORTF() bfin_read32(PORTF) |
| 2348 | #define bfin_write_PORTF(val) bfin_write32(PORTF, val) |
| 2349 | #define bfin_read_PORTF_SET() bfin_read32(PORTF_SET) |
| 2350 | #define bfin_write_PORTF_SET(val) bfin_write32(PORTF_SET, val) |
| 2351 | #define bfin_read_PORTF_CLEAR() bfin_read32(PORTF_CLEAR) |
| 2352 | #define bfin_write_PORTF_CLEAR(val) bfin_write32(PORTF_CLEAR, val) |
| 2353 | #define bfin_read_PORTF_DIR() bfin_read32(PORTF_DIR) |
| 2354 | #define bfin_write_PORTF_DIR(val) bfin_write32(PORTF_DIR, val) |
| 2355 | #define bfin_read_PORTF_DIR_SET() bfin_read32(PORTF_DIR_SET) |
| 2356 | #define bfin_write_PORTF_DIR_SET(val) bfin_write32(PORTF_DIR_SET, val) |
| 2357 | #define bfin_read_PORTF_DIR_CLEAR() bfin_read32(PORTF_DIR_CLEAR) |
| 2358 | #define bfin_write_PORTF_DIR_CLEAR(val) bfin_write32(PORTF_DIR_CLEAR, val) |
| 2359 | #define bfin_read_PORTF_INEN() bfin_read32(PORTF_INEN) |
| 2360 | #define bfin_write_PORTF_INEN(val) bfin_write32(PORTF_INEN, val) |
| 2361 | #define bfin_read_PORTF_INEN_SET() bfin_read32(PORTF_INEN_SET) |
| 2362 | #define bfin_write_PORTF_INEN_SET(val) bfin_write32(PORTF_INEN_SET, val) |
| 2363 | #define bfin_read_PORTF_INEN_CLEAR() bfin_read32(PORTF_INEN_CLEAR) |
| 2364 | #define bfin_write_PORTF_INEN_CLEAR(val) bfin_write32(PORTF_INEN_CLEAR, val) |
| 2365 | #define bfin_read_PORTF_MUX() bfin_read32(PORTF_MUX) |
| 2366 | #define bfin_write_PORTF_MUX(val) bfin_write32(PORTF_MUX, val) |
| 2367 | #define bfin_read_PORTF_DATA_TGL() bfin_read32(PORTF_DATA_TGL) |
| 2368 | #define bfin_write_PORTF_DATA_TGL(val) bfin_write32(PORTF_DATA_TGL, val) |
| 2369 | #define bfin_read_PORTF_POL() bfin_read32(PORTF_POL) |
| 2370 | #define bfin_write_PORTF_POL(val) bfin_write32(PORTF_POL, val) |
| 2371 | #define bfin_read_PORTF_POL_SET() bfin_read32(PORTF_POL_SET) |
| 2372 | #define bfin_write_PORTF_POL_SET(val) bfin_write32(PORTF_POL_SET, val) |
| 2373 | #define bfin_read_PORTF_POL_CLEAR() bfin_read32(PORTF_POL_CLEAR) |
| 2374 | #define bfin_write_PORTF_POL_CLEAR(val) bfin_write32(PORTF_POL_CLEAR, val) |
| 2375 | #define bfin_read_PORTF_LOCK() bfin_read32(PORTF_LOCK) |
| 2376 | #define bfin_write_PORTF_LOCK(val) bfin_write32(PORTF_LOCK, val) |
| 2377 | #define bfin_read_PORTF_REVID() bfin_read32(PORTF_REVID) |
| 2378 | #define bfin_write_PORTF_REVID(val) bfin_write32(PORTF_REVID, val) |
| 2379 | |
| 2380 | |
| 2381 | /* Port G Registers */ |
| 2382 | #define bfin_read_PORTG_FER() bfin_read32(PORTG_FER) |
| 2383 | #define bfin_write_PORTG_FER(val) bfin_write32(PORTG_FER, val) |
| 2384 | #define bfin_read_PORTG_FER_SET() bfin_read32(PORTG_FER_SET) |
| 2385 | #define bfin_write_PORTG_FER_SET(val) bfin_write32(PORTG_FER_SET, val) |
| 2386 | #define bfin_read_PORTG_FER_CLEAR() bfin_read32(PORTG_FER_CLEAR) |
| 2387 | #define bfin_write_PORTG_FER_CLEAR(val) bfin_write32(PORTG_FER_CLEAR, val) |
| 2388 | #define bfin_read_PORTG() bfin_read32(PORTG) |
| 2389 | #define bfin_write_PORTG(val) bfin_write32(PORTG, val) |
| 2390 | #define bfin_read_PORTG_SET() bfin_read32(PORTG_SET) |
| 2391 | #define bfin_write_PORTG_SET(val) bfin_write32(PORTG_SET, val) |
| 2392 | #define bfin_read_PORTG_CLEAR() bfin_read32(PORTG_CLEAR) |
| 2393 | #define bfin_write_PORTG_CLEAR(val) bfin_write32(PORTG_CLEAR, val) |
| 2394 | #define bfin_read_PORTG_DIR() bfin_read32(PORTG_DIR) |
| 2395 | #define bfin_write_PORTG_DIR(val) bfin_write32(PORTG_DIR, val) |
| 2396 | #define bfin_read_PORTG_DIR_SET() bfin_read32(PORTG_DIR_SET) |
| 2397 | #define bfin_write_PORTG_DIR_SET(val) bfin_write32(PORTG_DIR_SET, val) |
| 2398 | #define bfin_read_PORTG_DIR_CLEAR() bfin_read32(PORTG_DIR_CLEAR) |
| 2399 | #define bfin_write_PORTG_DIR_CLEAR(val) bfin_write32(PORTG_DIR_CLEAR, val) |
| 2400 | #define bfin_read_PORTG_INEN() bfin_read32(PORTG_INEN) |
| 2401 | #define bfin_write_PORTG_INEN(val) bfin_write32(PORTG_INEN, val) |
| 2402 | #define bfin_read_PORTG_INEN_SET() bfin_read32(PORTG_INEN_SET) |
| 2403 | #define bfin_write_PORTG_INEN_SET(val) bfin_write32(PORTG_INEN_SET, val) |
| 2404 | #define bfin_read_PORTG_INEN_CLEAR() bfin_read32(PORTG_INEN_CLEAR) |
| 2405 | #define bfin_write_PORTG_INEN_CLEAR(val) bfin_write32(PORTG_INEN_CLEAR, val) |
| 2406 | #define bfin_read_PORTG_MUX() bfin_read32(PORTG_MUX) |
| 2407 | #define bfin_write_PORTG_MUX(val) bfin_write32(PORTG_MUX, val) |
| 2408 | #define bfin_read_PORTG_DATA_TGL() bfin_read32(PORTG_DATA_TGL) |
| 2409 | #define bfin_write_PORTG_DATA_TGL(val) bfin_write32(PORTG_DATA_TGL, val) |
| 2410 | #define bfin_read_PORTG_POL() bfin_read32(PORTG_POL) |
| 2411 | #define bfin_write_PORTG_POL(val) bfin_write32(PORTG_POL, val) |
| 2412 | #define bfin_read_PORTG_POL_SET() bfin_read32(PORTG_POL_SET) |
| 2413 | #define bfin_write_PORTG_POL_SET(val) bfin_write32(PORTG_POL_SET, val) |
| 2414 | #define bfin_read_PORTG_POL_CLEAR() bfin_read32(PORTG_POL_CLEAR) |
| 2415 | #define bfin_write_PORTG_POL_CLEAR(val) bfin_write32(PORTG_POL_CLEAR, val) |
| 2416 | #define bfin_read_PORTG_LOCK() bfin_read32(PORTG_LOCK) |
| 2417 | #define bfin_write_PORTG_LOCK(val) bfin_write32(PORTG_LOCK, val) |
| 2418 | #define bfin_read_PORTG_REVID() bfin_read32(PORTG_REVID) |
| 2419 | #define bfin_write_PORTG_REVID(val) bfin_write32(PORTG_REVID, val) |
| 2420 | |
| 2421 | |
| 2422 | |
| 2423 | |
| 2424 | /* CAN Controller 0 Config 1 Registers */ |
| 2425 | |
| 2426 | #define bfin_read_CAN0_MC1() bfin_read16(CAN0_MC1) |
| 2427 | #define bfin_write_CAN0_MC1(val) bfin_write16(CAN0_MC1, val) |
| 2428 | #define bfin_read_CAN0_MD1() bfin_read16(CAN0_MD1) |
| 2429 | #define bfin_write_CAN0_MD1(val) bfin_write16(CAN0_MD1, val) |
| 2430 | #define bfin_read_CAN0_TRS1() bfin_read16(CAN0_TRS1) |
| 2431 | #define bfin_write_CAN0_TRS1(val) bfin_write16(CAN0_TRS1, val) |
| 2432 | #define bfin_read_CAN0_TRR1() bfin_read16(CAN0_TRR1) |
| 2433 | #define bfin_write_CAN0_TRR1(val) bfin_write16(CAN0_TRR1, val) |
| 2434 | #define bfin_read_CAN0_TA1() bfin_read16(CAN0_TA1) |
| 2435 | #define bfin_write_CAN0_TA1(val) bfin_write16(CAN0_TA1, val) |
| 2436 | #define bfin_read_CAN0_AA1() bfin_read16(CAN0_AA1) |
| 2437 | #define bfin_write_CAN0_AA1(val) bfin_write16(CAN0_AA1, val) |
| 2438 | #define bfin_read_CAN0_RMP1() bfin_read16(CAN0_RMP1) |
| 2439 | #define bfin_write_CAN0_RMP1(val) bfin_write16(CAN0_RMP1, val) |
| 2440 | #define bfin_read_CAN0_RML1() bfin_read16(CAN0_RML1) |
| 2441 | #define bfin_write_CAN0_RML1(val) bfin_write16(CAN0_RML1, val) |
| 2442 | #define bfin_read_CAN0_MBTIF1() bfin_read16(CAN0_MBTIF1) |
| 2443 | #define bfin_write_CAN0_MBTIF1(val) bfin_write16(CAN0_MBTIF1, val) |
| 2444 | #define bfin_read_CAN0_MBRIF1() bfin_read16(CAN0_MBRIF1) |
| 2445 | #define bfin_write_CAN0_MBRIF1(val) bfin_write16(CAN0_MBRIF1, val) |
| 2446 | #define bfin_read_CAN0_MBIM1() bfin_read16(CAN0_MBIM1) |
| 2447 | #define bfin_write_CAN0_MBIM1(val) bfin_write16(CAN0_MBIM1, val) |
| 2448 | #define bfin_read_CAN0_RFH1() bfin_read16(CAN0_RFH1) |
| 2449 | #define bfin_write_CAN0_RFH1(val) bfin_write16(CAN0_RFH1, val) |
| 2450 | #define bfin_read_CAN0_OPSS1() bfin_read16(CAN0_OPSS1) |
| 2451 | #define bfin_write_CAN0_OPSS1(val) bfin_write16(CAN0_OPSS1, val) |
| 2452 | |
| 2453 | /* CAN Controller 0 Config 2 Registers */ |
| 2454 | |
| 2455 | #define bfin_read_CAN0_MC2() bfin_read16(CAN0_MC2) |
| 2456 | #define bfin_write_CAN0_MC2(val) bfin_write16(CAN0_MC2, val) |
| 2457 | #define bfin_read_CAN0_MD2() bfin_read16(CAN0_MD2) |
| 2458 | #define bfin_write_CAN0_MD2(val) bfin_write16(CAN0_MD2, val) |
| 2459 | #define bfin_read_CAN0_TRS2() bfin_read16(CAN0_TRS2) |
| 2460 | #define bfin_write_CAN0_TRS2(val) bfin_write16(CAN0_TRS2, val) |
| 2461 | #define bfin_read_CAN0_TRR2() bfin_read16(CAN0_TRR2) |
| 2462 | #define bfin_write_CAN0_TRR2(val) bfin_write16(CAN0_TRR2, val) |
| 2463 | #define bfin_read_CAN0_TA2() bfin_read16(CAN0_TA2) |
| 2464 | #define bfin_write_CAN0_TA2(val) bfin_write16(CAN0_TA2, val) |
| 2465 | #define bfin_read_CAN0_AA2() bfin_read16(CAN0_AA2) |
| 2466 | #define bfin_write_CAN0_AA2(val) bfin_write16(CAN0_AA2, val) |
| 2467 | #define bfin_read_CAN0_RMP2() bfin_read16(CAN0_RMP2) |
| 2468 | #define bfin_write_CAN0_RMP2(val) bfin_write16(CAN0_RMP2, val) |
| 2469 | #define bfin_read_CAN0_RML2() bfin_read16(CAN0_RML2) |
| 2470 | #define bfin_write_CAN0_RML2(val) bfin_write16(CAN0_RML2, val) |
| 2471 | #define bfin_read_CAN0_MBTIF2() bfin_read16(CAN0_MBTIF2) |
| 2472 | #define bfin_write_CAN0_MBTIF2(val) bfin_write16(CAN0_MBTIF2, val) |
| 2473 | #define bfin_read_CAN0_MBRIF2() bfin_read16(CAN0_MBRIF2) |
| 2474 | #define bfin_write_CAN0_MBRIF2(val) bfin_write16(CAN0_MBRIF2, val) |
| 2475 | #define bfin_read_CAN0_MBIM2() bfin_read16(CAN0_MBIM2) |
| 2476 | #define bfin_write_CAN0_MBIM2(val) bfin_write16(CAN0_MBIM2, val) |
| 2477 | #define bfin_read_CAN0_RFH2() bfin_read16(CAN0_RFH2) |
| 2478 | #define bfin_write_CAN0_RFH2(val) bfin_write16(CAN0_RFH2, val) |
| 2479 | #define bfin_read_CAN0_OPSS2() bfin_read16(CAN0_OPSS2) |
| 2480 | #define bfin_write_CAN0_OPSS2(val) bfin_write16(CAN0_OPSS2, val) |
| 2481 | |
| 2482 | /* CAN Controller 0 Clock/Interrubfin_read_()t/Counter Registers */ |
| 2483 | |
| 2484 | #define bfin_read_CAN0_CLOCK() bfin_read16(CAN0_CLOCK) |
| 2485 | #define bfin_write_CAN0_CLOCK(val) bfin_write16(CAN0_CLOCK, val) |
| 2486 | #define bfin_read_CAN0_TIMING() bfin_read16(CAN0_TIMING) |
| 2487 | #define bfin_write_CAN0_TIMING(val) bfin_write16(CAN0_TIMING, val) |
| 2488 | #define bfin_read_CAN0_DEBUG() bfin_read16(CAN0_DEBUG) |
| 2489 | #define bfin_write_CAN0_DEBUG(val) bfin_write16(CAN0_DEBUG, val) |
| 2490 | #define bfin_read_CAN0_STATUS() bfin_read16(CAN0_STATUS) |
| 2491 | #define bfin_write_CAN0_STATUS(val) bfin_write16(CAN0_STATUS, val) |
| 2492 | #define bfin_read_CAN0_CEC() bfin_read16(CAN0_CEC) |
| 2493 | #define bfin_write_CAN0_CEC(val) bfin_write16(CAN0_CEC, val) |
| 2494 | #define bfin_read_CAN0_GIS() bfin_read16(CAN0_GIS) |
| 2495 | #define bfin_write_CAN0_GIS(val) bfin_write16(CAN0_GIS, val) |
| 2496 | #define bfin_read_CAN0_GIM() bfin_read16(CAN0_GIM) |
| 2497 | #define bfin_write_CAN0_GIM(val) bfin_write16(CAN0_GIM, val) |
| 2498 | #define bfin_read_CAN0_GIF() bfin_read16(CAN0_GIF) |
| 2499 | #define bfin_write_CAN0_GIF(val) bfin_write16(CAN0_GIF, val) |
| 2500 | #define bfin_read_CAN0_CONTROL() bfin_read16(CAN0_CONTROL) |
| 2501 | #define bfin_write_CAN0_CONTROL(val) bfin_write16(CAN0_CONTROL, val) |
| 2502 | #define bfin_read_CAN0_INTR() bfin_read16(CAN0_INTR) |
| 2503 | #define bfin_write_CAN0_INTR(val) bfin_write16(CAN0_INTR, val) |
| 2504 | #define bfin_read_CAN0_MBTD() bfin_read16(CAN0_MBTD) |
| 2505 | #define bfin_write_CAN0_MBTD(val) bfin_write16(CAN0_MBTD, val) |
| 2506 | #define bfin_read_CAN0_EWR() bfin_read16(CAN0_EWR) |
| 2507 | #define bfin_write_CAN0_EWR(val) bfin_write16(CAN0_EWR, val) |
| 2508 | #define bfin_read_CAN0_ESR() bfin_read16(CAN0_ESR) |
| 2509 | #define bfin_write_CAN0_ESR(val) bfin_write16(CAN0_ESR, val) |
| 2510 | #define bfin_read_CAN0_UCCNT() bfin_read16(CAN0_UCCNT) |
| 2511 | #define bfin_write_CAN0_UCCNT(val) bfin_write16(CAN0_UCCNT, val) |
| 2512 | #define bfin_read_CAN0_UCRC() bfin_read16(CAN0_UCRC) |
| 2513 | #define bfin_write_CAN0_UCRC(val) bfin_write16(CAN0_UCRC, val) |
| 2514 | #define bfin_read_CAN0_UCCNF() bfin_read16(CAN0_UCCNF) |
| 2515 | #define bfin_write_CAN0_UCCNF(val) bfin_write16(CAN0_UCCNF, val) |
| 2516 | |
| 2517 | /* CAN Controller 0 Accebfin_read_()tance Registers */ |
| 2518 | |
| 2519 | #define bfin_read_CAN0_AM00L() bfin_read16(CAN0_AM00L) |
| 2520 | #define bfin_write_CAN0_AM00L(val) bfin_write16(CAN0_AM00L, val) |
| 2521 | #define bfin_read_CAN0_AM00H() bfin_read16(CAN0_AM00H) |
| 2522 | #define bfin_write_CAN0_AM00H(val) bfin_write16(CAN0_AM00H, val) |
| 2523 | #define bfin_read_CAN0_AM01L() bfin_read16(CAN0_AM01L) |
| 2524 | #define bfin_write_CAN0_AM01L(val) bfin_write16(CAN0_AM01L, val) |
| 2525 | #define bfin_read_CAN0_AM01H() bfin_read16(CAN0_AM01H) |
| 2526 | #define bfin_write_CAN0_AM01H(val) bfin_write16(CAN0_AM01H, val) |
| 2527 | #define bfin_read_CAN0_AM02L() bfin_read16(CAN0_AM02L) |
| 2528 | #define bfin_write_CAN0_AM02L(val) bfin_write16(CAN0_AM02L, val) |
| 2529 | #define bfin_read_CAN0_AM02H() bfin_read16(CAN0_AM02H) |
| 2530 | #define bfin_write_CAN0_AM02H(val) bfin_write16(CAN0_AM02H, val) |
| 2531 | #define bfin_read_CAN0_AM03L() bfin_read16(CAN0_AM03L) |
| 2532 | #define bfin_write_CAN0_AM03L(val) bfin_write16(CAN0_AM03L, val) |
| 2533 | #define bfin_read_CAN0_AM03H() bfin_read16(CAN0_AM03H) |
| 2534 | #define bfin_write_CAN0_AM03H(val) bfin_write16(CAN0_AM03H, val) |
| 2535 | #define bfin_read_CAN0_AM04L() bfin_read16(CAN0_AM04L) |
| 2536 | #define bfin_write_CAN0_AM04L(val) bfin_write16(CAN0_AM04L, val) |
| 2537 | #define bfin_read_CAN0_AM04H() bfin_read16(CAN0_AM04H) |
| 2538 | #define bfin_write_CAN0_AM04H(val) bfin_write16(CAN0_AM04H, val) |
| 2539 | #define bfin_read_CAN0_AM05L() bfin_read16(CAN0_AM05L) |
| 2540 | #define bfin_write_CAN0_AM05L(val) bfin_write16(CAN0_AM05L, val) |
| 2541 | #define bfin_read_CAN0_AM05H() bfin_read16(CAN0_AM05H) |
| 2542 | #define bfin_write_CAN0_AM05H(val) bfin_write16(CAN0_AM05H, val) |
| 2543 | #define bfin_read_CAN0_AM06L() bfin_read16(CAN0_AM06L) |
| 2544 | #define bfin_write_CAN0_AM06L(val) bfin_write16(CAN0_AM06L, val) |
| 2545 | #define bfin_read_CAN0_AM06H() bfin_read16(CAN0_AM06H) |
| 2546 | #define bfin_write_CAN0_AM06H(val) bfin_write16(CAN0_AM06H, val) |
| 2547 | #define bfin_read_CAN0_AM07L() bfin_read16(CAN0_AM07L) |
| 2548 | #define bfin_write_CAN0_AM07L(val) bfin_write16(CAN0_AM07L, val) |
| 2549 | #define bfin_read_CAN0_AM07H() bfin_read16(CAN0_AM07H) |
| 2550 | #define bfin_write_CAN0_AM07H(val) bfin_write16(CAN0_AM07H, val) |
| 2551 | #define bfin_read_CAN0_AM08L() bfin_read16(CAN0_AM08L) |
| 2552 | #define bfin_write_CAN0_AM08L(val) bfin_write16(CAN0_AM08L, val) |
| 2553 | #define bfin_read_CAN0_AM08H() bfin_read16(CAN0_AM08H) |
| 2554 | #define bfin_write_CAN0_AM08H(val) bfin_write16(CAN0_AM08H, val) |
| 2555 | #define bfin_read_CAN0_AM09L() bfin_read16(CAN0_AM09L) |
| 2556 | #define bfin_write_CAN0_AM09L(val) bfin_write16(CAN0_AM09L, val) |
| 2557 | #define bfin_read_CAN0_AM09H() bfin_read16(CAN0_AM09H) |
| 2558 | #define bfin_write_CAN0_AM09H(val) bfin_write16(CAN0_AM09H, val) |
| 2559 | #define bfin_read_CAN0_AM10L() bfin_read16(CAN0_AM10L) |
| 2560 | #define bfin_write_CAN0_AM10L(val) bfin_write16(CAN0_AM10L, val) |
| 2561 | #define bfin_read_CAN0_AM10H() bfin_read16(CAN0_AM10H) |
| 2562 | #define bfin_write_CAN0_AM10H(val) bfin_write16(CAN0_AM10H, val) |
| 2563 | #define bfin_read_CAN0_AM11L() bfin_read16(CAN0_AM11L) |
| 2564 | #define bfin_write_CAN0_AM11L(val) bfin_write16(CAN0_AM11L, val) |
| 2565 | #define bfin_read_CAN0_AM11H() bfin_read16(CAN0_AM11H) |
| 2566 | #define bfin_write_CAN0_AM11H(val) bfin_write16(CAN0_AM11H, val) |
| 2567 | #define bfin_read_CAN0_AM12L() bfin_read16(CAN0_AM12L) |
| 2568 | #define bfin_write_CAN0_AM12L(val) bfin_write16(CAN0_AM12L, val) |
| 2569 | #define bfin_read_CAN0_AM12H() bfin_read16(CAN0_AM12H) |
| 2570 | #define bfin_write_CAN0_AM12H(val) bfin_write16(CAN0_AM12H, val) |
| 2571 | #define bfin_read_CAN0_AM13L() bfin_read16(CAN0_AM13L) |
| 2572 | #define bfin_write_CAN0_AM13L(val) bfin_write16(CAN0_AM13L, val) |
| 2573 | #define bfin_read_CAN0_AM13H() bfin_read16(CAN0_AM13H) |
| 2574 | #define bfin_write_CAN0_AM13H(val) bfin_write16(CAN0_AM13H, val) |
| 2575 | #define bfin_read_CAN0_AM14L() bfin_read16(CAN0_AM14L) |
| 2576 | #define bfin_write_CAN0_AM14L(val) bfin_write16(CAN0_AM14L, val) |
| 2577 | #define bfin_read_CAN0_AM14H() bfin_read16(CAN0_AM14H) |
| 2578 | #define bfin_write_CAN0_AM14H(val) bfin_write16(CAN0_AM14H, val) |
| 2579 | #define bfin_read_CAN0_AM15L() bfin_read16(CAN0_AM15L) |
| 2580 | #define bfin_write_CAN0_AM15L(val) bfin_write16(CAN0_AM15L, val) |
| 2581 | #define bfin_read_CAN0_AM15H() bfin_read16(CAN0_AM15H) |
| 2582 | #define bfin_write_CAN0_AM15H(val) bfin_write16(CAN0_AM15H, val) |
| 2583 | |
| 2584 | /* CAN Controller 0 Accebfin_read_()tance Registers */ |
| 2585 | |
| 2586 | #define bfin_read_CAN0_AM16L() bfin_read16(CAN0_AM16L) |
| 2587 | #define bfin_write_CAN0_AM16L(val) bfin_write16(CAN0_AM16L, val) |
| 2588 | #define bfin_read_CAN0_AM16H() bfin_read16(CAN0_AM16H) |
| 2589 | #define bfin_write_CAN0_AM16H(val) bfin_write16(CAN0_AM16H, val) |
| 2590 | #define bfin_read_CAN0_AM17L() bfin_read16(CAN0_AM17L) |
| 2591 | #define bfin_write_CAN0_AM17L(val) bfin_write16(CAN0_AM17L, val) |
| 2592 | #define bfin_read_CAN0_AM17H() bfin_read16(CAN0_AM17H) |
| 2593 | #define bfin_write_CAN0_AM17H(val) bfin_write16(CAN0_AM17H, val) |
| 2594 | #define bfin_read_CAN0_AM18L() bfin_read16(CAN0_AM18L) |
| 2595 | #define bfin_write_CAN0_AM18L(val) bfin_write16(CAN0_AM18L, val) |
| 2596 | #define bfin_read_CAN0_AM18H() bfin_read16(CAN0_AM18H) |
| 2597 | #define bfin_write_CAN0_AM18H(val) bfin_write16(CAN0_AM18H, val) |
| 2598 | #define bfin_read_CAN0_AM19L() bfin_read16(CAN0_AM19L) |
| 2599 | #define bfin_write_CAN0_AM19L(val) bfin_write16(CAN0_AM19L, val) |
| 2600 | #define bfin_read_CAN0_AM19H() bfin_read16(CAN0_AM19H) |
| 2601 | #define bfin_write_CAN0_AM19H(val) bfin_write16(CAN0_AM19H, val) |
| 2602 | #define bfin_read_CAN0_AM20L() bfin_read16(CAN0_AM20L) |
| 2603 | #define bfin_write_CAN0_AM20L(val) bfin_write16(CAN0_AM20L, val) |
| 2604 | #define bfin_read_CAN0_AM20H() bfin_read16(CAN0_AM20H) |
| 2605 | #define bfin_write_CAN0_AM20H(val) bfin_write16(CAN0_AM20H, val) |
| 2606 | #define bfin_read_CAN0_AM21L() bfin_read16(CAN0_AM21L) |
| 2607 | #define bfin_write_CAN0_AM21L(val) bfin_write16(CAN0_AM21L, val) |
| 2608 | #define bfin_read_CAN0_AM21H() bfin_read16(CAN0_AM21H) |
| 2609 | #define bfin_write_CAN0_AM21H(val) bfin_write16(CAN0_AM21H, val) |
| 2610 | #define bfin_read_CAN0_AM22L() bfin_read16(CAN0_AM22L) |
| 2611 | #define bfin_write_CAN0_AM22L(val) bfin_write16(CAN0_AM22L, val) |
| 2612 | #define bfin_read_CAN0_AM22H() bfin_read16(CAN0_AM22H) |
| 2613 | #define bfin_write_CAN0_AM22H(val) bfin_write16(CAN0_AM22H, val) |
| 2614 | #define bfin_read_CAN0_AM23L() bfin_read16(CAN0_AM23L) |
| 2615 | #define bfin_write_CAN0_AM23L(val) bfin_write16(CAN0_AM23L, val) |
| 2616 | #define bfin_read_CAN0_AM23H() bfin_read16(CAN0_AM23H) |
| 2617 | #define bfin_write_CAN0_AM23H(val) bfin_write16(CAN0_AM23H, val) |
| 2618 | #define bfin_read_CAN0_AM24L() bfin_read16(CAN0_AM24L) |
| 2619 | #define bfin_write_CAN0_AM24L(val) bfin_write16(CAN0_AM24L, val) |
| 2620 | #define bfin_read_CAN0_AM24H() bfin_read16(CAN0_AM24H) |
| 2621 | #define bfin_write_CAN0_AM24H(val) bfin_write16(CAN0_AM24H, val) |
| 2622 | #define bfin_read_CAN0_AM25L() bfin_read16(CAN0_AM25L) |
| 2623 | #define bfin_write_CAN0_AM25L(val) bfin_write16(CAN0_AM25L, val) |
| 2624 | #define bfin_read_CAN0_AM25H() bfin_read16(CAN0_AM25H) |
| 2625 | #define bfin_write_CAN0_AM25H(val) bfin_write16(CAN0_AM25H, val) |
| 2626 | #define bfin_read_CAN0_AM26L() bfin_read16(CAN0_AM26L) |
| 2627 | #define bfin_write_CAN0_AM26L(val) bfin_write16(CAN0_AM26L, val) |
| 2628 | #define bfin_read_CAN0_AM26H() bfin_read16(CAN0_AM26H) |
| 2629 | #define bfin_write_CAN0_AM26H(val) bfin_write16(CAN0_AM26H, val) |
| 2630 | #define bfin_read_CAN0_AM27L() bfin_read16(CAN0_AM27L) |
| 2631 | #define bfin_write_CAN0_AM27L(val) bfin_write16(CAN0_AM27L, val) |
| 2632 | #define bfin_read_CAN0_AM27H() bfin_read16(CAN0_AM27H) |
| 2633 | #define bfin_write_CAN0_AM27H(val) bfin_write16(CAN0_AM27H, val) |
| 2634 | #define bfin_read_CAN0_AM28L() bfin_read16(CAN0_AM28L) |
| 2635 | #define bfin_write_CAN0_AM28L(val) bfin_write16(CAN0_AM28L, val) |
| 2636 | #define bfin_read_CAN0_AM28H() bfin_read16(CAN0_AM28H) |
| 2637 | #define bfin_write_CAN0_AM28H(val) bfin_write16(CAN0_AM28H, val) |
| 2638 | #define bfin_read_CAN0_AM29L() bfin_read16(CAN0_AM29L) |
| 2639 | #define bfin_write_CAN0_AM29L(val) bfin_write16(CAN0_AM29L, val) |
| 2640 | #define bfin_read_CAN0_AM29H() bfin_read16(CAN0_AM29H) |
| 2641 | #define bfin_write_CAN0_AM29H(val) bfin_write16(CAN0_AM29H, val) |
| 2642 | #define bfin_read_CAN0_AM30L() bfin_read16(CAN0_AM30L) |
| 2643 | #define bfin_write_CAN0_AM30L(val) bfin_write16(CAN0_AM30L, val) |
| 2644 | #define bfin_read_CAN0_AM30H() bfin_read16(CAN0_AM30H) |
| 2645 | #define bfin_write_CAN0_AM30H(val) bfin_write16(CAN0_AM30H, val) |
| 2646 | #define bfin_read_CAN0_AM31L() bfin_read16(CAN0_AM31L) |
| 2647 | #define bfin_write_CAN0_AM31L(val) bfin_write16(CAN0_AM31L, val) |
| 2648 | #define bfin_read_CAN0_AM31H() bfin_read16(CAN0_AM31H) |
| 2649 | #define bfin_write_CAN0_AM31H(val) bfin_write16(CAN0_AM31H, val) |
| 2650 | |
| 2651 | /* CAN Controller 0 Mailbox Data Registers */ |
| 2652 | |
| 2653 | #define bfin_read_CAN0_MB00_DATA0() bfin_read16(CAN0_MB00_DATA0) |
| 2654 | #define bfin_write_CAN0_MB00_DATA0(val) bfin_write16(CAN0_MB00_DATA0, val) |
| 2655 | #define bfin_read_CAN0_MB00_DATA1() bfin_read16(CAN0_MB00_DATA1) |
| 2656 | #define bfin_write_CAN0_MB00_DATA1(val) bfin_write16(CAN0_MB00_DATA1, val) |
| 2657 | #define bfin_read_CAN0_MB00_DATA2() bfin_read16(CAN0_MB00_DATA2) |
| 2658 | #define bfin_write_CAN0_MB00_DATA2(val) bfin_write16(CAN0_MB00_DATA2, val) |
| 2659 | #define bfin_read_CAN0_MB00_DATA3() bfin_read16(CAN0_MB00_DATA3) |
| 2660 | #define bfin_write_CAN0_MB00_DATA3(val) bfin_write16(CAN0_MB00_DATA3, val) |
| 2661 | #define bfin_read_CAN0_MB00_LENGTH() bfin_read16(CAN0_MB00_LENGTH) |
| 2662 | #define bfin_write_CAN0_MB00_LENGTH(val) bfin_write16(CAN0_MB00_LENGTH, val) |
| 2663 | #define bfin_read_CAN0_MB00_TIMESTAMP() bfin_read16(CAN0_MB00_TIMESTAMP) |
| 2664 | #define bfin_write_CAN0_MB00_TIMESTAMP(val) bfin_write16(CAN0_MB00_TIMESTAMP, val) |
| 2665 | #define bfin_read_CAN0_MB00_ID0() bfin_read16(CAN0_MB00_ID0) |
| 2666 | #define bfin_write_CAN0_MB00_ID0(val) bfin_write16(CAN0_MB00_ID0, val) |
| 2667 | #define bfin_read_CAN0_MB00_ID1() bfin_read16(CAN0_MB00_ID1) |
| 2668 | #define bfin_write_CAN0_MB00_ID1(val) bfin_write16(CAN0_MB00_ID1, val) |
| 2669 | #define bfin_read_CAN0_MB01_DATA0() bfin_read16(CAN0_MB01_DATA0) |
| 2670 | #define bfin_write_CAN0_MB01_DATA0(val) bfin_write16(CAN0_MB01_DATA0, val) |
| 2671 | #define bfin_read_CAN0_MB01_DATA1() bfin_read16(CAN0_MB01_DATA1) |
| 2672 | #define bfin_write_CAN0_MB01_DATA1(val) bfin_write16(CAN0_MB01_DATA1, val) |
| 2673 | #define bfin_read_CAN0_MB01_DATA2() bfin_read16(CAN0_MB01_DATA2) |
| 2674 | #define bfin_write_CAN0_MB01_DATA2(val) bfin_write16(CAN0_MB01_DATA2, val) |
| 2675 | #define bfin_read_CAN0_MB01_DATA3() bfin_read16(CAN0_MB01_DATA3) |
| 2676 | #define bfin_write_CAN0_MB01_DATA3(val) bfin_write16(CAN0_MB01_DATA3, val) |
| 2677 | #define bfin_read_CAN0_MB01_LENGTH() bfin_read16(CAN0_MB01_LENGTH) |
| 2678 | #define bfin_write_CAN0_MB01_LENGTH(val) bfin_write16(CAN0_MB01_LENGTH, val) |
| 2679 | #define bfin_read_CAN0_MB01_TIMESTAMP() bfin_read16(CAN0_MB01_TIMESTAMP) |
| 2680 | #define bfin_write_CAN0_MB01_TIMESTAMP(val) bfin_write16(CAN0_MB01_TIMESTAMP, val) |
| 2681 | #define bfin_read_CAN0_MB01_ID0() bfin_read16(CAN0_MB01_ID0) |
| 2682 | #define bfin_write_CAN0_MB01_ID0(val) bfin_write16(CAN0_MB01_ID0, val) |
| 2683 | #define bfin_read_CAN0_MB01_ID1() bfin_read16(CAN0_MB01_ID1) |
| 2684 | #define bfin_write_CAN0_MB01_ID1(val) bfin_write16(CAN0_MB01_ID1, val) |
| 2685 | #define bfin_read_CAN0_MB02_DATA0() bfin_read16(CAN0_MB02_DATA0) |
| 2686 | #define bfin_write_CAN0_MB02_DATA0(val) bfin_write16(CAN0_MB02_DATA0, val) |
| 2687 | #define bfin_read_CAN0_MB02_DATA1() bfin_read16(CAN0_MB02_DATA1) |
| 2688 | #define bfin_write_CAN0_MB02_DATA1(val) bfin_write16(CAN0_MB02_DATA1, val) |
| 2689 | #define bfin_read_CAN0_MB02_DATA2() bfin_read16(CAN0_MB02_DATA2) |
| 2690 | #define bfin_write_CAN0_MB02_DATA2(val) bfin_write16(CAN0_MB02_DATA2, val) |
| 2691 | #define bfin_read_CAN0_MB02_DATA3() bfin_read16(CAN0_MB02_DATA3) |
| 2692 | #define bfin_write_CAN0_MB02_DATA3(val) bfin_write16(CAN0_MB02_DATA3, val) |
| 2693 | #define bfin_read_CAN0_MB02_LENGTH() bfin_read16(CAN0_MB02_LENGTH) |
| 2694 | #define bfin_write_CAN0_MB02_LENGTH(val) bfin_write16(CAN0_MB02_LENGTH, val) |
| 2695 | #define bfin_read_CAN0_MB02_TIMESTAMP() bfin_read16(CAN0_MB02_TIMESTAMP) |
| 2696 | #define bfin_write_CAN0_MB02_TIMESTAMP(val) bfin_write16(CAN0_MB02_TIMESTAMP, val) |
| 2697 | #define bfin_read_CAN0_MB02_ID0() bfin_read16(CAN0_MB02_ID0) |
| 2698 | #define bfin_write_CAN0_MB02_ID0(val) bfin_write16(CAN0_MB02_ID0, val) |
| 2699 | #define bfin_read_CAN0_MB02_ID1() bfin_read16(CAN0_MB02_ID1) |
| 2700 | #define bfin_write_CAN0_MB02_ID1(val) bfin_write16(CAN0_MB02_ID1, val) |
| 2701 | #define bfin_read_CAN0_MB03_DATA0() bfin_read16(CAN0_MB03_DATA0) |
| 2702 | #define bfin_write_CAN0_MB03_DATA0(val) bfin_write16(CAN0_MB03_DATA0, val) |
| 2703 | #define bfin_read_CAN0_MB03_DATA1() bfin_read16(CAN0_MB03_DATA1) |
| 2704 | #define bfin_write_CAN0_MB03_DATA1(val) bfin_write16(CAN0_MB03_DATA1, val) |
| 2705 | #define bfin_read_CAN0_MB03_DATA2() bfin_read16(CAN0_MB03_DATA2) |
| 2706 | #define bfin_write_CAN0_MB03_DATA2(val) bfin_write16(CAN0_MB03_DATA2, val) |
| 2707 | #define bfin_read_CAN0_MB03_DATA3() bfin_read16(CAN0_MB03_DATA3) |
| 2708 | #define bfin_write_CAN0_MB03_DATA3(val) bfin_write16(CAN0_MB03_DATA3, val) |
| 2709 | #define bfin_read_CAN0_MB03_LENGTH() bfin_read16(CAN0_MB03_LENGTH) |
| 2710 | #define bfin_write_CAN0_MB03_LENGTH(val) bfin_write16(CAN0_MB03_LENGTH, val) |
| 2711 | #define bfin_read_CAN0_MB03_TIMESTAMP() bfin_read16(CAN0_MB03_TIMESTAMP) |
| 2712 | #define bfin_write_CAN0_MB03_TIMESTAMP(val) bfin_write16(CAN0_MB03_TIMESTAMP, val) |
| 2713 | #define bfin_read_CAN0_MB03_ID0() bfin_read16(CAN0_MB03_ID0) |
| 2714 | #define bfin_write_CAN0_MB03_ID0(val) bfin_write16(CAN0_MB03_ID0, val) |
| 2715 | #define bfin_read_CAN0_MB03_ID1() bfin_read16(CAN0_MB03_ID1) |
| 2716 | #define bfin_write_CAN0_MB03_ID1(val) bfin_write16(CAN0_MB03_ID1, val) |
| 2717 | #define bfin_read_CAN0_MB04_DATA0() bfin_read16(CAN0_MB04_DATA0) |
| 2718 | #define bfin_write_CAN0_MB04_DATA0(val) bfin_write16(CAN0_MB04_DATA0, val) |
| 2719 | #define bfin_read_CAN0_MB04_DATA1() bfin_read16(CAN0_MB04_DATA1) |
| 2720 | #define bfin_write_CAN0_MB04_DATA1(val) bfin_write16(CAN0_MB04_DATA1, val) |
| 2721 | #define bfin_read_CAN0_MB04_DATA2() bfin_read16(CAN0_MB04_DATA2) |
| 2722 | #define bfin_write_CAN0_MB04_DATA2(val) bfin_write16(CAN0_MB04_DATA2, val) |
| 2723 | #define bfin_read_CAN0_MB04_DATA3() bfin_read16(CAN0_MB04_DATA3) |
| 2724 | #define bfin_write_CAN0_MB04_DATA3(val) bfin_write16(CAN0_MB04_DATA3, val) |
| 2725 | #define bfin_read_CAN0_MB04_LENGTH() bfin_read16(CAN0_MB04_LENGTH) |
| 2726 | #define bfin_write_CAN0_MB04_LENGTH(val) bfin_write16(CAN0_MB04_LENGTH, val) |
| 2727 | #define bfin_read_CAN0_MB04_TIMESTAMP() bfin_read16(CAN0_MB04_TIMESTAMP) |
| 2728 | #define bfin_write_CAN0_MB04_TIMESTAMP(val) bfin_write16(CAN0_MB04_TIMESTAMP, val) |
| 2729 | #define bfin_read_CAN0_MB04_ID0() bfin_read16(CAN0_MB04_ID0) |
| 2730 | #define bfin_write_CAN0_MB04_ID0(val) bfin_write16(CAN0_MB04_ID0, val) |
| 2731 | #define bfin_read_CAN0_MB04_ID1() bfin_read16(CAN0_MB04_ID1) |
| 2732 | #define bfin_write_CAN0_MB04_ID1(val) bfin_write16(CAN0_MB04_ID1, val) |
| 2733 | #define bfin_read_CAN0_MB05_DATA0() bfin_read16(CAN0_MB05_DATA0) |
| 2734 | #define bfin_write_CAN0_MB05_DATA0(val) bfin_write16(CAN0_MB05_DATA0, val) |
| 2735 | #define bfin_read_CAN0_MB05_DATA1() bfin_read16(CAN0_MB05_DATA1) |
| 2736 | #define bfin_write_CAN0_MB05_DATA1(val) bfin_write16(CAN0_MB05_DATA1, val) |
| 2737 | #define bfin_read_CAN0_MB05_DATA2() bfin_read16(CAN0_MB05_DATA2) |
| 2738 | #define bfin_write_CAN0_MB05_DATA2(val) bfin_write16(CAN0_MB05_DATA2, val) |
| 2739 | #define bfin_read_CAN0_MB05_DATA3() bfin_read16(CAN0_MB05_DATA3) |
| 2740 | #define bfin_write_CAN0_MB05_DATA3(val) bfin_write16(CAN0_MB05_DATA3, val) |
| 2741 | #define bfin_read_CAN0_MB05_LENGTH() bfin_read16(CAN0_MB05_LENGTH) |
| 2742 | #define bfin_write_CAN0_MB05_LENGTH(val) bfin_write16(CAN0_MB05_LENGTH, val) |
| 2743 | #define bfin_read_CAN0_MB05_TIMESTAMP() bfin_read16(CAN0_MB05_TIMESTAMP) |
| 2744 | #define bfin_write_CAN0_MB05_TIMESTAMP(val) bfin_write16(CAN0_MB05_TIMESTAMP, val) |
| 2745 | #define bfin_read_CAN0_MB05_ID0() bfin_read16(CAN0_MB05_ID0) |
| 2746 | #define bfin_write_CAN0_MB05_ID0(val) bfin_write16(CAN0_MB05_ID0, val) |
| 2747 | #define bfin_read_CAN0_MB05_ID1() bfin_read16(CAN0_MB05_ID1) |
| 2748 | #define bfin_write_CAN0_MB05_ID1(val) bfin_write16(CAN0_MB05_ID1, val) |
| 2749 | #define bfin_read_CAN0_MB06_DATA0() bfin_read16(CAN0_MB06_DATA0) |
| 2750 | #define bfin_write_CAN0_MB06_DATA0(val) bfin_write16(CAN0_MB06_DATA0, val) |
| 2751 | #define bfin_read_CAN0_MB06_DATA1() bfin_read16(CAN0_MB06_DATA1) |
| 2752 | #define bfin_write_CAN0_MB06_DATA1(val) bfin_write16(CAN0_MB06_DATA1, val) |
| 2753 | #define bfin_read_CAN0_MB06_DATA2() bfin_read16(CAN0_MB06_DATA2) |
| 2754 | #define bfin_write_CAN0_MB06_DATA2(val) bfin_write16(CAN0_MB06_DATA2, val) |
| 2755 | #define bfin_read_CAN0_MB06_DATA3() bfin_read16(CAN0_MB06_DATA3) |
| 2756 | #define bfin_write_CAN0_MB06_DATA3(val) bfin_write16(CAN0_MB06_DATA3, val) |
| 2757 | #define bfin_read_CAN0_MB06_LENGTH() bfin_read16(CAN0_MB06_LENGTH) |
| 2758 | #define bfin_write_CAN0_MB06_LENGTH(val) bfin_write16(CAN0_MB06_LENGTH, val) |
| 2759 | #define bfin_read_CAN0_MB06_TIMESTAMP() bfin_read16(CAN0_MB06_TIMESTAMP) |
| 2760 | #define bfin_write_CAN0_MB06_TIMESTAMP(val) bfin_write16(CAN0_MB06_TIMESTAMP, val) |
| 2761 | #define bfin_read_CAN0_MB06_ID0() bfin_read16(CAN0_MB06_ID0) |
| 2762 | #define bfin_write_CAN0_MB06_ID0(val) bfin_write16(CAN0_MB06_ID0, val) |
| 2763 | #define bfin_read_CAN0_MB06_ID1() bfin_read16(CAN0_MB06_ID1) |
| 2764 | #define bfin_write_CAN0_MB06_ID1(val) bfin_write16(CAN0_MB06_ID1, val) |
| 2765 | #define bfin_read_CAN0_MB07_DATA0() bfin_read16(CAN0_MB07_DATA0) |
| 2766 | #define bfin_write_CAN0_MB07_DATA0(val) bfin_write16(CAN0_MB07_DATA0, val) |
| 2767 | #define bfin_read_CAN0_MB07_DATA1() bfin_read16(CAN0_MB07_DATA1) |
| 2768 | #define bfin_write_CAN0_MB07_DATA1(val) bfin_write16(CAN0_MB07_DATA1, val) |
| 2769 | #define bfin_read_CAN0_MB07_DATA2() bfin_read16(CAN0_MB07_DATA2) |
| 2770 | #define bfin_write_CAN0_MB07_DATA2(val) bfin_write16(CAN0_MB07_DATA2, val) |
| 2771 | #define bfin_read_CAN0_MB07_DATA3() bfin_read16(CAN0_MB07_DATA3) |
| 2772 | #define bfin_write_CAN0_MB07_DATA3(val) bfin_write16(CAN0_MB07_DATA3, val) |
| 2773 | #define bfin_read_CAN0_MB07_LENGTH() bfin_read16(CAN0_MB07_LENGTH) |
| 2774 | #define bfin_write_CAN0_MB07_LENGTH(val) bfin_write16(CAN0_MB07_LENGTH, val) |
| 2775 | #define bfin_read_CAN0_MB07_TIMESTAMP() bfin_read16(CAN0_MB07_TIMESTAMP) |
| 2776 | #define bfin_write_CAN0_MB07_TIMESTAMP(val) bfin_write16(CAN0_MB07_TIMESTAMP, val) |
| 2777 | #define bfin_read_CAN0_MB07_ID0() bfin_read16(CAN0_MB07_ID0) |
| 2778 | #define bfin_write_CAN0_MB07_ID0(val) bfin_write16(CAN0_MB07_ID0, val) |
| 2779 | #define bfin_read_CAN0_MB07_ID1() bfin_read16(CAN0_MB07_ID1) |
| 2780 | #define bfin_write_CAN0_MB07_ID1(val) bfin_write16(CAN0_MB07_ID1, val) |
| 2781 | #define bfin_read_CAN0_MB08_DATA0() bfin_read16(CAN0_MB08_DATA0) |
| 2782 | #define bfin_write_CAN0_MB08_DATA0(val) bfin_write16(CAN0_MB08_DATA0, val) |
| 2783 | #define bfin_read_CAN0_MB08_DATA1() bfin_read16(CAN0_MB08_DATA1) |
| 2784 | #define bfin_write_CAN0_MB08_DATA1(val) bfin_write16(CAN0_MB08_DATA1, val) |
| 2785 | #define bfin_read_CAN0_MB08_DATA2() bfin_read16(CAN0_MB08_DATA2) |
| 2786 | #define bfin_write_CAN0_MB08_DATA2(val) bfin_write16(CAN0_MB08_DATA2, val) |
| 2787 | #define bfin_read_CAN0_MB08_DATA3() bfin_read16(CAN0_MB08_DATA3) |
| 2788 | #define bfin_write_CAN0_MB08_DATA3(val) bfin_write16(CAN0_MB08_DATA3, val) |
| 2789 | #define bfin_read_CAN0_MB08_LENGTH() bfin_read16(CAN0_MB08_LENGTH) |
| 2790 | #define bfin_write_CAN0_MB08_LENGTH(val) bfin_write16(CAN0_MB08_LENGTH, val) |
| 2791 | #define bfin_read_CAN0_MB08_TIMESTAMP() bfin_read16(CAN0_MB08_TIMESTAMP) |
| 2792 | #define bfin_write_CAN0_MB08_TIMESTAMP(val) bfin_write16(CAN0_MB08_TIMESTAMP, val) |
| 2793 | #define bfin_read_CAN0_MB08_ID0() bfin_read16(CAN0_MB08_ID0) |
| 2794 | #define bfin_write_CAN0_MB08_ID0(val) bfin_write16(CAN0_MB08_ID0, val) |
| 2795 | #define bfin_read_CAN0_MB08_ID1() bfin_read16(CAN0_MB08_ID1) |
| 2796 | #define bfin_write_CAN0_MB08_ID1(val) bfin_write16(CAN0_MB08_ID1, val) |
| 2797 | #define bfin_read_CAN0_MB09_DATA0() bfin_read16(CAN0_MB09_DATA0) |
| 2798 | #define bfin_write_CAN0_MB09_DATA0(val) bfin_write16(CAN0_MB09_DATA0, val) |
| 2799 | #define bfin_read_CAN0_MB09_DATA1() bfin_read16(CAN0_MB09_DATA1) |
| 2800 | #define bfin_write_CAN0_MB09_DATA1(val) bfin_write16(CAN0_MB09_DATA1, val) |
| 2801 | #define bfin_read_CAN0_MB09_DATA2() bfin_read16(CAN0_MB09_DATA2) |
| 2802 | #define bfin_write_CAN0_MB09_DATA2(val) bfin_write16(CAN0_MB09_DATA2, val) |
| 2803 | #define bfin_read_CAN0_MB09_DATA3() bfin_read16(CAN0_MB09_DATA3) |
| 2804 | #define bfin_write_CAN0_MB09_DATA3(val) bfin_write16(CAN0_MB09_DATA3, val) |
| 2805 | #define bfin_read_CAN0_MB09_LENGTH() bfin_read16(CAN0_MB09_LENGTH) |
| 2806 | #define bfin_write_CAN0_MB09_LENGTH(val) bfin_write16(CAN0_MB09_LENGTH, val) |
| 2807 | #define bfin_read_CAN0_MB09_TIMESTAMP() bfin_read16(CAN0_MB09_TIMESTAMP) |
| 2808 | #define bfin_write_CAN0_MB09_TIMESTAMP(val) bfin_write16(CAN0_MB09_TIMESTAMP, val) |
| 2809 | #define bfin_read_CAN0_MB09_ID0() bfin_read16(CAN0_MB09_ID0) |
| 2810 | #define bfin_write_CAN0_MB09_ID0(val) bfin_write16(CAN0_MB09_ID0, val) |
| 2811 | #define bfin_read_CAN0_MB09_ID1() bfin_read16(CAN0_MB09_ID1) |
| 2812 | #define bfin_write_CAN0_MB09_ID1(val) bfin_write16(CAN0_MB09_ID1, val) |
| 2813 | #define bfin_read_CAN0_MB10_DATA0() bfin_read16(CAN0_MB10_DATA0) |
| 2814 | #define bfin_write_CAN0_MB10_DATA0(val) bfin_write16(CAN0_MB10_DATA0, val) |
| 2815 | #define bfin_read_CAN0_MB10_DATA1() bfin_read16(CAN0_MB10_DATA1) |
| 2816 | #define bfin_write_CAN0_MB10_DATA1(val) bfin_write16(CAN0_MB10_DATA1, val) |
| 2817 | #define bfin_read_CAN0_MB10_DATA2() bfin_read16(CAN0_MB10_DATA2) |
| 2818 | #define bfin_write_CAN0_MB10_DATA2(val) bfin_write16(CAN0_MB10_DATA2, val) |
| 2819 | #define bfin_read_CAN0_MB10_DATA3() bfin_read16(CAN0_MB10_DATA3) |
| 2820 | #define bfin_write_CAN0_MB10_DATA3(val) bfin_write16(CAN0_MB10_DATA3, val) |
| 2821 | #define bfin_read_CAN0_MB10_LENGTH() bfin_read16(CAN0_MB10_LENGTH) |
| 2822 | #define bfin_write_CAN0_MB10_LENGTH(val) bfin_write16(CAN0_MB10_LENGTH, val) |
| 2823 | #define bfin_read_CAN0_MB10_TIMESTAMP() bfin_read16(CAN0_MB10_TIMESTAMP) |
| 2824 | #define bfin_write_CAN0_MB10_TIMESTAMP(val) bfin_write16(CAN0_MB10_TIMESTAMP, val) |
| 2825 | #define bfin_read_CAN0_MB10_ID0() bfin_read16(CAN0_MB10_ID0) |
| 2826 | #define bfin_write_CAN0_MB10_ID0(val) bfin_write16(CAN0_MB10_ID0, val) |
| 2827 | #define bfin_read_CAN0_MB10_ID1() bfin_read16(CAN0_MB10_ID1) |
| 2828 | #define bfin_write_CAN0_MB10_ID1(val) bfin_write16(CAN0_MB10_ID1, val) |
| 2829 | #define bfin_read_CAN0_MB11_DATA0() bfin_read16(CAN0_MB11_DATA0) |
| 2830 | #define bfin_write_CAN0_MB11_DATA0(val) bfin_write16(CAN0_MB11_DATA0, val) |
| 2831 | #define bfin_read_CAN0_MB11_DATA1() bfin_read16(CAN0_MB11_DATA1) |
| 2832 | #define bfin_write_CAN0_MB11_DATA1(val) bfin_write16(CAN0_MB11_DATA1, val) |
| 2833 | #define bfin_read_CAN0_MB11_DATA2() bfin_read16(CAN0_MB11_DATA2) |
| 2834 | #define bfin_write_CAN0_MB11_DATA2(val) bfin_write16(CAN0_MB11_DATA2, val) |
| 2835 | #define bfin_read_CAN0_MB11_DATA3() bfin_read16(CAN0_MB11_DATA3) |
| 2836 | #define bfin_write_CAN0_MB11_DATA3(val) bfin_write16(CAN0_MB11_DATA3, val) |
| 2837 | #define bfin_read_CAN0_MB11_LENGTH() bfin_read16(CAN0_MB11_LENGTH) |
| 2838 | #define bfin_write_CAN0_MB11_LENGTH(val) bfin_write16(CAN0_MB11_LENGTH, val) |
| 2839 | #define bfin_read_CAN0_MB11_TIMESTAMP() bfin_read16(CAN0_MB11_TIMESTAMP) |
| 2840 | #define bfin_write_CAN0_MB11_TIMESTAMP(val) bfin_write16(CAN0_MB11_TIMESTAMP, val) |
| 2841 | #define bfin_read_CAN0_MB11_ID0() bfin_read16(CAN0_MB11_ID0) |
| 2842 | #define bfin_write_CAN0_MB11_ID0(val) bfin_write16(CAN0_MB11_ID0, val) |
| 2843 | #define bfin_read_CAN0_MB11_ID1() bfin_read16(CAN0_MB11_ID1) |
| 2844 | #define bfin_write_CAN0_MB11_ID1(val) bfin_write16(CAN0_MB11_ID1, val) |
| 2845 | #define bfin_read_CAN0_MB12_DATA0() bfin_read16(CAN0_MB12_DATA0) |
| 2846 | #define bfin_write_CAN0_MB12_DATA0(val) bfin_write16(CAN0_MB12_DATA0, val) |
| 2847 | #define bfin_read_CAN0_MB12_DATA1() bfin_read16(CAN0_MB12_DATA1) |
| 2848 | #define bfin_write_CAN0_MB12_DATA1(val) bfin_write16(CAN0_MB12_DATA1, val) |
| 2849 | #define bfin_read_CAN0_MB12_DATA2() bfin_read16(CAN0_MB12_DATA2) |
| 2850 | #define bfin_write_CAN0_MB12_DATA2(val) bfin_write16(CAN0_MB12_DATA2, val) |
| 2851 | #define bfin_read_CAN0_MB12_DATA3() bfin_read16(CAN0_MB12_DATA3) |
| 2852 | #define bfin_write_CAN0_MB12_DATA3(val) bfin_write16(CAN0_MB12_DATA3, val) |
| 2853 | #define bfin_read_CAN0_MB12_LENGTH() bfin_read16(CAN0_MB12_LENGTH) |
| 2854 | #define bfin_write_CAN0_MB12_LENGTH(val) bfin_write16(CAN0_MB12_LENGTH, val) |
| 2855 | #define bfin_read_CAN0_MB12_TIMESTAMP() bfin_read16(CAN0_MB12_TIMESTAMP) |
| 2856 | #define bfin_write_CAN0_MB12_TIMESTAMP(val) bfin_write16(CAN0_MB12_TIMESTAMP, val) |
| 2857 | #define bfin_read_CAN0_MB12_ID0() bfin_read16(CAN0_MB12_ID0) |
| 2858 | #define bfin_write_CAN0_MB12_ID0(val) bfin_write16(CAN0_MB12_ID0, val) |
| 2859 | #define bfin_read_CAN0_MB12_ID1() bfin_read16(CAN0_MB12_ID1) |
| 2860 | #define bfin_write_CAN0_MB12_ID1(val) bfin_write16(CAN0_MB12_ID1, val) |
| 2861 | #define bfin_read_CAN0_MB13_DATA0() bfin_read16(CAN0_MB13_DATA0) |
| 2862 | #define bfin_write_CAN0_MB13_DATA0(val) bfin_write16(CAN0_MB13_DATA0, val) |
| 2863 | #define bfin_read_CAN0_MB13_DATA1() bfin_read16(CAN0_MB13_DATA1) |
| 2864 | #define bfin_write_CAN0_MB13_DATA1(val) bfin_write16(CAN0_MB13_DATA1, val) |
| 2865 | #define bfin_read_CAN0_MB13_DATA2() bfin_read16(CAN0_MB13_DATA2) |
| 2866 | #define bfin_write_CAN0_MB13_DATA2(val) bfin_write16(CAN0_MB13_DATA2, val) |
| 2867 | #define bfin_read_CAN0_MB13_DATA3() bfin_read16(CAN0_MB13_DATA3) |
| 2868 | #define bfin_write_CAN0_MB13_DATA3(val) bfin_write16(CAN0_MB13_DATA3, val) |
| 2869 | #define bfin_read_CAN0_MB13_LENGTH() bfin_read16(CAN0_MB13_LENGTH) |
| 2870 | #define bfin_write_CAN0_MB13_LENGTH(val) bfin_write16(CAN0_MB13_LENGTH, val) |
| 2871 | #define bfin_read_CAN0_MB13_TIMESTAMP() bfin_read16(CAN0_MB13_TIMESTAMP) |
| 2872 | #define bfin_write_CAN0_MB13_TIMESTAMP(val) bfin_write16(CAN0_MB13_TIMESTAMP, val) |
| 2873 | #define bfin_read_CAN0_MB13_ID0() bfin_read16(CAN0_MB13_ID0) |
| 2874 | #define bfin_write_CAN0_MB13_ID0(val) bfin_write16(CAN0_MB13_ID0, val) |
| 2875 | #define bfin_read_CAN0_MB13_ID1() bfin_read16(CAN0_MB13_ID1) |
| 2876 | #define bfin_write_CAN0_MB13_ID1(val) bfin_write16(CAN0_MB13_ID1, val) |
| 2877 | #define bfin_read_CAN0_MB14_DATA0() bfin_read16(CAN0_MB14_DATA0) |
| 2878 | #define bfin_write_CAN0_MB14_DATA0(val) bfin_write16(CAN0_MB14_DATA0, val) |
| 2879 | #define bfin_read_CAN0_MB14_DATA1() bfin_read16(CAN0_MB14_DATA1) |
| 2880 | #define bfin_write_CAN0_MB14_DATA1(val) bfin_write16(CAN0_MB14_DATA1, val) |
| 2881 | #define bfin_read_CAN0_MB14_DATA2() bfin_read16(CAN0_MB14_DATA2) |
| 2882 | #define bfin_write_CAN0_MB14_DATA2(val) bfin_write16(CAN0_MB14_DATA2, val) |
| 2883 | #define bfin_read_CAN0_MB14_DATA3() bfin_read16(CAN0_MB14_DATA3) |
| 2884 | #define bfin_write_CAN0_MB14_DATA3(val) bfin_write16(CAN0_MB14_DATA3, val) |
| 2885 | #define bfin_read_CAN0_MB14_LENGTH() bfin_read16(CAN0_MB14_LENGTH) |
| 2886 | #define bfin_write_CAN0_MB14_LENGTH(val) bfin_write16(CAN0_MB14_LENGTH, val) |
| 2887 | #define bfin_read_CAN0_MB14_TIMESTAMP() bfin_read16(CAN0_MB14_TIMESTAMP) |
| 2888 | #define bfin_write_CAN0_MB14_TIMESTAMP(val) bfin_write16(CAN0_MB14_TIMESTAMP, val) |
| 2889 | #define bfin_read_CAN0_MB14_ID0() bfin_read16(CAN0_MB14_ID0) |
| 2890 | #define bfin_write_CAN0_MB14_ID0(val) bfin_write16(CAN0_MB14_ID0, val) |
| 2891 | #define bfin_read_CAN0_MB14_ID1() bfin_read16(CAN0_MB14_ID1) |
| 2892 | #define bfin_write_CAN0_MB14_ID1(val) bfin_write16(CAN0_MB14_ID1, val) |
| 2893 | #define bfin_read_CAN0_MB15_DATA0() bfin_read16(CAN0_MB15_DATA0) |
| 2894 | #define bfin_write_CAN0_MB15_DATA0(val) bfin_write16(CAN0_MB15_DATA0, val) |
| 2895 | #define bfin_read_CAN0_MB15_DATA1() bfin_read16(CAN0_MB15_DATA1) |
| 2896 | #define bfin_write_CAN0_MB15_DATA1(val) bfin_write16(CAN0_MB15_DATA1, val) |
| 2897 | #define bfin_read_CAN0_MB15_DATA2() bfin_read16(CAN0_MB15_DATA2) |
| 2898 | #define bfin_write_CAN0_MB15_DATA2(val) bfin_write16(CAN0_MB15_DATA2, val) |
| 2899 | #define bfin_read_CAN0_MB15_DATA3() bfin_read16(CAN0_MB15_DATA3) |
| 2900 | #define bfin_write_CAN0_MB15_DATA3(val) bfin_write16(CAN0_MB15_DATA3, val) |
| 2901 | #define bfin_read_CAN0_MB15_LENGTH() bfin_read16(CAN0_MB15_LENGTH) |
| 2902 | #define bfin_write_CAN0_MB15_LENGTH(val) bfin_write16(CAN0_MB15_LENGTH, val) |
| 2903 | #define bfin_read_CAN0_MB15_TIMESTAMP() bfin_read16(CAN0_MB15_TIMESTAMP) |
| 2904 | #define bfin_write_CAN0_MB15_TIMESTAMP(val) bfin_write16(CAN0_MB15_TIMESTAMP, val) |
| 2905 | #define bfin_read_CAN0_MB15_ID0() bfin_read16(CAN0_MB15_ID0) |
| 2906 | #define bfin_write_CAN0_MB15_ID0(val) bfin_write16(CAN0_MB15_ID0, val) |
| 2907 | #define bfin_read_CAN0_MB15_ID1() bfin_read16(CAN0_MB15_ID1) |
| 2908 | #define bfin_write_CAN0_MB15_ID1(val) bfin_write16(CAN0_MB15_ID1, val) |
| 2909 | |
| 2910 | /* CAN Controller 0 Mailbox Data Registers */ |
| 2911 | |
| 2912 | #define bfin_read_CAN0_MB16_DATA0() bfin_read16(CAN0_MB16_DATA0) |
| 2913 | #define bfin_write_CAN0_MB16_DATA0(val) bfin_write16(CAN0_MB16_DATA0, val) |
| 2914 | #define bfin_read_CAN0_MB16_DATA1() bfin_read16(CAN0_MB16_DATA1) |
| 2915 | #define bfin_write_CAN0_MB16_DATA1(val) bfin_write16(CAN0_MB16_DATA1, val) |
| 2916 | #define bfin_read_CAN0_MB16_DATA2() bfin_read16(CAN0_MB16_DATA2) |
| 2917 | #define bfin_write_CAN0_MB16_DATA2(val) bfin_write16(CAN0_MB16_DATA2, val) |
| 2918 | #define bfin_read_CAN0_MB16_DATA3() bfin_read16(CAN0_MB16_DATA3) |
| 2919 | #define bfin_write_CAN0_MB16_DATA3(val) bfin_write16(CAN0_MB16_DATA3, val) |
| 2920 | #define bfin_read_CAN0_MB16_LENGTH() bfin_read16(CAN0_MB16_LENGTH) |
| 2921 | #define bfin_write_CAN0_MB16_LENGTH(val) bfin_write16(CAN0_MB16_LENGTH, val) |
| 2922 | #define bfin_read_CAN0_MB16_TIMESTAMP() bfin_read16(CAN0_MB16_TIMESTAMP) |
| 2923 | #define bfin_write_CAN0_MB16_TIMESTAMP(val) bfin_write16(CAN0_MB16_TIMESTAMP, val) |
| 2924 | #define bfin_read_CAN0_MB16_ID0() bfin_read16(CAN0_MB16_ID0) |
| 2925 | #define bfin_write_CAN0_MB16_ID0(val) bfin_write16(CAN0_MB16_ID0, val) |
| 2926 | #define bfin_read_CAN0_MB16_ID1() bfin_read16(CAN0_MB16_ID1) |
| 2927 | #define bfin_write_CAN0_MB16_ID1(val) bfin_write16(CAN0_MB16_ID1, val) |
| 2928 | #define bfin_read_CAN0_MB17_DATA0() bfin_read16(CAN0_MB17_DATA0) |
| 2929 | #define bfin_write_CAN0_MB17_DATA0(val) bfin_write16(CAN0_MB17_DATA0, val) |
| 2930 | #define bfin_read_CAN0_MB17_DATA1() bfin_read16(CAN0_MB17_DATA1) |
| 2931 | #define bfin_write_CAN0_MB17_DATA1(val) bfin_write16(CAN0_MB17_DATA1, val) |
| 2932 | #define bfin_read_CAN0_MB17_DATA2() bfin_read16(CAN0_MB17_DATA2) |
| 2933 | #define bfin_write_CAN0_MB17_DATA2(val) bfin_write16(CAN0_MB17_DATA2, val) |
| 2934 | #define bfin_read_CAN0_MB17_DATA3() bfin_read16(CAN0_MB17_DATA3) |
| 2935 | #define bfin_write_CAN0_MB17_DATA3(val) bfin_write16(CAN0_MB17_DATA3, val) |
| 2936 | #define bfin_read_CAN0_MB17_LENGTH() bfin_read16(CAN0_MB17_LENGTH) |
| 2937 | #define bfin_write_CAN0_MB17_LENGTH(val) bfin_write16(CAN0_MB17_LENGTH, val) |
| 2938 | #define bfin_read_CAN0_MB17_TIMESTAMP() bfin_read16(CAN0_MB17_TIMESTAMP) |
| 2939 | #define bfin_write_CAN0_MB17_TIMESTAMP(val) bfin_write16(CAN0_MB17_TIMESTAMP, val) |
| 2940 | #define bfin_read_CAN0_MB17_ID0() bfin_read16(CAN0_MB17_ID0) |
| 2941 | #define bfin_write_CAN0_MB17_ID0(val) bfin_write16(CAN0_MB17_ID0, val) |
| 2942 | #define bfin_read_CAN0_MB17_ID1() bfin_read16(CAN0_MB17_ID1) |
| 2943 | #define bfin_write_CAN0_MB17_ID1(val) bfin_write16(CAN0_MB17_ID1, val) |
| 2944 | #define bfin_read_CAN0_MB18_DATA0() bfin_read16(CAN0_MB18_DATA0) |
| 2945 | #define bfin_write_CAN0_MB18_DATA0(val) bfin_write16(CAN0_MB18_DATA0, val) |
| 2946 | #define bfin_read_CAN0_MB18_DATA1() bfin_read16(CAN0_MB18_DATA1) |
| 2947 | #define bfin_write_CAN0_MB18_DATA1(val) bfin_write16(CAN0_MB18_DATA1, val) |
| 2948 | #define bfin_read_CAN0_MB18_DATA2() bfin_read16(CAN0_MB18_DATA2) |
| 2949 | #define bfin_write_CAN0_MB18_DATA2(val) bfin_write16(CAN0_MB18_DATA2, val) |
| 2950 | #define bfin_read_CAN0_MB18_DATA3() bfin_read16(CAN0_MB18_DATA3) |
| 2951 | #define bfin_write_CAN0_MB18_DATA3(val) bfin_write16(CAN0_MB18_DATA3, val) |
| 2952 | #define bfin_read_CAN0_MB18_LENGTH() bfin_read16(CAN0_MB18_LENGTH) |
| 2953 | #define bfin_write_CAN0_MB18_LENGTH(val) bfin_write16(CAN0_MB18_LENGTH, val) |
| 2954 | #define bfin_read_CAN0_MB18_TIMESTAMP() bfin_read16(CAN0_MB18_TIMESTAMP) |
| 2955 | #define bfin_write_CAN0_MB18_TIMESTAMP(val) bfin_write16(CAN0_MB18_TIMESTAMP, val) |
| 2956 | #define bfin_read_CAN0_MB18_ID0() bfin_read16(CAN0_MB18_ID0) |
| 2957 | #define bfin_write_CAN0_MB18_ID0(val) bfin_write16(CAN0_MB18_ID0, val) |
| 2958 | #define bfin_read_CAN0_MB18_ID1() bfin_read16(CAN0_MB18_ID1) |
| 2959 | #define bfin_write_CAN0_MB18_ID1(val) bfin_write16(CAN0_MB18_ID1, val) |
| 2960 | #define bfin_read_CAN0_MB19_DATA0() bfin_read16(CAN0_MB19_DATA0) |
| 2961 | #define bfin_write_CAN0_MB19_DATA0(val) bfin_write16(CAN0_MB19_DATA0, val) |
| 2962 | #define bfin_read_CAN0_MB19_DATA1() bfin_read16(CAN0_MB19_DATA1) |
| 2963 | #define bfin_write_CAN0_MB19_DATA1(val) bfin_write16(CAN0_MB19_DATA1, val) |
| 2964 | #define bfin_read_CAN0_MB19_DATA2() bfin_read16(CAN0_MB19_DATA2) |
| 2965 | #define bfin_write_CAN0_MB19_DATA2(val) bfin_write16(CAN0_MB19_DATA2, val) |
| 2966 | #define bfin_read_CAN0_MB19_DATA3() bfin_read16(CAN0_MB19_DATA3) |
| 2967 | #define bfin_write_CAN0_MB19_DATA3(val) bfin_write16(CAN0_MB19_DATA3, val) |
| 2968 | #define bfin_read_CAN0_MB19_LENGTH() bfin_read16(CAN0_MB19_LENGTH) |
| 2969 | #define bfin_write_CAN0_MB19_LENGTH(val) bfin_write16(CAN0_MB19_LENGTH, val) |
| 2970 | #define bfin_read_CAN0_MB19_TIMESTAMP() bfin_read16(CAN0_MB19_TIMESTAMP) |
| 2971 | #define bfin_write_CAN0_MB19_TIMESTAMP(val) bfin_write16(CAN0_MB19_TIMESTAMP, val) |
| 2972 | #define bfin_read_CAN0_MB19_ID0() bfin_read16(CAN0_MB19_ID0) |
| 2973 | #define bfin_write_CAN0_MB19_ID0(val) bfin_write16(CAN0_MB19_ID0, val) |
| 2974 | #define bfin_read_CAN0_MB19_ID1() bfin_read16(CAN0_MB19_ID1) |
| 2975 | #define bfin_write_CAN0_MB19_ID1(val) bfin_write16(CAN0_MB19_ID1, val) |
| 2976 | #define bfin_read_CAN0_MB20_DATA0() bfin_read16(CAN0_MB20_DATA0) |
| 2977 | #define bfin_write_CAN0_MB20_DATA0(val) bfin_write16(CAN0_MB20_DATA0, val) |
| 2978 | #define bfin_read_CAN0_MB20_DATA1() bfin_read16(CAN0_MB20_DATA1) |
| 2979 | #define bfin_write_CAN0_MB20_DATA1(val) bfin_write16(CAN0_MB20_DATA1, val) |
| 2980 | #define bfin_read_CAN0_MB20_DATA2() bfin_read16(CAN0_MB20_DATA2) |
| 2981 | #define bfin_write_CAN0_MB20_DATA2(val) bfin_write16(CAN0_MB20_DATA2, val) |
| 2982 | #define bfin_read_CAN0_MB20_DATA3() bfin_read16(CAN0_MB20_DATA3) |
| 2983 | #define bfin_write_CAN0_MB20_DATA3(val) bfin_write16(CAN0_MB20_DATA3, val) |
| 2984 | #define bfin_read_CAN0_MB20_LENGTH() bfin_read16(CAN0_MB20_LENGTH) |
| 2985 | #define bfin_write_CAN0_MB20_LENGTH(val) bfin_write16(CAN0_MB20_LENGTH, val) |
| 2986 | #define bfin_read_CAN0_MB20_TIMESTAMP() bfin_read16(CAN0_MB20_TIMESTAMP) |
| 2987 | #define bfin_write_CAN0_MB20_TIMESTAMP(val) bfin_write16(CAN0_MB20_TIMESTAMP, val) |
| 2988 | #define bfin_read_CAN0_MB20_ID0() bfin_read16(CAN0_MB20_ID0) |
| 2989 | #define bfin_write_CAN0_MB20_ID0(val) bfin_write16(CAN0_MB20_ID0, val) |
| 2990 | #define bfin_read_CAN0_MB20_ID1() bfin_read16(CAN0_MB20_ID1) |
| 2991 | #define bfin_write_CAN0_MB20_ID1(val) bfin_write16(CAN0_MB20_ID1, val) |
| 2992 | #define bfin_read_CAN0_MB21_DATA0() bfin_read16(CAN0_MB21_DATA0) |
| 2993 | #define bfin_write_CAN0_MB21_DATA0(val) bfin_write16(CAN0_MB21_DATA0, val) |
| 2994 | #define bfin_read_CAN0_MB21_DATA1() bfin_read16(CAN0_MB21_DATA1) |
| 2995 | #define bfin_write_CAN0_MB21_DATA1(val) bfin_write16(CAN0_MB21_DATA1, val) |
| 2996 | #define bfin_read_CAN0_MB21_DATA2() bfin_read16(CAN0_MB21_DATA2) |
| 2997 | #define bfin_write_CAN0_MB21_DATA2(val) bfin_write16(CAN0_MB21_DATA2, val) |
| 2998 | #define bfin_read_CAN0_MB21_DATA3() bfin_read16(CAN0_MB21_DATA3) |
| 2999 | #define bfin_write_CAN0_MB21_DATA3(val) bfin_write16(CAN0_MB21_DATA3, val) |
| 3000 | #define bfin_read_CAN0_MB21_LENGTH() bfin_read16(CAN0_MB21_LENGTH) |
| 3001 | #define bfin_write_CAN0_MB21_LENGTH(val) bfin_write16(CAN0_MB21_LENGTH, val) |
| 3002 | #define bfin_read_CAN0_MB21_TIMESTAMP() bfin_read16(CAN0_MB21_TIMESTAMP) |
| 3003 | #define bfin_write_CAN0_MB21_TIMESTAMP(val) bfin_write16(CAN0_MB21_TIMESTAMP, val) |
| 3004 | #define bfin_read_CAN0_MB21_ID0() bfin_read16(CAN0_MB21_ID0) |
| 3005 | #define bfin_write_CAN0_MB21_ID0(val) bfin_write16(CAN0_MB21_ID0, val) |
| 3006 | #define bfin_read_CAN0_MB21_ID1() bfin_read16(CAN0_MB21_ID1) |
| 3007 | #define bfin_write_CAN0_MB21_ID1(val) bfin_write16(CAN0_MB21_ID1, val) |
| 3008 | #define bfin_read_CAN0_MB22_DATA0() bfin_read16(CAN0_MB22_DATA0) |
| 3009 | #define bfin_write_CAN0_MB22_DATA0(val) bfin_write16(CAN0_MB22_DATA0, val) |
| 3010 | #define bfin_read_CAN0_MB22_DATA1() bfin_read16(CAN0_MB22_DATA1) |
| 3011 | #define bfin_write_CAN0_MB22_DATA1(val) bfin_write16(CAN0_MB22_DATA1, val) |
| 3012 | #define bfin_read_CAN0_MB22_DATA2() bfin_read16(CAN0_MB22_DATA2) |
| 3013 | #define bfin_write_CAN0_MB22_DATA2(val) bfin_write16(CAN0_MB22_DATA2, val) |
| 3014 | #define bfin_read_CAN0_MB22_DATA3() bfin_read16(CAN0_MB22_DATA3) |
| 3015 | #define bfin_write_CAN0_MB22_DATA3(val) bfin_write16(CAN0_MB22_DATA3, val) |
| 3016 | #define bfin_read_CAN0_MB22_LENGTH() bfin_read16(CAN0_MB22_LENGTH) |
| 3017 | #define bfin_write_CAN0_MB22_LENGTH(val) bfin_write16(CAN0_MB22_LENGTH, val) |
| 3018 | #define bfin_read_CAN0_MB22_TIMESTAMP() bfin_read16(CAN0_MB22_TIMESTAMP) |
| 3019 | #define bfin_write_CAN0_MB22_TIMESTAMP(val) bfin_write16(CAN0_MB22_TIMESTAMP, val) |
| 3020 | #define bfin_read_CAN0_MB22_ID0() bfin_read16(CAN0_MB22_ID0) |
| 3021 | #define bfin_write_CAN0_MB22_ID0(val) bfin_write16(CAN0_MB22_ID0, val) |
| 3022 | #define bfin_read_CAN0_MB22_ID1() bfin_read16(CAN0_MB22_ID1) |
| 3023 | #define bfin_write_CAN0_MB22_ID1(val) bfin_write16(CAN0_MB22_ID1, val) |
| 3024 | #define bfin_read_CAN0_MB23_DATA0() bfin_read16(CAN0_MB23_DATA0) |
| 3025 | #define bfin_write_CAN0_MB23_DATA0(val) bfin_write16(CAN0_MB23_DATA0, val) |
| 3026 | #define bfin_read_CAN0_MB23_DATA1() bfin_read16(CAN0_MB23_DATA1) |
| 3027 | #define bfin_write_CAN0_MB23_DATA1(val) bfin_write16(CAN0_MB23_DATA1, val) |
| 3028 | #define bfin_read_CAN0_MB23_DATA2() bfin_read16(CAN0_MB23_DATA2) |
| 3029 | #define bfin_write_CAN0_MB23_DATA2(val) bfin_write16(CAN0_MB23_DATA2, val) |
| 3030 | #define bfin_read_CAN0_MB23_DATA3() bfin_read16(CAN0_MB23_DATA3) |
| 3031 | #define bfin_write_CAN0_MB23_DATA3(val) bfin_write16(CAN0_MB23_DATA3, val) |
| 3032 | #define bfin_read_CAN0_MB23_LENGTH() bfin_read16(CAN0_MB23_LENGTH) |
| 3033 | #define bfin_write_CAN0_MB23_LENGTH(val) bfin_write16(CAN0_MB23_LENGTH, val) |
| 3034 | #define bfin_read_CAN0_MB23_TIMESTAMP() bfin_read16(CAN0_MB23_TIMESTAMP) |
| 3035 | #define bfin_write_CAN0_MB23_TIMESTAMP(val) bfin_write16(CAN0_MB23_TIMESTAMP, val) |
| 3036 | #define bfin_read_CAN0_MB23_ID0() bfin_read16(CAN0_MB23_ID0) |
| 3037 | #define bfin_write_CAN0_MB23_ID0(val) bfin_write16(CAN0_MB23_ID0, val) |
| 3038 | #define bfin_read_CAN0_MB23_ID1() bfin_read16(CAN0_MB23_ID1) |
| 3039 | #define bfin_write_CAN0_MB23_ID1(val) bfin_write16(CAN0_MB23_ID1, val) |
| 3040 | #define bfin_read_CAN0_MB24_DATA0() bfin_read16(CAN0_MB24_DATA0) |
| 3041 | #define bfin_write_CAN0_MB24_DATA0(val) bfin_write16(CAN0_MB24_DATA0, val) |
| 3042 | #define bfin_read_CAN0_MB24_DATA1() bfin_read16(CAN0_MB24_DATA1) |
| 3043 | #define bfin_write_CAN0_MB24_DATA1(val) bfin_write16(CAN0_MB24_DATA1, val) |
| 3044 | #define bfin_read_CAN0_MB24_DATA2() bfin_read16(CAN0_MB24_DATA2) |
| 3045 | #define bfin_write_CAN0_MB24_DATA2(val) bfin_write16(CAN0_MB24_DATA2, val) |
| 3046 | #define bfin_read_CAN0_MB24_DATA3() bfin_read16(CAN0_MB24_DATA3) |
| 3047 | #define bfin_write_CAN0_MB24_DATA3(val) bfin_write16(CAN0_MB24_DATA3, val) |
| 3048 | #define bfin_read_CAN0_MB24_LENGTH() bfin_read16(CAN0_MB24_LENGTH) |
| 3049 | #define bfin_write_CAN0_MB24_LENGTH(val) bfin_write16(CAN0_MB24_LENGTH, val) |
| 3050 | #define bfin_read_CAN0_MB24_TIMESTAMP() bfin_read16(CAN0_MB24_TIMESTAMP) |
| 3051 | #define bfin_write_CAN0_MB24_TIMESTAMP(val) bfin_write16(CAN0_MB24_TIMESTAMP, val) |
| 3052 | #define bfin_read_CAN0_MB24_ID0() bfin_read16(CAN0_MB24_ID0) |
| 3053 | #define bfin_write_CAN0_MB24_ID0(val) bfin_write16(CAN0_MB24_ID0, val) |
| 3054 | #define bfin_read_CAN0_MB24_ID1() bfin_read16(CAN0_MB24_ID1) |
| 3055 | #define bfin_write_CAN0_MB24_ID1(val) bfin_write16(CAN0_MB24_ID1, val) |
| 3056 | #define bfin_read_CAN0_MB25_DATA0() bfin_read16(CAN0_MB25_DATA0) |
| 3057 | #define bfin_write_CAN0_MB25_DATA0(val) bfin_write16(CAN0_MB25_DATA0, val) |
| 3058 | #define bfin_read_CAN0_MB25_DATA1() bfin_read16(CAN0_MB25_DATA1) |
| 3059 | #define bfin_write_CAN0_MB25_DATA1(val) bfin_write16(CAN0_MB25_DATA1, val) |
| 3060 | #define bfin_read_CAN0_MB25_DATA2() bfin_read16(CAN0_MB25_DATA2) |
| 3061 | #define bfin_write_CAN0_MB25_DATA2(val) bfin_write16(CAN0_MB25_DATA2, val) |
| 3062 | #define bfin_read_CAN0_MB25_DATA3() bfin_read16(CAN0_MB25_DATA3) |
| 3063 | #define bfin_write_CAN0_MB25_DATA3(val) bfin_write16(CAN0_MB25_DATA3, val) |
| 3064 | #define bfin_read_CAN0_MB25_LENGTH() bfin_read16(CAN0_MB25_LENGTH) |
| 3065 | #define bfin_write_CAN0_MB25_LENGTH(val) bfin_write16(CAN0_MB25_LENGTH, val) |
| 3066 | #define bfin_read_CAN0_MB25_TIMESTAMP() bfin_read16(CAN0_MB25_TIMESTAMP) |
| 3067 | #define bfin_write_CAN0_MB25_TIMESTAMP(val) bfin_write16(CAN0_MB25_TIMESTAMP, val) |
| 3068 | #define bfin_read_CAN0_MB25_ID0() bfin_read16(CAN0_MB25_ID0) |
| 3069 | #define bfin_write_CAN0_MB25_ID0(val) bfin_write16(CAN0_MB25_ID0, val) |
| 3070 | #define bfin_read_CAN0_MB25_ID1() bfin_read16(CAN0_MB25_ID1) |
| 3071 | #define bfin_write_CAN0_MB25_ID1(val) bfin_write16(CAN0_MB25_ID1, val) |
| 3072 | #define bfin_read_CAN0_MB26_DATA0() bfin_read16(CAN0_MB26_DATA0) |
| 3073 | #define bfin_write_CAN0_MB26_DATA0(val) bfin_write16(CAN0_MB26_DATA0, val) |
| 3074 | #define bfin_read_CAN0_MB26_DATA1() bfin_read16(CAN0_MB26_DATA1) |
| 3075 | #define bfin_write_CAN0_MB26_DATA1(val) bfin_write16(CAN0_MB26_DATA1, val) |
| 3076 | #define bfin_read_CAN0_MB26_DATA2() bfin_read16(CAN0_MB26_DATA2) |
| 3077 | #define bfin_write_CAN0_MB26_DATA2(val) bfin_write16(CAN0_MB26_DATA2, val) |
| 3078 | #define bfin_read_CAN0_MB26_DATA3() bfin_read16(CAN0_MB26_DATA3) |
| 3079 | #define bfin_write_CAN0_MB26_DATA3(val) bfin_write16(CAN0_MB26_DATA3, val) |
| 3080 | #define bfin_read_CAN0_MB26_LENGTH() bfin_read16(CAN0_MB26_LENGTH) |
| 3081 | #define bfin_write_CAN0_MB26_LENGTH(val) bfin_write16(CAN0_MB26_LENGTH, val) |
| 3082 | #define bfin_read_CAN0_MB26_TIMESTAMP() bfin_read16(CAN0_MB26_TIMESTAMP) |
| 3083 | #define bfin_write_CAN0_MB26_TIMESTAMP(val) bfin_write16(CAN0_MB26_TIMESTAMP, val) |
| 3084 | #define bfin_read_CAN0_MB26_ID0() bfin_read16(CAN0_MB26_ID0) |
| 3085 | #define bfin_write_CAN0_MB26_ID0(val) bfin_write16(CAN0_MB26_ID0, val) |
| 3086 | #define bfin_read_CAN0_MB26_ID1() bfin_read16(CAN0_MB26_ID1) |
| 3087 | #define bfin_write_CAN0_MB26_ID1(val) bfin_write16(CAN0_MB26_ID1, val) |
| 3088 | #define bfin_read_CAN0_MB27_DATA0() bfin_read16(CAN0_MB27_DATA0) |
| 3089 | #define bfin_write_CAN0_MB27_DATA0(val) bfin_write16(CAN0_MB27_DATA0, val) |
| 3090 | #define bfin_read_CAN0_MB27_DATA1() bfin_read16(CAN0_MB27_DATA1) |
| 3091 | #define bfin_write_CAN0_MB27_DATA1(val) bfin_write16(CAN0_MB27_DATA1, val) |
| 3092 | #define bfin_read_CAN0_MB27_DATA2() bfin_read16(CAN0_MB27_DATA2) |
| 3093 | #define bfin_write_CAN0_MB27_DATA2(val) bfin_write16(CAN0_MB27_DATA2, val) |
| 3094 | #define bfin_read_CAN0_MB27_DATA3() bfin_read16(CAN0_MB27_DATA3) |
| 3095 | #define bfin_write_CAN0_MB27_DATA3(val) bfin_write16(CAN0_MB27_DATA3, val) |
| 3096 | #define bfin_read_CAN0_MB27_LENGTH() bfin_read16(CAN0_MB27_LENGTH) |
| 3097 | #define bfin_write_CAN0_MB27_LENGTH(val) bfin_write16(CAN0_MB27_LENGTH, val) |
| 3098 | #define bfin_read_CAN0_MB27_TIMESTAMP() bfin_read16(CAN0_MB27_TIMESTAMP) |
| 3099 | #define bfin_write_CAN0_MB27_TIMESTAMP(val) bfin_write16(CAN0_MB27_TIMESTAMP, val) |
| 3100 | #define bfin_read_CAN0_MB27_ID0() bfin_read16(CAN0_MB27_ID0) |
| 3101 | #define bfin_write_CAN0_MB27_ID0(val) bfin_write16(CAN0_MB27_ID0, val) |
| 3102 | #define bfin_read_CAN0_MB27_ID1() bfin_read16(CAN0_MB27_ID1) |
| 3103 | #define bfin_write_CAN0_MB27_ID1(val) bfin_write16(CAN0_MB27_ID1, val) |
| 3104 | #define bfin_read_CAN0_MB28_DATA0() bfin_read16(CAN0_MB28_DATA0) |
| 3105 | #define bfin_write_CAN0_MB28_DATA0(val) bfin_write16(CAN0_MB28_DATA0, val) |
| 3106 | #define bfin_read_CAN0_MB28_DATA1() bfin_read16(CAN0_MB28_DATA1) |
| 3107 | #define bfin_write_CAN0_MB28_DATA1(val) bfin_write16(CAN0_MB28_DATA1, val) |
| 3108 | #define bfin_read_CAN0_MB28_DATA2() bfin_read16(CAN0_MB28_DATA2) |
| 3109 | #define bfin_write_CAN0_MB28_DATA2(val) bfin_write16(CAN0_MB28_DATA2, val) |
| 3110 | #define bfin_read_CAN0_MB28_DATA3() bfin_read16(CAN0_MB28_DATA3) |
| 3111 | #define bfin_write_CAN0_MB28_DATA3(val) bfin_write16(CAN0_MB28_DATA3, val) |
| 3112 | #define bfin_read_CAN0_MB28_LENGTH() bfin_read16(CAN0_MB28_LENGTH) |
| 3113 | #define bfin_write_CAN0_MB28_LENGTH(val) bfin_write16(CAN0_MB28_LENGTH, val) |
| 3114 | #define bfin_read_CAN0_MB28_TIMESTAMP() bfin_read16(CAN0_MB28_TIMESTAMP) |
| 3115 | #define bfin_write_CAN0_MB28_TIMESTAMP(val) bfin_write16(CAN0_MB28_TIMESTAMP, val) |
| 3116 | #define bfin_read_CAN0_MB28_ID0() bfin_read16(CAN0_MB28_ID0) |
| 3117 | #define bfin_write_CAN0_MB28_ID0(val) bfin_write16(CAN0_MB28_ID0, val) |
| 3118 | #define bfin_read_CAN0_MB28_ID1() bfin_read16(CAN0_MB28_ID1) |
| 3119 | #define bfin_write_CAN0_MB28_ID1(val) bfin_write16(CAN0_MB28_ID1, val) |
| 3120 | #define bfin_read_CAN0_MB29_DATA0() bfin_read16(CAN0_MB29_DATA0) |
| 3121 | #define bfin_write_CAN0_MB29_DATA0(val) bfin_write16(CAN0_MB29_DATA0, val) |
| 3122 | #define bfin_read_CAN0_MB29_DATA1() bfin_read16(CAN0_MB29_DATA1) |
| 3123 | #define bfin_write_CAN0_MB29_DATA1(val) bfin_write16(CAN0_MB29_DATA1, val) |
| 3124 | #define bfin_read_CAN0_MB29_DATA2() bfin_read16(CAN0_MB29_DATA2) |
| 3125 | #define bfin_write_CAN0_MB29_DATA2(val) bfin_write16(CAN0_MB29_DATA2, val) |
| 3126 | #define bfin_read_CAN0_MB29_DATA3() bfin_read16(CAN0_MB29_DATA3) |
| 3127 | #define bfin_write_CAN0_MB29_DATA3(val) bfin_write16(CAN0_MB29_DATA3, val) |
| 3128 | #define bfin_read_CAN0_MB29_LENGTH() bfin_read16(CAN0_MB29_LENGTH) |
| 3129 | #define bfin_write_CAN0_MB29_LENGTH(val) bfin_write16(CAN0_MB29_LENGTH, val) |
| 3130 | #define bfin_read_CAN0_MB29_TIMESTAMP() bfin_read16(CAN0_MB29_TIMESTAMP) |
| 3131 | #define bfin_write_CAN0_MB29_TIMESTAMP(val) bfin_write16(CAN0_MB29_TIMESTAMP, val) |
| 3132 | #define bfin_read_CAN0_MB29_ID0() bfin_read16(CAN0_MB29_ID0) |
| 3133 | #define bfin_write_CAN0_MB29_ID0(val) bfin_write16(CAN0_MB29_ID0, val) |
| 3134 | #define bfin_read_CAN0_MB29_ID1() bfin_read16(CAN0_MB29_ID1) |
| 3135 | #define bfin_write_CAN0_MB29_ID1(val) bfin_write16(CAN0_MB29_ID1, val) |
| 3136 | #define bfin_read_CAN0_MB30_DATA0() bfin_read16(CAN0_MB30_DATA0) |
| 3137 | #define bfin_write_CAN0_MB30_DATA0(val) bfin_write16(CAN0_MB30_DATA0, val) |
| 3138 | #define bfin_read_CAN0_MB30_DATA1() bfin_read16(CAN0_MB30_DATA1) |
| 3139 | #define bfin_write_CAN0_MB30_DATA1(val) bfin_write16(CAN0_MB30_DATA1, val) |
| 3140 | #define bfin_read_CAN0_MB30_DATA2() bfin_read16(CAN0_MB30_DATA2) |
| 3141 | #define bfin_write_CAN0_MB30_DATA2(val) bfin_write16(CAN0_MB30_DATA2, val) |
| 3142 | #define bfin_read_CAN0_MB30_DATA3() bfin_read16(CAN0_MB30_DATA3) |
| 3143 | #define bfin_write_CAN0_MB30_DATA3(val) bfin_write16(CAN0_MB30_DATA3, val) |
| 3144 | #define bfin_read_CAN0_MB30_LENGTH() bfin_read16(CAN0_MB30_LENGTH) |
| 3145 | #define bfin_write_CAN0_MB30_LENGTH(val) bfin_write16(CAN0_MB30_LENGTH, val) |
| 3146 | #define bfin_read_CAN0_MB30_TIMESTAMP() bfin_read16(CAN0_MB30_TIMESTAMP) |
| 3147 | #define bfin_write_CAN0_MB30_TIMESTAMP(val) bfin_write16(CAN0_MB30_TIMESTAMP, val) |
| 3148 | #define bfin_read_CAN0_MB30_ID0() bfin_read16(CAN0_MB30_ID0) |
| 3149 | #define bfin_write_CAN0_MB30_ID0(val) bfin_write16(CAN0_MB30_ID0, val) |
| 3150 | #define bfin_read_CAN0_MB30_ID1() bfin_read16(CAN0_MB30_ID1) |
| 3151 | #define bfin_write_CAN0_MB30_ID1(val) bfin_write16(CAN0_MB30_ID1, val) |
| 3152 | #define bfin_read_CAN0_MB31_DATA0() bfin_read16(CAN0_MB31_DATA0) |
| 3153 | #define bfin_write_CAN0_MB31_DATA0(val) bfin_write16(CAN0_MB31_DATA0, val) |
| 3154 | #define bfin_read_CAN0_MB31_DATA1() bfin_read16(CAN0_MB31_DATA1) |
| 3155 | #define bfin_write_CAN0_MB31_DATA1(val) bfin_write16(CAN0_MB31_DATA1, val) |
| 3156 | #define bfin_read_CAN0_MB31_DATA2() bfin_read16(CAN0_MB31_DATA2) |
| 3157 | #define bfin_write_CAN0_MB31_DATA2(val) bfin_write16(CAN0_MB31_DATA2, val) |
| 3158 | #define bfin_read_CAN0_MB31_DATA3() bfin_read16(CAN0_MB31_DATA3) |
| 3159 | #define bfin_write_CAN0_MB31_DATA3(val) bfin_write16(CAN0_MB31_DATA3, val) |
| 3160 | #define bfin_read_CAN0_MB31_LENGTH() bfin_read16(CAN0_MB31_LENGTH) |
| 3161 | #define bfin_write_CAN0_MB31_LENGTH(val) bfin_write16(CAN0_MB31_LENGTH, val) |
| 3162 | #define bfin_read_CAN0_MB31_TIMESTAMP() bfin_read16(CAN0_MB31_TIMESTAMP) |
| 3163 | #define bfin_write_CAN0_MB31_TIMESTAMP(val) bfin_write16(CAN0_MB31_TIMESTAMP, val) |
| 3164 | #define bfin_read_CAN0_MB31_ID0() bfin_read16(CAN0_MB31_ID0) |
| 3165 | #define bfin_write_CAN0_MB31_ID0(val) bfin_write16(CAN0_MB31_ID0, val) |
| 3166 | #define bfin_read_CAN0_MB31_ID1() bfin_read16(CAN0_MB31_ID1) |
| 3167 | #define bfin_write_CAN0_MB31_ID1(val) bfin_write16(CAN0_MB31_ID1, val) |
| 3168 | |
| 3169 | /* Counter Registers */ |
| 3170 | |
| 3171 | #define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG) |
| 3172 | #define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val) |
| 3173 | #define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK) |
| 3174 | #define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val) |
| 3175 | #define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS) |
| 3176 | #define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val) |
| 3177 | #define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND) |
| 3178 | #define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val) |
| 3179 | #define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE) |
| 3180 | #define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val) |
| 3181 | #define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER) |
| 3182 | #define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val) |
| 3183 | #define bfin_read_CNT_MAX() bfin_read32(CNT_MAX) |
| 3184 | #define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val) |
| 3185 | #define bfin_read_CNT_MIN() bfin_read32(CNT_MIN) |
| 3186 | #define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val) |
| 3187 | |
| 3188 | /* RSI Register */ |
| 3189 | #define bfin_read_RSI_CLK_CTL() bfin_read16(RSI_CLK_CONTROL) |
| 3190 | #define bfin_write_RSI_CLK_CTL(val) bfin_write16(RSI_CLK_CONTROL, val) |
| 3191 | #define bfin_read_RSI_ARGUMENT() bfin_read32(RSI_ARGUMENT) |
| 3192 | #define bfin_write_RSI_ARGUMENT(val) bfin_write32(RSI_ARGUMENT, val) |
| 3193 | #define bfin_read_RSI_COMMAND() bfin_read16(RSI_COMMAND) |
| 3194 | #define bfin_write_RSI_COMMAND(val) bfin_write16(RSI_COMMAND, val) |
| 3195 | #define bfin_read_RSI_RESP_CMD() bfin_read16(RSI_RESP_CMD) |
| 3196 | #define bfin_write_RSI_RESP_CMD(val) bfin_write16(RSI_RESP_CMD, val) |
| 3197 | #define bfin_read_RSI_RESPONSE0() bfin_read32(RSI_RESPONSE0) |
| 3198 | #define bfin_write_RSI_RESPONSE0(val) bfin_write32(RSI_RESPONSE0, val) |
| 3199 | #define bfin_read_RSI_RESPONSE1() bfin_read32(RSI_RESPONSE1) |
| 3200 | #define bfin_write_RSI_RESPONSE1(val) bfin_write32(RSI_RESPONSE1, val) |
| 3201 | #define bfin_read_RSI_RESPONSE2() bfin_read32(RSI_RESPONSE2) |
| 3202 | #define bfin_write_RSI_RESPONSE2(val) bfin_write32(RSI_RESPONSE2, val) |
| 3203 | #define bfin_read_RSI_RESPONSE3() bfin_read32(RSI_RESPONSE3) |
| 3204 | #define bfin_write_RSI_RESPONSE3(val) bfin_write32(RSI_RESPONSE3, val) |
| 3205 | #define bfin_read_RSI_DATA_TIMER() bfin_read32(RSI_DATA_TIMER) |
| 3206 | #define bfin_write_RSI_DATA_TIMER(val) bfin_write32(RSI_DATA_TIMER, val) |
| 3207 | #define bfin_read_RSI_DATA_LGTH() bfin_read16(RSI_DATA_LGTH) |
| 3208 | #define bfin_write_RSI_DATA_LGTH(val) bfin_write16(RSI_DATA_LGTH, val) |
| 3209 | #define bfin_read_RSI_DATA_CTL() bfin_read16(RSI_DATA_CONTROL) |
| 3210 | #define bfin_write_RSI_DATA_CTL(val) bfin_write16(RSI_DATA_CONTROL, val) |
| 3211 | #define bfin_read_RSI_DATA_CNT() bfin_read16(RSI_DATA_CNT) |
| 3212 | #define bfin_write_RSI_DATA_CNT(val) bfin_write16(RSI_DATA_CNT, val) |
| 3213 | #define bfin_read_RSI_STATUS() bfin_read32(RSI_STATUS) |
| 3214 | #define bfin_write_RSI_STATUS(val) bfin_write32(RSI_STATUS, val) |
| 3215 | #define bfin_read_RSI_STATUS_CLR() bfin_read16(RSI_STATUSCL) |
| 3216 | #define bfin_write_RSI_STATUS_CLR(val) bfin_write16(RSI_STATUSCL, val) |
| 3217 | #define bfin_read_RSI_MASK0() bfin_read32(RSI_MASK0) |
| 3218 | #define bfin_write_RSI_MASK0(val) bfin_write32(RSI_MASK0, val) |
| 3219 | #define bfin_read_RSI_MASK1() bfin_read32(RSI_MASK1) |
| 3220 | #define bfin_write_RSI_MASK1(val) bfin_write32(RSI_MASK1, val) |
| 3221 | #define bfin_read_RSI_FIFO_CNT() bfin_read16(RSI_FIFO_CNT) |
| 3222 | #define bfin_write_RSI_FIFO_CNT(val) bfin_write16(RSI_FIFO_CNT, val) |
| 3223 | #define bfin_read_RSI_CEATA_CONTROL() bfin_read16(RSI_CEATA_CONTROL) |
| 3224 | #define bfin_write_RSI_CEATA_CONTROL(val) bfin_write16(RSI_CEATA_CONTROL, val) |
| 3225 | #define bfin_read_RSI_BLKSZ() bfin_read16(RSI_BLKSZ) |
| 3226 | #define bfin_write_RSI_BLKSZ(val) bfin_write16(RSI_BLKSZ, val) |
| 3227 | #define bfin_read_RSI_FIFO() bfin_read32(RSI_FIFO) |
| 3228 | #define bfin_write_RSI_FIFO(val) bfin_write32(RSI_FIFO, val) |
| 3229 | #define bfin_read_RSI_E_STATUS() bfin_read32(RSI_ESTAT) |
| 3230 | #define bfin_write_RSI_E_STATUS(val) bfin_write32(RSI_ESTAT, val) |
| 3231 | #define bfin_read_RSI_E_MASK() bfin_read32(RSI_EMASK) |
| 3232 | #define bfin_write_RSI_E_MASK(val) bfin_write32(RSI_EMASK, val) |
| 3233 | #define bfin_read_RSI_CFG() bfin_read16(RSI_CONFIG) |
| 3234 | #define bfin_write_RSI_CFG(val) bfin_write16(RSI_CONFIG, val) |
| 3235 | #define bfin_read_RSI_RD_WAIT_EN() bfin_read16(RSI_RD_WAIT_EN) |
| 3236 | #define bfin_write_RSI_RD_WAIT_EN(val) bfin_write16(RSI_RD_WAIT_EN, val) |
| 3237 | #define bfin_read_RSI_PID0() bfin_read16(RSI_PID0) |
| 3238 | #define bfin_write_RSI_PID0(val) bfin_write16(RSI_PID0, val) |
| 3239 | #define bfin_read_RSI_PID1() bfin_read16(RSI_PID1) |
| 3240 | #define bfin_write_RSI_PID1(val) bfin_write16(RSI_PID1, val) |
| 3241 | #define bfin_read_RSI_PID2() bfin_read16(RSI_PID2) |
| 3242 | #define bfin_write_RSI_PID2(val) bfin_write16(RSI_PID2, val) |
| 3243 | #define bfin_read_RSI_PID3() bfin_read16(RSI_PID3) |
| 3244 | #define bfin_write_RSI_PID3(val) bfin_write16(RSI_PID3, val) |
| 3245 | |
| 3246 | /* usb register */ |
| 3247 | #define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLL_OSC) |
| 3248 | #define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLL_OSC, val) |
| 3249 | #define bfin_write_USB_VBUS_CTL(val) bfin_write8(USB_VBUS_CTL, val) |
| 3250 | #define bfin_write_USB_APHY_CNTRL(val) bfin_write8(USB_PHY_CTL, val) |
| 3251 | #define bfin_read_USB_APHY_CNTRL() bfin_read8(USB_PHY_CTL) |
| 3252 | |
| 3253 | #endif /* _CDEF_BF60X_H */ |
| 3254 | |