blob: 28af087d9fbba24d0005fd66c34f765005565610 [file] [log] [blame]
Kumar Gala0bbaf062005-06-20 10:54:21 -05001/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07002 * drivers/net/gianfar.h
3 *
4 * Gianfar Ethernet Driver
5 * Driver for FEC on MPC8540 and TSEC on MPC8540/MPC8560
6 * Based on 8260_io/fcc_enet.c
7 *
8 * Author: Andy Fleming
9 * Maintainer: Kumar Gala (kumar.gala@freescale.com)
10 *
11 * Copyright (c) 2002-2004 Freescale Semiconductor, Inc.
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 *
18 * Still left to do:
19 * -Add support for module parameters
20 * -Add support for ethtool -s
21 * -Add patch for ethtool phys id
22 */
23#ifndef __GIANFAR_H
24#define __GIANFAR_H
25
26#include <linux/config.h>
27#include <linux/kernel.h>
28#include <linux/sched.h>
29#include <linux/string.h>
30#include <linux/errno.h>
31#include <linux/slab.h>
32#include <linux/interrupt.h>
33#include <linux/init.h>
34#include <linux/delay.h>
35#include <linux/netdevice.h>
36#include <linux/etherdevice.h>
37#include <linux/skbuff.h>
38#include <linux/spinlock.h>
39#include <linux/mm.h>
40#include <linux/fsl_devices.h>
41
42#include <asm/io.h>
43#include <asm/irq.h>
44#include <asm/uaccess.h>
45#include <linux/module.h>
46#include <linux/version.h>
47#include <linux/crc32.h>
48#include <linux/workqueue.h>
49#include <linux/ethtool.h>
50#include <linux/netdevice.h>
51#include "gianfar_phy.h"
52
53/* The maximum number of packets to be handled in one call of gfar_poll */
54#define GFAR_DEV_WEIGHT 64
55
Kumar Gala0bbaf062005-06-20 10:54:21 -050056/* Length for FCB */
57#define GMAC_FCB_LEN 8
58
59/* Default padding amount */
60#define DEFAULT_PADDING 2
61
Linus Torvalds1da177e2005-04-16 15:20:36 -070062/* Number of bytes to align the rx bufs to */
63#define RXBUF_ALIGNMENT 64
64
65/* The number of bytes which composes a unit for the purpose of
66 * allocating data buffers. ie-for any given MTU, the data buffer
67 * will be the next highest multiple of 512 bytes. */
68#define INCREMENTAL_BUFFER_SIZE 512
69
70
71#define MAC_ADDR_LEN 6
72
73#define PHY_INIT_TIMEOUT 100000
74#define GFAR_PHY_CHANGE_TIME 2
75
76#define DEVICE_NAME "%s: Gianfar Ethernet Controller Version 1.1, "
77#define DRV_NAME "gfar-enet"
78extern const char gfar_driver_name[];
79extern const char gfar_driver_version[];
80
81/* These need to be powers of 2 for this driver */
82#ifdef CONFIG_GFAR_NAPI
83#define DEFAULT_TX_RING_SIZE 256
84#define DEFAULT_RX_RING_SIZE 256
85#else
86#define DEFAULT_TX_RING_SIZE 64
87#define DEFAULT_RX_RING_SIZE 64
88#endif
89
90#define GFAR_RX_MAX_RING_SIZE 256
91#define GFAR_TX_MAX_RING_SIZE 256
92
93#define DEFAULT_RX_BUFFER_SIZE 1536
94#define TX_RING_MOD_MASK(size) (size-1)
95#define RX_RING_MOD_MASK(size) (size-1)
96#define JUMBO_BUFFER_SIZE 9728
97#define JUMBO_FRAME_SIZE 9600
98
99/* Latency of interface clock in nanoseconds */
Kumar Gala0bbaf062005-06-20 10:54:21 -0500100/* Interface clock latency , in this case, means the
Linus Torvalds1da177e2005-04-16 15:20:36 -0700101 * time described by a value of 1 in the interrupt
102 * coalescing registers' time fields. Since those fields
103 * refer to the time it takes for 64 clocks to pass, the
104 * latencies are as such:
105 * GBIT = 125MHz => 8ns/clock => 8*64 ns / tick
106 * 100 = 25 MHz => 40ns/clock => 40*64 ns / tick
107 * 10 = 2.5 MHz => 400ns/clock => 400*64 ns / tick
108 */
109#define GFAR_GBIT_TIME 512
110#define GFAR_100_TIME 2560
111#define GFAR_10_TIME 25600
112
113#define DEFAULT_TX_COALESCE 1
114#define DEFAULT_TXCOUNT 16
115#define DEFAULT_TXTIME 400
116
117#define DEFAULT_RX_COALESCE 1
118#define DEFAULT_RXCOUNT 16
119#define DEFAULT_RXTIME 400
120
121#define TBIPA_VALUE 0x1f
122#define MIIMCFG_INIT_VALUE 0x00000007
123#define MIIMCFG_RESET 0x80000000
124#define MIIMIND_BUSY 0x00000001
125
126/* MAC register bits */
127#define MACCFG1_SOFT_RESET 0x80000000
128#define MACCFG1_RESET_RX_MC 0x00080000
129#define MACCFG1_RESET_TX_MC 0x00040000
130#define MACCFG1_RESET_RX_FUN 0x00020000
131#define MACCFG1_RESET_TX_FUN 0x00010000
132#define MACCFG1_LOOPBACK 0x00000100
133#define MACCFG1_RX_FLOW 0x00000020
134#define MACCFG1_TX_FLOW 0x00000010
135#define MACCFG1_SYNCD_RX_EN 0x00000008
136#define MACCFG1_RX_EN 0x00000004
137#define MACCFG1_SYNCD_TX_EN 0x00000002
138#define MACCFG1_TX_EN 0x00000001
139
140#define MACCFG2_INIT_SETTINGS 0x00007205
141#define MACCFG2_FULL_DUPLEX 0x00000001
142#define MACCFG2_IF 0x00000300
143#define MACCFG2_MII 0x00000100
144#define MACCFG2_GMII 0x00000200
145#define MACCFG2_HUGEFRAME 0x00000020
146#define MACCFG2_LENGTHCHECK 0x00000010
147
148#define ECNTRL_INIT_SETTINGS 0x00001000
149#define ECNTRL_TBI_MODE 0x00000020
150
151#define MRBLR_INIT_SETTINGS DEFAULT_RX_BUFFER_SIZE
152
153#define MINFLR_INIT_SETTINGS 0x00000040
154
155/* Init to do tx snooping for buffers and descriptors */
156#define DMACTRL_INIT_SETTINGS 0x000000c3
157#define DMACTRL_GRS 0x00000010
158#define DMACTRL_GTS 0x00000008
159
160#define TSTAT_CLEAR_THALT 0x80000000
161
162/* Interrupt coalescing macros */
163#define IC_ICEN 0x80000000
164#define IC_ICFT_MASK 0x1fe00000
165#define IC_ICFT_SHIFT 21
166#define mk_ic_icft(x) \
167 (((unsigned int)x << IC_ICFT_SHIFT)&IC_ICFT_MASK)
168#define IC_ICTT_MASK 0x0000ffff
169#define mk_ic_ictt(x) (x&IC_ICTT_MASK)
170
171#define mk_ic_value(count, time) (IC_ICEN | \
172 mk_ic_icft(count) | \
173 mk_ic_ictt(time))
174
Kumar Gala0bbaf062005-06-20 10:54:21 -0500175#define RCTRL_PAL_MASK 0x001f0000
176#define RCTRL_VLEX 0x00002000
177#define RCTRL_FILREN 0x00001000
178#define RCTRL_GHTX 0x00000400
179#define RCTRL_IPCSEN 0x00000200
180#define RCTRL_TUCSEN 0x00000100
181#define RCTRL_PRSDEP_MASK 0x000000c0
182#define RCTRL_PRSDEP_INIT 0x000000c0
Linus Torvalds1da177e2005-04-16 15:20:36 -0700183#define RCTRL_PROM 0x00000008
Kumar Gala0bbaf062005-06-20 10:54:21 -0500184#define RCTRL_CHECKSUMMING (RCTRL_IPCSEN \
185 | RCTRL_TUCSEN | RCTRL_PRSDEP_INIT)
186#define RCTRL_EXTHASH (RCTRL_GHTX)
187#define RCTRL_VLAN (RCTRL_PRSDEP_INIT)
188
189
Linus Torvalds1da177e2005-04-16 15:20:36 -0700190#define RSTAT_CLEAR_RHALT 0x00800000
191
Kumar Gala0bbaf062005-06-20 10:54:21 -0500192#define TCTRL_IPCSEN 0x00004000
193#define TCTRL_TUCSEN 0x00002000
194#define TCTRL_VLINS 0x00001000
195#define TCTRL_INIT_CSUM (TCTRL_TUCSEN | TCTRL_IPCSEN)
196
Linus Torvalds1da177e2005-04-16 15:20:36 -0700197#define IEVENT_INIT_CLEAR 0xffffffff
198#define IEVENT_BABR 0x80000000
199#define IEVENT_RXC 0x40000000
200#define IEVENT_BSY 0x20000000
201#define IEVENT_EBERR 0x10000000
202#define IEVENT_MSRO 0x04000000
203#define IEVENT_GTSC 0x02000000
204#define IEVENT_BABT 0x01000000
205#define IEVENT_TXC 0x00800000
206#define IEVENT_TXE 0x00400000
207#define IEVENT_TXB 0x00200000
208#define IEVENT_TXF 0x00100000
209#define IEVENT_LC 0x00040000
210#define IEVENT_CRL 0x00020000
211#define IEVENT_XFUN 0x00010000
212#define IEVENT_RXB0 0x00008000
213#define IEVENT_GRSC 0x00000100
214#define IEVENT_RXF0 0x00000080
Kumar Gala0bbaf062005-06-20 10:54:21 -0500215#define IEVENT_FIR 0x00000008
216#define IEVENT_FIQ 0x00000004
217#define IEVENT_DPE 0x00000002
218#define IEVENT_PERR 0x00000001
Linus Torvalds1da177e2005-04-16 15:20:36 -0700219#define IEVENT_RX_MASK (IEVENT_RXB0 | IEVENT_RXF0)
220#define IEVENT_TX_MASK (IEVENT_TXB | IEVENT_TXF)
221#define IEVENT_ERR_MASK \
222(IEVENT_RXC | IEVENT_BSY | IEVENT_EBERR | IEVENT_MSRO | \
223 IEVENT_BABT | IEVENT_TXC | IEVENT_TXE | IEVENT_LC \
Kumar Gala0bbaf062005-06-20 10:54:21 -0500224 | IEVENT_CRL | IEVENT_XFUN | IEVENT_DPE | IEVENT_PERR)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700225
226#define IMASK_INIT_CLEAR 0x00000000
227#define IMASK_BABR 0x80000000
228#define IMASK_RXC 0x40000000
229#define IMASK_BSY 0x20000000
230#define IMASK_EBERR 0x10000000
231#define IMASK_MSRO 0x04000000
232#define IMASK_GRSC 0x02000000
233#define IMASK_BABT 0x01000000
234#define IMASK_TXC 0x00800000
235#define IMASK_TXEEN 0x00400000
236#define IMASK_TXBEN 0x00200000
237#define IMASK_TXFEN 0x00100000
238#define IMASK_LC 0x00040000
239#define IMASK_CRL 0x00020000
240#define IMASK_XFUN 0x00010000
241#define IMASK_RXB0 0x00008000
242#define IMASK_GTSC 0x00000100
243#define IMASK_RXFEN0 0x00000080
Kumar Gala0bbaf062005-06-20 10:54:21 -0500244#define IMASK_FIR 0x00000008
245#define IMASK_FIQ 0x00000004
246#define IMASK_DPE 0x00000002
247#define IMASK_PERR 0x00000001
Linus Torvalds1da177e2005-04-16 15:20:36 -0700248#define IMASK_RX_DISABLED ~(IMASK_RXFEN0 | IMASK_BSY)
249#define IMASK_DEFAULT (IMASK_TXEEN | IMASK_TXFEN | IMASK_TXBEN | \
250 IMASK_RXFEN0 | IMASK_BSY | IMASK_EBERR | IMASK_BABR | \
Kumar Gala0bbaf062005-06-20 10:54:21 -0500251 IMASK_XFUN | IMASK_RXC | IMASK_BABT | IMASK_DPE \
252 | IMASK_PERR)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700253
254
255/* Attribute fields */
256
257/* This enables rx snooping for buffers and descriptors */
258#ifdef CONFIG_GFAR_BDSTASH
259#define ATTR_BDSTASH 0x00000800
260#else
261#define ATTR_BDSTASH 0x00000000
262#endif
263
264#ifdef CONFIG_GFAR_BUFSTASH
265#define ATTR_BUFSTASH 0x00004000
266#define STASH_LENGTH 64
267#else
268#define ATTR_BUFSTASH 0x00000000
269#endif
270
271#define ATTR_SNOOPING 0x000000c0
272#define ATTR_INIT_SETTINGS (ATTR_SNOOPING \
273 | ATTR_BDSTASH | ATTR_BUFSTASH)
274
275#define ATTRELI_INIT_SETTINGS 0x0
276
277
278/* TxBD status field bits */
279#define TXBD_READY 0x8000
280#define TXBD_PADCRC 0x4000
281#define TXBD_WRAP 0x2000
282#define TXBD_INTERRUPT 0x1000
283#define TXBD_LAST 0x0800
284#define TXBD_CRC 0x0400
285#define TXBD_DEF 0x0200
286#define TXBD_HUGEFRAME 0x0080
287#define TXBD_LATECOLLISION 0x0080
288#define TXBD_RETRYLIMIT 0x0040
289#define TXBD_RETRYCOUNTMASK 0x003c
290#define TXBD_UNDERRUN 0x0002
Kumar Gala0bbaf062005-06-20 10:54:21 -0500291#define TXBD_TOE 0x0002
292
293/* Tx FCB param bits */
294#define TXFCB_VLN 0x80
295#define TXFCB_IP 0x40
296#define TXFCB_IP6 0x20
297#define TXFCB_TUP 0x10
298#define TXFCB_UDP 0x08
299#define TXFCB_CIP 0x04
300#define TXFCB_CTU 0x02
301#define TXFCB_NPH 0x01
302#define TXFCB_DEFAULT (TXFCB_IP|TXFCB_TUP|TXFCB_CTU|TXFCB_NPH)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700303
304/* RxBD status field bits */
305#define RXBD_EMPTY 0x8000
306#define RXBD_RO1 0x4000
307#define RXBD_WRAP 0x2000
308#define RXBD_INTERRUPT 0x1000
309#define RXBD_LAST 0x0800
310#define RXBD_FIRST 0x0400
311#define RXBD_MISS 0x0100
312#define RXBD_BROADCAST 0x0080
313#define RXBD_MULTICAST 0x0040
314#define RXBD_LARGE 0x0020
315#define RXBD_NONOCTET 0x0010
316#define RXBD_SHORT 0x0008
317#define RXBD_CRCERR 0x0004
318#define RXBD_OVERRUN 0x0002
319#define RXBD_TRUNCATED 0x0001
320#define RXBD_STATS 0x01ff
321
Kumar Gala0bbaf062005-06-20 10:54:21 -0500322/* Rx FCB status field bits */
323#define RXFCB_VLN 0x8000
324#define RXFCB_IP 0x4000
325#define RXFCB_IP6 0x2000
326#define RXFCB_TUP 0x1000
327#define RXFCB_CIP 0x0800
328#define RXFCB_CTU 0x0400
329#define RXFCB_EIP 0x0200
330#define RXFCB_ETU 0x0100
331#define RXFCB_PERR_MASK 0x000c
332#define RXFCB_PERR_BADL3 0x0008
333
Linus Torvalds1da177e2005-04-16 15:20:36 -0700334struct txbd8
335{
336 u16 status; /* Status Fields */
337 u16 length; /* Buffer length */
338 u32 bufPtr; /* Buffer Pointer */
339};
340
Kumar Gala0bbaf062005-06-20 10:54:21 -0500341struct txfcb {
342 u8 vln:1,
343 ip:1,
344 ip6:1,
345 tup:1,
346 udp:1,
347 cip:1,
348 ctu:1,
349 nph:1;
350 u8 reserved;
351 u8 l4os; /* Level 4 Header Offset */
352 u8 l3os; /* Level 3 Header Offset */
353 u16 phcs; /* Pseudo-header Checksum */
354 u16 vlctl; /* VLAN control word */
355};
356
Linus Torvalds1da177e2005-04-16 15:20:36 -0700357struct rxbd8
358{
359 u16 status; /* Status Fields */
360 u16 length; /* Buffer Length */
361 u32 bufPtr; /* Buffer Pointer */
362};
363
Kumar Gala0bbaf062005-06-20 10:54:21 -0500364struct rxfcb {
365 u16 vln:1,
366 ip:1,
367 ip6:1,
368 tup:1,
369 cip:1,
370 ctu:1,
371 eip:1,
372 etu:1;
373 u8 rq; /* Receive Queue index */
374 u8 pro; /* Layer 4 Protocol */
375 u16 reserved;
376 u16 vlctl; /* VLAN control word */
377};
378
Linus Torvalds1da177e2005-04-16 15:20:36 -0700379struct rmon_mib
380{
381 u32 tr64; /* 0x.680 - Transmit and Receive 64-byte Frame Counter */
382 u32 tr127; /* 0x.684 - Transmit and Receive 65-127 byte Frame Counter */
383 u32 tr255; /* 0x.688 - Transmit and Receive 128-255 byte Frame Counter */
384 u32 tr511; /* 0x.68c - Transmit and Receive 256-511 byte Frame Counter */
385 u32 tr1k; /* 0x.690 - Transmit and Receive 512-1023 byte Frame Counter */
386 u32 trmax; /* 0x.694 - Transmit and Receive 1024-1518 byte Frame Counter */
387 u32 trmgv; /* 0x.698 - Transmit and Receive 1519-1522 byte Good VLAN Frame */
388 u32 rbyt; /* 0x.69c - Receive Byte Counter */
389 u32 rpkt; /* 0x.6a0 - Receive Packet Counter */
390 u32 rfcs; /* 0x.6a4 - Receive FCS Error Counter */
391 u32 rmca; /* 0x.6a8 - Receive Multicast Packet Counter */
392 u32 rbca; /* 0x.6ac - Receive Broadcast Packet Counter */
393 u32 rxcf; /* 0x.6b0 - Receive Control Frame Packet Counter */
394 u32 rxpf; /* 0x.6b4 - Receive Pause Frame Packet Counter */
395 u32 rxuo; /* 0x.6b8 - Receive Unknown OP Code Counter */
396 u32 raln; /* 0x.6bc - Receive Alignment Error Counter */
397 u32 rflr; /* 0x.6c0 - Receive Frame Length Error Counter */
398 u32 rcde; /* 0x.6c4 - Receive Code Error Counter */
399 u32 rcse; /* 0x.6c8 - Receive Carrier Sense Error Counter */
400 u32 rund; /* 0x.6cc - Receive Undersize Packet Counter */
401 u32 rovr; /* 0x.6d0 - Receive Oversize Packet Counter */
402 u32 rfrg; /* 0x.6d4 - Receive Fragments Counter */
403 u32 rjbr; /* 0x.6d8 - Receive Jabber Counter */
404 u32 rdrp; /* 0x.6dc - Receive Drop Counter */
405 u32 tbyt; /* 0x.6e0 - Transmit Byte Counter Counter */
406 u32 tpkt; /* 0x.6e4 - Transmit Packet Counter */
407 u32 tmca; /* 0x.6e8 - Transmit Multicast Packet Counter */
408 u32 tbca; /* 0x.6ec - Transmit Broadcast Packet Counter */
409 u32 txpf; /* 0x.6f0 - Transmit Pause Control Frame Counter */
410 u32 tdfr; /* 0x.6f4 - Transmit Deferral Packet Counter */
411 u32 tedf; /* 0x.6f8 - Transmit Excessive Deferral Packet Counter */
412 u32 tscl; /* 0x.6fc - Transmit Single Collision Packet Counter */
413 u32 tmcl; /* 0x.700 - Transmit Multiple Collision Packet Counter */
414 u32 tlcl; /* 0x.704 - Transmit Late Collision Packet Counter */
415 u32 txcl; /* 0x.708 - Transmit Excessive Collision Packet Counter */
416 u32 tncl; /* 0x.70c - Transmit Total Collision Counter */
417 u8 res1[4];
418 u32 tdrp; /* 0x.714 - Transmit Drop Frame Counter */
419 u32 tjbr; /* 0x.718 - Transmit Jabber Frame Counter */
420 u32 tfcs; /* 0x.71c - Transmit FCS Error Counter */
421 u32 txcf; /* 0x.720 - Transmit Control Frame Counter */
422 u32 tovr; /* 0x.724 - Transmit Oversize Frame Counter */
423 u32 tund; /* 0x.728 - Transmit Undersize Frame Counter */
424 u32 tfrg; /* 0x.72c - Transmit Fragments Frame Counter */
425 u32 car1; /* 0x.730 - Carry Register One */
426 u32 car2; /* 0x.734 - Carry Register Two */
427 u32 cam1; /* 0x.738 - Carry Mask Register One */
428 u32 cam2; /* 0x.73c - Carry Mask Register Two */
429};
430
431struct gfar_extra_stats {
432 u64 kernel_dropped;
433 u64 rx_large;
434 u64 rx_short;
435 u64 rx_nonoctet;
436 u64 rx_crcerr;
437 u64 rx_overrun;
438 u64 rx_bsy;
439 u64 rx_babr;
440 u64 rx_trunc;
441 u64 eberr;
442 u64 tx_babt;
443 u64 tx_underrun;
444 u64 rx_skbmissing;
445 u64 tx_timeout;
446};
447
448#define GFAR_RMON_LEN ((sizeof(struct rmon_mib) - 16)/sizeof(u32))
449#define GFAR_EXTRA_STATS_LEN (sizeof(struct gfar_extra_stats)/sizeof(u64))
450
451/* Number of stats in the stats structure (ignore car and cam regs)*/
452#define GFAR_STATS_LEN (GFAR_RMON_LEN + GFAR_EXTRA_STATS_LEN)
453
454#define GFAR_INFOSTR_LEN 32
455
456struct gfar_stats {
457 u64 extra[GFAR_EXTRA_STATS_LEN];
458 u64 rmon[GFAR_RMON_LEN];
459};
460
461
462struct gfar {
Kumar Gala0bbaf062005-06-20 10:54:21 -0500463 u32 tsec_id; /* 0x.000 - Controller ID register */
464 u8 res1[12];
465 u32 ievent; /* 0x.010 - Interrupt Event Register */
466 u32 imask; /* 0x.014 - Interrupt Mask Register */
467 u32 edis; /* 0x.018 - Error Disabled Register */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700468 u8 res2[4];
Kumar Gala0bbaf062005-06-20 10:54:21 -0500469 u32 ecntrl; /* 0x.020 - Ethernet Control Register */
470 u32 minflr; /* 0x.024 - Minimum Frame Length Register */
471 u32 ptv; /* 0x.028 - Pause Time Value Register */
472 u32 dmactrl; /* 0x.02c - DMA Control Register */
473 u32 tbipa; /* 0x.030 - TBI PHY Address Register */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700474 u8 res3[88];
Kumar Gala0bbaf062005-06-20 10:54:21 -0500475 u32 fifo_tx_thr; /* 0x.08c - FIFO transmit threshold register */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700476 u8 res4[8];
Kumar Gala0bbaf062005-06-20 10:54:21 -0500477 u32 fifo_tx_starve; /* 0x.098 - FIFO transmit starve register */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700478 u32 fifo_tx_starve_shutoff; /* 0x.09c - FIFO transmit starve shutoff register */
Kumar Gala0bbaf062005-06-20 10:54:21 -0500479 u8 res5[4];
480 u32 fifo_rx_pause; /* 0x.0a4 - FIFO receive pause threshold register */
481 u32 fifo_rx_alarm; /* 0x.0a8 - FIFO receive alarm threshold register */
482 u8 res6[84];
483 u32 tctrl; /* 0x.100 - Transmit Control Register */
484 u32 tstat; /* 0x.104 - Transmit Status Register */
485 u32 dfvlan; /* 0x.108 - Default VLAN Control word */
486 u32 tbdlen; /* 0x.10c - Transmit Buffer Descriptor Data Length Register */
487 u32 txic; /* 0x.110 - Transmit Interrupt Coalescing Configuration Register */
488 u32 tqueue; /* 0x.114 - Transmit queue control register */
489 u8 res7[40];
490 u32 tr03wt; /* 0x.140 - TxBD Rings 0-3 round-robin weightings */
491 u32 tr47wt; /* 0x.144 - TxBD Rings 4-7 round-robin weightings */
492 u8 res8[52];
493 u32 tbdbph; /* 0x.17c - Tx data buffer pointer high */
494 u8 res9a[4];
495 u32 tbptr0; /* 0x.184 - TxBD Pointer for ring 0 */
496 u8 res9b[4];
497 u32 tbptr1; /* 0x.18c - TxBD Pointer for ring 1 */
498 u8 res9c[4];
499 u32 tbptr2; /* 0x.194 - TxBD Pointer for ring 2 */
500 u8 res9d[4];
501 u32 tbptr3; /* 0x.19c - TxBD Pointer for ring 3 */
502 u8 res9e[4];
503 u32 tbptr4; /* 0x.1a4 - TxBD Pointer for ring 4 */
504 u8 res9f[4];
505 u32 tbptr5; /* 0x.1ac - TxBD Pointer for ring 5 */
506 u8 res9g[4];
507 u32 tbptr6; /* 0x.1b4 - TxBD Pointer for ring 6 */
508 u8 res9h[4];
509 u32 tbptr7; /* 0x.1bc - TxBD Pointer for ring 7 */
510 u8 res9[64];
511 u32 tbaseh; /* 0x.200 - TxBD base address high */
512 u32 tbase0; /* 0x.204 - TxBD Base Address of ring 0 */
513 u8 res10a[4];
514 u32 tbase1; /* 0x.20c - TxBD Base Address of ring 1 */
515 u8 res10b[4];
516 u32 tbase2; /* 0x.214 - TxBD Base Address of ring 2 */
517 u8 res10c[4];
518 u32 tbase3; /* 0x.21c - TxBD Base Address of ring 3 */
519 u8 res10d[4];
520 u32 tbase4; /* 0x.224 - TxBD Base Address of ring 4 */
521 u8 res10e[4];
522 u32 tbase5; /* 0x.22c - TxBD Base Address of ring 5 */
523 u8 res10f[4];
524 u32 tbase6; /* 0x.234 - TxBD Base Address of ring 6 */
525 u8 res10g[4];
526 u32 tbase7; /* 0x.23c - TxBD Base Address of ring 7 */
527 u8 res10[192];
528 u32 rctrl; /* 0x.300 - Receive Control Register */
529 u32 rstat; /* 0x.304 - Receive Status Register */
530 u8 res12[8];
531 u32 rxic; /* 0x.310 - Receive Interrupt Coalescing Configuration Register */
532 u32 rqueue; /* 0x.314 - Receive queue control register */
533 u8 res13[24];
534 u32 rbifx; /* 0x.330 - Receive bit field extract control register */
535 u32 rqfar; /* 0x.334 - Receive queue filing table address register */
536 u32 rqfcr; /* 0x.338 - Receive queue filing table control register */
537 u32 rqfpr; /* 0x.33c - Receive queue filing table property register */
538 u32 mrblr; /* 0x.340 - Maximum Receive Buffer Length Register */
539 u8 res14[56];
540 u32 rbdbph; /* 0x.37c - Rx data buffer pointer high */
541 u8 res15a[4];
542 u32 rbptr0; /* 0x.384 - RxBD pointer for ring 0 */
543 u8 res15b[4];
544 u32 rbptr1; /* 0x.38c - RxBD pointer for ring 1 */
545 u8 res15c[4];
546 u32 rbptr2; /* 0x.394 - RxBD pointer for ring 2 */
547 u8 res15d[4];
548 u32 rbptr3; /* 0x.39c - RxBD pointer for ring 3 */
549 u8 res15e[4];
550 u32 rbptr4; /* 0x.3a4 - RxBD pointer for ring 4 */
551 u8 res15f[4];
552 u32 rbptr5; /* 0x.3ac - RxBD pointer for ring 5 */
553 u8 res15g[4];
554 u32 rbptr6; /* 0x.3b4 - RxBD pointer for ring 6 */
555 u8 res15h[4];
556 u32 rbptr7; /* 0x.3bc - RxBD pointer for ring 7 */
557 u8 res16[64];
558 u32 rbaseh; /* 0x.400 - RxBD base address high */
559 u32 rbase0; /* 0x.404 - RxBD base address of ring 0 */
560 u8 res17a[4];
561 u32 rbase1; /* 0x.40c - RxBD base address of ring 1 */
562 u8 res17b[4];
563 u32 rbase2; /* 0x.414 - RxBD base address of ring 2 */
564 u8 res17c[4];
565 u32 rbase3; /* 0x.41c - RxBD base address of ring 3 */
566 u8 res17d[4];
567 u32 rbase4; /* 0x.424 - RxBD base address of ring 4 */
568 u8 res17e[4];
569 u32 rbase5; /* 0x.42c - RxBD base address of ring 5 */
570 u8 res17f[4];
571 u32 rbase6; /* 0x.434 - RxBD base address of ring 6 */
572 u8 res17g[4];
573 u32 rbase7; /* 0x.43c - RxBD base address of ring 7 */
574 u8 res17[192];
575 u32 maccfg1; /* 0x.500 - MAC Configuration 1 Register */
576 u32 maccfg2; /* 0x.504 - MAC Configuration 2 Register */
577 u32 ipgifg; /* 0x.508 - Inter Packet Gap/Inter Frame Gap Register */
578 u32 hafdup; /* 0x.50c - Half Duplex Register */
579 u32 maxfrm; /* 0x.510 - Maximum Frame Length Register */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700580 u8 res18[12];
Kumar Gala0bbaf062005-06-20 10:54:21 -0500581 u32 miimcfg; /* 0x.520 - MII Management Configuration Register */
582 u32 miimcom; /* 0x.524 - MII Management Command Register */
583 u32 miimadd; /* 0x.528 - MII Management Address Register */
584 u32 miimcon; /* 0x.52c - MII Management Control Register */
585 u32 miimstat; /* 0x.530 - MII Management Status Register */
586 u32 miimind; /* 0x.534 - MII Management Indicator Register */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700587 u8 res19[4];
Kumar Gala0bbaf062005-06-20 10:54:21 -0500588 u32 ifstat; /* 0x.53c - Interface Status Register */
589 u32 macstnaddr1; /* 0x.540 - Station Address Part 1 Register */
590 u32 macstnaddr2; /* 0x.544 - Station Address Part 2 Register */
591 u32 mac01addr1; /* 0x.548 - MAC exact match address 1, part 1 */
592 u32 mac01addr2; /* 0x.54c - MAC exact match address 1, part 2 */
593 u32 mac02addr1; /* 0x.550 - MAC exact match address 2, part 1 */
594 u32 mac02addr2; /* 0x.554 - MAC exact match address 2, part 2 */
595 u32 mac03addr1; /* 0x.558 - MAC exact match address 3, part 1 */
596 u32 mac03addr2; /* 0x.55c - MAC exact match address 3, part 2 */
597 u32 mac04addr1; /* 0x.560 - MAC exact match address 4, part 1 */
598 u32 mac04addr2; /* 0x.564 - MAC exact match address 4, part 2 */
599 u32 mac05addr1; /* 0x.568 - MAC exact match address 5, part 1 */
600 u32 mac05addr2; /* 0x.56c - MAC exact match address 5, part 2 */
601 u32 mac06addr1; /* 0x.570 - MAC exact match address 6, part 1 */
602 u32 mac06addr2; /* 0x.574 - MAC exact match address 6, part 2 */
603 u32 mac07addr1; /* 0x.578 - MAC exact match address 7, part 1 */
604 u32 mac07addr2; /* 0x.57c - MAC exact match address 7, part 2 */
605 u32 mac08addr1; /* 0x.580 - MAC exact match address 8, part 1 */
606 u32 mac08addr2; /* 0x.584 - MAC exact match address 8, part 2 */
607 u32 mac09addr1; /* 0x.588 - MAC exact match address 9, part 1 */
608 u32 mac09addr2; /* 0x.58c - MAC exact match address 9, part 2 */
609 u32 mac10addr1; /* 0x.590 - MAC exact match address 10, part 1*/
610 u32 mac10addr2; /* 0x.594 - MAC exact match address 10, part 2*/
611 u32 mac11addr1; /* 0x.598 - MAC exact match address 11, part 1*/
612 u32 mac11addr2; /* 0x.59c - MAC exact match address 11, part 2*/
613 u32 mac12addr1; /* 0x.5a0 - MAC exact match address 12, part 1*/
614 u32 mac12addr2; /* 0x.5a4 - MAC exact match address 12, part 2*/
615 u32 mac13addr1; /* 0x.5a8 - MAC exact match address 13, part 1*/
616 u32 mac13addr2; /* 0x.5ac - MAC exact match address 13, part 2*/
617 u32 mac14addr1; /* 0x.5b0 - MAC exact match address 14, part 1*/
618 u32 mac14addr2; /* 0x.5b4 - MAC exact match address 14, part 2*/
619 u32 mac15addr1; /* 0x.5b8 - MAC exact match address 15, part 1*/
620 u32 mac15addr2; /* 0x.5bc - MAC exact match address 15, part 2*/
621 u8 res20[192];
622 struct rmon_mib rmon; /* 0x.680-0x.73c */
623 u32 rrej; /* 0x.740 - Receive filer rejected packet counter */
624 u8 res21[188];
625 u32 igaddr0; /* 0x.800 - Indivdual/Group address register 0*/
626 u32 igaddr1; /* 0x.804 - Indivdual/Group address register 1*/
627 u32 igaddr2; /* 0x.808 - Indivdual/Group address register 2*/
628 u32 igaddr3; /* 0x.80c - Indivdual/Group address register 3*/
629 u32 igaddr4; /* 0x.810 - Indivdual/Group address register 4*/
630 u32 igaddr5; /* 0x.814 - Indivdual/Group address register 5*/
631 u32 igaddr6; /* 0x.818 - Indivdual/Group address register 6*/
632 u32 igaddr7; /* 0x.81c - Indivdual/Group address register 7*/
Linus Torvalds1da177e2005-04-16 15:20:36 -0700633 u8 res22[96];
Kumar Gala0bbaf062005-06-20 10:54:21 -0500634 u32 gaddr0; /* 0x.880 - Group address register 0 */
635 u32 gaddr1; /* 0x.884 - Group address register 1 */
636 u32 gaddr2; /* 0x.888 - Group address register 2 */
637 u32 gaddr3; /* 0x.88c - Group address register 3 */
638 u32 gaddr4; /* 0x.890 - Group address register 4 */
639 u32 gaddr5; /* 0x.894 - Group address register 5 */
640 u32 gaddr6; /* 0x.898 - Group address register 6 */
641 u32 gaddr7; /* 0x.89c - Group address register 7 */
642 u8 res23a[352];
643 u32 fifocfg; /* 0x.a00 - FIFO interface config register */
644 u8 res23b[252];
645 u8 res23c[248];
646 u32 attr; /* 0x.bf8 - Attributes Register */
647 u32 attreli; /* 0x.bfc - Attributes Extract Length and Extract Index Register */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700648 u8 res24[1024];
649
650};
651
652/* Struct stolen almost completely (and shamelessly) from the FCC enet source
653 * (Ok, that's not so true anymore, but there is a family resemblence)
654 * The GFAR buffer descriptors track the ring buffers. The rx_bd_base
655 * and tx_bd_base always point to the currently available buffer.
656 * The dirty_tx tracks the current buffer that is being sent by the
657 * controller. The cur_tx and dirty_tx are equal under both completely
658 * empty and completely full conditions. The empty/ready indicator in
659 * the buffer descriptor determines the actual condition.
660 */
661struct gfar_private {
662 /* pointers to arrays of skbuffs for tx and rx */
663 struct sk_buff ** tx_skbuff;
664 struct sk_buff ** rx_skbuff;
665
666 /* indices pointing to the next free sbk in skb arrays */
667 u16 skb_curtx;
668 u16 skb_currx;
669
670 /* index of the first skb which hasn't been transmitted
671 * yet. */
672 u16 skb_dirtytx;
673
674 /* Configuration info for the coalescing features */
675 unsigned char txcoalescing;
676 unsigned short txcount;
677 unsigned short txtime;
678 unsigned char rxcoalescing;
679 unsigned short rxcount;
680 unsigned short rxtime;
681
682 /* GFAR addresses */
683 struct rxbd8 *rx_bd_base; /* Base addresses of Rx and Tx Buffers */
684 struct txbd8 *tx_bd_base;
685 struct rxbd8 *cur_rx; /* Next free rx ring entry */
686 struct txbd8 *cur_tx; /* Next free ring entry */
687 struct txbd8 *dirty_tx; /* The Ring entry to be freed. */
688 struct gfar *regs; /* Pointer to the GFAR memory mapped Registers */
Kumar Gala0bbaf062005-06-20 10:54:21 -0500689 u32 *hash_regs[16];
690 int hash_width;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700691 struct gfar *phyregs;
692 struct work_struct tq;
693 struct timer_list phy_info_timer;
694 struct net_device_stats stats; /* linux network statistics */
695 struct gfar_extra_stats extra_stats;
696 spinlock_t lock;
697 unsigned int rx_buffer_size;
698 unsigned int rx_stash_size;
699 unsigned int tx_ring_size;
700 unsigned int rx_ring_size;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700701
Kumar Gala0bbaf062005-06-20 10:54:21 -0500702 unsigned char vlan_enable:1,
703 rx_csum_enable:1,
704 extended_hash:1;
705 unsigned short padding;
706 struct vlan_group *vlgrp;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700707 /* Info structure initialized by board setup code */
708 unsigned int interruptTransmit;
709 unsigned int interruptReceive;
710 unsigned int interruptError;
711 struct gianfar_platform_data *einfo;
712
713 struct gfar_mii_info *mii_info;
714 int oldspeed;
715 int oldduplex;
716 int oldlink;
Kumar Gala0bbaf062005-06-20 10:54:21 -0500717
718 uint32_t msg_enable;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700719};
720
721extern inline u32 gfar_read(volatile unsigned *addr)
722{
723 u32 val;
724 val = in_be32(addr);
725 return val;
726}
727
728extern inline void gfar_write(volatile unsigned *addr, u32 val)
729{
730 out_be32(addr, val);
731}
732
733extern struct ethtool_ops *gfar_op_array[];
734
735#endif /* __GIANFAR_H */