Antoine Tenart | 374ddcb | 2014-03-18 15:32:45 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2014 Antoine Ténart <antoine.tenart@free-electrons.com> |
| 3 | * |
| 4 | * This file is licensed under the terms of the GNU General Public |
| 5 | * License version 2. This program is licensed "as is" without any |
| 6 | * warranty of any kind, whether express or implied. |
| 7 | */ |
| 8 | |
| 9 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 10 | |
| 11 | #include "skeleton.dtsi" |
| 12 | |
| 13 | / { |
| 14 | model = "Marvell Armada 1500 pro (BG2-Q) SoC"; |
| 15 | compatible = "marvell,berlin2q", "marvell,berlin"; |
| 16 | |
| 17 | cpus { |
| 18 | #address-cells = <1>; |
| 19 | #size-cells = <0>; |
| 20 | |
| 21 | cpu@0 { |
| 22 | compatible = "arm,cortex-a9"; |
| 23 | device_type = "cpu"; |
| 24 | next-level-cache = <&l2>; |
| 25 | reg = <0>; |
| 26 | }; |
| 27 | |
| 28 | cpu@1 { |
| 29 | compatible = "arm,cortex-a9"; |
| 30 | device_type = "cpu"; |
| 31 | next-level-cache = <&l2>; |
| 32 | reg = <1>; |
| 33 | }; |
| 34 | |
| 35 | cpu@2 { |
| 36 | compatible = "arm,cortex-a9"; |
| 37 | device_type = "cpu"; |
| 38 | next-level-cache = <&l2>; |
| 39 | reg = <2>; |
| 40 | }; |
| 41 | |
| 42 | cpu@3 { |
| 43 | compatible = "arm,cortex-a9"; |
| 44 | device_type = "cpu"; |
| 45 | next-level-cache = <&l2>; |
| 46 | reg = <3>; |
| 47 | }; |
| 48 | }; |
| 49 | |
| 50 | smclk: sysmgr-clock { |
| 51 | compatible = "fixed-clock"; |
| 52 | #clock-cells = <0>; |
| 53 | clock-frequency = <25000000>; |
| 54 | }; |
| 55 | |
| 56 | cfgclk: config-clock { |
| 57 | compatible = "fixed-clock"; |
| 58 | #clock-cells = <0>; |
| 59 | clock-frequency = <100000000>; |
| 60 | }; |
| 61 | |
| 62 | cpuclk: cpu-clock { |
| 63 | compatible = "fixed-clock"; |
| 64 | #clock-cells = <0>; |
| 65 | clock-frequency = <1200000000>; |
| 66 | }; |
| 67 | |
| 68 | twdclk: twdclk { |
| 69 | compatible = "fixed-factor-clock"; |
| 70 | #clock-cells = <0>; |
| 71 | clocks = <&cpuclk>; |
| 72 | clock-mult = <1>; |
| 73 | clock-div = <3>; |
| 74 | }; |
| 75 | |
| 76 | soc { |
| 77 | compatible = "simple-bus"; |
| 78 | #address-cells = <1>; |
| 79 | #size-cells = <1>; |
| 80 | |
| 81 | ranges = <0 0xf7000000 0x1000000>; |
| 82 | interrupt-parent = <&gic>; |
| 83 | |
| 84 | l2: l2-cache-controller@ac0000 { |
| 85 | compatible = "arm,pl310-cache"; |
| 86 | reg = <0xac0000 0x1000>; |
| 87 | cache-level = <2>; |
| 88 | }; |
| 89 | |
Sebastian Hesselbarth | 0bd4b34 | 2014-03-13 13:32:34 +0100 | [diff] [blame^] | 90 | scu: snoop-control-unit@ad0000 { |
| 91 | compatible = "arm,cortex-a9-scu"; |
| 92 | reg = <0xad0000 0x58>; |
| 93 | }; |
| 94 | |
Antoine Tenart | 374ddcb | 2014-03-18 15:32:45 +0100 | [diff] [blame] | 95 | local-timer@ad0600 { |
| 96 | compatible = "arm,cortex-a9-twd-timer"; |
| 97 | reg = <0xad0600 0x20>; |
| 98 | clocks = <&twdclk>; |
| 99 | interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>; |
| 100 | }; |
| 101 | |
| 102 | gic: interrupt-controller@ad1000 { |
| 103 | compatible = "arm,cortex-a9-gic"; |
| 104 | reg = <0xad1000 0x1000>, <0xad0100 0x100>; |
| 105 | interrupt-controller; |
| 106 | #interrupt-cells = <3>; |
| 107 | }; |
| 108 | |
| 109 | apb@e80000 { |
| 110 | compatible = "simple-bus"; |
| 111 | #address-cells = <1>; |
| 112 | #size-cells = <1>; |
| 113 | |
| 114 | ranges = <0 0xe80000 0x10000>; |
| 115 | interrupt-parent = <&aic>; |
| 116 | |
| 117 | timer0: timer@2c00 { |
| 118 | compatible = "snps,dw-apb-timer"; |
| 119 | reg = <0x2c00 0x14>; |
| 120 | clocks = <&cfgclk>; |
| 121 | clock-names = "timer"; |
| 122 | interrupts = <8>; |
| 123 | }; |
| 124 | |
| 125 | timer1: timer@2c14 { |
| 126 | compatible = "snps,dw-apb-timer"; |
| 127 | reg = <0x2c14 0x14>; |
| 128 | clocks = <&cfgclk>; |
| 129 | clock-names = "timer"; |
| 130 | status = "disabled"; |
| 131 | }; |
| 132 | |
| 133 | timer2: timer@2c28 { |
| 134 | compatible = "snps,dw-apb-timer"; |
| 135 | reg = <0x2c28 0x14>; |
| 136 | clocks = <&cfgclk>; |
| 137 | clock-names = "timer"; |
| 138 | status = "disabled"; |
| 139 | }; |
| 140 | |
| 141 | timer3: timer@2c3c { |
| 142 | compatible = "snps,dw-apb-timer"; |
| 143 | reg = <0x2c3c 0x14>; |
| 144 | clocks = <&cfgclk>; |
| 145 | clock-names = "timer"; |
| 146 | status = "disabled"; |
| 147 | }; |
| 148 | |
| 149 | timer4: timer@2c50 { |
| 150 | compatible = "snps,dw-apb-timer"; |
| 151 | reg = <0x2c50 0x14>; |
| 152 | clocks = <&cfgclk>; |
| 153 | clock-names = "timer"; |
| 154 | status = "disabled"; |
| 155 | }; |
| 156 | |
| 157 | timer5: timer@2c64 { |
| 158 | compatible = "snps,dw-apb-timer"; |
| 159 | reg = <0x2c64 0x14>; |
| 160 | clocks = <&cfgclk>; |
| 161 | clock-names = "timer"; |
| 162 | status = "disabled"; |
| 163 | }; |
| 164 | |
| 165 | timer6: timer@2c78 { |
| 166 | compatible = "snps,dw-apb-timer"; |
| 167 | reg = <0x2c78 0x14>; |
| 168 | clocks = <&cfgclk>; |
| 169 | clock-names = "timer"; |
| 170 | status = "disabled"; |
| 171 | }; |
| 172 | |
| 173 | timer7: timer@2c8c { |
| 174 | compatible = "snps,dw-apb-timer"; |
| 175 | reg = <0x2c8c 0x14>; |
| 176 | clocks = <&cfgclk>; |
| 177 | clock-names = "timer"; |
| 178 | status = "disabled"; |
| 179 | }; |
| 180 | |
| 181 | aic: interrupt-controller@3800 { |
| 182 | compatible = "snps,dw-apb-ictl"; |
| 183 | reg = <0x3800 0x30>; |
| 184 | interrupt-controller; |
| 185 | #interrupt-cells = <1>; |
| 186 | interrupt-parent = <&gic>; |
| 187 | interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; |
| 188 | }; |
| 189 | }; |
| 190 | |
Sebastian Hesselbarth | 0bd4b34 | 2014-03-13 13:32:34 +0100 | [diff] [blame^] | 191 | generic-regs@ea0110 { |
| 192 | compatible = "marvell,berlin-generic-regs", "syscon"; |
| 193 | reg = <0xea0110 0x10>; |
| 194 | }; |
| 195 | |
Antoine Tenart | 374ddcb | 2014-03-18 15:32:45 +0100 | [diff] [blame] | 196 | apb@fc0000 { |
| 197 | compatible = "simple-bus"; |
| 198 | #address-cells = <1>; |
| 199 | #size-cells = <1>; |
| 200 | |
| 201 | ranges = <0 0xfc0000 0x10000>; |
| 202 | interrupt-parent = <&sic>; |
| 203 | |
| 204 | uart0: uart@9000 { |
| 205 | compatible = "snps,dw-apb-uart"; |
| 206 | reg = <0x9000 0x100>; |
| 207 | interrupt-parent = <&sic>; |
| 208 | interrupts = <8>; |
| 209 | clocks = <&smclk>; |
| 210 | reg-shift = <2>; |
| 211 | status = "disabled"; |
| 212 | }; |
| 213 | |
| 214 | uart1: uart@a000 { |
| 215 | compatible = "snps,dw-apb-uart"; |
| 216 | reg = <0xa000 0x100>; |
| 217 | interrupt-parent = <&sic>; |
| 218 | interrupts = <9>; |
| 219 | clocks = <&smclk>; |
| 220 | reg-shift = <2>; |
| 221 | status = "disabled"; |
| 222 | }; |
| 223 | |
| 224 | sic: interrupt-controller@e000 { |
| 225 | compatible = "snps,dw-apb-ictl"; |
| 226 | reg = <0xe000 0x30>; |
| 227 | interrupt-controller; |
| 228 | #interrupt-cells = <1>; |
| 229 | interrupt-parent = <&gic>; |
| 230 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; |
| 231 | }; |
| 232 | }; |
| 233 | }; |
| 234 | }; |