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Carlo Caionecfb61a42014-05-01 14:29:27 +02001/*
2 * Functions and registers to access AXP20X power management chip.
3 *
4 * Copyright (C) 2013, Carlo Caione <carlo@caione.org>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __LINUX_MFD_AXP20X_H
12#define __LINUX_MFD_AXP20X_H
13
Hans de Goede69fb4dc2015-08-01 10:39:38 +020014#include <linux/regmap.h>
15
Carlo Caionecfb61a42014-05-01 14:29:27 +020016enum {
Michal Suchanekd8d79f82015-07-11 14:59:56 +020017 AXP152_ID = 0,
18 AXP202_ID,
Carlo Caionecfb61a42014-05-01 14:29:27 +020019 AXP209_ID,
Boris BREZILLONf05be582015-04-10 12:09:01 +080020 AXP221_ID,
Chen-Yu Tsai02071f02016-02-12 10:02:44 +080021 AXP223_ID,
Jacob Panaf7e9062014-10-06 21:17:14 -070022 AXP288_ID,
Chen-Yu Tsai20147f02016-03-29 17:22:26 +080023 AXP809_ID,
Jacob Panaf7e9062014-10-06 21:17:14 -070024 NR_AXP20X_VARIANTS,
Carlo Caionecfb61a42014-05-01 14:29:27 +020025};
26
27#define AXP20X_DATACACHE(m) (0x04 + (m))
28
29/* Power supply */
Michal Suchanekd8d79f82015-07-11 14:59:56 +020030#define AXP152_PWR_OP_MODE 0x01
31#define AXP152_LDO3456_DC1234_CTRL 0x12
32#define AXP152_ALDO_OP_MODE 0x13
33#define AXP152_LDO0_CTRL 0x15
34#define AXP152_DCDC2_V_OUT 0x23
35#define AXP152_DCDC2_V_SCAL 0x25
36#define AXP152_DCDC1_V_OUT 0x26
37#define AXP152_DCDC3_V_OUT 0x27
38#define AXP152_ALDO12_V_OUT 0x28
39#define AXP152_DLDO1_V_OUT 0x29
40#define AXP152_DLDO2_V_OUT 0x2a
41#define AXP152_DCDC4_V_OUT 0x2b
42#define AXP152_V_OFF 0x31
43#define AXP152_OFF_CTRL 0x32
44#define AXP152_PEK_KEY 0x36
45#define AXP152_DCDC_FREQ 0x37
46#define AXP152_DCDC_MODE 0x80
47
Carlo Caionecfb61a42014-05-01 14:29:27 +020048#define AXP20X_PWR_INPUT_STATUS 0x00
49#define AXP20X_PWR_OP_MODE 0x01
50#define AXP20X_USB_OTG_STATUS 0x02
51#define AXP20X_PWR_OUT_CTRL 0x12
52#define AXP20X_DCDC2_V_OUT 0x23
53#define AXP20X_DCDC2_LDO3_V_SCAL 0x25
54#define AXP20X_DCDC3_V_OUT 0x27
55#define AXP20X_LDO24_V_OUT 0x28
56#define AXP20X_LDO3_V_OUT 0x29
57#define AXP20X_VBUS_IPSOUT_MGMT 0x30
58#define AXP20X_V_OFF 0x31
59#define AXP20X_OFF_CTRL 0x32
60#define AXP20X_CHRG_CTRL1 0x33
61#define AXP20X_CHRG_CTRL2 0x34
62#define AXP20X_CHRG_BAK_CTRL 0x35
63#define AXP20X_PEK_KEY 0x36
64#define AXP20X_DCDC_FREQ 0x37
65#define AXP20X_V_LTF_CHRG 0x38
66#define AXP20X_V_HTF_CHRG 0x39
67#define AXP20X_APS_WARN_L1 0x3a
68#define AXP20X_APS_WARN_L2 0x3b
69#define AXP20X_V_LTF_DISCHRG 0x3c
70#define AXP20X_V_HTF_DISCHRG 0x3d
71
Boris BREZILLONf05be582015-04-10 12:09:01 +080072#define AXP22X_PWR_OUT_CTRL1 0x10
73#define AXP22X_PWR_OUT_CTRL2 0x12
74#define AXP22X_PWR_OUT_CTRL3 0x13
75#define AXP22X_DLDO1_V_OUT 0x15
76#define AXP22X_DLDO2_V_OUT 0x16
77#define AXP22X_DLDO3_V_OUT 0x17
78#define AXP22X_DLDO4_V_OUT 0x18
79#define AXP22X_ELDO1_V_OUT 0x19
80#define AXP22X_ELDO2_V_OUT 0x1a
81#define AXP22X_ELDO3_V_OUT 0x1b
82#define AXP22X_DC5LDO_V_OUT 0x1c
83#define AXP22X_DCDC1_V_OUT 0x21
84#define AXP22X_DCDC2_V_OUT 0x22
85#define AXP22X_DCDC3_V_OUT 0x23
86#define AXP22X_DCDC4_V_OUT 0x24
87#define AXP22X_DCDC5_V_OUT 0x25
88#define AXP22X_DCDC23_V_RAMP_CTRL 0x27
89#define AXP22X_ALDO1_V_OUT 0x28
90#define AXP22X_ALDO2_V_OUT 0x29
91#define AXP22X_ALDO3_V_OUT 0x2a
92#define AXP22X_CHRG_CTRL3 0x35
93
Carlo Caionecfb61a42014-05-01 14:29:27 +020094/* Interrupt */
Michal Suchanekd8d79f82015-07-11 14:59:56 +020095#define AXP152_IRQ1_EN 0x40
96#define AXP152_IRQ2_EN 0x41
97#define AXP152_IRQ3_EN 0x42
98#define AXP152_IRQ1_STATE 0x48
99#define AXP152_IRQ2_STATE 0x49
100#define AXP152_IRQ3_STATE 0x4a
101
Carlo Caionecfb61a42014-05-01 14:29:27 +0200102#define AXP20X_IRQ1_EN 0x40
103#define AXP20X_IRQ2_EN 0x41
104#define AXP20X_IRQ3_EN 0x42
105#define AXP20X_IRQ4_EN 0x43
106#define AXP20X_IRQ5_EN 0x44
Jacob Panaf7e9062014-10-06 21:17:14 -0700107#define AXP20X_IRQ6_EN 0x45
Carlo Caionecfb61a42014-05-01 14:29:27 +0200108#define AXP20X_IRQ1_STATE 0x48
109#define AXP20X_IRQ2_STATE 0x49
110#define AXP20X_IRQ3_STATE 0x4a
111#define AXP20X_IRQ4_STATE 0x4b
112#define AXP20X_IRQ5_STATE 0x4c
Jacob Panaf7e9062014-10-06 21:17:14 -0700113#define AXP20X_IRQ6_STATE 0x4d
Carlo Caionecfb61a42014-05-01 14:29:27 +0200114
115/* ADC */
116#define AXP20X_ACIN_V_ADC_H 0x56
117#define AXP20X_ACIN_V_ADC_L 0x57
118#define AXP20X_ACIN_I_ADC_H 0x58
119#define AXP20X_ACIN_I_ADC_L 0x59
120#define AXP20X_VBUS_V_ADC_H 0x5a
121#define AXP20X_VBUS_V_ADC_L 0x5b
122#define AXP20X_VBUS_I_ADC_H 0x5c
123#define AXP20X_VBUS_I_ADC_L 0x5d
124#define AXP20X_TEMP_ADC_H 0x5e
125#define AXP20X_TEMP_ADC_L 0x5f
126#define AXP20X_TS_IN_H 0x62
127#define AXP20X_TS_IN_L 0x63
128#define AXP20X_GPIO0_V_ADC_H 0x64
129#define AXP20X_GPIO0_V_ADC_L 0x65
130#define AXP20X_GPIO1_V_ADC_H 0x66
131#define AXP20X_GPIO1_V_ADC_L 0x67
132#define AXP20X_PWR_BATT_H 0x70
133#define AXP20X_PWR_BATT_M 0x71
134#define AXP20X_PWR_BATT_L 0x72
135#define AXP20X_BATT_V_H 0x78
136#define AXP20X_BATT_V_L 0x79
137#define AXP20X_BATT_CHRG_I_H 0x7a
138#define AXP20X_BATT_CHRG_I_L 0x7b
139#define AXP20X_BATT_DISCHRG_I_H 0x7c
140#define AXP20X_BATT_DISCHRG_I_L 0x7d
141#define AXP20X_IPSOUT_V_HIGH_H 0x7e
142#define AXP20X_IPSOUT_V_HIGH_L 0x7f
143
144/* Power supply */
145#define AXP20X_DCDC_MODE 0x80
146#define AXP20X_ADC_EN1 0x82
147#define AXP20X_ADC_EN2 0x83
148#define AXP20X_ADC_RATE 0x84
149#define AXP20X_GPIO10_IN_RANGE 0x85
150#define AXP20X_GPIO1_ADC_IRQ_RIS 0x86
151#define AXP20X_GPIO1_ADC_IRQ_FAL 0x87
152#define AXP20X_TIMER_CTRL 0x8a
153#define AXP20X_VBUS_MON 0x8b
154#define AXP20X_OVER_TMP 0x8f
155
Boris BREZILLONf05be582015-04-10 12:09:01 +0800156#define AXP22X_PWREN_CTRL1 0x8c
157#define AXP22X_PWREN_CTRL2 0x8d
158
Carlo Caionecfb61a42014-05-01 14:29:27 +0200159/* GPIO */
Michal Suchanekd8d79f82015-07-11 14:59:56 +0200160#define AXP152_GPIO0_CTRL 0x90
161#define AXP152_GPIO1_CTRL 0x91
162#define AXP152_GPIO2_CTRL 0x92
163#define AXP152_GPIO3_CTRL 0x93
164#define AXP152_LDOGPIO2_V_OUT 0x96
165#define AXP152_GPIO_INPUT 0x97
166#define AXP152_PWM0_FREQ_X 0x98
167#define AXP152_PWM0_FREQ_Y 0x99
168#define AXP152_PWM0_DUTY_CYCLE 0x9a
169#define AXP152_PWM1_FREQ_X 0x9b
170#define AXP152_PWM1_FREQ_Y 0x9c
171#define AXP152_PWM1_DUTY_CYCLE 0x9d
172
Carlo Caionecfb61a42014-05-01 14:29:27 +0200173#define AXP20X_GPIO0_CTRL 0x90
174#define AXP20X_LDO5_V_OUT 0x91
175#define AXP20X_GPIO1_CTRL 0x92
176#define AXP20X_GPIO2_CTRL 0x93
177#define AXP20X_GPIO20_SS 0x94
178#define AXP20X_GPIO3_CTRL 0x95
179
Boris BREZILLONf05be582015-04-10 12:09:01 +0800180#define AXP22X_LDO_IO0_V_OUT 0x91
181#define AXP22X_LDO_IO1_V_OUT 0x93
182#define AXP22X_GPIO_STATE 0x94
183#define AXP22X_GPIO_PULL_DOWN 0x95
184
Carlo Caionecfb61a42014-05-01 14:29:27 +0200185/* Battery */
186#define AXP20X_CHRG_CC_31_24 0xb0
187#define AXP20X_CHRG_CC_23_16 0xb1
188#define AXP20X_CHRG_CC_15_8 0xb2
189#define AXP20X_CHRG_CC_7_0 0xb3
190#define AXP20X_DISCHRG_CC_31_24 0xb4
191#define AXP20X_DISCHRG_CC_23_16 0xb5
192#define AXP20X_DISCHRG_CC_15_8 0xb6
193#define AXP20X_DISCHRG_CC_7_0 0xb7
194#define AXP20X_CC_CTRL 0xb8
195#define AXP20X_FG_RES 0xb9
196
Bruno Prémont553ed4b2015-08-08 17:58:40 +0200197/* OCV */
198#define AXP20X_RDC_H 0xba
199#define AXP20X_RDC_L 0xbb
200#define AXP20X_OCV(m) (0xc0 + (m))
201#define AXP20X_OCV_MAX 0xf
202
Boris BREZILLONf05be582015-04-10 12:09:01 +0800203/* AXP22X specific registers */
204#define AXP22X_BATLOW_THRES1 0xe6
205
Jacob Panaf7e9062014-10-06 21:17:14 -0700206/* AXP288 specific registers */
207#define AXP288_PMIC_ADC_H 0x56
208#define AXP288_PMIC_ADC_L 0x57
209#define AXP288_ADC_TS_PIN_CTRL 0x84
Jacob Panaf7e9062014-10-06 21:17:14 -0700210#define AXP288_PMIC_ADC_EN 0x84
Jacob Panaf7e9062014-10-06 21:17:14 -0700211
Todd E Brandt774e0b42015-01-07 13:25:52 -0800212/* Fuel Gauge */
213#define AXP288_FG_RDC1_REG 0xba
214#define AXP288_FG_RDC0_REG 0xbb
215#define AXP288_FG_OCVH_REG 0xbc
216#define AXP288_FG_OCVL_REG 0xbd
217#define AXP288_FG_OCV_CURVE_REG 0xc0
218#define AXP288_FG_DES_CAP1_REG 0xe0
219#define AXP288_FG_DES_CAP0_REG 0xe1
220#define AXP288_FG_CC_MTR1_REG 0xe2
221#define AXP288_FG_CC_MTR0_REG 0xe3
222#define AXP288_FG_OCV_CAP_REG 0xe4
223#define AXP288_FG_CC_CAP_REG 0xe5
224#define AXP288_FG_LOW_CAP_REG 0xe6
225#define AXP288_FG_TUNE0 0xe8
226#define AXP288_FG_TUNE1 0xe9
227#define AXP288_FG_TUNE2 0xea
228#define AXP288_FG_TUNE3 0xeb
229#define AXP288_FG_TUNE4 0xec
230#define AXP288_FG_TUNE5 0xed
Jacob Panaf7e9062014-10-06 21:17:14 -0700231
Carlo Caionecfb61a42014-05-01 14:29:27 +0200232/* Regulators IDs */
233enum {
234 AXP20X_LDO1 = 0,
235 AXP20X_LDO2,
236 AXP20X_LDO3,
237 AXP20X_LDO4,
238 AXP20X_LDO5,
239 AXP20X_DCDC2,
240 AXP20X_DCDC3,
241 AXP20X_REG_ID_MAX,
242};
243
Boris BREZILLONf05be582015-04-10 12:09:01 +0800244enum {
245 AXP22X_DCDC1 = 0,
246 AXP22X_DCDC2,
247 AXP22X_DCDC3,
248 AXP22X_DCDC4,
249 AXP22X_DCDC5,
250 AXP22X_DC1SW,
251 AXP22X_DC5LDO,
252 AXP22X_ALDO1,
253 AXP22X_ALDO2,
254 AXP22X_ALDO3,
255 AXP22X_ELDO1,
256 AXP22X_ELDO2,
257 AXP22X_ELDO3,
258 AXP22X_DLDO1,
259 AXP22X_DLDO2,
260 AXP22X_DLDO3,
261 AXP22X_DLDO4,
262 AXP22X_RTC_LDO,
263 AXP22X_LDO_IO0,
264 AXP22X_LDO_IO1,
265 AXP22X_REG_ID_MAX,
266};
267
Chen-Yu Tsai20147f02016-03-29 17:22:26 +0800268enum {
269 AXP809_DCDC1 = 0,
270 AXP809_DCDC2,
271 AXP809_DCDC3,
272 AXP809_DCDC4,
273 AXP809_DCDC5,
274 AXP809_DC1SW,
275 AXP809_DC5LDO,
276 AXP809_ALDO1,
277 AXP809_ALDO2,
278 AXP809_ALDO3,
279 AXP809_ELDO1,
280 AXP809_ELDO2,
281 AXP809_ELDO3,
282 AXP809_DLDO1,
283 AXP809_DLDO2,
284 AXP809_RTC_LDO,
285 AXP809_LDO_IO0,
286 AXP809_LDO_IO1,
287 AXP809_SW,
288 AXP809_REG_ID_MAX,
289};
290
Carlo Caionecfb61a42014-05-01 14:29:27 +0200291/* IRQs */
292enum {
Michal Suchanekd8d79f82015-07-11 14:59:56 +0200293 AXP152_IRQ_LDO0IN_CONNECT = 1,
294 AXP152_IRQ_LDO0IN_REMOVAL,
295 AXP152_IRQ_ALDO0IN_CONNECT,
296 AXP152_IRQ_ALDO0IN_REMOVAL,
297 AXP152_IRQ_DCDC1_V_LOW,
298 AXP152_IRQ_DCDC2_V_LOW,
299 AXP152_IRQ_DCDC3_V_LOW,
300 AXP152_IRQ_DCDC4_V_LOW,
301 AXP152_IRQ_PEK_SHORT,
302 AXP152_IRQ_PEK_LONG,
303 AXP152_IRQ_TIMER,
304 AXP152_IRQ_PEK_RIS_EDGE,
305 AXP152_IRQ_PEK_FAL_EDGE,
306 AXP152_IRQ_GPIO3_INPUT,
307 AXP152_IRQ_GPIO2_INPUT,
308 AXP152_IRQ_GPIO1_INPUT,
309 AXP152_IRQ_GPIO0_INPUT,
310};
311
312enum {
Carlo Caionecfb61a42014-05-01 14:29:27 +0200313 AXP20X_IRQ_ACIN_OVER_V = 1,
314 AXP20X_IRQ_ACIN_PLUGIN,
315 AXP20X_IRQ_ACIN_REMOVAL,
316 AXP20X_IRQ_VBUS_OVER_V,
317 AXP20X_IRQ_VBUS_PLUGIN,
318 AXP20X_IRQ_VBUS_REMOVAL,
319 AXP20X_IRQ_VBUS_V_LOW,
320 AXP20X_IRQ_BATT_PLUGIN,
321 AXP20X_IRQ_BATT_REMOVAL,
322 AXP20X_IRQ_BATT_ENT_ACT_MODE,
323 AXP20X_IRQ_BATT_EXIT_ACT_MODE,
324 AXP20X_IRQ_CHARG,
325 AXP20X_IRQ_CHARG_DONE,
326 AXP20X_IRQ_BATT_TEMP_HIGH,
327 AXP20X_IRQ_BATT_TEMP_LOW,
328 AXP20X_IRQ_DIE_TEMP_HIGH,
329 AXP20X_IRQ_CHARG_I_LOW,
330 AXP20X_IRQ_DCDC1_V_LONG,
331 AXP20X_IRQ_DCDC2_V_LONG,
332 AXP20X_IRQ_DCDC3_V_LONG,
333 AXP20X_IRQ_PEK_SHORT = 22,
334 AXP20X_IRQ_PEK_LONG,
335 AXP20X_IRQ_N_OE_PWR_ON,
336 AXP20X_IRQ_N_OE_PWR_OFF,
337 AXP20X_IRQ_VBUS_VALID,
338 AXP20X_IRQ_VBUS_NOT_VALID,
339 AXP20X_IRQ_VBUS_SESS_VALID,
340 AXP20X_IRQ_VBUS_SESS_END,
341 AXP20X_IRQ_LOW_PWR_LVL1,
342 AXP20X_IRQ_LOW_PWR_LVL2,
343 AXP20X_IRQ_TIMER,
344 AXP20X_IRQ_PEK_RIS_EDGE,
345 AXP20X_IRQ_PEK_FAL_EDGE,
346 AXP20X_IRQ_GPIO3_INPUT,
347 AXP20X_IRQ_GPIO2_INPUT,
348 AXP20X_IRQ_GPIO1_INPUT,
349 AXP20X_IRQ_GPIO0_INPUT,
350};
351
Boris BREZILLONf05be582015-04-10 12:09:01 +0800352enum axp22x_irqs {
353 AXP22X_IRQ_ACIN_OVER_V = 1,
354 AXP22X_IRQ_ACIN_PLUGIN,
355 AXP22X_IRQ_ACIN_REMOVAL,
356 AXP22X_IRQ_VBUS_OVER_V,
357 AXP22X_IRQ_VBUS_PLUGIN,
358 AXP22X_IRQ_VBUS_REMOVAL,
359 AXP22X_IRQ_VBUS_V_LOW,
360 AXP22X_IRQ_BATT_PLUGIN,
361 AXP22X_IRQ_BATT_REMOVAL,
362 AXP22X_IRQ_BATT_ENT_ACT_MODE,
363 AXP22X_IRQ_BATT_EXIT_ACT_MODE,
364 AXP22X_IRQ_CHARG,
365 AXP22X_IRQ_CHARG_DONE,
366 AXP22X_IRQ_BATT_TEMP_HIGH,
367 AXP22X_IRQ_BATT_TEMP_LOW,
368 AXP22X_IRQ_DIE_TEMP_HIGH,
369 AXP22X_IRQ_PEK_SHORT,
370 AXP22X_IRQ_PEK_LONG,
371 AXP22X_IRQ_LOW_PWR_LVL1,
372 AXP22X_IRQ_LOW_PWR_LVL2,
373 AXP22X_IRQ_TIMER,
374 AXP22X_IRQ_PEK_RIS_EDGE,
375 AXP22X_IRQ_PEK_FAL_EDGE,
376 AXP22X_IRQ_GPIO1_INPUT,
377 AXP22X_IRQ_GPIO0_INPUT,
378};
379
Jacob Panaf7e9062014-10-06 21:17:14 -0700380enum axp288_irqs {
381 AXP288_IRQ_VBUS_FALL = 2,
382 AXP288_IRQ_VBUS_RISE,
383 AXP288_IRQ_OV,
384 AXP288_IRQ_FALLING_ALT,
385 AXP288_IRQ_RISING_ALT,
386 AXP288_IRQ_OV_ALT,
387 AXP288_IRQ_DONE = 10,
388 AXP288_IRQ_CHARGING,
389 AXP288_IRQ_SAFE_QUIT,
390 AXP288_IRQ_SAFE_ENTER,
391 AXP288_IRQ_ABSENT,
392 AXP288_IRQ_APPEND,
393 AXP288_IRQ_QWBTU,
394 AXP288_IRQ_WBTU,
395 AXP288_IRQ_QWBTO,
396 AXP288_IRQ_WBTO,
397 AXP288_IRQ_QCBTU,
398 AXP288_IRQ_CBTU,
399 AXP288_IRQ_QCBTO,
400 AXP288_IRQ_CBTO,
401 AXP288_IRQ_WL2,
402 AXP288_IRQ_WL1,
403 AXP288_IRQ_GPADC,
404 AXP288_IRQ_OT = 31,
405 AXP288_IRQ_GPIO0,
406 AXP288_IRQ_GPIO1,
407 AXP288_IRQ_POKO,
408 AXP288_IRQ_POKL,
409 AXP288_IRQ_POKS,
410 AXP288_IRQ_POKN,
411 AXP288_IRQ_POKP,
412 AXP288_IRQ_TIMER,
413 AXP288_IRQ_MV_CHNG,
414 AXP288_IRQ_BC_USB_CHNG,
415};
416
Chen-Yu Tsai20147f02016-03-29 17:22:26 +0800417enum axp809_irqs {
418 AXP809_IRQ_ACIN_OVER_V = 1,
419 AXP809_IRQ_ACIN_PLUGIN,
420 AXP809_IRQ_ACIN_REMOVAL,
421 AXP809_IRQ_VBUS_OVER_V,
422 AXP809_IRQ_VBUS_PLUGIN,
423 AXP809_IRQ_VBUS_REMOVAL,
424 AXP809_IRQ_VBUS_V_LOW,
425 AXP809_IRQ_BATT_PLUGIN,
426 AXP809_IRQ_BATT_REMOVAL,
427 AXP809_IRQ_BATT_ENT_ACT_MODE,
428 AXP809_IRQ_BATT_EXIT_ACT_MODE,
429 AXP809_IRQ_CHARG,
430 AXP809_IRQ_CHARG_DONE,
431 AXP809_IRQ_BATT_CHG_TEMP_HIGH,
432 AXP809_IRQ_BATT_CHG_TEMP_HIGH_END,
433 AXP809_IRQ_BATT_CHG_TEMP_LOW,
434 AXP809_IRQ_BATT_CHG_TEMP_LOW_END,
435 AXP809_IRQ_BATT_ACT_TEMP_HIGH,
436 AXP809_IRQ_BATT_ACT_TEMP_HIGH_END,
437 AXP809_IRQ_BATT_ACT_TEMP_LOW,
438 AXP809_IRQ_BATT_ACT_TEMP_LOW_END,
439 AXP809_IRQ_DIE_TEMP_HIGH,
440 AXP809_IRQ_LOW_PWR_LVL1,
441 AXP809_IRQ_LOW_PWR_LVL2,
442 AXP809_IRQ_TIMER,
443 AXP809_IRQ_PEK_RIS_EDGE,
444 AXP809_IRQ_PEK_FAL_EDGE,
445 AXP809_IRQ_PEK_SHORT,
446 AXP809_IRQ_PEK_LONG,
447 AXP809_IRQ_PEK_OVER_OFF,
448 AXP809_IRQ_GPIO1_INPUT,
449 AXP809_IRQ_GPIO0_INPUT,
450};
451
Jacob Panaf7e9062014-10-06 21:17:14 -0700452#define AXP288_TS_ADC_H 0x58
453#define AXP288_TS_ADC_L 0x59
454#define AXP288_GP_ADC_H 0x5a
455#define AXP288_GP_ADC_L 0x5b
456
Carlo Caionecfb61a42014-05-01 14:29:27 +0200457struct axp20x_dev {
458 struct device *dev;
Chen-Yu Tsai4fd41152016-02-12 10:02:42 +0800459 int irq;
Carlo Caionecfb61a42014-05-01 14:29:27 +0200460 struct regmap *regmap;
461 struct regmap_irq_chip_data *regmap_irqc;
462 long variant;
Jacob Panaf7e9062014-10-06 21:17:14 -0700463 int nr_cells;
464 struct mfd_cell *cells;
465 const struct regmap_config *regmap_cfg;
466 const struct regmap_irq_chip *regmap_irq_chip;
Carlo Caionecfb61a42014-05-01 14:29:27 +0200467};
468
Todd E Brandt774e0b42015-01-07 13:25:52 -0800469#define BATTID_LEN 64
470#define OCV_CURVE_SIZE 32
471#define MAX_THERM_CURVE_SIZE 25
472#define PD_DEF_MIN_TEMP 0
473#define PD_DEF_MAX_TEMP 55
474
475struct axp20x_fg_pdata {
476 char battid[BATTID_LEN + 1];
477 int design_cap;
478 int min_volt;
479 int max_volt;
480 int max_temp;
481 int min_temp;
482 int cap1;
483 int cap0;
484 int rdc1;
485 int rdc0;
486 int ocv_curve[OCV_CURVE_SIZE];
487 int tcsz;
488 int thermistor_curve[MAX_THERM_CURVE_SIZE][2];
489};
490
Ramakrishna Pallala843735b2015-05-04 22:16:07 +0530491struct axp20x_chrg_pdata {
492 int max_cc;
493 int max_cv;
494 int def_cc;
495 int def_cv;
496};
497
Ramakrishna Pallalaf0312372015-04-30 20:44:45 +0530498struct axp288_extcon_pdata {
499 /* GPIO pin control to switch D+/D- lines b/w PMIC and SOC */
500 struct gpio_desc *gpio_mux_cntl;
501};
502
Hans de Goede69fb4dc2015-08-01 10:39:38 +0200503/* generic helper function for reading 9-16 bit wide regs */
504static inline int axp20x_read_variable_width(struct regmap *regmap,
505 unsigned int reg, unsigned int width)
506{
507 unsigned int reg_val, result;
508 int err;
509
510 err = regmap_read(regmap, reg, &reg_val);
511 if (err)
512 return err;
513
514 result = reg_val << (width - 8);
515
516 err = regmap_read(regmap, reg + 1, &reg_val);
517 if (err)
518 return err;
519
520 result |= reg_val;
521
522 return result;
523}
524
Chen-Yu Tsai4fd41152016-02-12 10:02:42 +0800525/**
526 * axp20x_match_device(): Setup axp20x variant related fields
527 *
528 * @axp20x: axp20x device to setup (.dev field must be set)
529 * @dev: device associated with this axp20x device
530 *
531 * This lets the axp20x core configure the mfd cells and register maps
532 * for later use.
533 */
534int axp20x_match_device(struct axp20x_dev *axp20x);
535
536/**
537 * axp20x_device_probe(): Probe a configured axp20x device
538 *
539 * @axp20x: axp20x device to probe (must be configured)
540 *
541 * This function lets the axp20x core register the axp20x mfd devices
542 * and irqchip. The axp20x device passed in must be fully configured
543 * with axp20x_match_device, its irq set, and regmap created.
544 */
545int axp20x_device_probe(struct axp20x_dev *axp20x);
546
547/**
548 * axp20x_device_probe(): Remove a axp20x device
549 *
550 * @axp20x: axp20x device to remove
551 *
552 * This tells the axp20x core to remove the associated mfd devices
553 */
554int axp20x_device_remove(struct axp20x_dev *axp20x);
555
Carlo Caionecfb61a42014-05-01 14:29:27 +0200556#endif /* __LINUX_MFD_AXP20X_H */