Kumar Gala | a2f40cc | 2005-09-03 15:55:33 -0700 | [diff] [blame] | 1 | /* |
Kumar Gala | a2f40cc | 2005-09-03 15:55:33 -0700 | [diff] [blame] | 2 | * Watchdog timer for PowerPC Book-E systems |
| 3 | * |
| 4 | * Author: Matthew McClintock |
Kumar Gala | 4c8d3d9 | 2005-11-13 16:06:30 -0800 | [diff] [blame] | 5 | * Maintainer: Kumar Gala <galak@kernel.crashing.org> |
Kumar Gala | a2f40cc | 2005-09-03 15:55:33 -0700 | [diff] [blame] | 6 | * |
Timur Tabi | 112e754 | 2011-02-08 17:39:46 -0600 | [diff] [blame] | 7 | * Copyright 2005, 2008, 2010-2011 Freescale Semiconductor Inc. |
Kumar Gala | a2f40cc | 2005-09-03 15:55:33 -0700 | [diff] [blame] | 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify it |
| 10 | * under the terms of the GNU General Public License as published by the |
| 11 | * Free Software Foundation; either version 2 of the License, or (at your |
| 12 | * option) any later version. |
| 13 | */ |
| 14 | |
Joe Perches | 27c766a | 2012-02-15 15:06:19 -0800 | [diff] [blame] | 15 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
| 16 | |
Kumar Gala | a2f40cc | 2005-09-03 15:55:33 -0700 | [diff] [blame] | 17 | #include <linux/module.h> |
Chen Gong | f172ddc6 | 2008-04-29 16:42:05 +0800 | [diff] [blame] | 18 | #include <linux/smp.h> |
Kumar Gala | a2f40cc | 2005-09-03 15:55:33 -0700 | [diff] [blame] | 19 | #include <linux/watchdog.h> |
| 20 | |
| 21 | #include <asm/reg_booke.h> |
Chris Friesen | dcfb748 | 2009-08-12 12:02:46 -0600 | [diff] [blame] | 22 | #include <asm/time.h> |
| 23 | #include <asm/div64.h> |
Kumar Gala | a2f40cc | 2005-09-03 15:55:33 -0700 | [diff] [blame] | 24 | |
Dave Jiang | 40ebbcb | 2007-04-12 13:34:55 -0700 | [diff] [blame] | 25 | /* If the kernel parameter wdt=1, the watchdog will be enabled at boot. |
Kumar Gala | a2f40cc | 2005-09-03 15:55:33 -0700 | [diff] [blame] | 26 | * Also, the wdt_period sets the watchdog timer period timeout. |
| 27 | * For E500 cpus the wdt_period sets which bit changing from 0->1 will |
| 28 | * trigger a watchog timeout. This watchdog timeout will occur 3 times, the |
| 29 | * first time nothing will happen, the second time a watchdog exception will |
| 30 | * occur, and the final time the board will reset. |
| 31 | */ |
| 32 | |
Chen Gong | f172ddc6 | 2008-04-29 16:42:05 +0800 | [diff] [blame] | 33 | u32 booke_wdt_enabled; |
Timur Tabi | e0dc09f | 2010-10-13 14:19:36 -0500 | [diff] [blame] | 34 | u32 booke_wdt_period = CONFIG_BOOKE_WDT_DEFAULT_TIMEOUT; |
Kumar Gala | a2f40cc | 2005-09-03 15:55:33 -0700 | [diff] [blame] | 35 | |
Shaohui Xie | be0884c | 2012-05-11 13:33:40 +0800 | [diff] [blame] | 36 | #ifdef CONFIG_PPC_FSL_BOOK3E |
Chris Friesen | dcfb748 | 2009-08-12 12:02:46 -0600 | [diff] [blame] | 37 | #define WDTP(x) ((((x)&0x3)<<30)|(((x)&0x3c)<<15)) |
Luuk Paulussen | 0fb0657 | 2010-04-15 15:59:10 +1200 | [diff] [blame] | 38 | #define WDTP_MASK (WDTP(0x3f)) |
Kumar Gala | a2f40cc | 2005-09-03 15:55:33 -0700 | [diff] [blame] | 39 | #else |
| 40 | #define WDTP(x) (TCR_WP(x)) |
Matthias Fuchs | 0a0e9e0 | 2008-11-05 21:53:56 +0100 | [diff] [blame] | 41 | #define WDTP_MASK (TCR_WP_MASK) |
Kumar Gala | a2f40cc | 2005-09-03 15:55:33 -0700 | [diff] [blame] | 42 | #endif |
| 43 | |
Tang Yuantian | d2deeba | 2014-05-08 10:04:26 +0800 | [diff] [blame] | 44 | /* Checks wdt=x and wdt_period=xx command-line option */ |
| 45 | notrace int __init early_parse_wdt(char *p) |
| 46 | { |
| 47 | if (p && strncmp(p, "0", 1) != 0) |
| 48 | booke_wdt_enabled = 1; |
| 49 | |
| 50 | return 0; |
| 51 | } |
| 52 | early_param("wdt", early_parse_wdt); |
| 53 | |
| 54 | int __init early_parse_wdt_period(char *p) |
| 55 | { |
| 56 | unsigned long ret; |
| 57 | if (p) { |
| 58 | if (!kstrtol(p, 0, &ret)) |
| 59 | booke_wdt_period = ret; |
| 60 | } |
| 61 | |
| 62 | return 0; |
| 63 | } |
| 64 | early_param("wdt_period", early_parse_wdt_period); |
| 65 | |
Guenter Roeck | 52e5cc4 | 2013-02-05 12:14:23 -0800 | [diff] [blame] | 66 | #ifdef CONFIG_PPC_FSL_BOOK3E |
Chen Gong | f172ddc6 | 2008-04-29 16:42:05 +0800 | [diff] [blame] | 67 | |
Chris Friesen | dcfb748 | 2009-08-12 12:02:46 -0600 | [diff] [blame] | 68 | /* For the specified period, determine the number of seconds |
| 69 | * corresponding to the reset time. There will be a watchdog |
| 70 | * exception at approximately 3/5 of this time. |
| 71 | * |
| 72 | * The formula to calculate this is given by: |
| 73 | * 2.5 * (2^(63-period+1)) / timebase_freq |
| 74 | * |
| 75 | * In order to simplify things, we assume that period is |
| 76 | * at least 1. This will still result in a very long timeout. |
| 77 | */ |
| 78 | static unsigned long long period_to_sec(unsigned int period) |
| 79 | { |
| 80 | unsigned long long tmp = 1ULL << (64 - period); |
| 81 | unsigned long tmp2 = ppc_tb_freq; |
| 82 | |
| 83 | /* tmp may be a very large number and we don't want to overflow, |
| 84 | * so divide the timebase freq instead of multiplying tmp |
| 85 | */ |
| 86 | tmp2 = tmp2 / 5 * 2; |
| 87 | |
| 88 | do_div(tmp, tmp2); |
| 89 | return tmp; |
| 90 | } |
| 91 | |
| 92 | /* |
| 93 | * This procedure will find the highest period which will give a timeout |
| 94 | * greater than the one required. e.g. for a bus speed of 66666666 and |
| 95 | * and a parameter of 2 secs, then this procedure will return a value of 38. |
| 96 | */ |
| 97 | static unsigned int sec_to_period(unsigned int secs) |
| 98 | { |
| 99 | unsigned int period; |
| 100 | for (period = 63; period > 0; period--) { |
| 101 | if (period_to_sec(period) >= secs) |
| 102 | return period; |
| 103 | } |
| 104 | return 0; |
| 105 | } |
| 106 | |
Guenter Roeck | 52e5cc4 | 2013-02-05 12:14:23 -0800 | [diff] [blame] | 107 | #define MAX_WDT_TIMEOUT period_to_sec(1) |
| 108 | |
| 109 | #else /* CONFIG_PPC_FSL_BOOK3E */ |
| 110 | |
| 111 | static unsigned long long period_to_sec(unsigned int period) |
| 112 | { |
| 113 | return period; |
| 114 | } |
| 115 | |
| 116 | static unsigned int sec_to_period(unsigned int secs) |
| 117 | { |
| 118 | return secs; |
| 119 | } |
| 120 | |
| 121 | #define MAX_WDT_TIMEOUT 3 /* from Kconfig */ |
| 122 | |
| 123 | #endif /* !CONFIG_PPC_FSL_BOOK3E */ |
| 124 | |
Randy Vinson | 6ae98ed | 2010-12-06 14:02:23 -0700 | [diff] [blame] | 125 | static void __booke_wdt_set(void *data) |
| 126 | { |
| 127 | u32 val; |
Tang Yuantian | d2deeba | 2014-05-08 10:04:26 +0800 | [diff] [blame] | 128 | struct watchdog_device *wdog = data; |
Randy Vinson | 6ae98ed | 2010-12-06 14:02:23 -0700 | [diff] [blame] | 129 | |
| 130 | val = mfspr(SPRN_TCR); |
| 131 | val &= ~WDTP_MASK; |
Tang Yuantian | d2deeba | 2014-05-08 10:04:26 +0800 | [diff] [blame] | 132 | val |= WDTP(sec_to_period(wdog->timeout)); |
Randy Vinson | 6ae98ed | 2010-12-06 14:02:23 -0700 | [diff] [blame] | 133 | |
| 134 | mtspr(SPRN_TCR, val); |
| 135 | } |
| 136 | |
Tang Yuantian | d2deeba | 2014-05-08 10:04:26 +0800 | [diff] [blame] | 137 | static void booke_wdt_set(void *data) |
Randy Vinson | 6ae98ed | 2010-12-06 14:02:23 -0700 | [diff] [blame] | 138 | { |
Tang Yuantian | d2deeba | 2014-05-08 10:04:26 +0800 | [diff] [blame] | 139 | on_each_cpu(__booke_wdt_set, data, 0); |
Randy Vinson | 6ae98ed | 2010-12-06 14:02:23 -0700 | [diff] [blame] | 140 | } |
| 141 | |
Chen Gong | f172ddc6 | 2008-04-29 16:42:05 +0800 | [diff] [blame] | 142 | static void __booke_wdt_ping(void *data) |
Stefan Roese | f31909c | 2007-02-07 09:45:55 +0100 | [diff] [blame] | 143 | { |
| 144 | mtspr(SPRN_TSR, TSR_ENW|TSR_WIS); |
| 145 | } |
| 146 | |
Guenter Roeck | 52e5cc4 | 2013-02-05 12:14:23 -0800 | [diff] [blame] | 147 | static int booke_wdt_ping(struct watchdog_device *wdog) |
Chen Gong | f172ddc6 | 2008-04-29 16:42:05 +0800 | [diff] [blame] | 148 | { |
Ingo Molnar | f6f88e9 | 2008-07-15 22:08:52 +0200 | [diff] [blame] | 149 | on_each_cpu(__booke_wdt_ping, NULL, 0); |
Guenter Roeck | 52e5cc4 | 2013-02-05 12:14:23 -0800 | [diff] [blame] | 150 | |
| 151 | return 0; |
Chen Gong | f172ddc6 | 2008-04-29 16:42:05 +0800 | [diff] [blame] | 152 | } |
| 153 | |
| 154 | static void __booke_wdt_enable(void *data) |
Kumar Gala | a2f40cc | 2005-09-03 15:55:33 -0700 | [diff] [blame] | 155 | { |
| 156 | u32 val; |
Tang Yuantian | d2deeba | 2014-05-08 10:04:26 +0800 | [diff] [blame] | 157 | struct watchdog_device *wdog = data; |
Kumar Gala | a2f40cc | 2005-09-03 15:55:33 -0700 | [diff] [blame] | 158 | |
Stefan Roese | f31909c | 2007-02-07 09:45:55 +0100 | [diff] [blame] | 159 | /* clear status before enabling watchdog */ |
Chen Gong | f172ddc6 | 2008-04-29 16:42:05 +0800 | [diff] [blame] | 160 | __booke_wdt_ping(NULL); |
Kumar Gala | a2f40cc | 2005-09-03 15:55:33 -0700 | [diff] [blame] | 161 | val = mfspr(SPRN_TCR); |
Matthias Fuchs | 0a0e9e0 | 2008-11-05 21:53:56 +0100 | [diff] [blame] | 162 | val &= ~WDTP_MASK; |
Tang Yuantian | d2deeba | 2014-05-08 10:04:26 +0800 | [diff] [blame] | 163 | val |= (TCR_WIE|TCR_WRC(WRC_CHIP)|WDTP(sec_to_period(wdog->timeout))); |
Kumar Gala | a2f40cc | 2005-09-03 15:55:33 -0700 | [diff] [blame] | 164 | |
| 165 | mtspr(SPRN_TCR, val); |
| 166 | } |
| 167 | |
Timur Tabi | fbdd714 | 2010-09-20 11:23:42 -0500 | [diff] [blame] | 168 | /** |
| 169 | * booke_wdt_disable - disable the watchdog on the given CPU |
| 170 | * |
| 171 | * This function is called on each CPU. It disables the watchdog on that CPU. |
| 172 | * |
| 173 | * TCR[WRC] cannot be changed once it has been set to non-zero, but we can |
| 174 | * effectively disable the watchdog by setting its period to the maximum value. |
| 175 | */ |
| 176 | static void __booke_wdt_disable(void *data) |
| 177 | { |
| 178 | u32 val; |
| 179 | |
| 180 | val = mfspr(SPRN_TCR); |
| 181 | val &= ~(TCR_WIE | WDTP_MASK); |
| 182 | mtspr(SPRN_TCR, val); |
| 183 | |
| 184 | /* clear status to make sure nothing is pending */ |
| 185 | __booke_wdt_ping(NULL); |
| 186 | |
| 187 | } |
| 188 | |
Guenter Roeck | 52e5cc4 | 2013-02-05 12:14:23 -0800 | [diff] [blame] | 189 | static int booke_wdt_start(struct watchdog_device *wdog) |
| 190 | { |
Tang Yuantian | d2deeba | 2014-05-08 10:04:26 +0800 | [diff] [blame] | 191 | on_each_cpu(__booke_wdt_enable, wdog, 0); |
| 192 | pr_debug("watchdog enabled (timeout = %u sec)\n", wdog->timeout); |
| 193 | |
Guenter Roeck | 52e5cc4 | 2013-02-05 12:14:23 -0800 | [diff] [blame] | 194 | return 0; |
| 195 | } |
| 196 | |
| 197 | static int booke_wdt_stop(struct watchdog_device *wdog) |
| 198 | { |
| 199 | on_each_cpu(__booke_wdt_disable, NULL, 0); |
Guenter Roeck | 52e5cc4 | 2013-02-05 12:14:23 -0800 | [diff] [blame] | 200 | pr_debug("watchdog disabled\n"); |
| 201 | |
| 202 | return 0; |
| 203 | } |
| 204 | |
| 205 | static int booke_wdt_set_timeout(struct watchdog_device *wdt_dev, |
| 206 | unsigned int timeout) |
| 207 | { |
| 208 | if (timeout > MAX_WDT_TIMEOUT) |
| 209 | return -EINVAL; |
Guenter Roeck | 52e5cc4 | 2013-02-05 12:14:23 -0800 | [diff] [blame] | 210 | wdt_dev->timeout = timeout; |
Tang Yuantian | d2deeba | 2014-05-08 10:04:26 +0800 | [diff] [blame] | 211 | booke_wdt_set(wdt_dev); |
Guenter Roeck | 52e5cc4 | 2013-02-05 12:14:23 -0800 | [diff] [blame] | 212 | |
| 213 | return 0; |
| 214 | } |
| 215 | |
| 216 | static struct watchdog_info booke_wdt_info = { |
Chen Gong | f172ddc6 | 2008-04-29 16:42:05 +0800 | [diff] [blame] | 217 | .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING, |
| 218 | .identity = "PowerPC Book-E Watchdog", |
Kumar Gala | a2f40cc | 2005-09-03 15:55:33 -0700 | [diff] [blame] | 219 | }; |
| 220 | |
Guenter Roeck | 52e5cc4 | 2013-02-05 12:14:23 -0800 | [diff] [blame] | 221 | static struct watchdog_ops booke_wdt_ops = { |
Chen Gong | f172ddc6 | 2008-04-29 16:42:05 +0800 | [diff] [blame] | 222 | .owner = THIS_MODULE, |
Guenter Roeck | 52e5cc4 | 2013-02-05 12:14:23 -0800 | [diff] [blame] | 223 | .start = booke_wdt_start, |
| 224 | .stop = booke_wdt_stop, |
| 225 | .ping = booke_wdt_ping, |
| 226 | .set_timeout = booke_wdt_set_timeout, |
Kumar Gala | a2f40cc | 2005-09-03 15:55:33 -0700 | [diff] [blame] | 227 | }; |
| 228 | |
Guenter Roeck | 52e5cc4 | 2013-02-05 12:14:23 -0800 | [diff] [blame] | 229 | static struct watchdog_device booke_wdt_dev = { |
| 230 | .info = &booke_wdt_info, |
| 231 | .ops = &booke_wdt_ops, |
| 232 | .min_timeout = 1, |
| 233 | .max_timeout = 0xFFFF |
Kumar Gala | a2f40cc | 2005-09-03 15:55:33 -0700 | [diff] [blame] | 234 | }; |
| 235 | |
| 236 | static void __exit booke_wdt_exit(void) |
| 237 | { |
Guenter Roeck | 52e5cc4 | 2013-02-05 12:14:23 -0800 | [diff] [blame] | 238 | watchdog_unregister_device(&booke_wdt_dev); |
Kumar Gala | a2f40cc | 2005-09-03 15:55:33 -0700 | [diff] [blame] | 239 | } |
| 240 | |
Kumar Gala | a2f40cc | 2005-09-03 15:55:33 -0700 | [diff] [blame] | 241 | static int __init booke_wdt_init(void) |
| 242 | { |
| 243 | int ret = 0; |
Guenter Roeck | 52e5cc4 | 2013-02-05 12:14:23 -0800 | [diff] [blame] | 244 | bool nowayout = WATCHDOG_NOWAYOUT; |
Kumar Gala | a2f40cc | 2005-09-03 15:55:33 -0700 | [diff] [blame] | 245 | |
Joe Perches | 27c766a | 2012-02-15 15:06:19 -0800 | [diff] [blame] | 246 | pr_info("powerpc book-e watchdog driver loaded\n"); |
Guenter Roeck | 52e5cc4 | 2013-02-05 12:14:23 -0800 | [diff] [blame] | 247 | booke_wdt_info.firmware_version = cur_cpu_spec->pvr_value; |
| 248 | booke_wdt_set_timeout(&booke_wdt_dev, |
Tang Yuantian | d2deeba | 2014-05-08 10:04:26 +0800 | [diff] [blame] | 249 | period_to_sec(booke_wdt_period)); |
Guenter Roeck | 52e5cc4 | 2013-02-05 12:14:23 -0800 | [diff] [blame] | 250 | watchdog_set_nowayout(&booke_wdt_dev, nowayout); |
| 251 | if (booke_wdt_enabled) |
Tang Yuantian | d2deeba | 2014-05-08 10:04:26 +0800 | [diff] [blame] | 252 | booke_wdt_start(&booke_wdt_dev); |
Kumar Gala | a2f40cc | 2005-09-03 15:55:33 -0700 | [diff] [blame] | 253 | |
Guenter Roeck | 52e5cc4 | 2013-02-05 12:14:23 -0800 | [diff] [blame] | 254 | ret = watchdog_register_device(&booke_wdt_dev); |
Kumar Gala | a2f40cc | 2005-09-03 15:55:33 -0700 | [diff] [blame] | 255 | |
| 256 | return ret; |
| 257 | } |
Timur Tabi | fbdd714 | 2010-09-20 11:23:42 -0500 | [diff] [blame] | 258 | |
| 259 | module_init(booke_wdt_init); |
| 260 | module_exit(booke_wdt_exit); |
| 261 | |
| 262 | MODULE_DESCRIPTION("PowerPC Book-E watchdog driver"); |
| 263 | MODULE_LICENSE("GPL"); |