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gerrit-public.fairphone.software / kernel / msm-4.9 / 0d03943c0b50ad47ec6bb157a5d02d6ba9da477e / . / drivers / staging / rtl8192u / r819xU_phy.h
blob: 66cbe3f9cafd9116e42ea7a47be0fc16637288f0 [file] [log] [blame]
Jerry Chuang8fc85982009-11-03 07:17:11 -0200[diff] [blame]1#ifndef _R819XU_PHY_H
2#define _R819XU_PHY_H
3
Xenia Ragiadakou2703d1b2013-06-25 02:28:59 +0300[diff] [blame]4/* Channel switch: The size of command tables for switch channel */
Jerry Chuang8fc85982009-11-03 07:17:11 -0200[diff] [blame]5#define MAX_PRECMD_CNT 16
6#define MAX_RFDEPENDCMD_CNT 16
7#define MAX_POSTCMD_CNT 16
8
Xenia Ragiadakou19e918f2013-06-25 02:28:58 +0300[diff] [blame]9typedef enum _SwChnlCmdID {
Jerry Chuang8fc85982009-11-03 07:17:11 -0200[diff] [blame]10 CmdID_End,
11 CmdID_SetTxPowerLevel,
12 CmdID_BBRegWrite10,
13 CmdID_WritePortUlong,
14 CmdID_WritePortUshort,
15 CmdID_WritePortUchar,
16 CmdID_RF_WriteReg,
Xenia Ragiadakou19e918f2013-06-25 02:28:58 +0300[diff] [blame]17} SwChnlCmdID;
Jerry Chuang8fc85982009-11-03 07:17:11 -0200[diff] [blame]18
Xenia Ragiadakou2703d1b2013-06-25 02:28:59 +0300[diff] [blame]19/* -----------------------Define structure---------------------- */
Jerry Chuang8fc85982009-11-03 07:17:11 -0200[diff] [blame]20/* 1. Switch channel related */
Xenia Ragiadakou19e918f2013-06-25 02:28:58 +0300[diff] [blame]21typedef struct _SwChnlCmd {
Jerry Chuang8fc85982009-11-03 07:17:11 -0200[diff] [blame]22 SwChnlCmdID CmdID;
Xenia Ragiadakou19e918f2013-06-25 02:28:58 +0300[diff] [blame]23 u32 Para1;
24 u32 Para2;
25 u32 msDelay;
Xenia Ragiadakou889cfe22013-10-10 10:43:55 +0300[diff] [blame]26} __packed SwChnlCmd;
Jerry Chuang8fc85982009-11-03 07:17:11 -0200[diff] [blame]27
28extern u32 rtl819XMACPHY_Array_PG[];
29extern u32 rtl819XPHY_REG_1T2RArray[];
30extern u32 rtl819XAGCTAB_Array[];
31extern u32 rtl819XRadioA_Array[];
32extern u32 rtl819XRadioB_Array[];
33extern u32 rtl819XRadioC_Array[];
34extern u32 rtl819XRadioD_Array[];
35
Xenia Ragiadakou19e918f2013-06-25 02:28:58 +0300[diff] [blame]36typedef enum _HW90_BLOCK {
Jerry Chuang8fc85982009-11-03 07:17:11 -0200[diff] [blame]37 HW90_BLOCK_MAC = 0,
38 HW90_BLOCK_PHY0 = 1,
39 HW90_BLOCK_PHY1 = 2,
40 HW90_BLOCK_RF = 3,
Xenia Ragiadakou2703d1b2013-06-25 02:28:59 +0300[diff] [blame]41 HW90_BLOCK_MAXIMUM = 4, /* Never use this */
Xenia Ragiadakou19e918f2013-06-25 02:28:58 +0300[diff] [blame]42} HW90_BLOCK_E, *PHW90_BLOCK_E;
Jerry Chuang8fc85982009-11-03 07:17:11 -0200[diff] [blame]43
Xenia Ragiadakou19e918f2013-06-25 02:28:58 +0300[diff] [blame]44typedef enum _RF90_RADIO_PATH {
Xenia Ragiadakou2703d1b2013-06-25 02:28:59 +0300[diff] [blame]45 RF90_PATH_A = 0, /* Radio Path A */
46 RF90_PATH_B = 1, /* Radio Path B */
47 RF90_PATH_C = 2, /* Radio Path C */
48 RF90_PATH_D = 3, /* Radio Path D */
49 RF90_PATH_MAX /* Max RF number 92 support */
Xenia Ragiadakou19e918f2013-06-25 02:28:58 +0300[diff] [blame]50} RF90_RADIO_PATH_E, *PRF90_RADIO_PATH_E;
Jerry Chuang8fc85982009-11-03 07:17:11 -0200[diff] [blame]51
52#define bMaskByte0 0xff
53#define bMaskByte1 0xff00
54#define bMaskByte2 0xff0000
55#define bMaskByte3 0xff000000
56#define bMaskHWord 0xffff0000
57#define bMaskLWord 0x0000ffff
58#define bMaskDWord 0xffffffff
59
Xenia Ragiadakou88d8fe22013-05-11 17:22:22 +0300[diff] [blame]60extern u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device *dev, u32 eRFPath);
Xenia Ragiadakou59f30ae2013-06-25 02:29:01 +0300[diff] [blame]61extern void rtl8192_setBBreg(struct net_device *dev, u32 reg_addr,
62 u32 bitmask, u32 data);
63extern u32 rtl8192_QueryBBReg(struct net_device *dev, u32 reg_addr,
64 u32 bitmask);
65extern void rtl8192_phy_SetRFReg(struct net_device *dev,
66 RF90_RADIO_PATH_E eRFPath, u32 reg_addr, u32 bitmask, u32 data);
67extern u32 rtl8192_phy_QueryRFReg(struct net_device *dev,
68 RF90_RADIO_PATH_E eRFPath, u32 reg_addr, u32 bitmask);
Xenia Ragiadakou88d8fe22013-05-11 17:22:22 +0300[diff] [blame]69extern void rtl8192_phy_configmac(struct net_device *dev);
70extern void rtl8192_phyConfigBB(struct net_device *dev, u8 ConfigType);
Xenia Ragiadakou59f30ae2013-06-25 02:29:01 +0300[diff] [blame]71extern u8 rtl8192_phy_checkBBAndRF(struct net_device *dev,
72 HW90_BLOCK_E CheckBlock, RF90_RADIO_PATH_E eRFPath);
Xenia Ragiadakou88d8fe22013-05-11 17:22:22 +0300[diff] [blame]73extern void rtl8192_BBConfig(struct net_device *dev);
74extern void rtl8192_phy_getTxPower(struct net_device *dev);
75extern void rtl8192_phy_setTxPower(struct net_device *dev, u8 channel);
76extern void rtl8192_phy_RFConfig(struct net_device *dev);
77extern void rtl8192_phy_updateInitGain(struct net_device *dev);
Xenia Ragiadakou59f30ae2013-06-25 02:29:01 +0300[diff] [blame]78extern u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device *dev,
79 RF90_RADIO_PATH_E eRFPath);
Jerry Chuang8fc85982009-11-03 07:17:11 -0200[diff] [blame]80
Xenia Ragiadakou88d8fe22013-05-11 17:22:22 +0300[diff] [blame]81extern u8 rtl8192_phy_SwChnl(struct net_device *dev, u8 channel);
Xenia Ragiadakou59f30ae2013-06-25 02:29:01 +0300[diff] [blame]82extern void rtl8192_SetBWMode(struct net_device *dev,
83 HT_CHANNEL_WIDTH bandwidth, HT_EXTCHNL_OFFSET offset);
Jerry Chuang8fc85982009-11-03 07:17:11 -0200[diff] [blame]84extern void rtl8192_SwChnl_WorkItem(struct net_device *dev);
85void rtl8192_SetBWModeWorkItem(struct net_device *dev);
Xenia Ragiadakou59f30ae2013-06-25 02:29:01 +0300[diff] [blame]86extern bool rtl8192_SetRFPowerState(struct net_device *dev,
87 RT_RF_POWER_STATE eRFPowerState);
Xenia Ragiadakou19e918f2013-06-25 02:28:58 +0300[diff] [blame]88extern void InitialGain819xUsb(struct net_device *dev, u8 Operation);
Jerry Chuang8fc85982009-11-03 07:17:11 -0200[diff] [blame]89
Jerry Chuang8fc85982009-11-03 07:17:11 -0200[diff] [blame]90extern void InitialGainOperateWorkItemCallBack(struct work_struct *work);
Jerry Chuang8fc85982009-11-03 07:17:11 -0200[diff] [blame]91
92#endif