Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Agere Systems Inc. |
| 3 | * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs |
| 4 | * |
| 5 | * Copyright © 2005 Agere Systems Inc. |
| 6 | * All rights reserved. |
| 7 | * http://www.agere.com |
| 8 | * |
| 9 | * Copyright (c) 2011 Mark Einon <mark.einon@gmail.com> |
| 10 | * |
| 11 | *------------------------------------------------------------------------------ |
| 12 | * |
| 13 | * SOFTWARE LICENSE |
| 14 | * |
| 15 | * This software is provided subject to the following terms and conditions, |
| 16 | * which you should read carefully before using the software. Using this |
| 17 | * software indicates your acceptance of these terms and conditions. If you do |
| 18 | * not agree with these terms and conditions, do not use the software. |
| 19 | * |
| 20 | * Copyright © 2005 Agere Systems Inc. |
| 21 | * All rights reserved. |
| 22 | * |
| 23 | * Redistribution and use in source or binary forms, with or without |
| 24 | * modifications, are permitted provided that the following conditions are met: |
| 25 | * |
| 26 | * . Redistributions of source code must retain the above copyright notice, this |
| 27 | * list of conditions and the following Disclaimer as comments in the code as |
| 28 | * well as in the documentation and/or other materials provided with the |
| 29 | * distribution. |
| 30 | * |
| 31 | * . Redistributions in binary form must reproduce the above copyright notice, |
| 32 | * this list of conditions and the following Disclaimer in the documentation |
| 33 | * and/or other materials provided with the distribution. |
| 34 | * |
| 35 | * . Neither the name of Agere Systems Inc. nor the names of the contributors |
| 36 | * may be used to endorse or promote products derived from this software |
| 37 | * without specific prior written permission. |
| 38 | * |
| 39 | * Disclaimer |
| 40 | * |
| 41 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, |
| 42 | * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF |
| 43 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY |
| 44 | * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN |
| 45 | * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY |
| 46 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 47 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 48 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 49 | * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT |
| 50 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT |
| 51 | * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH |
| 52 | * DAMAGE. |
| 53 | * |
| 54 | */ |
| 55 | |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 56 | #include <linux/pci.h> |
| 57 | #include <linux/init.h> |
| 58 | #include <linux/module.h> |
| 59 | #include <linux/types.h> |
| 60 | #include <linux/kernel.h> |
| 61 | |
| 62 | #include <linux/sched.h> |
| 63 | #include <linux/ptrace.h> |
| 64 | #include <linux/slab.h> |
| 65 | #include <linux/ctype.h> |
| 66 | #include <linux/string.h> |
| 67 | #include <linux/timer.h> |
| 68 | #include <linux/interrupt.h> |
| 69 | #include <linux/in.h> |
| 70 | #include <linux/delay.h> |
| 71 | #include <linux/bitops.h> |
| 72 | #include <linux/io.h> |
| 73 | #include <asm/system.h> |
| 74 | |
| 75 | #include <linux/netdevice.h> |
| 76 | #include <linux/etherdevice.h> |
| 77 | #include <linux/skbuff.h> |
| 78 | #include <linux/if_arp.h> |
| 79 | #include <linux/ioport.h> |
| 80 | #include <linux/crc32.h> |
| 81 | #include <linux/random.h> |
| 82 | #include <linux/phy.h> |
| 83 | |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 84 | #include "et131x.h" |
| 85 | |
| 86 | MODULE_AUTHOR("Victor Soriano <vjsoriano@agere.com>"); |
| 87 | MODULE_AUTHOR("Mark Einon <mark.einon@gmail.com>"); |
| 88 | MODULE_LICENSE("Dual BSD/GPL"); |
| 89 | MODULE_DESCRIPTION("10/100/1000 Base-T Ethernet Driver " |
| 90 | "for the ET1310 by Agere Systems"); |
| 91 | |
Mark Einon | bd156af | 2011-10-20 01:18:32 +0100 | [diff] [blame] | 92 | /* EEPROM defines */ |
| 93 | #define MAX_NUM_REGISTER_POLLS 1000 |
| 94 | #define MAX_NUM_WRITE_RETRIES 2 |
| 95 | |
| 96 | /* MAC defines */ |
| 97 | #define COUNTER_WRAP_16_BIT 0x10000 |
| 98 | #define COUNTER_WRAP_12_BIT 0x1000 |
| 99 | |
| 100 | /* PCI defines */ |
| 101 | #define INTERNAL_MEM_SIZE 0x400 /* 1024 of internal memory */ |
| 102 | #define INTERNAL_MEM_RX_OFFSET 0x1FF /* 50% Tx, 50% Rx */ |
| 103 | |
| 104 | /* ISR defines */ |
| 105 | /* |
| 106 | * For interrupts, normal running is: |
| 107 | * rxdma_xfr_done, phy_interrupt, mac_stat_interrupt, |
| 108 | * watchdog_interrupt & txdma_xfer_done |
| 109 | * |
| 110 | * In both cases, when flow control is enabled for either Tx or bi-direction, |
| 111 | * we additional enable rx_fbr0_low and rx_fbr1_low, so we know when the |
| 112 | * buffer rings are running low. |
| 113 | */ |
| 114 | #define INT_MASK_DISABLE 0xffffffff |
| 115 | |
| 116 | /* NOTE: Masking out MAC_STAT Interrupt for now... |
| 117 | * #define INT_MASK_ENABLE 0xfff6bf17 |
| 118 | * #define INT_MASK_ENABLE_NO_FLOW 0xfff6bfd7 |
| 119 | */ |
| 120 | #define INT_MASK_ENABLE 0xfffebf17 |
| 121 | #define INT_MASK_ENABLE_NO_FLOW 0xfffebfd7 |
| 122 | |
Mark Einon | 1c1c1b5 | 2011-10-20 01:18:36 +0100 | [diff] [blame] | 123 | /* General defines */ |
| 124 | /* Packet and header sizes */ |
| 125 | #define NIC_MIN_PACKET_SIZE 60 |
| 126 | |
| 127 | /* Multicast list size */ |
| 128 | #define NIC_MAX_MCAST_LIST 128 |
| 129 | |
| 130 | /* Supported Filters */ |
| 131 | #define ET131X_PACKET_TYPE_DIRECTED 0x0001 |
| 132 | #define ET131X_PACKET_TYPE_MULTICAST 0x0002 |
| 133 | #define ET131X_PACKET_TYPE_BROADCAST 0x0004 |
| 134 | #define ET131X_PACKET_TYPE_PROMISCUOUS 0x0008 |
| 135 | #define ET131X_PACKET_TYPE_ALL_MULTICAST 0x0010 |
| 136 | |
| 137 | /* Tx Timeout */ |
| 138 | #define ET131X_TX_TIMEOUT (1 * HZ) |
| 139 | #define NIC_SEND_HANG_THRESHOLD 0 |
| 140 | |
| 141 | /* MP_TCB flags */ |
| 142 | #define fMP_DEST_MULTI 0x00000001 |
| 143 | #define fMP_DEST_BROAD 0x00000002 |
| 144 | |
| 145 | /* MP_ADAPTER flags */ |
| 146 | #define fMP_ADAPTER_RECV_LOOKASIDE 0x00000004 |
| 147 | #define fMP_ADAPTER_INTERRUPT_IN_USE 0x00000008 |
| 148 | #define fMP_ADAPTER_SECONDARY 0x00000010 |
| 149 | |
| 150 | /* MP_SHARED flags */ |
| 151 | #define fMP_ADAPTER_SHUTDOWN 0x00100000 |
| 152 | #define fMP_ADAPTER_LOWER_POWER 0x00200000 |
| 153 | |
| 154 | #define fMP_ADAPTER_NON_RECOVER_ERROR 0x00800000 |
| 155 | #define fMP_ADAPTER_RESET_IN_PROGRESS 0x01000000 |
| 156 | #define fMP_ADAPTER_NO_CABLE 0x02000000 |
| 157 | #define fMP_ADAPTER_HARDWARE_ERROR 0x04000000 |
| 158 | #define fMP_ADAPTER_REMOVE_IN_PROGRESS 0x08000000 |
| 159 | #define fMP_ADAPTER_HALT_IN_PROGRESS 0x10000000 |
| 160 | |
| 161 | #define fMP_ADAPTER_FAIL_SEND_MASK 0x3ff00000 |
| 162 | #define fMP_ADAPTER_NOT_READY_MASK 0x3ff00000 |
| 163 | |
| 164 | /* Some offsets in PCI config space that are actually used. */ |
| 165 | #define ET1310_PCI_MAX_PYLD 0x4C |
| 166 | #define ET1310_PCI_MAC_ADDRESS 0xA4 |
| 167 | #define ET1310_PCI_EEPROM_STATUS 0xB2 |
| 168 | #define ET1310_PCI_ACK_NACK 0xC0 |
| 169 | #define ET1310_PCI_REPLAY 0xC2 |
| 170 | #define ET1310_PCI_L0L1LATENCY 0xCF |
| 171 | |
| 172 | /* PCI Vendor/Product IDs */ |
| 173 | #define ET131X_PCI_VENDOR_ID 0x11C1 /* Agere Systems */ |
| 174 | #define ET131X_PCI_DEVICE_ID_GIG 0xED00 /* ET1310 1000 Base-T 8 */ |
| 175 | #define ET131X_PCI_DEVICE_ID_FAST 0xED01 /* ET1310 100 Base-T */ |
| 176 | |
| 177 | /* Define order of magnitude converter */ |
| 178 | #define NANO_IN_A_MICRO 1000 |
| 179 | |
| 180 | #define PARM_RX_NUM_BUFS_DEF 4 |
| 181 | #define PARM_RX_TIME_INT_DEF 10 |
| 182 | #define PARM_RX_MEM_END_DEF 0x2bc |
| 183 | #define PARM_TX_TIME_INT_DEF 40 |
| 184 | #define PARM_TX_NUM_BUFS_DEF 4 |
| 185 | #define PARM_DMA_CACHE_DEF 0 |
| 186 | |
Mark Einon | 562550b | 2011-10-20 01:18:37 +0100 | [diff] [blame] | 187 | /* RX defines */ |
Mark Einon | 6abafc1 | 2011-10-20 01:18:41 +0100 | [diff] [blame] | 188 | #define USE_FBR0 1 |
Mark Einon | 562550b | 2011-10-20 01:18:37 +0100 | [diff] [blame] | 189 | |
| 190 | #define FBR_CHUNKS 32 |
| 191 | |
| 192 | #define MAX_DESC_PER_RING_RX 1024 |
| 193 | |
| 194 | /* number of RFDs - default and min */ |
| 195 | #ifdef USE_FBR0 |
| 196 | #define RFD_LOW_WATER_MARK 40 |
Mark Einon | 562550b | 2011-10-20 01:18:37 +0100 | [diff] [blame] | 197 | #define NIC_DEFAULT_NUM_RFD 1024 |
Mark Einon | 6abafc1 | 2011-10-20 01:18:41 +0100 | [diff] [blame] | 198 | #define NUM_FBRS 2 |
Mark Einon | 562550b | 2011-10-20 01:18:37 +0100 | [diff] [blame] | 199 | #else |
| 200 | #define RFD_LOW_WATER_MARK 20 |
Mark Einon | 562550b | 2011-10-20 01:18:37 +0100 | [diff] [blame] | 201 | #define NIC_DEFAULT_NUM_RFD 256 |
Mark Einon | 6abafc1 | 2011-10-20 01:18:41 +0100 | [diff] [blame] | 202 | #define NUM_FBRS 1 |
Mark Einon | 562550b | 2011-10-20 01:18:37 +0100 | [diff] [blame] | 203 | #endif |
| 204 | |
Mark Einon | 6abafc1 | 2011-10-20 01:18:41 +0100 | [diff] [blame] | 205 | #define NIC_MIN_NUM_RFD 64 |
| 206 | |
Mark Einon | 562550b | 2011-10-20 01:18:37 +0100 | [diff] [blame] | 207 | #define NUM_PACKETS_HANDLED 256 |
| 208 | |
| 209 | #define ALCATEL_BAD_STATUS 0xe47f0000 |
| 210 | #define ALCATEL_MULTICAST_PKT 0x01000000 |
| 211 | #define ALCATEL_BROADCAST_PKT 0x02000000 |
| 212 | |
| 213 | /* typedefs for Free Buffer Descriptors */ |
| 214 | struct fbr_desc { |
| 215 | u32 addr_lo; |
| 216 | u32 addr_hi; |
| 217 | u32 word2; /* Bits 10-31 reserved, 0-9 descriptor */ |
| 218 | }; |
| 219 | |
| 220 | /* Packet Status Ring Descriptors |
| 221 | * |
| 222 | * Word 0: |
| 223 | * |
| 224 | * top 16 bits are from the Alcatel Status Word as enumerated in |
| 225 | * PE-MCXMAC Data Sheet IPD DS54 0210-1 (also IPD-DS80 0205-2) |
| 226 | * |
| 227 | * 0: hp hash pass |
| 228 | * 1: ipa IP checksum assist |
| 229 | * 2: ipp IP checksum pass |
| 230 | * 3: tcpa TCP checksum assist |
| 231 | * 4: tcpp TCP checksum pass |
| 232 | * 5: wol WOL Event |
| 233 | * 6: rxmac_error RXMAC Error Indicator |
| 234 | * 7: drop Drop packet |
| 235 | * 8: ft Frame Truncated |
| 236 | * 9: jp Jumbo Packet |
| 237 | * 10: vp VLAN Packet |
| 238 | * 11-15: unused |
| 239 | * 16: asw_prev_pkt_dropped e.g. IFG too small on previous |
| 240 | * 17: asw_RX_DV_event short receive event detected |
| 241 | * 18: asw_false_carrier_event bad carrier since last good packet |
| 242 | * 19: asw_code_err one or more nibbles signalled as errors |
| 243 | * 20: asw_CRC_err CRC error |
| 244 | * 21: asw_len_chk_err frame length field incorrect |
| 245 | * 22: asw_too_long frame length > 1518 bytes |
| 246 | * 23: asw_OK valid CRC + no code error |
| 247 | * 24: asw_multicast has a multicast address |
| 248 | * 25: asw_broadcast has a broadcast address |
| 249 | * 26: asw_dribble_nibble spurious bits after EOP |
| 250 | * 27: asw_control_frame is a control frame |
| 251 | * 28: asw_pause_frame is a pause frame |
| 252 | * 29: asw_unsupported_op unsupported OP code |
| 253 | * 30: asw_VLAN_tag VLAN tag detected |
| 254 | * 31: asw_long_evt Rx long event |
| 255 | * |
| 256 | * Word 1: |
| 257 | * 0-15: length length in bytes |
| 258 | * 16-25: bi Buffer Index |
| 259 | * 26-27: ri Ring Index |
| 260 | * 28-31: reserved |
| 261 | */ |
| 262 | |
| 263 | struct pkt_stat_desc { |
| 264 | u32 word0; |
| 265 | u32 word1; |
| 266 | }; |
| 267 | |
| 268 | /* Typedefs for the RX DMA status word */ |
| 269 | |
| 270 | /* |
| 271 | * rx status word 0 holds part of the status bits of the Rx DMA engine |
| 272 | * that get copied out to memory by the ET-1310. Word 0 is a 32 bit word |
| 273 | * which contains the Free Buffer ring 0 and 1 available offset. |
| 274 | * |
| 275 | * bit 0-9 FBR1 offset |
| 276 | * bit 10 Wrap flag for FBR1 |
| 277 | * bit 16-25 FBR0 offset |
| 278 | * bit 26 Wrap flag for FBR0 |
| 279 | */ |
| 280 | |
| 281 | /* |
| 282 | * RXSTAT_WORD1_t structure holds part of the status bits of the Rx DMA engine |
| 283 | * that get copied out to memory by the ET-1310. Word 3 is a 32 bit word |
| 284 | * which contains the Packet Status Ring available offset. |
| 285 | * |
| 286 | * bit 0-15 reserved |
| 287 | * bit 16-27 PSRoffset |
| 288 | * bit 28 PSRwrap |
| 289 | * bit 29-31 unused |
| 290 | */ |
| 291 | |
| 292 | /* |
| 293 | * struct rx_status_block is a structure representing the status of the Rx |
| 294 | * DMA engine it sits in free memory, and is pointed to by 0x101c / 0x1020 |
| 295 | */ |
| 296 | struct rx_status_block { |
| 297 | u32 word0; |
| 298 | u32 word1; |
| 299 | }; |
| 300 | |
| 301 | /* |
Mark Einon | 6abafc1 | 2011-10-20 01:18:41 +0100 | [diff] [blame] | 302 | * Structure for look-up table holding free buffer ring pointers, addresses |
| 303 | * and state. |
Mark Einon | 562550b | 2011-10-20 01:18:37 +0100 | [diff] [blame] | 304 | */ |
| 305 | struct fbr_lookup { |
Mark Einon | 6abafc1 | 2011-10-20 01:18:41 +0100 | [diff] [blame] | 306 | void *virt[MAX_DESC_PER_RING_RX]; |
| 307 | void *buffer1[MAX_DESC_PER_RING_RX]; |
| 308 | void *buffer2[MAX_DESC_PER_RING_RX]; |
| 309 | u32 bus_high[MAX_DESC_PER_RING_RX]; |
| 310 | u32 bus_low[MAX_DESC_PER_RING_RX]; |
| 311 | void *ring_virtaddr; |
| 312 | dma_addr_t ring_physaddr; |
| 313 | void *mem_virtaddrs[MAX_DESC_PER_RING_RX / FBR_CHUNKS]; |
| 314 | dma_addr_t mem_physaddrs[MAX_DESC_PER_RING_RX / FBR_CHUNKS]; |
| 315 | uint64_t real_physaddr; |
| 316 | uint64_t offset; |
| 317 | u32 local_full; |
| 318 | u32 num_entries; |
| 319 | u32 buffsize; |
Mark Einon | 562550b | 2011-10-20 01:18:37 +0100 | [diff] [blame] | 320 | }; |
| 321 | |
| 322 | /* |
| 323 | * struct rx_ring is the sructure representing the adaptor's local |
| 324 | * reference(s) to the rings |
Mark Einon | e592a9b | 2011-10-20 01:18:42 +0100 | [diff] [blame] | 325 | * |
| 326 | ****************************************************************************** |
| 327 | * IMPORTANT NOTE :- fbr_lookup *fbr[NUM_FBRS] uses index 0 to refer to FBR1 |
| 328 | * and index 1 to refer to FRB0 |
| 329 | ****************************************************************************** |
Mark Einon | 562550b | 2011-10-20 01:18:37 +0100 | [diff] [blame] | 330 | */ |
| 331 | struct rx_ring { |
Mark Einon | 6abafc1 | 2011-10-20 01:18:41 +0100 | [diff] [blame] | 332 | struct fbr_lookup *fbr[NUM_FBRS]; |
Mark Einon | 562550b | 2011-10-20 01:18:37 +0100 | [diff] [blame] | 333 | void *ps_ring_virtaddr; |
| 334 | dma_addr_t ps_ring_physaddr; |
| 335 | u32 local_psr_full; |
| 336 | u32 psr_num_entries; |
| 337 | |
| 338 | struct rx_status_block *rx_status_block; |
| 339 | dma_addr_t rx_status_bus; |
| 340 | |
| 341 | struct list_head recv_buff_pool; |
| 342 | |
| 343 | /* RECV */ |
| 344 | struct list_head recv_list; |
| 345 | u32 num_ready_recv; |
| 346 | |
| 347 | u32 num_rfd; |
| 348 | |
| 349 | bool unfinished_receives; |
| 350 | |
| 351 | struct list_head recv_packet_pool; |
| 352 | |
| 353 | /* lookaside lists */ |
| 354 | struct kmem_cache *recv_lookaside; |
| 355 | }; |
| 356 | |
Mark Einon | 17ec9ff | 2011-10-20 01:18:38 +0100 | [diff] [blame] | 357 | /* TX defines */ |
| 358 | /* |
| 359 | * word 2 of the control bits in the Tx Descriptor ring for the ET-1310 |
| 360 | * |
| 361 | * 0-15: length of packet |
| 362 | * 16-27: VLAN tag |
| 363 | * 28: VLAN CFI |
| 364 | * 29-31: VLAN priority |
| 365 | * |
| 366 | * word 3 of the control bits in the Tx Descriptor ring for the ET-1310 |
| 367 | * |
| 368 | * 0: last packet in the sequence |
| 369 | * 1: first packet in the sequence |
| 370 | * 2: interrupt the processor when this pkt sent |
| 371 | * 3: Control word - no packet data |
| 372 | * 4: Issue half-duplex backpressure : XON/XOFF |
| 373 | * 5: send pause frame |
| 374 | * 6: Tx frame has error |
| 375 | * 7: append CRC |
| 376 | * 8: MAC override |
| 377 | * 9: pad packet |
| 378 | * 10: Packet is a Huge packet |
| 379 | * 11: append VLAN tag |
| 380 | * 12: IP checksum assist |
| 381 | * 13: TCP checksum assist |
| 382 | * 14: UDP checksum assist |
| 383 | */ |
| 384 | |
| 385 | /* struct tx_desc represents each descriptor on the ring */ |
| 386 | struct tx_desc { |
| 387 | u32 addr_hi; |
| 388 | u32 addr_lo; |
| 389 | u32 len_vlan; /* control words how to xmit the */ |
| 390 | u32 flags; /* data (detailed above) */ |
| 391 | }; |
| 392 | |
| 393 | /* |
| 394 | * The status of the Tx DMA engine it sits in free memory, and is pointed to |
| 395 | * by 0x101c / 0x1020. This is a DMA10 type |
| 396 | */ |
| 397 | |
| 398 | /* TCB (Transmit Control Block: Host Side) */ |
| 399 | struct tcb { |
| 400 | struct tcb *next; /* Next entry in ring */ |
| 401 | u32 flags; /* Our flags for the packet */ |
| 402 | u32 count; /* Used to spot stuck/lost packets */ |
| 403 | u32 stale; /* Used to spot stuck/lost packets */ |
| 404 | struct sk_buff *skb; /* Network skb we are tied to */ |
| 405 | u32 index; /* Ring indexes */ |
| 406 | u32 index_start; |
| 407 | }; |
| 408 | |
| 409 | /* Structure representing our local reference(s) to the ring */ |
| 410 | struct tx_ring { |
| 411 | /* TCB (Transmit Control Block) memory and lists */ |
| 412 | struct tcb *tcb_ring; |
| 413 | |
| 414 | /* List of TCBs that are ready to be used */ |
| 415 | struct tcb *tcb_qhead; |
| 416 | struct tcb *tcb_qtail; |
| 417 | |
| 418 | /* list of TCBs that are currently being sent. NOTE that access to all |
| 419 | * three of these (including used) are controlled via the |
| 420 | * TCBSendQLock. This lock should be secured prior to incementing / |
| 421 | * decrementing used, or any queue manipulation on send_head / |
| 422 | * tail |
| 423 | */ |
| 424 | struct tcb *send_head; |
| 425 | struct tcb *send_tail; |
| 426 | int used; |
| 427 | |
| 428 | /* The actual descriptor ring */ |
| 429 | struct tx_desc *tx_desc_ring; |
| 430 | dma_addr_t tx_desc_ring_pa; |
| 431 | |
| 432 | /* send_idx indicates where we last wrote to in the descriptor ring. */ |
| 433 | u32 send_idx; |
| 434 | |
| 435 | /* The location of the write-back status block */ |
| 436 | u32 *tx_status; |
| 437 | dma_addr_t tx_status_pa; |
| 438 | |
| 439 | /* Packets since the last IRQ: used for interrupt coalescing */ |
| 440 | int since_irq; |
| 441 | }; |
| 442 | |
Mark Einon | fd0651a | 2011-10-20 01:18:35 +0100 | [diff] [blame] | 443 | /* ADAPTER defines */ |
| 444 | /* |
| 445 | * Do not change these values: if changed, then change also in respective |
| 446 | * TXdma and Rxdma engines |
| 447 | */ |
| 448 | #define NUM_DESC_PER_RING_TX 512 /* TX Do not change these values */ |
| 449 | #define NUM_TCB 64 |
| 450 | |
| 451 | /* |
| 452 | * These values are all superseded by registry entries to facilitate tuning. |
| 453 | * Once the desired performance has been achieved, the optimal registry values |
| 454 | * should be re-populated to these #defines: |
| 455 | */ |
| 456 | #define NUM_TRAFFIC_CLASSES 1 |
| 457 | |
| 458 | #define TX_ERROR_PERIOD 1000 |
| 459 | |
| 460 | #define LO_MARK_PERCENT_FOR_PSR 15 |
| 461 | #define LO_MARK_PERCENT_FOR_RX 15 |
| 462 | |
| 463 | /* RFD (Receive Frame Descriptor) */ |
| 464 | struct rfd { |
| 465 | struct list_head list_node; |
| 466 | struct sk_buff *skb; |
| 467 | u32 len; /* total size of receive frame */ |
| 468 | u16 bufferindex; |
| 469 | u8 ringindex; |
| 470 | }; |
| 471 | |
| 472 | /* Flow Control */ |
| 473 | #define FLOW_BOTH 0 |
| 474 | #define FLOW_TXONLY 1 |
| 475 | #define FLOW_RXONLY 2 |
| 476 | #define FLOW_NONE 3 |
| 477 | |
| 478 | /* Struct to define some device statistics */ |
| 479 | struct ce_stats { |
| 480 | /* MIB II variables |
| 481 | * |
| 482 | * NOTE: atomic_t types are only guaranteed to store 24-bits; if we |
| 483 | * MUST have 32, then we'll need another way to perform atomic |
| 484 | * operations |
| 485 | */ |
| 486 | u32 unicast_pkts_rcvd; |
| 487 | atomic_t unicast_pkts_xmtd; |
| 488 | u32 multicast_pkts_rcvd; |
| 489 | atomic_t multicast_pkts_xmtd; |
| 490 | u32 broadcast_pkts_rcvd; |
| 491 | atomic_t broadcast_pkts_xmtd; |
| 492 | u32 rcvd_pkts_dropped; |
| 493 | |
| 494 | /* Tx Statistics. */ |
| 495 | u32 tx_underflows; |
| 496 | |
| 497 | u32 tx_collisions; |
| 498 | u32 tx_excessive_collisions; |
| 499 | u32 tx_first_collisions; |
| 500 | u32 tx_late_collisions; |
| 501 | u32 tx_max_pkt_errs; |
| 502 | u32 tx_deferred; |
| 503 | |
| 504 | /* Rx Statistics. */ |
| 505 | u32 rx_overflows; |
| 506 | |
| 507 | u32 rx_length_errs; |
| 508 | u32 rx_align_errs; |
| 509 | u32 rx_crc_errs; |
| 510 | u32 rx_code_violations; |
| 511 | u32 rx_other_errs; |
| 512 | |
| 513 | u32 synchronous_iterations; |
| 514 | u32 interrupt_status; |
| 515 | }; |
| 516 | |
| 517 | /* The private adapter structure */ |
| 518 | struct et131x_adapter { |
| 519 | struct net_device *netdev; |
| 520 | struct pci_dev *pdev; |
| 521 | struct mii_bus *mii_bus; |
| 522 | struct phy_device *phydev; |
| 523 | struct work_struct task; |
| 524 | |
| 525 | /* Flags that indicate current state of the adapter */ |
| 526 | u32 flags; |
| 527 | |
| 528 | /* local link state, to determine if a state change has occurred */ |
| 529 | int link; |
| 530 | |
| 531 | /* Configuration */ |
| 532 | u8 rom_addr[ETH_ALEN]; |
| 533 | u8 addr[ETH_ALEN]; |
| 534 | bool has_eeprom; |
| 535 | u8 eeprom_data[2]; |
| 536 | |
| 537 | /* Spinlocks */ |
| 538 | spinlock_t lock; |
| 539 | |
| 540 | spinlock_t tcb_send_qlock; |
| 541 | spinlock_t tcb_ready_qlock; |
| 542 | spinlock_t send_hw_lock; |
| 543 | |
| 544 | spinlock_t rcv_lock; |
| 545 | spinlock_t rcv_pend_lock; |
| 546 | spinlock_t fbr_lock; |
| 547 | |
| 548 | spinlock_t phy_lock; |
| 549 | |
| 550 | /* Packet Filter and look ahead size */ |
| 551 | u32 packet_filter; |
| 552 | |
| 553 | /* multicast list */ |
| 554 | u32 multicast_addr_count; |
| 555 | u8 multicast_list[NIC_MAX_MCAST_LIST][ETH_ALEN]; |
| 556 | |
| 557 | /* Pointer to the device's PCI register space */ |
| 558 | struct address_map __iomem *regs; |
| 559 | |
| 560 | /* Registry parameters */ |
| 561 | u8 wanted_flow; /* Flow we want for 802.3x flow control */ |
| 562 | u32 registry_jumbo_packet; /* Max supported ethernet packet size */ |
| 563 | |
| 564 | /* Derived from the registry: */ |
| 565 | u8 flowcontrol; /* flow control validated by the far-end */ |
| 566 | |
| 567 | /* Minimize init-time */ |
| 568 | struct timer_list error_timer; |
| 569 | |
| 570 | /* variable putting the phy into coma mode when boot up with no cable |
| 571 | * plugged in after 5 seconds |
| 572 | */ |
| 573 | u8 boot_coma; |
| 574 | |
| 575 | /* Next two used to save power information at power down. This |
| 576 | * information will be used during power up to set up parts of Power |
| 577 | * Management in JAGCore |
| 578 | */ |
| 579 | u16 pdown_speed; |
| 580 | u8 pdown_duplex; |
| 581 | |
| 582 | /* Tx Memory Variables */ |
| 583 | struct tx_ring tx_ring; |
| 584 | |
| 585 | /* Rx Memory Variables */ |
| 586 | struct rx_ring rx_ring; |
| 587 | |
| 588 | /* Stats */ |
| 589 | struct ce_stats stats; |
| 590 | |
| 591 | struct net_device_stats net_stats; |
| 592 | }; |
| 593 | |
Mark Einon | 2d0c64a | 2011-10-20 01:18:31 +0100 | [diff] [blame] | 594 | void et131x_error_timer_handler(unsigned long data); |
| 595 | void et131x_enable_interrupts(struct et131x_adapter *adapter); |
| 596 | void et131x_disable_interrupts(struct et131x_adapter *adapter); |
| 597 | void et131x_align_allocated_memory(struct et131x_adapter *adapter, |
| 598 | u64 *phys_addr, |
| 599 | u64 *offset, u64 mask); |
| 600 | void et131x_adapter_setup(struct et131x_adapter *adapter); |
| 601 | void et131x_soft_reset(struct et131x_adapter *adapter); |
| 602 | void et131x_isr_handler(struct work_struct *work); |
| 603 | void et1310_setup_device_for_multicast(struct et131x_adapter *adapter); |
| 604 | void et1310_setup_device_for_unicast(struct et131x_adapter *adapter); |
| 605 | void et131x_up(struct net_device *netdev); |
| 606 | void et131x_down(struct net_device *netdev); |
| 607 | struct net_device *et131x_device_alloc(void); |
| 608 | void et131x_enable_txrx(struct net_device *netdev); |
| 609 | void et131x_disable_txrx(struct net_device *netdev); |
| 610 | int et1310_in_phy_coma(struct et131x_adapter *adapter); |
| 611 | void et1310_phy_access_mii_bit(struct et131x_adapter *adapter, |
| 612 | u16 action, |
| 613 | u16 regnum, u16 bitnum, u8 *value); |
| 614 | int et131x_phy_mii_read(struct et131x_adapter *adapter, u8 addr, |
| 615 | u8 reg, u16 *value); |
| 616 | int32_t et131x_mii_write(struct et131x_adapter *adapter, |
| 617 | u8 reg, u16 value); |
| 618 | void et131x_rx_dma_memory_free(struct et131x_adapter *adapter); |
| 619 | void et131x_rx_dma_disable(struct et131x_adapter *adapter); |
| 620 | void et131x_rx_dma_enable(struct et131x_adapter *adapter); |
| 621 | void et131x_reset_recv(struct et131x_adapter *adapter); |
| 622 | void et131x_init_send(struct et131x_adapter *adapter); |
| 623 | void et131x_tx_dma_enable(struct et131x_adapter *adapter); |
| 624 | |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 625 | /* EEPROM functions */ |
| 626 | |
| 627 | static int eeprom_wait_ready(struct pci_dev *pdev, u32 *status) |
| 628 | { |
| 629 | u32 reg; |
| 630 | int i; |
| 631 | |
| 632 | /* |
| 633 | * 1. Check LBCIF Status Register for bits 6 & 3:2 all equal to 0 and |
| 634 | * bits 7,1:0 both equal to 1, at least once after reset. |
| 635 | * Subsequent operations need only to check that bits 1:0 are equal |
| 636 | * to 1 prior to starting a single byte read/write |
| 637 | */ |
| 638 | |
| 639 | for (i = 0; i < MAX_NUM_REGISTER_POLLS; i++) { |
| 640 | /* Read registers grouped in DWORD1 */ |
| 641 | if (pci_read_config_dword(pdev, LBCIF_DWORD1_GROUP, ®)) |
| 642 | return -EIO; |
| 643 | |
| 644 | /* I2C idle and Phy Queue Avail both true */ |
| 645 | if ((reg & 0x3000) == 0x3000) { |
| 646 | if (status) |
| 647 | *status = reg; |
| 648 | return reg & 0xFF; |
| 649 | } |
| 650 | } |
| 651 | return -ETIMEDOUT; |
| 652 | } |
| 653 | |
| 654 | |
| 655 | /** |
| 656 | * eeprom_write - Write a byte to the ET1310's EEPROM |
| 657 | * @adapter: pointer to our private adapter structure |
| 658 | * @addr: the address to write |
| 659 | * @data: the value to write |
| 660 | * |
| 661 | * Returns 1 for a successful write. |
| 662 | */ |
| 663 | static int eeprom_write(struct et131x_adapter *adapter, u32 addr, u8 data) |
| 664 | { |
| 665 | struct pci_dev *pdev = adapter->pdev; |
| 666 | int index = 0; |
| 667 | int retries; |
| 668 | int err = 0; |
| 669 | int i2c_wack = 0; |
| 670 | int writeok = 0; |
| 671 | u32 status; |
| 672 | u32 val = 0; |
| 673 | |
| 674 | /* |
| 675 | * For an EEPROM, an I2C single byte write is defined as a START |
| 676 | * condition followed by the device address, EEPROM address, one byte |
| 677 | * of data and a STOP condition. The STOP condition will trigger the |
| 678 | * EEPROM's internally timed write cycle to the nonvolatile memory. |
| 679 | * All inputs are disabled during this write cycle and the EEPROM will |
| 680 | * not respond to any access until the internal write is complete. |
| 681 | */ |
| 682 | |
| 683 | err = eeprom_wait_ready(pdev, NULL); |
| 684 | if (err) |
| 685 | return err; |
| 686 | |
| 687 | /* |
| 688 | * 2. Write to the LBCIF Control Register: bit 7=1, bit 6=1, bit 3=0, |
| 689 | * and bits 1:0 both =0. Bit 5 should be set according to the |
| 690 | * type of EEPROM being accessed (1=two byte addressing, 0=one |
| 691 | * byte addressing). |
| 692 | */ |
| 693 | if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER, |
| 694 | LBCIF_CONTROL_LBCIF_ENABLE | LBCIF_CONTROL_I2C_WRITE)) |
| 695 | return -EIO; |
| 696 | |
| 697 | i2c_wack = 1; |
| 698 | |
| 699 | /* Prepare EEPROM address for Step 3 */ |
| 700 | |
| 701 | for (retries = 0; retries < MAX_NUM_WRITE_RETRIES; retries++) { |
| 702 | /* Write the address to the LBCIF Address Register */ |
| 703 | if (pci_write_config_dword(pdev, LBCIF_ADDRESS_REGISTER, addr)) |
| 704 | break; |
| 705 | /* |
| 706 | * Write the data to the LBCIF Data Register (the I2C write |
| 707 | * will begin). |
| 708 | */ |
| 709 | if (pci_write_config_byte(pdev, LBCIF_DATA_REGISTER, data)) |
| 710 | break; |
| 711 | /* |
| 712 | * Monitor bit 1:0 of the LBCIF Status Register. When bits |
| 713 | * 1:0 are both equal to 1, the I2C write has completed and the |
| 714 | * internal write cycle of the EEPROM is about to start. |
| 715 | * (bits 1:0 = 01 is a legal state while waiting from both |
| 716 | * equal to 1, but bits 1:0 = 10 is invalid and implies that |
| 717 | * something is broken). |
| 718 | */ |
| 719 | err = eeprom_wait_ready(pdev, &status); |
| 720 | if (err < 0) |
| 721 | return 0; |
| 722 | |
| 723 | /* |
| 724 | * Check bit 3 of the LBCIF Status Register. If equal to 1, |
| 725 | * an error has occurred.Don't break here if we are revision |
| 726 | * 1, this is so we do a blind write for load bug. |
| 727 | */ |
| 728 | if ((status & LBCIF_STATUS_GENERAL_ERROR) |
| 729 | && adapter->pdev->revision == 0) |
| 730 | break; |
| 731 | |
| 732 | /* |
| 733 | * Check bit 2 of the LBCIF Status Register. If equal to 1 an |
| 734 | * ACK error has occurred on the address phase of the write. |
| 735 | * This could be due to an actual hardware failure or the |
| 736 | * EEPROM may still be in its internal write cycle from a |
| 737 | * previous write. This write operation was ignored and must be |
| 738 | *repeated later. |
| 739 | */ |
| 740 | if (status & LBCIF_STATUS_ACK_ERROR) { |
| 741 | /* |
| 742 | * This could be due to an actual hardware failure |
| 743 | * or the EEPROM may still be in its internal write |
| 744 | * cycle from a previous write. This write operation |
| 745 | * was ignored and must be repeated later. |
| 746 | */ |
| 747 | udelay(10); |
| 748 | continue; |
| 749 | } |
| 750 | |
| 751 | writeok = 1; |
| 752 | break; |
| 753 | } |
| 754 | |
| 755 | /* |
| 756 | * Set bit 6 of the LBCIF Control Register = 0. |
| 757 | */ |
| 758 | udelay(10); |
| 759 | |
| 760 | while (i2c_wack) { |
| 761 | if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER, |
| 762 | LBCIF_CONTROL_LBCIF_ENABLE)) |
| 763 | writeok = 0; |
| 764 | |
| 765 | /* Do read until internal ACK_ERROR goes away meaning write |
| 766 | * completed |
| 767 | */ |
| 768 | do { |
| 769 | pci_write_config_dword(pdev, |
| 770 | LBCIF_ADDRESS_REGISTER, |
| 771 | addr); |
| 772 | do { |
| 773 | pci_read_config_dword(pdev, |
| 774 | LBCIF_DATA_REGISTER, &val); |
| 775 | } while ((val & 0x00010000) == 0); |
| 776 | } while (val & 0x00040000); |
| 777 | |
| 778 | if ((val & 0xFF00) != 0xC000 || index == 10000) |
| 779 | break; |
| 780 | index++; |
| 781 | } |
| 782 | return writeok ? 0 : -EIO; |
| 783 | } |
| 784 | |
| 785 | /** |
| 786 | * eeprom_read - Read a byte from the ET1310's EEPROM |
| 787 | * @adapter: pointer to our private adapter structure |
| 788 | * @addr: the address from which to read |
| 789 | * @pdata: a pointer to a byte in which to store the value of the read |
| 790 | * @eeprom_id: the ID of the EEPROM |
| 791 | * @addrmode: how the EEPROM is to be accessed |
| 792 | * |
| 793 | * Returns 1 for a successful read |
| 794 | */ |
| 795 | static int eeprom_read(struct et131x_adapter *adapter, u32 addr, u8 *pdata) |
| 796 | { |
| 797 | struct pci_dev *pdev = adapter->pdev; |
| 798 | int err; |
| 799 | u32 status; |
| 800 | |
| 801 | /* |
| 802 | * A single byte read is similar to the single byte write, with the |
| 803 | * exception of the data flow: |
| 804 | */ |
| 805 | |
| 806 | err = eeprom_wait_ready(pdev, NULL); |
| 807 | if (err) |
| 808 | return err; |
| 809 | /* |
| 810 | * Write to the LBCIF Control Register: bit 7=1, bit 6=0, bit 3=0, |
| 811 | * and bits 1:0 both =0. Bit 5 should be set according to the type |
| 812 | * of EEPROM being accessed (1=two byte addressing, 0=one byte |
| 813 | * addressing). |
| 814 | */ |
| 815 | if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER, |
| 816 | LBCIF_CONTROL_LBCIF_ENABLE)) |
| 817 | return -EIO; |
| 818 | /* |
| 819 | * Write the address to the LBCIF Address Register (I2C read will |
| 820 | * begin). |
| 821 | */ |
| 822 | if (pci_write_config_dword(pdev, LBCIF_ADDRESS_REGISTER, addr)) |
| 823 | return -EIO; |
| 824 | /* |
| 825 | * Monitor bit 0 of the LBCIF Status Register. When = 1, I2C read |
| 826 | * is complete. (if bit 1 =1 and bit 0 stays = 0, a hardware failure |
| 827 | * has occurred). |
| 828 | */ |
| 829 | err = eeprom_wait_ready(pdev, &status); |
| 830 | if (err < 0) |
| 831 | return err; |
| 832 | /* |
| 833 | * Regardless of error status, read data byte from LBCIF Data |
| 834 | * Register. |
| 835 | */ |
| 836 | *pdata = err; |
| 837 | /* |
| 838 | * Check bit 2 of the LBCIF Status Register. If = 1, |
| 839 | * then an error has occurred. |
| 840 | */ |
| 841 | return (status & LBCIF_STATUS_ACK_ERROR) ? -EIO : 0; |
| 842 | } |
| 843 | |
| 844 | int et131x_init_eeprom(struct et131x_adapter *adapter) |
| 845 | { |
| 846 | struct pci_dev *pdev = adapter->pdev; |
| 847 | u8 eestatus; |
| 848 | |
| 849 | /* We first need to check the EEPROM Status code located at offset |
| 850 | * 0xB2 of config space |
| 851 | */ |
| 852 | pci_read_config_byte(pdev, ET1310_PCI_EEPROM_STATUS, |
| 853 | &eestatus); |
| 854 | |
| 855 | /* THIS IS A WORKAROUND: |
| 856 | * I need to call this function twice to get my card in a |
| 857 | * LG M1 Express Dual running. I tried also a msleep before this |
| 858 | * function, because I thougth there could be some time condidions |
| 859 | * but it didn't work. Call the whole function twice also work. |
| 860 | */ |
| 861 | if (pci_read_config_byte(pdev, ET1310_PCI_EEPROM_STATUS, &eestatus)) { |
| 862 | dev_err(&pdev->dev, |
| 863 | "Could not read PCI config space for EEPROM Status\n"); |
| 864 | return -EIO; |
| 865 | } |
| 866 | |
| 867 | /* Determine if the error(s) we care about are present. If they are |
| 868 | * present we need to fail. |
| 869 | */ |
| 870 | if (eestatus & 0x4C) { |
| 871 | int write_failed = 0; |
| 872 | if (pdev->revision == 0x01) { |
| 873 | int i; |
| 874 | static const u8 eedata[4] = { 0xFE, 0x13, 0x10, 0xFF }; |
| 875 | |
| 876 | /* Re-write the first 4 bytes if we have an eeprom |
| 877 | * present and the revision id is 1, this fixes the |
| 878 | * corruption seen with 1310 B Silicon |
| 879 | */ |
| 880 | for (i = 0; i < 3; i++) |
| 881 | if (eeprom_write(adapter, i, eedata[i]) < 0) |
| 882 | write_failed = 1; |
| 883 | } |
| 884 | if (pdev->revision != 0x01 || write_failed) { |
| 885 | dev_err(&pdev->dev, |
| 886 | "Fatal EEPROM Status Error - 0x%04x\n", eestatus); |
| 887 | |
| 888 | /* This error could mean that there was an error |
| 889 | * reading the eeprom or that the eeprom doesn't exist. |
| 890 | * We will treat each case the same and not try to |
| 891 | * gather additional information that normally would |
| 892 | * come from the eeprom, like MAC Address |
| 893 | */ |
| 894 | adapter->has_eeprom = 0; |
| 895 | return -EIO; |
| 896 | } |
| 897 | } |
| 898 | adapter->has_eeprom = 1; |
| 899 | |
| 900 | /* Read the EEPROM for information regarding LED behavior. Refer to |
| 901 | * ET1310_phy.c, et131x_xcvr_init(), for its use. |
| 902 | */ |
| 903 | eeprom_read(adapter, 0x70, &adapter->eeprom_data[0]); |
| 904 | eeprom_read(adapter, 0x71, &adapter->eeprom_data[1]); |
| 905 | |
| 906 | if (adapter->eeprom_data[0] != 0xcd) |
| 907 | /* Disable all optional features */ |
| 908 | adapter->eeprom_data[1] = 0x00; |
| 909 | |
| 910 | return 0; |
| 911 | } |
| 912 | |
| 913 | /* MAC functions */ |
| 914 | |
| 915 | /** |
| 916 | * et1310_config_mac_regs1 - Initialize the first part of MAC regs |
| 917 | * @adapter: pointer to our adapter structure |
| 918 | */ |
| 919 | void et1310_config_mac_regs1(struct et131x_adapter *adapter) |
| 920 | { |
| 921 | struct mac_regs __iomem *macregs = &adapter->regs->mac; |
| 922 | u32 station1; |
| 923 | u32 station2; |
| 924 | u32 ipg; |
| 925 | |
| 926 | /* First we need to reset everything. Write to MAC configuration |
| 927 | * register 1 to perform reset. |
| 928 | */ |
| 929 | writel(0xC00F0000, ¯egs->cfg1); |
| 930 | |
| 931 | /* Next lets configure the MAC Inter-packet gap register */ |
| 932 | ipg = 0x38005860; /* IPG1 0x38 IPG2 0x58 B2B 0x60 */ |
| 933 | ipg |= 0x50 << 8; /* ifg enforce 0x50 */ |
| 934 | writel(ipg, ¯egs->ipg); |
| 935 | |
| 936 | /* Next lets configure the MAC Half Duplex register */ |
| 937 | /* BEB trunc 0xA, Ex Defer, Rexmit 0xF Coll 0x37 */ |
| 938 | writel(0x00A1F037, ¯egs->hfdp); |
| 939 | |
| 940 | /* Next lets configure the MAC Interface Control register */ |
| 941 | writel(0, ¯egs->if_ctrl); |
| 942 | |
| 943 | /* Let's move on to setting up the mii management configuration */ |
| 944 | writel(0x07, ¯egs->mii_mgmt_cfg); /* Clock reset 0x7 */ |
| 945 | |
| 946 | /* Next lets configure the MAC Station Address register. These |
| 947 | * values are read from the EEPROM during initialization and stored |
| 948 | * in the adapter structure. We write what is stored in the adapter |
| 949 | * structure to the MAC Station Address registers high and low. This |
| 950 | * station address is used for generating and checking pause control |
| 951 | * packets. |
| 952 | */ |
| 953 | station2 = (adapter->addr[1] << ET_MAC_STATION_ADDR2_OC2_SHIFT) | |
| 954 | (adapter->addr[0] << ET_MAC_STATION_ADDR2_OC1_SHIFT); |
| 955 | station1 = (adapter->addr[5] << ET_MAC_STATION_ADDR1_OC6_SHIFT) | |
| 956 | (adapter->addr[4] << ET_MAC_STATION_ADDR1_OC5_SHIFT) | |
| 957 | (adapter->addr[3] << ET_MAC_STATION_ADDR1_OC4_SHIFT) | |
| 958 | adapter->addr[2]; |
| 959 | writel(station1, ¯egs->station_addr_1); |
| 960 | writel(station2, ¯egs->station_addr_2); |
| 961 | |
| 962 | /* Max ethernet packet in bytes that will passed by the mac without |
| 963 | * being truncated. Allow the MAC to pass 4 more than our max packet |
| 964 | * size. This is 4 for the Ethernet CRC. |
| 965 | * |
| 966 | * Packets larger than (registry_jumbo_packet) that do not contain a |
| 967 | * VLAN ID will be dropped by the Rx function. |
| 968 | */ |
| 969 | writel(adapter->registry_jumbo_packet + 4, ¯egs->max_fm_len); |
| 970 | |
| 971 | /* clear out MAC config reset */ |
| 972 | writel(0, ¯egs->cfg1); |
| 973 | } |
| 974 | |
| 975 | /** |
| 976 | * et1310_config_mac_regs2 - Initialize the second part of MAC regs |
| 977 | * @adapter: pointer to our adapter structure |
| 978 | */ |
| 979 | void et1310_config_mac_regs2(struct et131x_adapter *adapter) |
| 980 | { |
| 981 | int32_t delay = 0; |
| 982 | struct mac_regs __iomem *mac = &adapter->regs->mac; |
| 983 | struct phy_device *phydev = adapter->phydev; |
| 984 | u32 cfg1; |
| 985 | u32 cfg2; |
| 986 | u32 ifctrl; |
| 987 | u32 ctl; |
| 988 | |
| 989 | ctl = readl(&adapter->regs->txmac.ctl); |
| 990 | cfg1 = readl(&mac->cfg1); |
| 991 | cfg2 = readl(&mac->cfg2); |
| 992 | ifctrl = readl(&mac->if_ctrl); |
| 993 | |
| 994 | /* Set up the if mode bits */ |
| 995 | cfg2 &= ~0x300; |
| 996 | if (phydev && phydev->speed == SPEED_1000) { |
| 997 | cfg2 |= 0x200; |
| 998 | /* Phy mode bit */ |
| 999 | ifctrl &= ~(1 << 24); |
| 1000 | } else { |
| 1001 | cfg2 |= 0x100; |
| 1002 | ifctrl |= (1 << 24); |
| 1003 | } |
| 1004 | |
| 1005 | /* We need to enable Rx/Tx */ |
| 1006 | cfg1 |= CFG1_RX_ENABLE | CFG1_TX_ENABLE | CFG1_TX_FLOW; |
| 1007 | /* Initialize loop back to off */ |
| 1008 | cfg1 &= ~(CFG1_LOOPBACK | CFG1_RX_FLOW); |
| 1009 | if (adapter->flowcontrol == FLOW_RXONLY || |
| 1010 | adapter->flowcontrol == FLOW_BOTH) |
| 1011 | cfg1 |= CFG1_RX_FLOW; |
| 1012 | writel(cfg1, &mac->cfg1); |
| 1013 | |
| 1014 | /* Now we need to initialize the MAC Configuration 2 register */ |
| 1015 | /* preamble 7, check length, huge frame off, pad crc, crc enable |
| 1016 | full duplex off */ |
| 1017 | cfg2 |= 0x7016; |
| 1018 | cfg2 &= ~0x0021; |
| 1019 | |
| 1020 | /* Turn on duplex if needed */ |
| 1021 | if (phydev && phydev->duplex == DUPLEX_FULL) |
| 1022 | cfg2 |= 0x01; |
| 1023 | |
| 1024 | ifctrl &= ~(1 << 26); |
| 1025 | if (phydev && phydev->duplex == DUPLEX_HALF) |
| 1026 | ifctrl |= (1<<26); /* Enable ghd */ |
| 1027 | |
| 1028 | writel(ifctrl, &mac->if_ctrl); |
| 1029 | writel(cfg2, &mac->cfg2); |
| 1030 | |
| 1031 | do { |
| 1032 | udelay(10); |
| 1033 | delay++; |
| 1034 | cfg1 = readl(&mac->cfg1); |
| 1035 | } while ((cfg1 & CFG1_WAIT) != CFG1_WAIT && delay < 100); |
| 1036 | |
| 1037 | if (delay == 100) { |
| 1038 | dev_warn(&adapter->pdev->dev, |
| 1039 | "Syncd bits did not respond correctly cfg1 word 0x%08x\n", |
| 1040 | cfg1); |
| 1041 | } |
| 1042 | |
| 1043 | /* Enable txmac */ |
| 1044 | ctl |= 0x09; /* TX mac enable, FC disable */ |
| 1045 | writel(ctl, &adapter->regs->txmac.ctl); |
| 1046 | |
| 1047 | /* Ready to start the RXDMA/TXDMA engine */ |
| 1048 | if (adapter->flags & fMP_ADAPTER_LOWER_POWER) { |
| 1049 | et131x_rx_dma_enable(adapter); |
| 1050 | et131x_tx_dma_enable(adapter); |
| 1051 | } |
| 1052 | } |
| 1053 | |
| 1054 | void et1310_config_rxmac_regs(struct et131x_adapter *adapter) |
| 1055 | { |
| 1056 | struct rxmac_regs __iomem *rxmac = &adapter->regs->rxmac; |
| 1057 | struct phy_device *phydev = adapter->phydev; |
| 1058 | u32 sa_lo; |
| 1059 | u32 sa_hi = 0; |
| 1060 | u32 pf_ctrl = 0; |
| 1061 | |
| 1062 | /* Disable the MAC while it is being configured (also disable WOL) */ |
| 1063 | writel(0x8, &rxmac->ctrl); |
| 1064 | |
| 1065 | /* Initialize WOL to disabled. */ |
| 1066 | writel(0, &rxmac->crc0); |
| 1067 | writel(0, &rxmac->crc12); |
| 1068 | writel(0, &rxmac->crc34); |
| 1069 | |
| 1070 | /* We need to set the WOL mask0 - mask4 next. We initialize it to |
| 1071 | * its default Values of 0x00000000 because there are not WOL masks |
| 1072 | * as of this time. |
| 1073 | */ |
| 1074 | writel(0, &rxmac->mask0_word0); |
| 1075 | writel(0, &rxmac->mask0_word1); |
| 1076 | writel(0, &rxmac->mask0_word2); |
| 1077 | writel(0, &rxmac->mask0_word3); |
| 1078 | |
| 1079 | writel(0, &rxmac->mask1_word0); |
| 1080 | writel(0, &rxmac->mask1_word1); |
| 1081 | writel(0, &rxmac->mask1_word2); |
| 1082 | writel(0, &rxmac->mask1_word3); |
| 1083 | |
| 1084 | writel(0, &rxmac->mask2_word0); |
| 1085 | writel(0, &rxmac->mask2_word1); |
| 1086 | writel(0, &rxmac->mask2_word2); |
| 1087 | writel(0, &rxmac->mask2_word3); |
| 1088 | |
| 1089 | writel(0, &rxmac->mask3_word0); |
| 1090 | writel(0, &rxmac->mask3_word1); |
| 1091 | writel(0, &rxmac->mask3_word2); |
| 1092 | writel(0, &rxmac->mask3_word3); |
| 1093 | |
| 1094 | writel(0, &rxmac->mask4_word0); |
| 1095 | writel(0, &rxmac->mask4_word1); |
| 1096 | writel(0, &rxmac->mask4_word2); |
| 1097 | writel(0, &rxmac->mask4_word3); |
| 1098 | |
| 1099 | /* Lets setup the WOL Source Address */ |
| 1100 | sa_lo = (adapter->addr[2] << ET_WOL_LO_SA3_SHIFT) | |
| 1101 | (adapter->addr[3] << ET_WOL_LO_SA4_SHIFT) | |
| 1102 | (adapter->addr[4] << ET_WOL_LO_SA5_SHIFT) | |
| 1103 | adapter->addr[5]; |
| 1104 | writel(sa_lo, &rxmac->sa_lo); |
| 1105 | |
| 1106 | sa_hi = (u32) (adapter->addr[0] << ET_WOL_HI_SA1_SHIFT) | |
| 1107 | adapter->addr[1]; |
| 1108 | writel(sa_hi, &rxmac->sa_hi); |
| 1109 | |
| 1110 | /* Disable all Packet Filtering */ |
| 1111 | writel(0, &rxmac->pf_ctrl); |
| 1112 | |
| 1113 | /* Let's initialize the Unicast Packet filtering address */ |
| 1114 | if (adapter->packet_filter & ET131X_PACKET_TYPE_DIRECTED) { |
| 1115 | et1310_setup_device_for_unicast(adapter); |
| 1116 | pf_ctrl |= 4; /* Unicast filter */ |
| 1117 | } else { |
| 1118 | writel(0, &rxmac->uni_pf_addr1); |
| 1119 | writel(0, &rxmac->uni_pf_addr2); |
| 1120 | writel(0, &rxmac->uni_pf_addr3); |
| 1121 | } |
| 1122 | |
| 1123 | /* Let's initialize the Multicast hash */ |
| 1124 | if (!(adapter->packet_filter & ET131X_PACKET_TYPE_ALL_MULTICAST)) { |
| 1125 | pf_ctrl |= 2; /* Multicast filter */ |
| 1126 | et1310_setup_device_for_multicast(adapter); |
| 1127 | } |
| 1128 | |
| 1129 | /* Runt packet filtering. Didn't work in version A silicon. */ |
| 1130 | pf_ctrl |= (NIC_MIN_PACKET_SIZE + 4) << 16; |
| 1131 | pf_ctrl |= 8; /* Fragment filter */ |
| 1132 | |
| 1133 | if (adapter->registry_jumbo_packet > 8192) |
| 1134 | /* In order to transmit jumbo packets greater than 8k, the |
| 1135 | * FIFO between RxMAC and RxDMA needs to be reduced in size |
| 1136 | * to (16k - Jumbo packet size). In order to implement this, |
| 1137 | * we must use "cut through" mode in the RxMAC, which chops |
| 1138 | * packets down into segments which are (max_size * 16). In |
| 1139 | * this case we selected 256 bytes, since this is the size of |
| 1140 | * the PCI-Express TLP's that the 1310 uses. |
| 1141 | * |
| 1142 | * seg_en on, fc_en off, size 0x10 |
| 1143 | */ |
| 1144 | writel(0x41, &rxmac->mcif_ctrl_max_seg); |
| 1145 | else |
| 1146 | writel(0, &rxmac->mcif_ctrl_max_seg); |
| 1147 | |
| 1148 | /* Initialize the MCIF water marks */ |
| 1149 | writel(0, &rxmac->mcif_water_mark); |
| 1150 | |
| 1151 | /* Initialize the MIF control */ |
| 1152 | writel(0, &rxmac->mif_ctrl); |
| 1153 | |
| 1154 | /* Initialize the Space Available Register */ |
| 1155 | writel(0, &rxmac->space_avail); |
| 1156 | |
| 1157 | /* Initialize the the mif_ctrl register |
| 1158 | * bit 3: Receive code error. One or more nibbles were signaled as |
| 1159 | * errors during the reception of the packet. Clear this |
| 1160 | * bit in Gigabit, set it in 100Mbit. This was derived |
| 1161 | * experimentally at UNH. |
| 1162 | * bit 4: Receive CRC error. The packet's CRC did not match the |
| 1163 | * internally generated CRC. |
| 1164 | * bit 5: Receive length check error. Indicates that frame length |
| 1165 | * field value in the packet does not match the actual data |
| 1166 | * byte length and is not a type field. |
| 1167 | * bit 16: Receive frame truncated. |
| 1168 | * bit 17: Drop packet enable |
| 1169 | */ |
| 1170 | if (phydev && phydev->speed == SPEED_100) |
| 1171 | writel(0x30038, &rxmac->mif_ctrl); |
| 1172 | else |
| 1173 | writel(0x30030, &rxmac->mif_ctrl); |
| 1174 | |
| 1175 | /* Finally we initialize RxMac to be enabled & WOL disabled. Packet |
| 1176 | * filter is always enabled since it is where the runt packets are |
| 1177 | * supposed to be dropped. For version A silicon, runt packet |
| 1178 | * dropping doesn't work, so it is disabled in the pf_ctrl register, |
| 1179 | * but we still leave the packet filter on. |
| 1180 | */ |
| 1181 | writel(pf_ctrl, &rxmac->pf_ctrl); |
| 1182 | writel(0x9, &rxmac->ctrl); |
| 1183 | } |
| 1184 | |
| 1185 | void et1310_config_txmac_regs(struct et131x_adapter *adapter) |
| 1186 | { |
| 1187 | struct txmac_regs __iomem *txmac = &adapter->regs->txmac; |
| 1188 | |
| 1189 | /* We need to update the Control Frame Parameters |
| 1190 | * cfpt - control frame pause timer set to 64 (0x40) |
| 1191 | * cfep - control frame extended pause timer set to 0x0 |
| 1192 | */ |
| 1193 | if (adapter->flowcontrol == FLOW_NONE) |
| 1194 | writel(0, &txmac->cf_param); |
| 1195 | else |
| 1196 | writel(0x40, &txmac->cf_param); |
| 1197 | } |
| 1198 | |
| 1199 | void et1310_config_macstat_regs(struct et131x_adapter *adapter) |
| 1200 | { |
| 1201 | struct macstat_regs __iomem *macstat = |
| 1202 | &adapter->regs->macstat; |
| 1203 | |
| 1204 | /* Next we need to initialize all the macstat registers to zero on |
| 1205 | * the device. |
| 1206 | */ |
| 1207 | writel(0, &macstat->txrx_0_64_byte_frames); |
| 1208 | writel(0, &macstat->txrx_65_127_byte_frames); |
| 1209 | writel(0, &macstat->txrx_128_255_byte_frames); |
| 1210 | writel(0, &macstat->txrx_256_511_byte_frames); |
| 1211 | writel(0, &macstat->txrx_512_1023_byte_frames); |
| 1212 | writel(0, &macstat->txrx_1024_1518_byte_frames); |
| 1213 | writel(0, &macstat->txrx_1519_1522_gvln_frames); |
| 1214 | |
| 1215 | writel(0, &macstat->rx_bytes); |
| 1216 | writel(0, &macstat->rx_packets); |
| 1217 | writel(0, &macstat->rx_fcs_errs); |
| 1218 | writel(0, &macstat->rx_multicast_packets); |
| 1219 | writel(0, &macstat->rx_broadcast_packets); |
| 1220 | writel(0, &macstat->rx_control_frames); |
| 1221 | writel(0, &macstat->rx_pause_frames); |
| 1222 | writel(0, &macstat->rx_unknown_opcodes); |
| 1223 | writel(0, &macstat->rx_align_errs); |
| 1224 | writel(0, &macstat->rx_frame_len_errs); |
| 1225 | writel(0, &macstat->rx_code_errs); |
| 1226 | writel(0, &macstat->rx_carrier_sense_errs); |
| 1227 | writel(0, &macstat->rx_undersize_packets); |
| 1228 | writel(0, &macstat->rx_oversize_packets); |
| 1229 | writel(0, &macstat->rx_fragment_packets); |
| 1230 | writel(0, &macstat->rx_jabbers); |
| 1231 | writel(0, &macstat->rx_drops); |
| 1232 | |
| 1233 | writel(0, &macstat->tx_bytes); |
| 1234 | writel(0, &macstat->tx_packets); |
| 1235 | writel(0, &macstat->tx_multicast_packets); |
| 1236 | writel(0, &macstat->tx_broadcast_packets); |
| 1237 | writel(0, &macstat->tx_pause_frames); |
| 1238 | writel(0, &macstat->tx_deferred); |
| 1239 | writel(0, &macstat->tx_excessive_deferred); |
| 1240 | writel(0, &macstat->tx_single_collisions); |
| 1241 | writel(0, &macstat->tx_multiple_collisions); |
| 1242 | writel(0, &macstat->tx_late_collisions); |
| 1243 | writel(0, &macstat->tx_excessive_collisions); |
| 1244 | writel(0, &macstat->tx_total_collisions); |
| 1245 | writel(0, &macstat->tx_pause_honored_frames); |
| 1246 | writel(0, &macstat->tx_drops); |
| 1247 | writel(0, &macstat->tx_jabbers); |
| 1248 | writel(0, &macstat->tx_fcs_errs); |
| 1249 | writel(0, &macstat->tx_control_frames); |
| 1250 | writel(0, &macstat->tx_oversize_frames); |
| 1251 | writel(0, &macstat->tx_undersize_frames); |
| 1252 | writel(0, &macstat->tx_fragments); |
| 1253 | writel(0, &macstat->carry_reg1); |
| 1254 | writel(0, &macstat->carry_reg2); |
| 1255 | |
| 1256 | /* Unmask any counters that we want to track the overflow of. |
| 1257 | * Initially this will be all counters. It may become clear later |
| 1258 | * that we do not need to track all counters. |
| 1259 | */ |
| 1260 | writel(0xFFFFBE32, &macstat->carry_reg1_mask); |
| 1261 | writel(0xFFFE7E8B, &macstat->carry_reg2_mask); |
| 1262 | } |
| 1263 | |
| 1264 | void et1310_config_flow_control(struct et131x_adapter *adapter) |
| 1265 | { |
| 1266 | struct phy_device *phydev = adapter->phydev; |
| 1267 | |
| 1268 | if (phydev->duplex == DUPLEX_HALF) { |
| 1269 | adapter->flowcontrol = FLOW_NONE; |
| 1270 | } else { |
| 1271 | char remote_pause, remote_async_pause; |
| 1272 | |
| 1273 | et1310_phy_access_mii_bit(adapter, |
| 1274 | TRUEPHY_BIT_READ, 5, 10, &remote_pause); |
| 1275 | et1310_phy_access_mii_bit(adapter, |
| 1276 | TRUEPHY_BIT_READ, 5, 11, |
| 1277 | &remote_async_pause); |
| 1278 | |
| 1279 | if ((remote_pause == TRUEPHY_BIT_SET) && |
| 1280 | (remote_async_pause == TRUEPHY_BIT_SET)) { |
| 1281 | adapter->flowcontrol = adapter->wanted_flow; |
| 1282 | } else if ((remote_pause == TRUEPHY_BIT_SET) && |
| 1283 | (remote_async_pause == TRUEPHY_BIT_CLEAR)) { |
| 1284 | if (adapter->wanted_flow == FLOW_BOTH) |
| 1285 | adapter->flowcontrol = FLOW_BOTH; |
| 1286 | else |
| 1287 | adapter->flowcontrol = FLOW_NONE; |
| 1288 | } else if ((remote_pause == TRUEPHY_BIT_CLEAR) && |
| 1289 | (remote_async_pause == TRUEPHY_BIT_CLEAR)) { |
| 1290 | adapter->flowcontrol = FLOW_NONE; |
| 1291 | } else {/* if (remote_pause == TRUEPHY_CLEAR_BIT && |
| 1292 | remote_async_pause == TRUEPHY_SET_BIT) */ |
| 1293 | if (adapter->wanted_flow == FLOW_BOTH) |
| 1294 | adapter->flowcontrol = FLOW_RXONLY; |
| 1295 | else |
| 1296 | adapter->flowcontrol = FLOW_NONE; |
| 1297 | } |
| 1298 | } |
| 1299 | } |
| 1300 | |
| 1301 | /** |
| 1302 | * et1310_update_macstat_host_counters - Update the local copy of the statistics |
| 1303 | * @adapter: pointer to the adapter structure |
| 1304 | */ |
| 1305 | void et1310_update_macstat_host_counters(struct et131x_adapter *adapter) |
| 1306 | { |
| 1307 | struct ce_stats *stats = &adapter->stats; |
| 1308 | struct macstat_regs __iomem *macstat = |
| 1309 | &adapter->regs->macstat; |
| 1310 | |
| 1311 | stats->tx_collisions += readl(&macstat->tx_total_collisions); |
| 1312 | stats->tx_first_collisions += readl(&macstat->tx_single_collisions); |
| 1313 | stats->tx_deferred += readl(&macstat->tx_deferred); |
| 1314 | stats->tx_excessive_collisions += |
| 1315 | readl(&macstat->tx_multiple_collisions); |
| 1316 | stats->tx_late_collisions += readl(&macstat->tx_late_collisions); |
| 1317 | stats->tx_underflows += readl(&macstat->tx_undersize_frames); |
| 1318 | stats->tx_max_pkt_errs += readl(&macstat->tx_oversize_frames); |
| 1319 | |
| 1320 | stats->rx_align_errs += readl(&macstat->rx_align_errs); |
| 1321 | stats->rx_crc_errs += readl(&macstat->rx_code_errs); |
| 1322 | stats->rcvd_pkts_dropped += readl(&macstat->rx_drops); |
| 1323 | stats->rx_overflows += readl(&macstat->rx_oversize_packets); |
| 1324 | stats->rx_code_violations += readl(&macstat->rx_fcs_errs); |
| 1325 | stats->rx_length_errs += readl(&macstat->rx_frame_len_errs); |
| 1326 | stats->rx_other_errs += readl(&macstat->rx_fragment_packets); |
| 1327 | } |
| 1328 | |
| 1329 | /** |
| 1330 | * et1310_handle_macstat_interrupt |
| 1331 | * @adapter: pointer to the adapter structure |
| 1332 | * |
| 1333 | * One of the MACSTAT counters has wrapped. Update the local copy of |
| 1334 | * the statistics held in the adapter structure, checking the "wrap" |
| 1335 | * bit for each counter. |
| 1336 | */ |
| 1337 | void et1310_handle_macstat_interrupt(struct et131x_adapter *adapter) |
| 1338 | { |
| 1339 | u32 carry_reg1; |
| 1340 | u32 carry_reg2; |
| 1341 | |
| 1342 | /* Read the interrupt bits from the register(s). These are Clear On |
| 1343 | * Write. |
| 1344 | */ |
| 1345 | carry_reg1 = readl(&adapter->regs->macstat.carry_reg1); |
| 1346 | carry_reg2 = readl(&adapter->regs->macstat.carry_reg2); |
| 1347 | |
| 1348 | writel(carry_reg1, &adapter->regs->macstat.carry_reg1); |
| 1349 | writel(carry_reg2, &adapter->regs->macstat.carry_reg2); |
| 1350 | |
| 1351 | /* We need to do update the host copy of all the MAC_STAT counters. |
| 1352 | * For each counter, check it's overflow bit. If the overflow bit is |
| 1353 | * set, then increment the host version of the count by one complete |
| 1354 | * revolution of the counter. This routine is called when the counter |
| 1355 | * block indicates that one of the counters has wrapped. |
| 1356 | */ |
| 1357 | if (carry_reg1 & (1 << 14)) |
| 1358 | adapter->stats.rx_code_violations += COUNTER_WRAP_16_BIT; |
| 1359 | if (carry_reg1 & (1 << 8)) |
| 1360 | adapter->stats.rx_align_errs += COUNTER_WRAP_12_BIT; |
| 1361 | if (carry_reg1 & (1 << 7)) |
| 1362 | adapter->stats.rx_length_errs += COUNTER_WRAP_16_BIT; |
| 1363 | if (carry_reg1 & (1 << 2)) |
| 1364 | adapter->stats.rx_other_errs += COUNTER_WRAP_16_BIT; |
| 1365 | if (carry_reg1 & (1 << 6)) |
| 1366 | adapter->stats.rx_crc_errs += COUNTER_WRAP_16_BIT; |
| 1367 | if (carry_reg1 & (1 << 3)) |
| 1368 | adapter->stats.rx_overflows += COUNTER_WRAP_16_BIT; |
| 1369 | if (carry_reg1 & (1 << 0)) |
| 1370 | adapter->stats.rcvd_pkts_dropped += COUNTER_WRAP_16_BIT; |
| 1371 | if (carry_reg2 & (1 << 16)) |
| 1372 | adapter->stats.tx_max_pkt_errs += COUNTER_WRAP_12_BIT; |
| 1373 | if (carry_reg2 & (1 << 15)) |
| 1374 | adapter->stats.tx_underflows += COUNTER_WRAP_12_BIT; |
| 1375 | if (carry_reg2 & (1 << 6)) |
| 1376 | adapter->stats.tx_first_collisions += COUNTER_WRAP_12_BIT; |
| 1377 | if (carry_reg2 & (1 << 8)) |
| 1378 | adapter->stats.tx_deferred += COUNTER_WRAP_12_BIT; |
| 1379 | if (carry_reg2 & (1 << 5)) |
| 1380 | adapter->stats.tx_excessive_collisions += COUNTER_WRAP_12_BIT; |
| 1381 | if (carry_reg2 & (1 << 4)) |
| 1382 | adapter->stats.tx_late_collisions += COUNTER_WRAP_12_BIT; |
| 1383 | if (carry_reg2 & (1 << 2)) |
| 1384 | adapter->stats.tx_collisions += COUNTER_WRAP_12_BIT; |
| 1385 | } |
| 1386 | |
| 1387 | void et1310_setup_device_for_multicast(struct et131x_adapter *adapter) |
| 1388 | { |
| 1389 | struct rxmac_regs __iomem *rxmac = &adapter->regs->rxmac; |
| 1390 | uint32_t nIndex; |
| 1391 | uint32_t result; |
| 1392 | uint32_t hash1 = 0; |
| 1393 | uint32_t hash2 = 0; |
| 1394 | uint32_t hash3 = 0; |
| 1395 | uint32_t hash4 = 0; |
| 1396 | u32 pm_csr; |
| 1397 | |
| 1398 | /* If ET131X_PACKET_TYPE_MULTICAST is specified, then we provision |
| 1399 | * the multi-cast LIST. If it is NOT specified, (and "ALL" is not |
| 1400 | * specified) then we should pass NO multi-cast addresses to the |
| 1401 | * driver. |
| 1402 | */ |
| 1403 | if (adapter->packet_filter & ET131X_PACKET_TYPE_MULTICAST) { |
| 1404 | /* Loop through our multicast array and set up the device */ |
| 1405 | for (nIndex = 0; nIndex < adapter->multicast_addr_count; |
| 1406 | nIndex++) { |
| 1407 | result = ether_crc(6, adapter->multicast_list[nIndex]); |
| 1408 | |
| 1409 | result = (result & 0x3F800000) >> 23; |
| 1410 | |
| 1411 | if (result < 32) { |
| 1412 | hash1 |= (1 << result); |
| 1413 | } else if ((31 < result) && (result < 64)) { |
| 1414 | result -= 32; |
| 1415 | hash2 |= (1 << result); |
| 1416 | } else if ((63 < result) && (result < 96)) { |
| 1417 | result -= 64; |
| 1418 | hash3 |= (1 << result); |
| 1419 | } else { |
| 1420 | result -= 96; |
| 1421 | hash4 |= (1 << result); |
| 1422 | } |
| 1423 | } |
| 1424 | } |
| 1425 | |
| 1426 | /* Write out the new hash to the device */ |
| 1427 | pm_csr = readl(&adapter->regs->global.pm_csr); |
| 1428 | if (!et1310_in_phy_coma(adapter)) { |
| 1429 | writel(hash1, &rxmac->multi_hash1); |
| 1430 | writel(hash2, &rxmac->multi_hash2); |
| 1431 | writel(hash3, &rxmac->multi_hash3); |
| 1432 | writel(hash4, &rxmac->multi_hash4); |
| 1433 | } |
| 1434 | } |
| 1435 | |
| 1436 | void et1310_setup_device_for_unicast(struct et131x_adapter *adapter) |
| 1437 | { |
| 1438 | struct rxmac_regs __iomem *rxmac = &adapter->regs->rxmac; |
| 1439 | u32 uni_pf1; |
| 1440 | u32 uni_pf2; |
| 1441 | u32 uni_pf3; |
| 1442 | u32 pm_csr; |
| 1443 | |
| 1444 | /* Set up unicast packet filter reg 3 to be the first two octets of |
| 1445 | * the MAC address for both address |
| 1446 | * |
| 1447 | * Set up unicast packet filter reg 2 to be the octets 2 - 5 of the |
| 1448 | * MAC address for second address |
| 1449 | * |
| 1450 | * Set up unicast packet filter reg 3 to be the octets 2 - 5 of the |
| 1451 | * MAC address for first address |
| 1452 | */ |
| 1453 | uni_pf3 = (adapter->addr[0] << ET_UNI_PF_ADDR2_1_SHIFT) | |
| 1454 | (adapter->addr[1] << ET_UNI_PF_ADDR2_2_SHIFT) | |
| 1455 | (adapter->addr[0] << ET_UNI_PF_ADDR1_1_SHIFT) | |
| 1456 | adapter->addr[1]; |
| 1457 | |
| 1458 | uni_pf2 = (adapter->addr[2] << ET_UNI_PF_ADDR2_3_SHIFT) | |
| 1459 | (adapter->addr[3] << ET_UNI_PF_ADDR2_4_SHIFT) | |
| 1460 | (adapter->addr[4] << ET_UNI_PF_ADDR2_5_SHIFT) | |
| 1461 | adapter->addr[5]; |
| 1462 | |
| 1463 | uni_pf1 = (adapter->addr[2] << ET_UNI_PF_ADDR1_3_SHIFT) | |
| 1464 | (adapter->addr[3] << ET_UNI_PF_ADDR1_4_SHIFT) | |
| 1465 | (adapter->addr[4] << ET_UNI_PF_ADDR1_5_SHIFT) | |
| 1466 | adapter->addr[5]; |
| 1467 | |
| 1468 | pm_csr = readl(&adapter->regs->global.pm_csr); |
| 1469 | if (!et1310_in_phy_coma(adapter)) { |
| 1470 | writel(uni_pf1, &rxmac->uni_pf_addr1); |
| 1471 | writel(uni_pf2, &rxmac->uni_pf_addr2); |
| 1472 | writel(uni_pf3, &rxmac->uni_pf_addr3); |
| 1473 | } |
| 1474 | } |
| 1475 | |
| 1476 | /* PHY functions */ |
| 1477 | |
| 1478 | int et131x_mdio_read(struct mii_bus *bus, int phy_addr, int reg) |
| 1479 | { |
| 1480 | struct net_device *netdev = bus->priv; |
| 1481 | struct et131x_adapter *adapter = netdev_priv(netdev); |
| 1482 | u16 value; |
| 1483 | int ret; |
| 1484 | |
| 1485 | ret = et131x_phy_mii_read(adapter, phy_addr, reg, &value); |
| 1486 | |
| 1487 | if (ret < 0) |
| 1488 | return ret; |
| 1489 | else |
| 1490 | return value; |
| 1491 | } |
| 1492 | |
| 1493 | int et131x_mdio_write(struct mii_bus *bus, int phy_addr, int reg, u16 value) |
| 1494 | { |
| 1495 | struct net_device *netdev = bus->priv; |
| 1496 | struct et131x_adapter *adapter = netdev_priv(netdev); |
| 1497 | |
| 1498 | return et131x_mii_write(adapter, reg, value); |
| 1499 | } |
| 1500 | |
| 1501 | int et131x_mdio_reset(struct mii_bus *bus) |
| 1502 | { |
| 1503 | struct net_device *netdev = bus->priv; |
| 1504 | struct et131x_adapter *adapter = netdev_priv(netdev); |
| 1505 | |
| 1506 | et131x_mii_write(adapter, MII_BMCR, BMCR_RESET); |
| 1507 | |
| 1508 | return 0; |
| 1509 | } |
| 1510 | |
| 1511 | int et131x_mii_read(struct et131x_adapter *adapter, u8 reg, u16 *value) |
| 1512 | { |
| 1513 | struct phy_device *phydev = adapter->phydev; |
| 1514 | |
| 1515 | if (!phydev) |
| 1516 | return -EIO; |
| 1517 | |
| 1518 | return et131x_phy_mii_read(adapter, phydev->addr, reg, value); |
| 1519 | } |
| 1520 | |
| 1521 | /** |
| 1522 | * et131x_phy_mii_read - Read from the PHY through the MII Interface on the MAC |
| 1523 | * @adapter: pointer to our private adapter structure |
| 1524 | * @addr: the address of the transceiver |
| 1525 | * @reg: the register to read |
| 1526 | * @value: pointer to a 16-bit value in which the value will be stored |
| 1527 | * |
| 1528 | * Returns 0 on success, errno on failure (as defined in errno.h) |
| 1529 | */ |
| 1530 | int et131x_phy_mii_read(struct et131x_adapter *adapter, u8 addr, |
| 1531 | u8 reg, u16 *value) |
| 1532 | { |
| 1533 | struct mac_regs __iomem *mac = &adapter->regs->mac; |
| 1534 | int status = 0; |
| 1535 | u32 delay = 0; |
| 1536 | u32 mii_addr; |
| 1537 | u32 mii_cmd; |
| 1538 | u32 mii_indicator; |
| 1539 | |
| 1540 | /* Save a local copy of the registers we are dealing with so we can |
| 1541 | * set them back |
| 1542 | */ |
| 1543 | mii_addr = readl(&mac->mii_mgmt_addr); |
| 1544 | mii_cmd = readl(&mac->mii_mgmt_cmd); |
| 1545 | |
| 1546 | /* Stop the current operation */ |
| 1547 | writel(0, &mac->mii_mgmt_cmd); |
| 1548 | |
| 1549 | /* Set up the register we need to read from on the correct PHY */ |
| 1550 | writel(MII_ADDR(addr, reg), &mac->mii_mgmt_addr); |
| 1551 | |
| 1552 | writel(0x1, &mac->mii_mgmt_cmd); |
| 1553 | |
| 1554 | do { |
| 1555 | udelay(50); |
| 1556 | delay++; |
| 1557 | mii_indicator = readl(&mac->mii_mgmt_indicator); |
| 1558 | } while ((mii_indicator & MGMT_WAIT) && delay < 50); |
| 1559 | |
| 1560 | /* If we hit the max delay, we could not read the register */ |
| 1561 | if (delay == 50) { |
| 1562 | dev_warn(&adapter->pdev->dev, |
| 1563 | "reg 0x%08x could not be read\n", reg); |
| 1564 | dev_warn(&adapter->pdev->dev, "status is 0x%08x\n", |
| 1565 | mii_indicator); |
| 1566 | |
| 1567 | status = -EIO; |
| 1568 | } |
| 1569 | |
| 1570 | /* If we hit here we were able to read the register and we need to |
| 1571 | * return the value to the caller */ |
| 1572 | *value = readl(&mac->mii_mgmt_stat) & 0xFFFF; |
| 1573 | |
| 1574 | /* Stop the read operation */ |
| 1575 | writel(0, &mac->mii_mgmt_cmd); |
| 1576 | |
| 1577 | /* set the registers we touched back to the state at which we entered |
| 1578 | * this function |
| 1579 | */ |
| 1580 | writel(mii_addr, &mac->mii_mgmt_addr); |
| 1581 | writel(mii_cmd, &mac->mii_mgmt_cmd); |
| 1582 | |
| 1583 | return status; |
| 1584 | } |
| 1585 | |
| 1586 | /** |
| 1587 | * et131x_mii_write - Write to a PHY register through the MII interface of the MAC |
| 1588 | * @adapter: pointer to our private adapter structure |
| 1589 | * @reg: the register to read |
| 1590 | * @value: 16-bit value to write |
| 1591 | * |
| 1592 | * FIXME: one caller in netdev still |
| 1593 | * |
| 1594 | * Return 0 on success, errno on failure (as defined in errno.h) |
| 1595 | */ |
| 1596 | int et131x_mii_write(struct et131x_adapter *adapter, u8 reg, u16 value) |
| 1597 | { |
| 1598 | struct mac_regs __iomem *mac = &adapter->regs->mac; |
| 1599 | struct phy_device *phydev = adapter->phydev; |
| 1600 | int status = 0; |
| 1601 | u8 addr; |
| 1602 | u32 delay = 0; |
| 1603 | u32 mii_addr; |
| 1604 | u32 mii_cmd; |
| 1605 | u32 mii_indicator; |
| 1606 | |
| 1607 | if (!phydev) |
| 1608 | return -EIO; |
| 1609 | |
| 1610 | addr = phydev->addr; |
| 1611 | |
| 1612 | /* Save a local copy of the registers we are dealing with so we can |
| 1613 | * set them back |
| 1614 | */ |
| 1615 | mii_addr = readl(&mac->mii_mgmt_addr); |
| 1616 | mii_cmd = readl(&mac->mii_mgmt_cmd); |
| 1617 | |
| 1618 | /* Stop the current operation */ |
| 1619 | writel(0, &mac->mii_mgmt_cmd); |
| 1620 | |
| 1621 | /* Set up the register we need to write to on the correct PHY */ |
| 1622 | writel(MII_ADDR(addr, reg), &mac->mii_mgmt_addr); |
| 1623 | |
| 1624 | /* Add the value to write to the registers to the mac */ |
| 1625 | writel(value, &mac->mii_mgmt_ctrl); |
| 1626 | |
| 1627 | do { |
| 1628 | udelay(50); |
| 1629 | delay++; |
| 1630 | mii_indicator = readl(&mac->mii_mgmt_indicator); |
| 1631 | } while ((mii_indicator & MGMT_BUSY) && delay < 100); |
| 1632 | |
| 1633 | /* If we hit the max delay, we could not write the register */ |
| 1634 | if (delay == 100) { |
| 1635 | u16 tmp; |
| 1636 | |
| 1637 | dev_warn(&adapter->pdev->dev, |
| 1638 | "reg 0x%08x could not be written", reg); |
| 1639 | dev_warn(&adapter->pdev->dev, "status is 0x%08x\n", |
| 1640 | mii_indicator); |
| 1641 | dev_warn(&adapter->pdev->dev, "command is 0x%08x\n", |
| 1642 | readl(&mac->mii_mgmt_cmd)); |
| 1643 | |
| 1644 | et131x_mii_read(adapter, reg, &tmp); |
| 1645 | |
| 1646 | status = -EIO; |
| 1647 | } |
| 1648 | /* Stop the write operation */ |
| 1649 | writel(0, &mac->mii_mgmt_cmd); |
| 1650 | |
| 1651 | /* |
| 1652 | * set the registers we touched back to the state at which we entered |
| 1653 | * this function |
| 1654 | */ |
| 1655 | writel(mii_addr, &mac->mii_mgmt_addr); |
| 1656 | writel(mii_cmd, &mac->mii_mgmt_cmd); |
| 1657 | |
| 1658 | return status; |
| 1659 | } |
| 1660 | |
| 1661 | /** |
| 1662 | * et1310_phy_power_down - PHY power control |
| 1663 | * @adapter: device to control |
| 1664 | * @down: true for off/false for back on |
| 1665 | * |
| 1666 | * one hundred, ten, one thousand megs |
| 1667 | * How would you like to have your LAN accessed |
| 1668 | * Can't you see that this code processed |
| 1669 | * Phy power, phy power.. |
| 1670 | */ |
| 1671 | void et1310_phy_power_down(struct et131x_adapter *adapter, bool down) |
| 1672 | { |
| 1673 | u16 data; |
| 1674 | |
| 1675 | et131x_mii_read(adapter, MII_BMCR, &data); |
| 1676 | data &= ~BMCR_PDOWN; |
| 1677 | if (down) |
| 1678 | data |= BMCR_PDOWN; |
| 1679 | et131x_mii_write(adapter, MII_BMCR, data); |
| 1680 | } |
| 1681 | |
| 1682 | /* Still used from _mac for BIT_READ */ |
| 1683 | void et1310_phy_access_mii_bit(struct et131x_adapter *adapter, u16 action, |
| 1684 | u16 regnum, u16 bitnum, u8 *value) |
| 1685 | { |
| 1686 | u16 reg; |
| 1687 | u16 mask = 0x0001 << bitnum; |
| 1688 | |
| 1689 | /* Read the requested register */ |
| 1690 | et131x_mii_read(adapter, regnum, ®); |
| 1691 | |
| 1692 | switch (action) { |
| 1693 | case TRUEPHY_BIT_READ: |
| 1694 | *value = (reg & mask) >> bitnum; |
| 1695 | break; |
| 1696 | |
| 1697 | case TRUEPHY_BIT_SET: |
| 1698 | et131x_mii_write(adapter, regnum, reg | mask); |
| 1699 | break; |
| 1700 | |
| 1701 | case TRUEPHY_BIT_CLEAR: |
| 1702 | et131x_mii_write(adapter, regnum, reg & ~mask); |
| 1703 | break; |
| 1704 | |
| 1705 | default: |
| 1706 | break; |
| 1707 | } |
| 1708 | } |
| 1709 | |
| 1710 | /** |
| 1711 | * et131x_xcvr_init - Init the phy if we are setting it into force mode |
| 1712 | * @adapter: pointer to our private adapter structure |
| 1713 | * |
| 1714 | */ |
| 1715 | void et131x_xcvr_init(struct et131x_adapter *adapter) |
| 1716 | { |
| 1717 | u16 imr; |
| 1718 | u16 isr; |
| 1719 | u16 lcr2; |
| 1720 | |
| 1721 | et131x_mii_read(adapter, PHY_INTERRUPT_STATUS, &isr); |
| 1722 | et131x_mii_read(adapter, PHY_INTERRUPT_MASK, &imr); |
| 1723 | |
| 1724 | /* Set the link status interrupt only. Bad behavior when link status |
| 1725 | * and auto neg are set, we run into a nested interrupt problem |
| 1726 | */ |
| 1727 | imr |= (ET_PHY_INT_MASK_AUTONEGSTAT & |
| 1728 | ET_PHY_INT_MASK_LINKSTAT & |
| 1729 | ET_PHY_INT_MASK_ENABLE); |
| 1730 | |
| 1731 | et131x_mii_write(adapter, PHY_INTERRUPT_MASK, imr); |
| 1732 | |
| 1733 | /* Set the LED behavior such that LED 1 indicates speed (off = |
| 1734 | * 10Mbits, blink = 100Mbits, on = 1000Mbits) and LED 2 indicates |
| 1735 | * link and activity (on for link, blink off for activity). |
| 1736 | * |
| 1737 | * NOTE: Some customizations have been added here for specific |
| 1738 | * vendors; The LED behavior is now determined by vendor data in the |
| 1739 | * EEPROM. However, the above description is the default. |
| 1740 | */ |
| 1741 | if ((adapter->eeprom_data[1] & 0x4) == 0) { |
| 1742 | et131x_mii_read(adapter, PHY_LED_2, &lcr2); |
| 1743 | |
| 1744 | lcr2 &= (ET_LED2_LED_100TX & ET_LED2_LED_1000T); |
| 1745 | lcr2 |= (LED_VAL_LINKON_ACTIVE << LED_LINK_SHIFT); |
| 1746 | |
| 1747 | if ((adapter->eeprom_data[1] & 0x8) == 0) |
| 1748 | lcr2 |= (LED_VAL_1000BT_100BTX << LED_TXRX_SHIFT); |
| 1749 | else |
| 1750 | lcr2 |= (LED_VAL_LINKON << LED_TXRX_SHIFT); |
| 1751 | |
| 1752 | et131x_mii_write(adapter, PHY_LED_2, lcr2); |
| 1753 | } |
| 1754 | } |
| 1755 | |
| 1756 | /* PM functions */ |
| 1757 | |
| 1758 | /** |
| 1759 | * et1310_in_phy_coma - check if the device is in phy coma |
| 1760 | * @adapter: pointer to our adapter structure |
| 1761 | * |
| 1762 | * Returns 0 if the device is not in phy coma, 1 if it is in phy coma |
| 1763 | */ |
| 1764 | int et1310_in_phy_coma(struct et131x_adapter *adapter) |
| 1765 | { |
| 1766 | u32 pmcsr; |
| 1767 | |
| 1768 | pmcsr = readl(&adapter->regs->global.pm_csr); |
| 1769 | |
| 1770 | return ET_PM_PHY_SW_COMA & pmcsr ? 1 : 0; |
| 1771 | } |
| 1772 | |
| 1773 | /** |
| 1774 | * et1310_enable_phy_coma - called when network cable is unplugged |
| 1775 | * @adapter: pointer to our adapter structure |
| 1776 | * |
| 1777 | * driver receive an phy status change interrupt while in D0 and check that |
| 1778 | * phy_status is down. |
| 1779 | * |
| 1780 | * -- gate off JAGCore; |
| 1781 | * -- set gigE PHY in Coma mode |
| 1782 | * -- wake on phy_interrupt; Perform software reset JAGCore, |
| 1783 | * re-initialize jagcore and gigE PHY |
| 1784 | * |
| 1785 | * Add D0-ASPM-PhyLinkDown Support: |
| 1786 | * -- while in D0, when there is a phy_interrupt indicating phy link |
| 1787 | * down status, call the MPSetPhyComa routine to enter this active |
| 1788 | * state power saving mode |
| 1789 | * -- while in D0-ASPM-PhyLinkDown mode, when there is a phy_interrupt |
| 1790 | * indicating linkup status, call the MPDisablePhyComa routine to |
| 1791 | * restore JAGCore and gigE PHY |
| 1792 | */ |
| 1793 | void et1310_enable_phy_coma(struct et131x_adapter *adapter) |
| 1794 | { |
| 1795 | unsigned long flags; |
| 1796 | u32 pmcsr; |
| 1797 | |
| 1798 | pmcsr = readl(&adapter->regs->global.pm_csr); |
| 1799 | |
| 1800 | /* Save the GbE PHY speed and duplex modes. Need to restore this |
| 1801 | * when cable is plugged back in |
| 1802 | */ |
| 1803 | /* |
| 1804 | * TODO - when PM is re-enabled, check if we need to |
| 1805 | * perform a similar task as this - |
| 1806 | * adapter->pdown_speed = adapter->ai_force_speed; |
| 1807 | * adapter->pdown_duplex = adapter->ai_force_duplex; |
| 1808 | */ |
| 1809 | |
| 1810 | /* Stop sending packets. */ |
| 1811 | spin_lock_irqsave(&adapter->send_hw_lock, flags); |
| 1812 | adapter->flags |= fMP_ADAPTER_LOWER_POWER; |
| 1813 | spin_unlock_irqrestore(&adapter->send_hw_lock, flags); |
| 1814 | |
| 1815 | /* Wait for outstanding Receive packets */ |
| 1816 | |
| 1817 | et131x_disable_txrx(adapter->netdev); |
| 1818 | |
| 1819 | /* Gate off JAGCore 3 clock domains */ |
| 1820 | pmcsr &= ~ET_PMCSR_INIT; |
| 1821 | writel(pmcsr, &adapter->regs->global.pm_csr); |
| 1822 | |
| 1823 | /* Program gigE PHY in to Coma mode */ |
| 1824 | pmcsr |= ET_PM_PHY_SW_COMA; |
| 1825 | writel(pmcsr, &adapter->regs->global.pm_csr); |
| 1826 | } |
| 1827 | |
| 1828 | /** |
| 1829 | * et1310_disable_phy_coma - Disable the Phy Coma Mode |
| 1830 | * @adapter: pointer to our adapter structure |
| 1831 | */ |
| 1832 | void et1310_disable_phy_coma(struct et131x_adapter *adapter) |
| 1833 | { |
| 1834 | u32 pmcsr; |
| 1835 | |
| 1836 | pmcsr = readl(&adapter->regs->global.pm_csr); |
| 1837 | |
| 1838 | /* Disable phy_sw_coma register and re-enable JAGCore clocks */ |
| 1839 | pmcsr |= ET_PMCSR_INIT; |
| 1840 | pmcsr &= ~ET_PM_PHY_SW_COMA; |
| 1841 | writel(pmcsr, &adapter->regs->global.pm_csr); |
| 1842 | |
| 1843 | /* Restore the GbE PHY speed and duplex modes; |
| 1844 | * Reset JAGCore; re-configure and initialize JAGCore and gigE PHY |
| 1845 | */ |
| 1846 | /* TODO - when PM is re-enabled, check if we need to |
| 1847 | * perform a similar task as this - |
| 1848 | * adapter->ai_force_speed = adapter->pdown_speed; |
| 1849 | * adapter->ai_force_duplex = adapter->pdown_duplex; |
| 1850 | */ |
| 1851 | |
| 1852 | /* Re-initialize the send structures */ |
| 1853 | et131x_init_send(adapter); |
| 1854 | |
| 1855 | /* Reset the RFD list and re-start RU */ |
| 1856 | et131x_reset_recv(adapter); |
| 1857 | |
| 1858 | /* Bring the device back to the state it was during init prior to |
| 1859 | * autonegotiation being complete. This way, when we get the auto-neg |
| 1860 | * complete interrupt, we can complete init by calling ConfigMacREGS2. |
| 1861 | */ |
| 1862 | et131x_soft_reset(adapter); |
| 1863 | |
| 1864 | /* setup et1310 as per the documentation ?? */ |
| 1865 | et131x_adapter_setup(adapter); |
| 1866 | |
| 1867 | /* Allow Tx to restart */ |
| 1868 | adapter->flags &= ~fMP_ADAPTER_LOWER_POWER; |
| 1869 | |
| 1870 | et131x_enable_txrx(adapter->netdev); |
| 1871 | } |
| 1872 | |
| 1873 | /* RX functions */ |
| 1874 | |
| 1875 | static inline u32 bump_free_buff_ring(u32 *free_buff_ring, u32 limit) |
| 1876 | { |
| 1877 | u32 tmp_free_buff_ring = *free_buff_ring; |
| 1878 | tmp_free_buff_ring++; |
| 1879 | /* This works for all cases where limit < 1024. The 1023 case |
| 1880 | works because 1023++ is 1024 which means the if condition is not |
| 1881 | taken but the carry of the bit into the wrap bit toggles the wrap |
| 1882 | value correctly */ |
| 1883 | if ((tmp_free_buff_ring & ET_DMA10_MASK) > limit) { |
| 1884 | tmp_free_buff_ring &= ~ET_DMA10_MASK; |
| 1885 | tmp_free_buff_ring ^= ET_DMA10_WRAP; |
| 1886 | } |
| 1887 | /* For the 1023 case */ |
| 1888 | tmp_free_buff_ring &= (ET_DMA10_MASK|ET_DMA10_WRAP); |
| 1889 | *free_buff_ring = tmp_free_buff_ring; |
| 1890 | return tmp_free_buff_ring; |
| 1891 | } |
| 1892 | |
| 1893 | /** |
| 1894 | * et131x_rx_dma_memory_alloc |
| 1895 | * @adapter: pointer to our private adapter structure |
| 1896 | * |
| 1897 | * Returns 0 on success and errno on failure (as defined in errno.h) |
| 1898 | * |
| 1899 | * Allocates Free buffer ring 1 for sure, free buffer ring 0 if required, |
| 1900 | * and the Packet Status Ring. |
| 1901 | */ |
| 1902 | int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter) |
| 1903 | { |
| 1904 | u32 i, j; |
| 1905 | u32 bufsize; |
| 1906 | u32 pktstat_ringsize, fbr_chunksize; |
| 1907 | struct rx_ring *rx_ring; |
| 1908 | |
| 1909 | /* Setup some convenience pointers */ |
| 1910 | rx_ring = &adapter->rx_ring; |
| 1911 | |
| 1912 | /* Alloc memory for the lookup table */ |
| 1913 | #ifdef USE_FBR0 |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 1914 | rx_ring->fbr[1] = kmalloc(sizeof(struct fbr_lookup), GFP_KERNEL); |
Mark Einon | e592a9b | 2011-10-20 01:18:42 +0100 | [diff] [blame] | 1915 | #endif |
| 1916 | rx_ring->fbr[0] = kmalloc(sizeof(struct fbr_lookup), GFP_KERNEL); |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 1917 | |
| 1918 | /* The first thing we will do is configure the sizes of the buffer |
| 1919 | * rings. These will change based on jumbo packet support. Larger |
| 1920 | * jumbo packets increases the size of each entry in FBR0, and the |
| 1921 | * number of entries in FBR0, while at the same time decreasing the |
| 1922 | * number of entries in FBR1. |
| 1923 | * |
| 1924 | * FBR1 holds "large" frames, FBR0 holds "small" frames. If FBR1 |
| 1925 | * entries are huge in order to accommodate a "jumbo" frame, then it |
| 1926 | * will have less entries. Conversely, FBR1 will now be relied upon |
| 1927 | * to carry more "normal" frames, thus it's entry size also increases |
| 1928 | * and the number of entries goes up too (since it now carries |
| 1929 | * "small" + "regular" packets. |
| 1930 | * |
| 1931 | * In this scheme, we try to maintain 512 entries between the two |
| 1932 | * rings. Also, FBR1 remains a constant size - when it's size doubles |
| 1933 | * the number of entries halves. FBR0 increases in size, however. |
| 1934 | */ |
| 1935 | |
| 1936 | if (adapter->registry_jumbo_packet < 2048) { |
| 1937 | #ifdef USE_FBR0 |
Mark Einon | e592a9b | 2011-10-20 01:18:42 +0100 | [diff] [blame] | 1938 | rx_ring->fbr[1]->buffsize = 256; |
Mark Einon | 6abafc1 | 2011-10-20 01:18:41 +0100 | [diff] [blame] | 1939 | rx_ring->fbr[1]->num_entries = 512; |
Mark Einon | e592a9b | 2011-10-20 01:18:42 +0100 | [diff] [blame] | 1940 | #endif |
| 1941 | rx_ring->fbr[0]->buffsize = 2048; |
| 1942 | rx_ring->fbr[0]->num_entries = 512; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 1943 | } else if (adapter->registry_jumbo_packet < 4096) { |
| 1944 | #ifdef USE_FBR0 |
Mark Einon | e592a9b | 2011-10-20 01:18:42 +0100 | [diff] [blame] | 1945 | rx_ring->fbr[1]->buffsize = 512; |
| 1946 | rx_ring->fbr[1]->num_entries = 1024; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 1947 | #endif |
Mark Einon | e592a9b | 2011-10-20 01:18:42 +0100 | [diff] [blame] | 1948 | rx_ring->fbr[0]->buffsize = 4096; |
| 1949 | rx_ring->fbr[0]->num_entries = 512; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 1950 | } else { |
| 1951 | #ifdef USE_FBR0 |
Mark Einon | e592a9b | 2011-10-20 01:18:42 +0100 | [diff] [blame] | 1952 | rx_ring->fbr[1]->buffsize = 1024; |
| 1953 | rx_ring->fbr[1]->num_entries = 768; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 1954 | #endif |
Mark Einon | e592a9b | 2011-10-20 01:18:42 +0100 | [diff] [blame] | 1955 | rx_ring->fbr[0]->buffsize = 16384; |
| 1956 | rx_ring->fbr[0]->num_entries = 128; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 1957 | } |
| 1958 | |
| 1959 | #ifdef USE_FBR0 |
Mark Einon | e592a9b | 2011-10-20 01:18:42 +0100 | [diff] [blame] | 1960 | adapter->rx_ring.psr_num_entries = adapter->rx_ring.fbr[1]->num_entries + |
| 1961 | adapter->rx_ring.fbr[0]->num_entries; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 1962 | #else |
Mark Einon | e592a9b | 2011-10-20 01:18:42 +0100 | [diff] [blame] | 1963 | adapter->rx_ring.psr_num_entries = adapter->rx_ring.fbr[0]->num_entries; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 1964 | #endif |
| 1965 | |
| 1966 | /* Allocate an area of memory for Free Buffer Ring 1 */ |
Mark Einon | e592a9b | 2011-10-20 01:18:42 +0100 | [diff] [blame] | 1967 | bufsize = (sizeof(struct fbr_desc) * rx_ring->fbr[0]->num_entries) + 0xfff; |
Mark Einon | 0d1b7a8 | 2011-10-20 01:18:43 +0100 | [diff] [blame^] | 1968 | rx_ring->fbr[0]->ring_virtaddr = dma_alloc_coherent(&adapter->pdev->dev, |
| 1969 | bufsize, |
| 1970 | &rx_ring->fbr[0]->ring_physaddr, |
| 1971 | GFP_KERNEL); |
Mark Einon | e592a9b | 2011-10-20 01:18:42 +0100 | [diff] [blame] | 1972 | if (!rx_ring->fbr[0]->ring_virtaddr) { |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 1973 | dev_err(&adapter->pdev->dev, |
| 1974 | "Cannot alloc memory for Free Buffer Ring 1\n"); |
| 1975 | return -ENOMEM; |
| 1976 | } |
| 1977 | |
| 1978 | /* Save physical address |
| 1979 | * |
| 1980 | * NOTE: pci_alloc_consistent(), used above to alloc DMA regions, |
| 1981 | * ALWAYS returns SAC (32-bit) addresses. If DAC (64-bit) addresses |
| 1982 | * are ever returned, make sure the high part is retrieved here |
| 1983 | * before storing the adjusted address. |
| 1984 | */ |
Mark Einon | e592a9b | 2011-10-20 01:18:42 +0100 | [diff] [blame] | 1985 | rx_ring->fbr[0]->real_physaddr = rx_ring->fbr[0]->ring_physaddr; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 1986 | |
| 1987 | /* Align Free Buffer Ring 1 on a 4K boundary */ |
| 1988 | et131x_align_allocated_memory(adapter, |
Mark Einon | e592a9b | 2011-10-20 01:18:42 +0100 | [diff] [blame] | 1989 | &rx_ring->fbr[0]->real_physaddr, |
| 1990 | &rx_ring->fbr[0]->offset, 0x0FFF); |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 1991 | |
Mark Einon | e592a9b | 2011-10-20 01:18:42 +0100 | [diff] [blame] | 1992 | rx_ring->fbr[0]->ring_virtaddr = |
| 1993 | (void *)((u8 *) rx_ring->fbr[0]->ring_virtaddr + |
| 1994 | rx_ring->fbr[0]->offset); |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 1995 | |
| 1996 | #ifdef USE_FBR0 |
| 1997 | /* Allocate an area of memory for Free Buffer Ring 0 */ |
Mark Einon | e592a9b | 2011-10-20 01:18:42 +0100 | [diff] [blame] | 1998 | bufsize = (sizeof(struct fbr_desc) * rx_ring->fbr[1]->num_entries) + 0xfff; |
Mark Einon | 0d1b7a8 | 2011-10-20 01:18:43 +0100 | [diff] [blame^] | 1999 | rx_ring->fbr[1]->ring_virtaddr = dma_alloc_coherent(&adapter->pdev->dev, |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2000 | bufsize, |
Mark Einon | 0d1b7a8 | 2011-10-20 01:18:43 +0100 | [diff] [blame^] | 2001 | &rx_ring->fbr[1]->ring_physaddr, |
| 2002 | GFP_KERNEL); |
Mark Einon | e592a9b | 2011-10-20 01:18:42 +0100 | [diff] [blame] | 2003 | if (!rx_ring->fbr[1]->ring_virtaddr) { |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2004 | dev_err(&adapter->pdev->dev, |
| 2005 | "Cannot alloc memory for Free Buffer Ring 0\n"); |
| 2006 | return -ENOMEM; |
| 2007 | } |
| 2008 | |
| 2009 | /* Save physical address |
| 2010 | * |
| 2011 | * NOTE: pci_alloc_consistent(), used above to alloc DMA regions, |
| 2012 | * ALWAYS returns SAC (32-bit) addresses. If DAC (64-bit) addresses |
| 2013 | * are ever returned, make sure the high part is retrieved here before |
| 2014 | * storing the adjusted address. |
| 2015 | */ |
Mark Einon | e592a9b | 2011-10-20 01:18:42 +0100 | [diff] [blame] | 2016 | rx_ring->fbr[1]->real_physaddr = rx_ring->fbr[1]->ring_physaddr; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2017 | |
| 2018 | /* Align Free Buffer Ring 0 on a 4K boundary */ |
| 2019 | et131x_align_allocated_memory(adapter, |
Mark Einon | e592a9b | 2011-10-20 01:18:42 +0100 | [diff] [blame] | 2020 | &rx_ring->fbr[1]->real_physaddr, |
| 2021 | &rx_ring->fbr[1]->offset, 0x0FFF); |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2022 | |
Mark Einon | e592a9b | 2011-10-20 01:18:42 +0100 | [diff] [blame] | 2023 | rx_ring->fbr[1]->ring_virtaddr = |
| 2024 | (void *)((u8 *) rx_ring->fbr[1]->ring_virtaddr + |
| 2025 | rx_ring->fbr[1]->offset); |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2026 | #endif |
Mark Einon | e592a9b | 2011-10-20 01:18:42 +0100 | [diff] [blame] | 2027 | for (i = 0; i < (rx_ring->fbr[0]->num_entries / FBR_CHUNKS); i++) { |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2028 | u64 fbr1_offset; |
| 2029 | u64 fbr1_tmp_physaddr; |
| 2030 | u32 fbr1_align; |
| 2031 | |
| 2032 | /* This code allocates an area of memory big enough for N |
| 2033 | * free buffers + (buffer_size - 1) so that the buffers can |
| 2034 | * be aligned on 4k boundaries. If each buffer were aligned |
| 2035 | * to a buffer_size boundary, the effect would be to double |
| 2036 | * the size of FBR0. By allocating N buffers at once, we |
| 2037 | * reduce this overhead. |
| 2038 | */ |
Mark Einon | e592a9b | 2011-10-20 01:18:42 +0100 | [diff] [blame] | 2039 | if (rx_ring->fbr[0]->buffsize > 4096) |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2040 | fbr1_align = 4096; |
| 2041 | else |
Mark Einon | e592a9b | 2011-10-20 01:18:42 +0100 | [diff] [blame] | 2042 | fbr1_align = rx_ring->fbr[0]->buffsize; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2043 | |
| 2044 | fbr_chunksize = |
Mark Einon | e592a9b | 2011-10-20 01:18:42 +0100 | [diff] [blame] | 2045 | (FBR_CHUNKS * rx_ring->fbr[0]->buffsize) + fbr1_align - 1; |
Mark Einon | 6abafc1 | 2011-10-20 01:18:41 +0100 | [diff] [blame] | 2046 | rx_ring->fbr[0]->mem_virtaddrs[i] = |
Mark Einon | 0d1b7a8 | 2011-10-20 01:18:43 +0100 | [diff] [blame^] | 2047 | dma_alloc_coherent(&adapter->pdev->dev, fbr_chunksize, |
| 2048 | &rx_ring->fbr[0]->mem_physaddrs[i], GFP_KERNEL); |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2049 | |
Mark Einon | 6abafc1 | 2011-10-20 01:18:41 +0100 | [diff] [blame] | 2050 | if (!rx_ring->fbr[0]->mem_virtaddrs[i]) { |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2051 | dev_err(&adapter->pdev->dev, |
| 2052 | "Could not alloc memory\n"); |
| 2053 | return -ENOMEM; |
| 2054 | } |
| 2055 | |
| 2056 | /* See NOTE in "Save Physical Address" comment above */ |
Mark Einon | e592a9b | 2011-10-20 01:18:42 +0100 | [diff] [blame] | 2057 | fbr1_tmp_physaddr = rx_ring->fbr[0]->mem_physaddrs[i]; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2058 | |
| 2059 | et131x_align_allocated_memory(adapter, |
Mark Einon | e592a9b | 2011-10-20 01:18:42 +0100 | [diff] [blame] | 2060 | &fbr1_tmp_physaddr, |
| 2061 | &fbr1_offset, (fbr1_align - 1)); |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2062 | |
| 2063 | for (j = 0; j < FBR_CHUNKS; j++) { |
| 2064 | u32 index = (i * FBR_CHUNKS) + j; |
| 2065 | |
Mark Einon | e592a9b | 2011-10-20 01:18:42 +0100 | [diff] [blame] | 2066 | /* Save the Virtual address of this index for quick |
| 2067 | * access later |
| 2068 | */ |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2069 | rx_ring->fbr[0]->virt[index] = |
Mark Einon | 6abafc1 | 2011-10-20 01:18:41 +0100 | [diff] [blame] | 2070 | (u8 *) rx_ring->fbr[0]->mem_virtaddrs[i] + |
Mark Einon | e592a9b | 2011-10-20 01:18:42 +0100 | [diff] [blame] | 2071 | (j * rx_ring->fbr[0]->buffsize) + fbr1_offset; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2072 | |
Mark Einon | e592a9b | 2011-10-20 01:18:42 +0100 | [diff] [blame] | 2073 | /* now store the physical address in the descriptor |
| 2074 | * so the device can access it |
| 2075 | */ |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2076 | rx_ring->fbr[0]->bus_high[index] = |
Mark Einon | e592a9b | 2011-10-20 01:18:42 +0100 | [diff] [blame] | 2077 | (u32) (fbr1_tmp_physaddr >> 32); |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2078 | rx_ring->fbr[0]->bus_low[index] = |
Mark Einon | e592a9b | 2011-10-20 01:18:42 +0100 | [diff] [blame] | 2079 | (u32) fbr1_tmp_physaddr; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2080 | |
Mark Einon | e592a9b | 2011-10-20 01:18:42 +0100 | [diff] [blame] | 2081 | fbr1_tmp_physaddr += rx_ring->fbr[0]->buffsize; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2082 | |
| 2083 | rx_ring->fbr[0]->buffer1[index] = |
| 2084 | rx_ring->fbr[0]->virt[index]; |
| 2085 | rx_ring->fbr[0]->buffer2[index] = |
| 2086 | rx_ring->fbr[0]->virt[index] - 4; |
| 2087 | } |
| 2088 | } |
Mark Einon | e592a9b | 2011-10-20 01:18:42 +0100 | [diff] [blame] | 2089 | |
| 2090 | #ifdef USE_FBR0 |
| 2091 | /* Same for FBR0 (if in use) */ |
| 2092 | for (i = 0; i < (rx_ring->fbr[1]->num_entries / FBR_CHUNKS); i++) { |
| 2093 | u64 fbr0_offset; |
| 2094 | u64 fbr0_tmp_physaddr; |
| 2095 | |
| 2096 | fbr_chunksize = |
| 2097 | ((FBR_CHUNKS + 1) * rx_ring->fbr[1]->buffsize) - 1; |
| 2098 | rx_ring->fbr[1]->mem_virtaddrs[i] = |
Mark Einon | 0d1b7a8 | 2011-10-20 01:18:43 +0100 | [diff] [blame^] | 2099 | dma_alloc_coherent(&adapter->pdev->dev, fbr_chunksize, |
| 2100 | &rx_ring->fbr[1]->mem_physaddrs[i], GFP_KERNEL); |
Mark Einon | e592a9b | 2011-10-20 01:18:42 +0100 | [diff] [blame] | 2101 | |
| 2102 | if (!rx_ring->fbr[1]->mem_virtaddrs[i]) { |
| 2103 | dev_err(&adapter->pdev->dev, |
| 2104 | "Could not alloc memory\n"); |
| 2105 | return -ENOMEM; |
| 2106 | } |
| 2107 | |
| 2108 | /* See NOTE in "Save Physical Address" comment above */ |
| 2109 | fbr0_tmp_physaddr = rx_ring->fbr[1]->mem_physaddrs[i]; |
| 2110 | |
| 2111 | et131x_align_allocated_memory(adapter, |
| 2112 | &fbr0_tmp_physaddr, |
| 2113 | &fbr0_offset, |
| 2114 | rx_ring->fbr[1]->buffsize - 1); |
| 2115 | |
| 2116 | for (j = 0; j < FBR_CHUNKS; j++) { |
| 2117 | u32 index = (i * FBR_CHUNKS) + j; |
| 2118 | |
| 2119 | rx_ring->fbr[1]->virt[index] = |
| 2120 | (u8 *) rx_ring->fbr[1]->mem_virtaddrs[i] + |
| 2121 | (j * rx_ring->fbr[1]->buffsize) + fbr0_offset; |
| 2122 | |
| 2123 | rx_ring->fbr[1]->bus_high[index] = |
| 2124 | (u32) (fbr0_tmp_physaddr >> 32); |
| 2125 | rx_ring->fbr[1]->bus_low[index] = |
| 2126 | (u32) fbr0_tmp_physaddr; |
| 2127 | |
| 2128 | fbr0_tmp_physaddr += rx_ring->fbr[1]->buffsize; |
| 2129 | |
| 2130 | rx_ring->fbr[1]->buffer1[index] = |
| 2131 | rx_ring->fbr[1]->virt[index]; |
| 2132 | rx_ring->fbr[1]->buffer2[index] = |
| 2133 | rx_ring->fbr[1]->virt[index] - 4; |
| 2134 | } |
| 2135 | } |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2136 | #endif |
| 2137 | |
| 2138 | /* Allocate an area of memory for FIFO of Packet Status ring entries */ |
| 2139 | pktstat_ringsize = |
| 2140 | sizeof(struct pkt_stat_desc) * adapter->rx_ring.psr_num_entries; |
| 2141 | |
Mark Einon | 0d1b7a8 | 2011-10-20 01:18:43 +0100 | [diff] [blame^] | 2142 | rx_ring->ps_ring_virtaddr = dma_alloc_coherent(&adapter->pdev->dev, |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2143 | pktstat_ringsize, |
Mark Einon | 0d1b7a8 | 2011-10-20 01:18:43 +0100 | [diff] [blame^] | 2144 | &rx_ring->ps_ring_physaddr, |
| 2145 | GFP_KERNEL); |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2146 | |
| 2147 | if (!rx_ring->ps_ring_virtaddr) { |
| 2148 | dev_err(&adapter->pdev->dev, |
| 2149 | "Cannot alloc memory for Packet Status Ring\n"); |
| 2150 | return -ENOMEM; |
| 2151 | } |
| 2152 | printk(KERN_INFO "Packet Status Ring %lx\n", |
| 2153 | (unsigned long) rx_ring->ps_ring_physaddr); |
| 2154 | |
| 2155 | /* |
| 2156 | * NOTE : pci_alloc_consistent(), used above to alloc DMA regions, |
| 2157 | * ALWAYS returns SAC (32-bit) addresses. If DAC (64-bit) addresses |
| 2158 | * are ever returned, make sure the high part is retrieved here before |
| 2159 | * storing the adjusted address. |
| 2160 | */ |
| 2161 | |
| 2162 | /* Allocate an area of memory for writeback of status information */ |
Mark Einon | 0d1b7a8 | 2011-10-20 01:18:43 +0100 | [diff] [blame^] | 2163 | rx_ring->rx_status_block = dma_alloc_coherent(&adapter->pdev->dev, |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2164 | sizeof(struct rx_status_block), |
Mark Einon | 0d1b7a8 | 2011-10-20 01:18:43 +0100 | [diff] [blame^] | 2165 | &rx_ring->rx_status_bus, |
| 2166 | GFP_KERNEL); |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2167 | if (!rx_ring->rx_status_block) { |
| 2168 | dev_err(&adapter->pdev->dev, |
| 2169 | "Cannot alloc memory for Status Block\n"); |
| 2170 | return -ENOMEM; |
| 2171 | } |
| 2172 | rx_ring->num_rfd = NIC_DEFAULT_NUM_RFD; |
| 2173 | printk(KERN_INFO "PRS %lx\n", (unsigned long)rx_ring->rx_status_bus); |
| 2174 | |
| 2175 | /* Recv |
| 2176 | * pci_pool_create initializes a lookaside list. After successful |
| 2177 | * creation, nonpaged fixed-size blocks can be allocated from and |
| 2178 | * freed to the lookaside list. |
| 2179 | * RFDs will be allocated from this pool. |
| 2180 | */ |
| 2181 | rx_ring->recv_lookaside = kmem_cache_create(adapter->netdev->name, |
| 2182 | sizeof(struct rfd), |
| 2183 | 0, |
| 2184 | SLAB_CACHE_DMA | |
| 2185 | SLAB_HWCACHE_ALIGN, |
| 2186 | NULL); |
| 2187 | |
| 2188 | adapter->flags |= fMP_ADAPTER_RECV_LOOKASIDE; |
| 2189 | |
| 2190 | /* The RFDs are going to be put on lists later on, so initialize the |
| 2191 | * lists now. |
| 2192 | */ |
| 2193 | INIT_LIST_HEAD(&rx_ring->recv_list); |
| 2194 | return 0; |
| 2195 | } |
| 2196 | |
| 2197 | /** |
| 2198 | * et131x_rx_dma_memory_free - Free all memory allocated within this module. |
| 2199 | * @adapter: pointer to our private adapter structure |
| 2200 | */ |
| 2201 | void et131x_rx_dma_memory_free(struct et131x_adapter *adapter) |
| 2202 | { |
| 2203 | u32 index; |
| 2204 | u32 bufsize; |
| 2205 | u32 pktstat_ringsize; |
| 2206 | struct rfd *rfd; |
| 2207 | struct rx_ring *rx_ring; |
| 2208 | |
| 2209 | /* Setup some convenience pointers */ |
| 2210 | rx_ring = &adapter->rx_ring; |
| 2211 | |
| 2212 | /* Free RFDs and associated packet descriptors */ |
| 2213 | WARN_ON(rx_ring->num_ready_recv != rx_ring->num_rfd); |
| 2214 | |
| 2215 | while (!list_empty(&rx_ring->recv_list)) { |
| 2216 | rfd = (struct rfd *) list_entry(rx_ring->recv_list.next, |
| 2217 | struct rfd, list_node); |
| 2218 | |
| 2219 | list_del(&rfd->list_node); |
| 2220 | rfd->skb = NULL; |
| 2221 | kmem_cache_free(adapter->rx_ring.recv_lookaside, rfd); |
| 2222 | } |
| 2223 | |
| 2224 | /* Free Free Buffer Ring 1 */ |
Mark Einon | 6abafc1 | 2011-10-20 01:18:41 +0100 | [diff] [blame] | 2225 | if (rx_ring->fbr[0]->ring_virtaddr) { |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2226 | /* First the packet memory */ |
| 2227 | for (index = 0; index < |
Mark Einon | 6abafc1 | 2011-10-20 01:18:41 +0100 | [diff] [blame] | 2228 | (rx_ring->fbr[0]->num_entries / FBR_CHUNKS); index++) { |
| 2229 | if (rx_ring->fbr[0]->mem_virtaddrs[index]) { |
Mark Einon | e592a9b | 2011-10-20 01:18:42 +0100 | [diff] [blame] | 2230 | u32 fbr1_align; |
| 2231 | |
| 2232 | if (rx_ring->fbr[0]->buffsize > 4096) |
| 2233 | fbr1_align = 4096; |
| 2234 | else |
| 2235 | fbr1_align = rx_ring->fbr[0]->buffsize; |
| 2236 | |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2237 | bufsize = |
Mark Einon | e592a9b | 2011-10-20 01:18:42 +0100 | [diff] [blame] | 2238 | (rx_ring->fbr[0]->buffsize * FBR_CHUNKS) + |
| 2239 | fbr1_align - 1; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2240 | |
| 2241 | pci_free_consistent(adapter->pdev, |
| 2242 | bufsize, |
Mark Einon | 6abafc1 | 2011-10-20 01:18:41 +0100 | [diff] [blame] | 2243 | rx_ring->fbr[0]->mem_virtaddrs[index], |
| 2244 | rx_ring->fbr[0]->mem_physaddrs[index]); |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2245 | |
Mark Einon | 6abafc1 | 2011-10-20 01:18:41 +0100 | [diff] [blame] | 2246 | rx_ring->fbr[0]->mem_virtaddrs[index] = NULL; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2247 | } |
| 2248 | } |
| 2249 | |
| 2250 | /* Now the FIFO itself */ |
Mark Einon | 6abafc1 | 2011-10-20 01:18:41 +0100 | [diff] [blame] | 2251 | rx_ring->fbr[0]->ring_virtaddr = (void *)((u8 *) |
| 2252 | rx_ring->fbr[0]->ring_virtaddr - rx_ring->fbr[0]->offset); |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2253 | |
Mark Einon | 6abafc1 | 2011-10-20 01:18:41 +0100 | [diff] [blame] | 2254 | bufsize = (sizeof(struct fbr_desc) * rx_ring->fbr[0]->num_entries) |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2255 | + 0xfff; |
| 2256 | |
Mark Einon | e592a9b | 2011-10-20 01:18:42 +0100 | [diff] [blame] | 2257 | pci_free_consistent(adapter->pdev, bufsize, |
Mark Einon | 6abafc1 | 2011-10-20 01:18:41 +0100 | [diff] [blame] | 2258 | rx_ring->fbr[0]->ring_virtaddr, |
| 2259 | rx_ring->fbr[0]->ring_physaddr); |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2260 | |
Mark Einon | 6abafc1 | 2011-10-20 01:18:41 +0100 | [diff] [blame] | 2261 | rx_ring->fbr[0]->ring_virtaddr = NULL; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2262 | } |
Mark Einon | e592a9b | 2011-10-20 01:18:42 +0100 | [diff] [blame] | 2263 | |
| 2264 | #ifdef USE_FBR0 |
| 2265 | /* Now the same for Free Buffer Ring 0 */ |
| 2266 | if (rx_ring->fbr[1]->ring_virtaddr) { |
| 2267 | /* First the packet memory */ |
| 2268 | for (index = 0; index < |
| 2269 | (rx_ring->fbr[1]->num_entries / FBR_CHUNKS); index++) { |
| 2270 | if (rx_ring->fbr[1]->mem_virtaddrs[index]) { |
| 2271 | bufsize = |
| 2272 | (rx_ring->fbr[1]->buffsize * |
| 2273 | (FBR_CHUNKS + 1)) - 1; |
| 2274 | |
| 2275 | pci_free_consistent(adapter->pdev, |
| 2276 | bufsize, |
| 2277 | rx_ring->fbr[1]->mem_virtaddrs[index], |
| 2278 | rx_ring->fbr[1]->mem_physaddrs[index]); |
| 2279 | |
| 2280 | rx_ring->fbr[1]->mem_virtaddrs[index] = NULL; |
| 2281 | } |
| 2282 | } |
| 2283 | |
| 2284 | /* Now the FIFO itself */ |
| 2285 | rx_ring->fbr[1]->ring_virtaddr = (void *)((u8 *) |
| 2286 | rx_ring->fbr[1]->ring_virtaddr - rx_ring->fbr[1]->offset); |
| 2287 | |
| 2288 | bufsize = (sizeof(struct fbr_desc) * rx_ring->fbr[1]->num_entries) |
| 2289 | + 0xfff; |
| 2290 | |
| 2291 | pci_free_consistent(adapter->pdev, |
| 2292 | bufsize, |
| 2293 | rx_ring->fbr[1]->ring_virtaddr, |
| 2294 | rx_ring->fbr[1]->ring_physaddr); |
| 2295 | |
| 2296 | rx_ring->fbr[1]->ring_virtaddr = NULL; |
| 2297 | } |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2298 | #endif |
| 2299 | |
| 2300 | /* Free Packet Status Ring */ |
| 2301 | if (rx_ring->ps_ring_virtaddr) { |
| 2302 | pktstat_ringsize = |
| 2303 | sizeof(struct pkt_stat_desc) * |
| 2304 | adapter->rx_ring.psr_num_entries; |
| 2305 | |
| 2306 | pci_free_consistent(adapter->pdev, pktstat_ringsize, |
| 2307 | rx_ring->ps_ring_virtaddr, |
| 2308 | rx_ring->ps_ring_physaddr); |
| 2309 | |
| 2310 | rx_ring->ps_ring_virtaddr = NULL; |
| 2311 | } |
| 2312 | |
| 2313 | /* Free area of memory for the writeback of status information */ |
| 2314 | if (rx_ring->rx_status_block) { |
| 2315 | pci_free_consistent(adapter->pdev, |
| 2316 | sizeof(struct rx_status_block), |
| 2317 | rx_ring->rx_status_block, rx_ring->rx_status_bus); |
| 2318 | rx_ring->rx_status_block = NULL; |
| 2319 | } |
| 2320 | |
| 2321 | /* Free receive buffer pool */ |
| 2322 | |
| 2323 | /* Free receive packet pool */ |
| 2324 | |
| 2325 | /* Destroy the lookaside (RFD) pool */ |
| 2326 | if (adapter->flags & fMP_ADAPTER_RECV_LOOKASIDE) { |
| 2327 | kmem_cache_destroy(rx_ring->recv_lookaside); |
| 2328 | adapter->flags &= ~fMP_ADAPTER_RECV_LOOKASIDE; |
| 2329 | } |
| 2330 | |
| 2331 | /* Free the FBR Lookup Table */ |
| 2332 | #ifdef USE_FBR0 |
Mark Einon | e592a9b | 2011-10-20 01:18:42 +0100 | [diff] [blame] | 2333 | kfree(rx_ring->fbr[1]); |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2334 | #endif |
| 2335 | |
Mark Einon | e592a9b | 2011-10-20 01:18:42 +0100 | [diff] [blame] | 2336 | kfree(rx_ring->fbr[0]); |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2337 | |
| 2338 | /* Reset Counters */ |
| 2339 | rx_ring->num_ready_recv = 0; |
| 2340 | } |
| 2341 | |
| 2342 | /** |
| 2343 | * et131x_init_recv - Initialize receive data structures. |
| 2344 | * @adapter: pointer to our private adapter structure |
| 2345 | * |
| 2346 | * Returns 0 on success and errno on failure (as defined in errno.h) |
| 2347 | */ |
| 2348 | int et131x_init_recv(struct et131x_adapter *adapter) |
| 2349 | { |
| 2350 | int status = -ENOMEM; |
| 2351 | struct rfd *rfd = NULL; |
| 2352 | u32 rfdct; |
| 2353 | u32 numrfd = 0; |
| 2354 | struct rx_ring *rx_ring; |
| 2355 | |
| 2356 | /* Setup some convenience pointers */ |
| 2357 | rx_ring = &adapter->rx_ring; |
| 2358 | |
| 2359 | /* Setup each RFD */ |
| 2360 | for (rfdct = 0; rfdct < rx_ring->num_rfd; rfdct++) { |
| 2361 | rfd = kmem_cache_alloc(rx_ring->recv_lookaside, |
| 2362 | GFP_ATOMIC | GFP_DMA); |
| 2363 | |
| 2364 | if (!rfd) { |
| 2365 | dev_err(&adapter->pdev->dev, |
| 2366 | "Couldn't alloc RFD out of kmem_cache\n"); |
| 2367 | status = -ENOMEM; |
| 2368 | continue; |
| 2369 | } |
| 2370 | |
| 2371 | rfd->skb = NULL; |
| 2372 | |
| 2373 | /* Add this RFD to the recv_list */ |
| 2374 | list_add_tail(&rfd->list_node, &rx_ring->recv_list); |
| 2375 | |
| 2376 | /* Increment both the available RFD's, and the total RFD's. */ |
| 2377 | rx_ring->num_ready_recv++; |
| 2378 | numrfd++; |
| 2379 | } |
| 2380 | |
| 2381 | if (numrfd > NIC_MIN_NUM_RFD) |
| 2382 | status = 0; |
| 2383 | |
| 2384 | rx_ring->num_rfd = numrfd; |
| 2385 | |
| 2386 | if (status != 0) { |
| 2387 | kmem_cache_free(rx_ring->recv_lookaside, rfd); |
| 2388 | dev_err(&adapter->pdev->dev, |
| 2389 | "Allocation problems in et131x_init_recv\n"); |
| 2390 | } |
| 2391 | return status; |
| 2392 | } |
| 2393 | |
| 2394 | /** |
| 2395 | * et131x_config_rx_dma_regs - Start of Rx_DMA init sequence |
| 2396 | * @adapter: pointer to our adapter structure |
| 2397 | */ |
| 2398 | void et131x_config_rx_dma_regs(struct et131x_adapter *adapter) |
| 2399 | { |
| 2400 | struct rxdma_regs __iomem *rx_dma = &adapter->regs->rxdma; |
| 2401 | struct rx_ring *rx_local = &adapter->rx_ring; |
| 2402 | struct fbr_desc *fbr_entry; |
| 2403 | u32 entry; |
| 2404 | u32 psr_num_des; |
| 2405 | unsigned long flags; |
| 2406 | |
| 2407 | /* Halt RXDMA to perform the reconfigure. */ |
| 2408 | et131x_rx_dma_disable(adapter); |
| 2409 | |
| 2410 | /* Load the completion writeback physical address |
| 2411 | * |
| 2412 | * NOTE : pci_alloc_consistent(), used above to alloc DMA regions, |
| 2413 | * ALWAYS returns SAC (32-bit) addresses. If DAC (64-bit) addresses |
| 2414 | * are ever returned, make sure the high part is retrieved here |
| 2415 | * before storing the adjusted address. |
| 2416 | */ |
| 2417 | writel((u32) ((u64)rx_local->rx_status_bus >> 32), |
| 2418 | &rx_dma->dma_wb_base_hi); |
| 2419 | writel((u32) rx_local->rx_status_bus, &rx_dma->dma_wb_base_lo); |
| 2420 | |
| 2421 | memset(rx_local->rx_status_block, 0, sizeof(struct rx_status_block)); |
| 2422 | |
| 2423 | /* Set the address and parameters of the packet status ring into the |
| 2424 | * 1310's registers |
| 2425 | */ |
| 2426 | writel((u32) ((u64)rx_local->ps_ring_physaddr >> 32), |
| 2427 | &rx_dma->psr_base_hi); |
| 2428 | writel((u32) rx_local->ps_ring_physaddr, &rx_dma->psr_base_lo); |
| 2429 | writel(rx_local->psr_num_entries - 1, &rx_dma->psr_num_des); |
| 2430 | writel(0, &rx_dma->psr_full_offset); |
| 2431 | |
| 2432 | psr_num_des = readl(&rx_dma->psr_num_des) & 0xFFF; |
| 2433 | writel((psr_num_des * LO_MARK_PERCENT_FOR_PSR) / 100, |
| 2434 | &rx_dma->psr_min_des); |
| 2435 | |
| 2436 | spin_lock_irqsave(&adapter->rcv_lock, flags); |
| 2437 | |
| 2438 | /* These local variables track the PSR in the adapter structure */ |
| 2439 | rx_local->local_psr_full = 0; |
| 2440 | |
| 2441 | /* Now's the best time to initialize FBR1 contents */ |
Mark Einon | 6abafc1 | 2011-10-20 01:18:41 +0100 | [diff] [blame] | 2442 | fbr_entry = (struct fbr_desc *) rx_local->fbr[0]->ring_virtaddr; |
| 2443 | for (entry = 0; entry < rx_local->fbr[0]->num_entries; entry++) { |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2444 | fbr_entry->addr_hi = rx_local->fbr[0]->bus_high[entry]; |
| 2445 | fbr_entry->addr_lo = rx_local->fbr[0]->bus_low[entry]; |
| 2446 | fbr_entry->word2 = entry; |
| 2447 | fbr_entry++; |
| 2448 | } |
| 2449 | |
Mark Einon | e592a9b | 2011-10-20 01:18:42 +0100 | [diff] [blame] | 2450 | /* Set the address and parameters of Free buffer ring 1 (and 0 if |
| 2451 | * required) into the 1310's registers |
| 2452 | */ |
Mark Einon | 6abafc1 | 2011-10-20 01:18:41 +0100 | [diff] [blame] | 2453 | writel((u32) (rx_local->fbr[0]->real_physaddr >> 32), |
Mark Einon | e592a9b | 2011-10-20 01:18:42 +0100 | [diff] [blame] | 2454 | &rx_dma->fbr1_base_hi); |
| 2455 | writel((u32) rx_local->fbr[0]->real_physaddr, &rx_dma->fbr1_base_lo); |
| 2456 | writel(rx_local->fbr[0]->num_entries - 1, &rx_dma->fbr1_num_des); |
| 2457 | writel(ET_DMA10_WRAP, &rx_dma->fbr1_full_offset); |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2458 | |
Mark Einon | e592a9b | 2011-10-20 01:18:42 +0100 | [diff] [blame] | 2459 | /* This variable tracks the free buffer ring 1 full position, so it |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2460 | * has to match the above. |
| 2461 | */ |
Mark Einon | 6abafc1 | 2011-10-20 01:18:41 +0100 | [diff] [blame] | 2462 | rx_local->fbr[0]->local_full = ET_DMA10_WRAP; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2463 | writel( |
Mark Einon | 6abafc1 | 2011-10-20 01:18:41 +0100 | [diff] [blame] | 2464 | ((rx_local->fbr[0]->num_entries * LO_MARK_PERCENT_FOR_RX) / 100) - 1, |
Mark Einon | e592a9b | 2011-10-20 01:18:42 +0100 | [diff] [blame] | 2465 | &rx_dma->fbr1_min_des); |
| 2466 | |
| 2467 | #ifdef USE_FBR0 |
| 2468 | /* Now's the best time to initialize FBR0 contents */ |
| 2469 | fbr_entry = (struct fbr_desc *) rx_local->fbr[1]->ring_virtaddr; |
| 2470 | for (entry = 0; entry < rx_local->fbr[1]->num_entries; entry++) { |
| 2471 | fbr_entry->addr_hi = rx_local->fbr[1]->bus_high[entry]; |
| 2472 | fbr_entry->addr_lo = rx_local->fbr[1]->bus_low[entry]; |
| 2473 | fbr_entry->word2 = entry; |
| 2474 | fbr_entry++; |
| 2475 | } |
| 2476 | |
| 2477 | writel((u32) (rx_local->fbr[1]->real_physaddr >> 32), |
| 2478 | &rx_dma->fbr0_base_hi); |
| 2479 | writel((u32) rx_local->fbr[1]->real_physaddr, &rx_dma->fbr0_base_lo); |
| 2480 | writel(rx_local->fbr[1]->num_entries - 1, &rx_dma->fbr0_num_des); |
| 2481 | writel(ET_DMA10_WRAP, &rx_dma->fbr0_full_offset); |
| 2482 | |
| 2483 | /* This variable tracks the free buffer ring 0 full position, so it |
| 2484 | * has to match the above. |
| 2485 | */ |
| 2486 | rx_local->fbr[1]->local_full = ET_DMA10_WRAP; |
| 2487 | writel( |
| 2488 | ((rx_local->fbr[1]->num_entries * LO_MARK_PERCENT_FOR_RX) / 100) - 1, |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2489 | &rx_dma->fbr0_min_des); |
| 2490 | #endif |
| 2491 | |
| 2492 | /* Program the number of packets we will receive before generating an |
| 2493 | * interrupt. |
| 2494 | * For version B silicon, this value gets updated once autoneg is |
| 2495 | *complete. |
| 2496 | */ |
| 2497 | writel(PARM_RX_NUM_BUFS_DEF, &rx_dma->num_pkt_done); |
| 2498 | |
| 2499 | /* The "time_done" is not working correctly to coalesce interrupts |
| 2500 | * after a given time period, but rather is giving us an interrupt |
| 2501 | * regardless of whether we have received packets. |
| 2502 | * This value gets updated once autoneg is complete. |
| 2503 | */ |
| 2504 | writel(PARM_RX_TIME_INT_DEF, &rx_dma->max_pkt_time); |
| 2505 | |
| 2506 | spin_unlock_irqrestore(&adapter->rcv_lock, flags); |
| 2507 | } |
| 2508 | |
| 2509 | /** |
| 2510 | * et131x_set_rx_dma_timer - Set the heartbeat timer according to line rate. |
| 2511 | * @adapter: pointer to our adapter structure |
| 2512 | */ |
| 2513 | void et131x_set_rx_dma_timer(struct et131x_adapter *adapter) |
| 2514 | { |
| 2515 | struct phy_device *phydev = adapter->phydev; |
| 2516 | |
| 2517 | if (!phydev) |
| 2518 | return; |
| 2519 | |
| 2520 | /* For version B silicon, we do not use the RxDMA timer for 10 and 100 |
| 2521 | * Mbits/s line rates. We do not enable and RxDMA interrupt coalescing. |
| 2522 | */ |
| 2523 | if ((phydev->speed == SPEED_100) || (phydev->speed == SPEED_10)) { |
| 2524 | writel(0, &adapter->regs->rxdma.max_pkt_time); |
| 2525 | writel(1, &adapter->regs->rxdma.num_pkt_done); |
| 2526 | } |
| 2527 | } |
| 2528 | |
| 2529 | /** |
| 2530 | * NICReturnRFD - Recycle a RFD and put it back onto the receive list |
| 2531 | * @adapter: pointer to our adapter |
| 2532 | * @rfd: pointer to the RFD |
| 2533 | */ |
| 2534 | static void nic_return_rfd(struct et131x_adapter *adapter, struct rfd *rfd) |
| 2535 | { |
| 2536 | struct rx_ring *rx_local = &adapter->rx_ring; |
| 2537 | struct rxdma_regs __iomem *rx_dma = &adapter->regs->rxdma; |
| 2538 | u16 buff_index = rfd->bufferindex; |
| 2539 | u8 ring_index = rfd->ringindex; |
| 2540 | unsigned long flags; |
| 2541 | |
| 2542 | /* We don't use any of the OOB data besides status. Otherwise, we |
| 2543 | * need to clean up OOB data |
| 2544 | */ |
| 2545 | if ( |
| 2546 | #ifdef USE_FBR0 |
Mark Einon | e592a9b | 2011-10-20 01:18:42 +0100 | [diff] [blame] | 2547 | (ring_index == 0 && buff_index < rx_local->fbr[1]->num_entries) || |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2548 | #endif |
Mark Einon | e592a9b | 2011-10-20 01:18:42 +0100 | [diff] [blame] | 2549 | (ring_index == 1 && buff_index < rx_local->fbr[0]->num_entries)) { |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2550 | spin_lock_irqsave(&adapter->fbr_lock, flags); |
| 2551 | |
| 2552 | if (ring_index == 1) { |
| 2553 | struct fbr_desc *next = |
Mark Einon | e592a9b | 2011-10-20 01:18:42 +0100 | [diff] [blame] | 2554 | (struct fbr_desc *) (rx_local->fbr[0]->ring_virtaddr) + |
| 2555 | INDEX10(rx_local->fbr[0]->local_full); |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2556 | |
| 2557 | /* Handle the Free Buffer Ring advancement here. Write |
| 2558 | * the PA / Buffer Index for the returned buffer into |
| 2559 | * the oldest (next to be freed)FBR entry |
| 2560 | */ |
Mark Einon | e592a9b | 2011-10-20 01:18:42 +0100 | [diff] [blame] | 2561 | next->addr_hi = rx_local->fbr[0]->bus_high[buff_index]; |
| 2562 | next->addr_lo = rx_local->fbr[0]->bus_low[buff_index]; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2563 | next->word2 = buff_index; |
| 2564 | |
Mark Einon | e592a9b | 2011-10-20 01:18:42 +0100 | [diff] [blame] | 2565 | writel(bump_free_buff_ring(&rx_local->fbr[0]->local_full, |
| 2566 | rx_local->fbr[0]->num_entries - 1), |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2567 | &rx_dma->fbr1_full_offset); |
| 2568 | } |
| 2569 | #ifdef USE_FBR0 |
| 2570 | else { |
| 2571 | struct fbr_desc *next = (struct fbr_desc *) |
Mark Einon | e592a9b | 2011-10-20 01:18:42 +0100 | [diff] [blame] | 2572 | rx_local->fbr[1]->ring_virtaddr + |
| 2573 | INDEX10(rx_local->fbr[1]->local_full); |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2574 | |
| 2575 | /* Handle the Free Buffer Ring advancement here. Write |
| 2576 | * the PA / Buffer Index for the returned buffer into |
| 2577 | * the oldest (next to be freed) FBR entry |
| 2578 | */ |
Mark Einon | e592a9b | 2011-10-20 01:18:42 +0100 | [diff] [blame] | 2579 | next->addr_hi = rx_local->fbr[1]->bus_high[buff_index]; |
| 2580 | next->addr_lo = rx_local->fbr[1]->bus_low[buff_index]; |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2581 | next->word2 = buff_index; |
| 2582 | |
Mark Einon | 6abafc1 | 2011-10-20 01:18:41 +0100 | [diff] [blame] | 2583 | writel(bump_free_buff_ring( |
Mark Einon | e592a9b | 2011-10-20 01:18:42 +0100 | [diff] [blame] | 2584 | &rx_local->fbr[1]->local_full, |
| 2585 | rx_local->fbr[1]->num_entries - 1), |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2586 | &rx_dma->fbr0_full_offset); |
| 2587 | } |
| 2588 | #endif |
| 2589 | spin_unlock_irqrestore(&adapter->fbr_lock, flags); |
| 2590 | } else { |
| 2591 | dev_err(&adapter->pdev->dev, |
| 2592 | "%s illegal Buffer Index returned\n", __func__); |
| 2593 | } |
| 2594 | |
| 2595 | /* The processing on this RFD is done, so put it back on the tail of |
| 2596 | * our list |
| 2597 | */ |
| 2598 | spin_lock_irqsave(&adapter->rcv_lock, flags); |
| 2599 | list_add_tail(&rfd->list_node, &rx_local->recv_list); |
| 2600 | rx_local->num_ready_recv++; |
| 2601 | spin_unlock_irqrestore(&adapter->rcv_lock, flags); |
| 2602 | |
| 2603 | WARN_ON(rx_local->num_ready_recv > rx_local->num_rfd); |
| 2604 | } |
| 2605 | |
| 2606 | /** |
| 2607 | * et131x_rx_dma_disable - Stop of Rx_DMA on the ET1310 |
| 2608 | * @adapter: pointer to our adapter structure |
| 2609 | */ |
| 2610 | void et131x_rx_dma_disable(struct et131x_adapter *adapter) |
| 2611 | { |
| 2612 | u32 csr; |
| 2613 | /* Setup the receive dma configuration register */ |
| 2614 | writel(0x00002001, &adapter->regs->rxdma.csr); |
| 2615 | csr = readl(&adapter->regs->rxdma.csr); |
| 2616 | if ((csr & 0x00020000) == 0) { /* Check halt status (bit 17) */ |
| 2617 | udelay(5); |
| 2618 | csr = readl(&adapter->regs->rxdma.csr); |
| 2619 | if ((csr & 0x00020000) == 0) |
| 2620 | dev_err(&adapter->pdev->dev, |
| 2621 | "RX Dma failed to enter halt state. CSR 0x%08x\n", |
| 2622 | csr); |
| 2623 | } |
| 2624 | } |
| 2625 | |
| 2626 | /** |
| 2627 | * et131x_rx_dma_enable - re-start of Rx_DMA on the ET1310. |
| 2628 | * @adapter: pointer to our adapter structure |
| 2629 | */ |
| 2630 | void et131x_rx_dma_enable(struct et131x_adapter *adapter) |
| 2631 | { |
| 2632 | /* Setup the receive dma configuration register for normal operation */ |
| 2633 | u32 csr = 0x2000; /* FBR1 enable */ |
| 2634 | |
Mark Einon | e592a9b | 2011-10-20 01:18:42 +0100 | [diff] [blame] | 2635 | if (adapter->rx_ring.fbr[0]->buffsize == 4096) |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2636 | csr |= 0x0800; |
Mark Einon | e592a9b | 2011-10-20 01:18:42 +0100 | [diff] [blame] | 2637 | else if (adapter->rx_ring.fbr[0]->buffsize == 8192) |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2638 | csr |= 0x1000; |
Mark Einon | e592a9b | 2011-10-20 01:18:42 +0100 | [diff] [blame] | 2639 | else if (adapter->rx_ring.fbr[0]->buffsize == 16384) |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2640 | csr |= 0x1800; |
| 2641 | #ifdef USE_FBR0 |
| 2642 | csr |= 0x0400; /* FBR0 enable */ |
Mark Einon | e592a9b | 2011-10-20 01:18:42 +0100 | [diff] [blame] | 2643 | if (adapter->rx_ring.fbr[1]->buffsize == 256) |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2644 | csr |= 0x0100; |
Mark Einon | e592a9b | 2011-10-20 01:18:42 +0100 | [diff] [blame] | 2645 | else if (adapter->rx_ring.fbr[1]->buffsize == 512) |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2646 | csr |= 0x0200; |
Mark Einon | e592a9b | 2011-10-20 01:18:42 +0100 | [diff] [blame] | 2647 | else if (adapter->rx_ring.fbr[1]->buffsize == 1024) |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2648 | csr |= 0x0300; |
| 2649 | #endif |
| 2650 | writel(csr, &adapter->regs->rxdma.csr); |
| 2651 | |
| 2652 | csr = readl(&adapter->regs->rxdma.csr); |
| 2653 | if ((csr & 0x00020000) != 0) { |
| 2654 | udelay(5); |
| 2655 | csr = readl(&adapter->regs->rxdma.csr); |
| 2656 | if ((csr & 0x00020000) != 0) { |
| 2657 | dev_err(&adapter->pdev->dev, |
| 2658 | "RX Dma failed to exit halt state. CSR 0x%08x\n", |
| 2659 | csr); |
| 2660 | } |
| 2661 | } |
| 2662 | } |
| 2663 | |
Mark Einon | 920d74a | 2011-10-20 01:18:40 +0100 | [diff] [blame] | 2664 | |
| 2665 | static inline void add_10bit(u32 *v, int n) |
| 2666 | { |
| 2667 | *v = INDEX10(*v + n) | (*v & ET_DMA10_WRAP); |
| 2668 | } |
| 2669 | |
| 2670 | static inline void add_12bit(u32 *v, int n) |
| 2671 | { |
| 2672 | *v = INDEX12(*v + n) | (*v & ET_DMA12_WRAP); |
| 2673 | } |
| 2674 | |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2675 | /** |
| 2676 | * nic_rx_pkts - Checks the hardware for available packets |
| 2677 | * @adapter: pointer to our adapter |
| 2678 | * |
| 2679 | * Returns rfd, a pointer to our MPRFD. |
| 2680 | * |
| 2681 | * Checks the hardware for available packets, using completion ring |
| 2682 | * If packets are available, it gets an RFD from the recv_list, attaches |
| 2683 | * the packet to it, puts the RFD in the RecvPendList, and also returns |
| 2684 | * the pointer to the RFD. |
| 2685 | */ |
| 2686 | static struct rfd *nic_rx_pkts(struct et131x_adapter *adapter) |
| 2687 | { |
| 2688 | struct rx_ring *rx_local = &adapter->rx_ring; |
| 2689 | struct rx_status_block *status; |
| 2690 | struct pkt_stat_desc *psr; |
| 2691 | struct rfd *rfd; |
| 2692 | u32 i; |
| 2693 | u8 *buf; |
| 2694 | unsigned long flags; |
| 2695 | struct list_head *element; |
| 2696 | u8 ring_index; |
| 2697 | u16 buff_index; |
| 2698 | u32 len; |
| 2699 | u32 word0; |
| 2700 | u32 word1; |
| 2701 | |
| 2702 | /* RX Status block is written by the DMA engine prior to every |
| 2703 | * interrupt. It contains the next to be used entry in the Packet |
| 2704 | * Status Ring, and also the two Free Buffer rings. |
| 2705 | */ |
| 2706 | status = rx_local->rx_status_block; |
| 2707 | word1 = status->word1 >> 16; /* Get the useful bits */ |
| 2708 | |
| 2709 | /* Check the PSR and wrap bits do not match */ |
| 2710 | if ((word1 & 0x1FFF) == (rx_local->local_psr_full & 0x1FFF)) |
| 2711 | /* Looks like this ring is not updated yet */ |
| 2712 | return NULL; |
| 2713 | |
| 2714 | /* The packet status ring indicates that data is available. */ |
| 2715 | psr = (struct pkt_stat_desc *) (rx_local->ps_ring_virtaddr) + |
| 2716 | (rx_local->local_psr_full & 0xFFF); |
| 2717 | |
| 2718 | /* Grab any information that is required once the PSR is |
| 2719 | * advanced, since we can no longer rely on the memory being |
| 2720 | * accurate |
| 2721 | */ |
| 2722 | len = psr->word1 & 0xFFFF; |
| 2723 | ring_index = (psr->word1 >> 26) & 0x03; |
| 2724 | buff_index = (psr->word1 >> 16) & 0x3FF; |
| 2725 | word0 = psr->word0; |
| 2726 | |
| 2727 | /* Indicate that we have used this PSR entry. */ |
| 2728 | /* FIXME wrap 12 */ |
| 2729 | add_12bit(&rx_local->local_psr_full, 1); |
| 2730 | if ( |
| 2731 | (rx_local->local_psr_full & 0xFFF) > rx_local->psr_num_entries - 1) { |
| 2732 | /* Clear psr full and toggle the wrap bit */ |
| 2733 | rx_local->local_psr_full &= ~0xFFF; |
| 2734 | rx_local->local_psr_full ^= 0x1000; |
| 2735 | } |
| 2736 | |
| 2737 | writel(rx_local->local_psr_full, |
| 2738 | &adapter->regs->rxdma.psr_full_offset); |
| 2739 | |
| 2740 | #ifndef USE_FBR0 |
| 2741 | if (ring_index != 1) |
| 2742 | return NULL; |
| 2743 | #endif |
| 2744 | |
| 2745 | #ifdef USE_FBR0 |
| 2746 | if (ring_index > 1 || |
| 2747 | (ring_index == 0 && |
Mark Einon | e592a9b | 2011-10-20 01:18:42 +0100 | [diff] [blame] | 2748 | buff_index > rx_local->fbr[1]->num_entries - 1) || |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2749 | (ring_index == 1 && |
Mark Einon | e592a9b | 2011-10-20 01:18:42 +0100 | [diff] [blame] | 2750 | buff_index > rx_local->fbr[0]->num_entries - 1)) |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2751 | #else |
Mark Einon | e592a9b | 2011-10-20 01:18:42 +0100 | [diff] [blame] | 2752 | if (ring_index != 1 || buff_index > rx_local->fbr[0]->num_entries - 1) |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2753 | #endif |
| 2754 | { |
| 2755 | /* Illegal buffer or ring index cannot be used by S/W*/ |
| 2756 | dev_err(&adapter->pdev->dev, |
| 2757 | "NICRxPkts PSR Entry %d indicates " |
| 2758 | "length of %d and/or bad bi(%d)\n", |
| 2759 | rx_local->local_psr_full & 0xFFF, |
| 2760 | len, buff_index); |
| 2761 | return NULL; |
| 2762 | } |
| 2763 | |
| 2764 | /* Get and fill the RFD. */ |
| 2765 | spin_lock_irqsave(&adapter->rcv_lock, flags); |
| 2766 | |
| 2767 | rfd = NULL; |
| 2768 | element = rx_local->recv_list.next; |
| 2769 | rfd = (struct rfd *) list_entry(element, struct rfd, list_node); |
| 2770 | |
| 2771 | if (rfd == NULL) { |
| 2772 | spin_unlock_irqrestore(&adapter->rcv_lock, flags); |
| 2773 | return NULL; |
| 2774 | } |
| 2775 | |
| 2776 | list_del(&rfd->list_node); |
| 2777 | rx_local->num_ready_recv--; |
| 2778 | |
| 2779 | spin_unlock_irqrestore(&adapter->rcv_lock, flags); |
| 2780 | |
| 2781 | rfd->bufferindex = buff_index; |
| 2782 | rfd->ringindex = ring_index; |
| 2783 | |
| 2784 | /* In V1 silicon, there is a bug which screws up filtering of |
| 2785 | * runt packets. Therefore runt packet filtering is disabled |
| 2786 | * in the MAC and the packets are dropped here. They are |
| 2787 | * also counted here. |
| 2788 | */ |
| 2789 | if (len < (NIC_MIN_PACKET_SIZE + 4)) { |
| 2790 | adapter->stats.rx_other_errs++; |
| 2791 | len = 0; |
| 2792 | } |
| 2793 | |
| 2794 | if (len) { |
| 2795 | /* Determine if this is a multicast packet coming in */ |
| 2796 | if ((word0 & ALCATEL_MULTICAST_PKT) && |
| 2797 | !(word0 & ALCATEL_BROADCAST_PKT)) { |
| 2798 | /* Promiscuous mode and Multicast mode are |
| 2799 | * not mutually exclusive as was first |
| 2800 | * thought. I guess Promiscuous is just |
| 2801 | * considered a super-set of the other |
| 2802 | * filters. Generally filter is 0x2b when in |
| 2803 | * promiscuous mode. |
| 2804 | */ |
| 2805 | if ((adapter->packet_filter & |
| 2806 | ET131X_PACKET_TYPE_MULTICAST) |
| 2807 | && !(adapter->packet_filter & |
| 2808 | ET131X_PACKET_TYPE_PROMISCUOUS) |
| 2809 | && !(adapter->packet_filter & |
| 2810 | ET131X_PACKET_TYPE_ALL_MULTICAST)) { |
Mark Einon | e592a9b | 2011-10-20 01:18:42 +0100 | [diff] [blame] | 2811 | /* |
| 2812 | * Note - ring_index for fbr[] array is reversed |
| 2813 | * 1 for FBR0 etc |
| 2814 | */ |
| 2815 | buf = rx_local->fbr[(ring_index == 0 ? 1 : 0)]-> |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2816 | virt[buff_index]; |
| 2817 | |
| 2818 | /* Loop through our list to see if the |
| 2819 | * destination address of this packet |
| 2820 | * matches one in our list. |
| 2821 | */ |
| 2822 | for (i = 0; i < adapter->multicast_addr_count; |
| 2823 | i++) { |
| 2824 | if (buf[0] == |
| 2825 | adapter->multicast_list[i][0] |
| 2826 | && buf[1] == |
| 2827 | adapter->multicast_list[i][1] |
| 2828 | && buf[2] == |
| 2829 | adapter->multicast_list[i][2] |
| 2830 | && buf[3] == |
| 2831 | adapter->multicast_list[i][3] |
| 2832 | && buf[4] == |
| 2833 | adapter->multicast_list[i][4] |
| 2834 | && buf[5] == |
| 2835 | adapter->multicast_list[i][5]) { |
| 2836 | break; |
| 2837 | } |
| 2838 | } |
| 2839 | |
| 2840 | /* If our index is equal to the number |
| 2841 | * of Multicast address we have, then |
| 2842 | * this means we did not find this |
| 2843 | * packet's matching address in our |
| 2844 | * list. Set the len to zero, |
| 2845 | * so we free our RFD when we return |
| 2846 | * from this function. |
| 2847 | */ |
| 2848 | if (i == adapter->multicast_addr_count) |
| 2849 | len = 0; |
| 2850 | } |
| 2851 | |
| 2852 | if (len > 0) |
| 2853 | adapter->stats.multicast_pkts_rcvd++; |
| 2854 | } else if (word0 & ALCATEL_BROADCAST_PKT) |
| 2855 | adapter->stats.broadcast_pkts_rcvd++; |
| 2856 | else |
| 2857 | /* Not sure what this counter measures in |
| 2858 | * promiscuous mode. Perhaps we should check |
| 2859 | * the MAC address to see if it is directed |
| 2860 | * to us in promiscuous mode. |
| 2861 | */ |
| 2862 | adapter->stats.unicast_pkts_rcvd++; |
| 2863 | } |
| 2864 | |
| 2865 | if (len > 0) { |
| 2866 | struct sk_buff *skb = NULL; |
| 2867 | |
| 2868 | /*rfd->len = len - 4; */ |
| 2869 | rfd->len = len; |
| 2870 | |
| 2871 | skb = dev_alloc_skb(rfd->len + 2); |
| 2872 | if (!skb) { |
| 2873 | dev_err(&adapter->pdev->dev, |
| 2874 | "Couldn't alloc an SKB for Rx\n"); |
| 2875 | return NULL; |
| 2876 | } |
| 2877 | |
| 2878 | adapter->net_stats.rx_bytes += rfd->len; |
| 2879 | |
Mark Einon | e592a9b | 2011-10-20 01:18:42 +0100 | [diff] [blame] | 2880 | /* |
| 2881 | * Note - ring_index for fbr[] array is reversed, |
| 2882 | * 1 for FBR0 etc |
| 2883 | */ |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2884 | memcpy(skb_put(skb, rfd->len), |
Mark Einon | e592a9b | 2011-10-20 01:18:42 +0100 | [diff] [blame] | 2885 | rx_local->fbr[(ring_index == 0 ? 1 : 0)]->virt[buff_index], |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 2886 | rfd->len); |
| 2887 | |
| 2888 | skb->dev = adapter->netdev; |
| 2889 | skb->protocol = eth_type_trans(skb, adapter->netdev); |
| 2890 | skb->ip_summed = CHECKSUM_NONE; |
| 2891 | |
| 2892 | netif_rx(skb); |
| 2893 | } else { |
| 2894 | rfd->len = 0; |
| 2895 | } |
| 2896 | |
| 2897 | nic_return_rfd(adapter, rfd); |
| 2898 | return rfd; |
| 2899 | } |
| 2900 | |
| 2901 | /** |
| 2902 | * et131x_reset_recv - Reset the receive list |
| 2903 | * @adapter: pointer to our adapter |
| 2904 | * |
| 2905 | * Assumption, Rcv spinlock has been acquired. |
| 2906 | */ |
| 2907 | void et131x_reset_recv(struct et131x_adapter *adapter) |
| 2908 | { |
| 2909 | WARN_ON(list_empty(&adapter->rx_ring.recv_list)); |
| 2910 | } |
| 2911 | |
| 2912 | /** |
| 2913 | * et131x_handle_recv_interrupt - Interrupt handler for receive processing |
| 2914 | * @adapter: pointer to our adapter |
| 2915 | * |
| 2916 | * Assumption, Rcv spinlock has been acquired. |
| 2917 | */ |
| 2918 | void et131x_handle_recv_interrupt(struct et131x_adapter *adapter) |
| 2919 | { |
| 2920 | struct rfd *rfd = NULL; |
| 2921 | u32 count = 0; |
| 2922 | bool done = true; |
| 2923 | |
| 2924 | /* Process up to available RFD's */ |
| 2925 | while (count < NUM_PACKETS_HANDLED) { |
| 2926 | if (list_empty(&adapter->rx_ring.recv_list)) { |
| 2927 | WARN_ON(adapter->rx_ring.num_ready_recv != 0); |
| 2928 | done = false; |
| 2929 | break; |
| 2930 | } |
| 2931 | |
| 2932 | rfd = nic_rx_pkts(adapter); |
| 2933 | |
| 2934 | if (rfd == NULL) |
| 2935 | break; |
| 2936 | |
| 2937 | /* Do not receive any packets until a filter has been set. |
| 2938 | * Do not receive any packets until we have link. |
| 2939 | * If length is zero, return the RFD in order to advance the |
| 2940 | * Free buffer ring. |
| 2941 | */ |
| 2942 | if (!adapter->packet_filter || |
| 2943 | !netif_carrier_ok(adapter->netdev) || |
| 2944 | rfd->len == 0) |
| 2945 | continue; |
| 2946 | |
| 2947 | /* Increment the number of packets we received */ |
| 2948 | adapter->net_stats.rx_packets++; |
| 2949 | |
| 2950 | /* Set the status on the packet, either resources or success */ |
| 2951 | if (adapter->rx_ring.num_ready_recv < RFD_LOW_WATER_MARK) { |
| 2952 | dev_warn(&adapter->pdev->dev, |
| 2953 | "RFD's are running out\n"); |
| 2954 | } |
| 2955 | count++; |
| 2956 | } |
| 2957 | |
| 2958 | if (count == NUM_PACKETS_HANDLED || !done) { |
| 2959 | adapter->rx_ring.unfinished_receives = true; |
| 2960 | writel(PARM_TX_TIME_INT_DEF * NANO_IN_A_MICRO, |
| 2961 | &adapter->regs->global.watchdog_timer); |
| 2962 | } else |
| 2963 | /* Watchdog timer will disable itself if appropriate. */ |
| 2964 | adapter->rx_ring.unfinished_receives = false; |
| 2965 | } |
| 2966 | |
| 2967 | /* TX functions */ |
| 2968 | |
| 2969 | /** |
| 2970 | * et131x_tx_dma_memory_alloc |
| 2971 | * @adapter: pointer to our private adapter structure |
| 2972 | * |
| 2973 | * Returns 0 on success and errno on failure (as defined in errno.h). |
| 2974 | * |
| 2975 | * Allocates memory that will be visible both to the device and to the CPU. |
| 2976 | * The OS will pass us packets, pointers to which we will insert in the Tx |
| 2977 | * Descriptor queue. The device will read this queue to find the packets in |
| 2978 | * memory. The device will update the "status" in memory each time it xmits a |
| 2979 | * packet. |
| 2980 | */ |
| 2981 | int et131x_tx_dma_memory_alloc(struct et131x_adapter *adapter) |
| 2982 | { |
| 2983 | int desc_size = 0; |
| 2984 | struct tx_ring *tx_ring = &adapter->tx_ring; |
| 2985 | |
| 2986 | /* Allocate memory for the TCB's (Transmit Control Block) */ |
| 2987 | adapter->tx_ring.tcb_ring = |
| 2988 | kcalloc(NUM_TCB, sizeof(struct tcb), GFP_ATOMIC | GFP_DMA); |
| 2989 | if (!adapter->tx_ring.tcb_ring) { |
| 2990 | dev_err(&adapter->pdev->dev, "Cannot alloc memory for TCBs\n"); |
| 2991 | return -ENOMEM; |
| 2992 | } |
| 2993 | |
| 2994 | /* Allocate enough memory for the Tx descriptor ring, and allocate |
| 2995 | * some extra so that the ring can be aligned on a 4k boundary. |
| 2996 | */ |
| 2997 | desc_size = (sizeof(struct tx_desc) * NUM_DESC_PER_RING_TX) + 4096 - 1; |
| 2998 | tx_ring->tx_desc_ring = |
Mark Einon | 0d1b7a8 | 2011-10-20 01:18:43 +0100 | [diff] [blame^] | 2999 | (struct tx_desc *) dma_alloc_coherent(&adapter->pdev->dev, desc_size, |
| 3000 | &tx_ring->tx_desc_ring_pa, GFP_KERNEL); |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3001 | if (!adapter->tx_ring.tx_desc_ring) { |
| 3002 | dev_err(&adapter->pdev->dev, |
| 3003 | "Cannot alloc memory for Tx Ring\n"); |
| 3004 | return -ENOMEM; |
| 3005 | } |
| 3006 | |
| 3007 | /* Save physical address |
| 3008 | * |
| 3009 | * NOTE: pci_alloc_consistent(), used above to alloc DMA regions, |
| 3010 | * ALWAYS returns SAC (32-bit) addresses. If DAC (64-bit) addresses |
| 3011 | * are ever returned, make sure the high part is retrieved here before |
| 3012 | * storing the adjusted address. |
| 3013 | */ |
| 3014 | /* Allocate memory for the Tx status block */ |
Mark Einon | 0d1b7a8 | 2011-10-20 01:18:43 +0100 | [diff] [blame^] | 3015 | tx_ring->tx_status = dma_alloc_coherent(&adapter->pdev->dev, |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3016 | sizeof(u32), |
Mark Einon | 0d1b7a8 | 2011-10-20 01:18:43 +0100 | [diff] [blame^] | 3017 | &tx_ring->tx_status_pa, |
| 3018 | GFP_KERNEL); |
Mark Einon | d279674 | 2011-10-20 01:18:30 +0100 | [diff] [blame] | 3019 | if (!adapter->tx_ring.tx_status_pa) { |
| 3020 | dev_err(&adapter->pdev->dev, |
| 3021 | "Cannot alloc memory for Tx status block\n"); |
| 3022 | return -ENOMEM; |
| 3023 | } |
| 3024 | return 0; |
| 3025 | } |
| 3026 | |
| 3027 | /** |
| 3028 | * et131x_tx_dma_memory_free - Free all memory allocated within this module |
| 3029 | * @adapter: pointer to our private adapter structure |
| 3030 | * |
| 3031 | * Returns 0 on success and errno on failure (as defined in errno.h). |
| 3032 | */ |
| 3033 | void et131x_tx_dma_memory_free(struct et131x_adapter *adapter) |
| 3034 | { |
| 3035 | int desc_size = 0; |
| 3036 | |
| 3037 | if (adapter->tx_ring.tx_desc_ring) { |
| 3038 | /* Free memory relating to Tx rings here */ |
| 3039 | desc_size = (sizeof(struct tx_desc) * NUM_DESC_PER_RING_TX) |
| 3040 | + 4096 - 1; |
| 3041 | pci_free_consistent(adapter->pdev, |
| 3042 | desc_size, |
| 3043 | adapter->tx_ring.tx_desc_ring, |
| 3044 | adapter->tx_ring.tx_desc_ring_pa); |
| 3045 | adapter->tx_ring.tx_desc_ring = NULL; |
| 3046 | } |
| 3047 | |
| 3048 | /* Free memory for the Tx status block */ |
| 3049 | if (adapter->tx_ring.tx_status) { |
| 3050 | pci_free_consistent(adapter->pdev, |
| 3051 | sizeof(u32), |
| 3052 | adapter->tx_ring.tx_status, |
| 3053 | adapter->tx_ring.tx_status_pa); |
| 3054 | |
| 3055 | adapter->tx_ring.tx_status = NULL; |
| 3056 | } |
| 3057 | /* Free the memory for the tcb structures */ |
| 3058 | kfree(adapter->tx_ring.tcb_ring); |
| 3059 | } |
| 3060 | |
| 3061 | /** |
| 3062 | * et131x_config_tx_dma_regs - Set up the tx dma section of the JAGCore. |
| 3063 | * @adapter: pointer to our private adapter structure |
| 3064 | * |
| 3065 | * Configure the transmit engine with the ring buffers we have created |
| 3066 | * and prepare it for use. |
| 3067 | */ |
| 3068 | void et131x_config_tx_dma_regs(struct et131x_adapter *adapter) |
| 3069 | { |
| 3070 | struct txdma_regs __iomem *txdma = &adapter->regs->txdma; |
| 3071 | |
| 3072 | /* Load the hardware with the start of the transmit descriptor ring. */ |
| 3073 | writel((u32) ((u64)adapter->tx_ring.tx_desc_ring_pa >> 32), |
| 3074 | &txdma->pr_base_hi); |
| 3075 | writel((u32) adapter->tx_ring.tx_desc_ring_pa, |
| 3076 | &txdma->pr_base_lo); |
| 3077 | |
| 3078 | /* Initialise the transmit DMA engine */ |
| 3079 | writel(NUM_DESC_PER_RING_TX - 1, &txdma->pr_num_des); |
| 3080 | |
| 3081 | /* Load the completion writeback physical address */ |
| 3082 | writel((u32)((u64)adapter->tx_ring.tx_status_pa >> 32), |
| 3083 | &txdma->dma_wb_base_hi); |
| 3084 | writel((u32)adapter->tx_ring.tx_status_pa, &txdma->dma_wb_base_lo); |
| 3085 | |
| 3086 | *adapter->tx_ring.tx_status = 0; |
| 3087 | |
| 3088 | writel(0, &txdma->service_request); |
| 3089 | adapter->tx_ring.send_idx = 0; |
| 3090 | } |
| 3091 | |
| 3092 | /** |
| 3093 | * et131x_tx_dma_disable - Stop of Tx_DMA on the ET1310 |
| 3094 | * @adapter: pointer to our adapter structure |
| 3095 | */ |
| 3096 | void et131x_tx_dma_disable(struct et131x_adapter *adapter) |
| 3097 | { |
| 3098 | /* Setup the tramsmit dma configuration register */ |
| 3099 | writel(ET_TXDMA_CSR_HALT|ET_TXDMA_SNGL_EPKT, |
| 3100 | &adapter->regs->txdma.csr); |
| 3101 | } |
| 3102 | |
| 3103 | /** |
| 3104 | * et131x_tx_dma_enable - re-start of Tx_DMA on the ET1310. |
| 3105 | * @adapter: pointer to our adapter structure |
| 3106 | * |
| 3107 | * Mainly used after a return to the D0 (full-power) state from a lower state. |
| 3108 | */ |
| 3109 | void et131x_tx_dma_enable(struct et131x_adapter *adapter) |
| 3110 | { |
| 3111 | /* Setup the transmit dma configuration register for normal |
| 3112 | * operation |
| 3113 | */ |
| 3114 | writel(ET_TXDMA_SNGL_EPKT|(PARM_DMA_CACHE_DEF << ET_TXDMA_CACHE_SHIFT), |
| 3115 | &adapter->regs->txdma.csr); |
| 3116 | } |
| 3117 | |
| 3118 | /** |
| 3119 | * et131x_init_send - Initialize send data structures |
| 3120 | * @adapter: pointer to our private adapter structure |
| 3121 | */ |
| 3122 | void et131x_init_send(struct et131x_adapter *adapter) |
| 3123 | { |
| 3124 | struct tcb *tcb; |
| 3125 | u32 ct; |
| 3126 | struct tx_ring *tx_ring; |
| 3127 | |
| 3128 | /* Setup some convenience pointers */ |
| 3129 | tx_ring = &adapter->tx_ring; |
| 3130 | tcb = adapter->tx_ring.tcb_ring; |
| 3131 | |
| 3132 | tx_ring->tcb_qhead = tcb; |
| 3133 | |
| 3134 | memset(tcb, 0, sizeof(struct tcb) * NUM_TCB); |
| 3135 | |
| 3136 | /* Go through and set up each TCB */ |
| 3137 | for (ct = 0; ct++ < NUM_TCB; tcb++) |
| 3138 | /* Set the link pointer in HW TCB to the next TCB in the |
| 3139 | * chain |
| 3140 | */ |
| 3141 | tcb->next = tcb + 1; |
| 3142 | |
| 3143 | /* Set the tail pointer */ |
| 3144 | tcb--; |
| 3145 | tx_ring->tcb_qtail = tcb; |
| 3146 | tcb->next = NULL; |
| 3147 | /* Curr send queue should now be empty */ |
| 3148 | tx_ring->send_head = NULL; |
| 3149 | tx_ring->send_tail = NULL; |
| 3150 | } |
| 3151 | |
| 3152 | /** |
| 3153 | * nic_send_packet - NIC specific send handler for version B silicon. |
| 3154 | * @adapter: pointer to our adapter |
| 3155 | * @tcb: pointer to struct tcb |
| 3156 | * |
| 3157 | * Returns 0 or errno. |
| 3158 | */ |
| 3159 | static int nic_send_packet(struct et131x_adapter *adapter, struct tcb *tcb) |
| 3160 | { |
| 3161 | u32 i; |
| 3162 | struct tx_desc desc[24]; /* 24 x 16 byte */ |
| 3163 | u32 frag = 0; |
| 3164 | u32 thiscopy, remainder; |
| 3165 | struct sk_buff *skb = tcb->skb; |
| 3166 | u32 nr_frags = skb_shinfo(skb)->nr_frags + 1; |
| 3167 | struct skb_frag_struct *frags = &skb_shinfo(skb)->frags[0]; |
| 3168 | unsigned long flags; |
| 3169 | struct phy_device *phydev = adapter->phydev; |
| 3170 | |
| 3171 | /* Part of the optimizations of this send routine restrict us to |
| 3172 | * sending 24 fragments at a pass. In practice we should never see |
| 3173 | * more than 5 fragments. |
| 3174 | * |
| 3175 | * NOTE: The older version of this function (below) can handle any |
| 3176 | * number of fragments. If needed, we can call this function, |
| 3177 | * although it is less efficient. |
| 3178 | */ |
| 3179 | if (nr_frags > 23) |
| 3180 | return -EIO; |
| 3181 | |
| 3182 | memset(desc, 0, sizeof(struct tx_desc) * (nr_frags + 1)); |
| 3183 | |
| 3184 | for (i = 0; i < nr_frags; i++) { |
| 3185 | /* If there is something in this element, lets get a |
| 3186 | * descriptor from the ring and get the necessary data |
| 3187 | */ |
| 3188 | if (i == 0) { |
| 3189 | /* If the fragments are smaller than a standard MTU, |
| 3190 | * then map them to a single descriptor in the Tx |
| 3191 | * Desc ring. However, if they're larger, as is |
| 3192 | * possible with support for jumbo packets, then |
| 3193 | * split them each across 2 descriptors. |
| 3194 | * |
| 3195 | * This will work until we determine why the hardware |
| 3196 | * doesn't seem to like large fragments. |
| 3197 | */ |
| 3198 | if ((skb->len - skb->data_len) <= 1514) { |
| 3199 | desc[frag].addr_hi = 0; |
| 3200 | /* Low 16bits are length, high is vlan and |
| 3201 | unused currently so zero */ |
| 3202 | desc[frag].len_vlan = |
| 3203 | skb->len - skb->data_len; |
| 3204 | |
| 3205 | /* NOTE: Here, the dma_addr_t returned from |
| 3206 | * pci_map_single() is implicitly cast as a |
| 3207 | * u32. Although dma_addr_t can be |
| 3208 | * 64-bit, the address returned by |
| 3209 | * pci_map_single() is always 32-bit |
| 3210 | * addressable (as defined by the pci/dma |
| 3211 | * subsystem) |
| 3212 | */ |
| 3213 | desc[frag++].addr_lo = |
| 3214 | pci_map_single(adapter->pdev, |
| 3215 | skb->data, |
| 3216 | skb->len - |
| 3217 | skb->data_len, |
| 3218 | PCI_DMA_TODEVICE); |
| 3219 | } else { |
| 3220 | desc[frag].addr_hi = 0; |
| 3221 | desc[frag].len_vlan = |
| 3222 | (skb->len - skb->data_len) / 2; |
| 3223 | |
| 3224 | /* NOTE: Here, the dma_addr_t returned from |
| 3225 | * pci_map_single() is implicitly cast as a |
| 3226 | * u32. Although dma_addr_t can be |
| 3227 | * 64-bit, the address returned by |
| 3228 | * pci_map_single() is always 32-bit |
| 3229 | * addressable (as defined by the pci/dma |
| 3230 | * subsystem) |
| 3231 | */ |
| 3232 | desc[frag++].addr_lo = |
| 3233 | pci_map_single(adapter->pdev, |
| 3234 | skb->data, |
| 3235 | ((skb->len - |
| 3236 | skb->data_len) / 2), |
| 3237 | PCI_DMA_TODEVICE); |
| 3238 | desc[frag].addr_hi = 0; |
| 3239 | |
| 3240 | desc[frag].len_vlan = |
| 3241 | (skb->len - skb->data_len) / 2; |
| 3242 | |
| 3243 | /* NOTE: Here, the dma_addr_t returned from |
| 3244 | * pci_map_single() is implicitly cast as a |
| 3245 | * u32. Although dma_addr_t can be |
| 3246 | * 64-bit, the address returned by |
| 3247 | * pci_map_single() is always 32-bit |
| 3248 | * addressable (as defined by the pci/dma |
| 3249 | * subsystem) |
| 3250 | */ |
| 3251 | desc[frag++].addr_lo = |
| 3252 | pci_map_single(adapter->pdev, |
| 3253 | skb->data + |
| 3254 | ((skb->len - |
| 3255 | skb->data_len) / 2), |
| 3256 | ((skb->len - |
| 3257 | skb->data_len) / 2), |
| 3258 | PCI_DMA_TODEVICE); |
| 3259 | } |
| 3260 | } else { |
| 3261 | desc[frag].addr_hi = 0; |
| 3262 | desc[frag].len_vlan = |
| 3263 | frags[i - 1].size; |
| 3264 | |
| 3265 | /* NOTE: Here, the dma_addr_t returned from |
| 3266 | * pci_map_page() is implicitly cast as a u32. |
| 3267 | * Although dma_addr_t can be 64-bit, the address |
| 3268 | * returned by pci_map_page() is always 32-bit |
| 3269 | * addressable (as defined by the pci/dma subsystem) |
| 3270 | */ |
| 3271 | desc[frag++].addr_lo = |
| 3272 | pci_map_page(adapter->pdev, |
| 3273 | frags[i - 1].page, |
| 3274 | frags[i - 1].page_offset, |
| 3275 | frags[i - 1].size, |
| 3276 | PCI_DMA_TODEVICE); |
| 3277 | } |
| 3278 | } |
| 3279 | |
| 3280 | if (frag == 0) |
| 3281 | return -EIO; |
| 3282 | |
| 3283 | if (phydev && phydev->speed == SPEED_1000) { |
| 3284 | if (++adapter->tx_ring.since_irq == PARM_TX_NUM_BUFS_DEF) { |
| 3285 | /* Last element & Interrupt flag */ |
| 3286 | desc[frag - 1].flags = 0x5; |
| 3287 | adapter->tx_ring.since_irq = 0; |
| 3288 | } else { /* Last element */ |
| 3289 | desc[frag - 1].flags = 0x1; |
| 3290 | } |
| 3291 | } else |
| 3292 | desc[frag - 1].flags = 0x5; |
| 3293 | |
| 3294 | desc[0].flags |= 2; /* First element flag */ |
| 3295 | |
| 3296 | tcb->index_start = adapter->tx_ring.send_idx; |
| 3297 | tcb->stale = 0; |
| 3298 | |
| 3299 | spin_lock_irqsave(&adapter->send_hw_lock, flags); |
| 3300 | |
| 3301 | thiscopy = NUM_DESC_PER_RING_TX - |
| 3302 | INDEX10(adapter->tx_ring.send_idx); |
| 3303 | |
| 3304 | if (thiscopy >= frag) { |
| 3305 | remainder = 0; |
| 3306 | thiscopy = frag; |
| 3307 | } else { |
| 3308 | remainder = frag - thiscopy; |
| 3309 | } |
| 3310 | |
| 3311 | memcpy(adapter->tx_ring.tx_desc_ring + |
| 3312 | INDEX10(adapter->tx_ring.send_idx), desc, |
| 3313 | sizeof(struct tx_desc) * thiscopy); |
| 3314 | |
| 3315 | add_10bit(&adapter->tx_ring.send_idx, thiscopy); |
| 3316 | |
| 3317 | if (INDEX10(adapter->tx_ring.send_idx) == 0 || |
| 3318 | INDEX10(adapter->tx_ring.send_idx) == NUM_DESC_PER_RING_TX) { |
| 3319 | adapter->tx_ring.send_idx &= ~ET_DMA10_MASK; |
| 3320 | adapter->tx_ring.send_idx ^= ET_DMA10_WRAP; |
| 3321 | } |
| 3322 | |
| 3323 | if (remainder) { |
| 3324 | memcpy(adapter->tx_ring.tx_desc_ring, |
| 3325 | desc + thiscopy, |
| 3326 | sizeof(struct tx_desc) * remainder); |
| 3327 | |
| 3328 | add_10bit(&adapter->tx_ring.send_idx, remainder); |
| 3329 | } |
| 3330 | |
| 3331 | if (INDEX10(adapter->tx_ring.send_idx) == 0) { |
| 3332 | if (adapter->tx_ring.send_idx) |
| 3333 | tcb->index = NUM_DESC_PER_RING_TX - 1; |
| 3334 | else |
| 3335 | tcb->index = ET_DMA10_WRAP|(NUM_DESC_PER_RING_TX - 1); |
| 3336 | } else |
| 3337 | tcb->index = adapter->tx_ring.send_idx - 1; |
| 3338 | |
| 3339 | spin_lock(&adapter->tcb_send_qlock); |
| 3340 | |
| 3341 | if (adapter->tx_ring.send_tail) |
| 3342 | adapter->tx_ring.send_tail->next = tcb; |
| 3343 | else |
| 3344 | adapter->tx_ring.send_head = tcb; |
| 3345 | |
| 3346 | adapter->tx_ring.send_tail = tcb; |
| 3347 | |
| 3348 | WARN_ON(tcb->next != NULL); |
| 3349 | |
| 3350 | adapter->tx_ring.used++; |
| 3351 | |
| 3352 | spin_unlock(&adapter->tcb_send_qlock); |
| 3353 | |
| 3354 | /* Write the new write pointer back to the device. */ |
| 3355 | writel(adapter->tx_ring.send_idx, |
| 3356 | &adapter->regs->txdma.service_request); |
| 3357 | |
| 3358 | /* For Gig only, we use Tx Interrupt coalescing. Enable the software |
| 3359 | * timer to wake us up if this packet isn't followed by N more. |
| 3360 | */ |
| 3361 | if (phydev && phydev->speed == SPEED_1000) { |
| 3362 | writel(PARM_TX_TIME_INT_DEF * NANO_IN_A_MICRO, |
| 3363 | &adapter->regs->global.watchdog_timer); |
| 3364 | } |
| 3365 | spin_unlock_irqrestore(&adapter->send_hw_lock, flags); |
| 3366 | |
| 3367 | return 0; |
| 3368 | } |
| 3369 | |
| 3370 | /** |
| 3371 | * send_packet - Do the work to send a packet |
| 3372 | * @skb: the packet(s) to send |
| 3373 | * @adapter: a pointer to the device's private adapter structure |
| 3374 | * |
| 3375 | * Return 0 in almost all cases; non-zero value in extreme hard failure only. |
| 3376 | * |
| 3377 | * Assumption: Send spinlock has been acquired |
| 3378 | */ |
| 3379 | static int send_packet(struct sk_buff *skb, struct et131x_adapter *adapter) |
| 3380 | { |
| 3381 | int status; |
| 3382 | struct tcb *tcb = NULL; |
| 3383 | u16 *shbufva; |
| 3384 | unsigned long flags; |
| 3385 | |
| 3386 | /* All packets must have at least a MAC address and a protocol type */ |
| 3387 | if (skb->len < ETH_HLEN) |
| 3388 | return -EIO; |
| 3389 | |
| 3390 | /* Get a TCB for this packet */ |
| 3391 | spin_lock_irqsave(&adapter->tcb_ready_qlock, flags); |
| 3392 | |
| 3393 | tcb = adapter->tx_ring.tcb_qhead; |
| 3394 | |
| 3395 | if (tcb == NULL) { |
| 3396 | spin_unlock_irqrestore(&adapter->tcb_ready_qlock, flags); |
| 3397 | return -ENOMEM; |
| 3398 | } |
| 3399 | |
| 3400 | adapter->tx_ring.tcb_qhead = tcb->next; |
| 3401 | |
| 3402 | if (adapter->tx_ring.tcb_qhead == NULL) |
| 3403 | adapter->tx_ring.tcb_qtail = NULL; |
| 3404 | |
| 3405 | spin_unlock_irqrestore(&adapter->tcb_ready_qlock, flags); |
| 3406 | |
| 3407 | tcb->skb = skb; |
| 3408 | |
| 3409 | if (skb->data != NULL && skb->len - skb->data_len >= 6) { |
| 3410 | shbufva = (u16 *) skb->data; |
| 3411 | |
| 3412 | if ((shbufva[0] == 0xffff) && |
| 3413 | (shbufva[1] == 0xffff) && (shbufva[2] == 0xffff)) { |
| 3414 | tcb->flags |= fMP_DEST_BROAD; |
| 3415 | } else if ((shbufva[0] & 0x3) == 0x0001) { |
| 3416 | tcb->flags |= fMP_DEST_MULTI; |
| 3417 | } |
| 3418 | } |
| 3419 | |
| 3420 | tcb->next = NULL; |
| 3421 | |
| 3422 | /* Call the NIC specific send handler. */ |
| 3423 | status = nic_send_packet(adapter, tcb); |
| 3424 | |
| 3425 | if (status != 0) { |
| 3426 | spin_lock_irqsave(&adapter->tcb_ready_qlock, flags); |
| 3427 | |
| 3428 | if (adapter->tx_ring.tcb_qtail) |
| 3429 | adapter->tx_ring.tcb_qtail->next = tcb; |
| 3430 | else |
| 3431 | /* Apparently ready Q is empty. */ |
| 3432 | adapter->tx_ring.tcb_qhead = tcb; |
| 3433 | |
| 3434 | adapter->tx_ring.tcb_qtail = tcb; |
| 3435 | spin_unlock_irqrestore(&adapter->tcb_ready_qlock, flags); |
| 3436 | return status; |
| 3437 | } |
| 3438 | WARN_ON(adapter->tx_ring.used > NUM_TCB); |
| 3439 | return 0; |
| 3440 | } |
| 3441 | |
| 3442 | /** |
| 3443 | * et131x_send_packets - This function is called by the OS to send packets |
| 3444 | * @skb: the packet(s) to send |
| 3445 | * @netdev:device on which to TX the above packet(s) |
| 3446 | * |
| 3447 | * Return 0 in almost all cases; non-zero value in extreme hard failure only |
| 3448 | */ |
| 3449 | int et131x_send_packets(struct sk_buff *skb, struct net_device *netdev) |
| 3450 | { |
| 3451 | int status = 0; |
| 3452 | struct et131x_adapter *adapter = NULL; |
| 3453 | |
| 3454 | adapter = netdev_priv(netdev); |
| 3455 | |
| 3456 | /* Send these packets |
| 3457 | * |
| 3458 | * NOTE: The Linux Tx entry point is only given one packet at a time |
| 3459 | * to Tx, so the PacketCount and it's array used makes no sense here |
| 3460 | */ |
| 3461 | |
| 3462 | /* TCB is not available */ |
| 3463 | if (adapter->tx_ring.used >= NUM_TCB) { |
| 3464 | /* NOTE: If there's an error on send, no need to queue the |
| 3465 | * packet under Linux; if we just send an error up to the |
| 3466 | * netif layer, it will resend the skb to us. |
| 3467 | */ |
| 3468 | status = -ENOMEM; |
| 3469 | } else { |
| 3470 | /* We need to see if the link is up; if it's not, make the |
| 3471 | * netif layer think we're good and drop the packet |
| 3472 | */ |
| 3473 | if ((adapter->flags & fMP_ADAPTER_FAIL_SEND_MASK) || |
| 3474 | !netif_carrier_ok(netdev)) { |
| 3475 | dev_kfree_skb_any(skb); |
| 3476 | skb = NULL; |
| 3477 | |
| 3478 | adapter->net_stats.tx_dropped++; |
| 3479 | } else { |
| 3480 | status = send_packet(skb, adapter); |
| 3481 | if (status != 0 && status != -ENOMEM) { |
| 3482 | /* On any other error, make netif think we're |
| 3483 | * OK and drop the packet |
| 3484 | */ |
| 3485 | dev_kfree_skb_any(skb); |
| 3486 | skb = NULL; |
| 3487 | adapter->net_stats.tx_dropped++; |
| 3488 | } |
| 3489 | } |
| 3490 | } |
| 3491 | return status; |
| 3492 | } |
| 3493 | |
| 3494 | /** |
| 3495 | * free_send_packet - Recycle a struct tcb |
| 3496 | * @adapter: pointer to our adapter |
| 3497 | * @tcb: pointer to struct tcb |
| 3498 | * |
| 3499 | * Complete the packet if necessary |
| 3500 | * Assumption - Send spinlock has been acquired |
| 3501 | */ |
| 3502 | static inline void free_send_packet(struct et131x_adapter *adapter, |
| 3503 | struct tcb *tcb) |
| 3504 | { |
| 3505 | unsigned long flags; |
| 3506 | struct tx_desc *desc = NULL; |
| 3507 | struct net_device_stats *stats = &adapter->net_stats; |
| 3508 | |
| 3509 | if (tcb->flags & fMP_DEST_BROAD) |
| 3510 | atomic_inc(&adapter->stats.broadcast_pkts_xmtd); |
| 3511 | else if (tcb->flags & fMP_DEST_MULTI) |
| 3512 | atomic_inc(&adapter->stats.multicast_pkts_xmtd); |
| 3513 | else |
| 3514 | atomic_inc(&adapter->stats.unicast_pkts_xmtd); |
| 3515 | |
| 3516 | if (tcb->skb) { |
| 3517 | stats->tx_bytes += tcb->skb->len; |
| 3518 | |
| 3519 | /* Iterate through the TX descriptors on the ring |
| 3520 | * corresponding to this packet and umap the fragments |
| 3521 | * they point to |
| 3522 | */ |
| 3523 | do { |
| 3524 | desc = (struct tx_desc *) |
| 3525 | (adapter->tx_ring.tx_desc_ring + |
| 3526 | INDEX10(tcb->index_start)); |
| 3527 | |
| 3528 | pci_unmap_single(adapter->pdev, |
| 3529 | desc->addr_lo, |
| 3530 | desc->len_vlan, PCI_DMA_TODEVICE); |
| 3531 | |
| 3532 | add_10bit(&tcb->index_start, 1); |
| 3533 | if (INDEX10(tcb->index_start) >= |
| 3534 | NUM_DESC_PER_RING_TX) { |
| 3535 | tcb->index_start &= ~ET_DMA10_MASK; |
| 3536 | tcb->index_start ^= ET_DMA10_WRAP; |
| 3537 | } |
| 3538 | } while (desc != (adapter->tx_ring.tx_desc_ring + |
| 3539 | INDEX10(tcb->index))); |
| 3540 | |
| 3541 | dev_kfree_skb_any(tcb->skb); |
| 3542 | } |
| 3543 | |
| 3544 | memset(tcb, 0, sizeof(struct tcb)); |
| 3545 | |
| 3546 | /* Add the TCB to the Ready Q */ |
| 3547 | spin_lock_irqsave(&adapter->tcb_ready_qlock, flags); |
| 3548 | |
| 3549 | adapter->net_stats.tx_packets++; |
| 3550 | |
| 3551 | if (adapter->tx_ring.tcb_qtail) |
| 3552 | adapter->tx_ring.tcb_qtail->next = tcb; |
| 3553 | else |
| 3554 | /* Apparently ready Q is empty. */ |
| 3555 | adapter->tx_ring.tcb_qhead = tcb; |
| 3556 | |
| 3557 | adapter->tx_ring.tcb_qtail = tcb; |
| 3558 | |
| 3559 | spin_unlock_irqrestore(&adapter->tcb_ready_qlock, flags); |
| 3560 | WARN_ON(adapter->tx_ring.used < 0); |
| 3561 | } |
| 3562 | |
| 3563 | /** |
| 3564 | * et131x_free_busy_send_packets - Free and complete the stopped active sends |
| 3565 | * @adapter: pointer to our adapter |
| 3566 | * |
| 3567 | * Assumption - Send spinlock has been acquired |
| 3568 | */ |
| 3569 | void et131x_free_busy_send_packets(struct et131x_adapter *adapter) |
| 3570 | { |
| 3571 | struct tcb *tcb; |
| 3572 | unsigned long flags; |
| 3573 | u32 freed = 0; |
| 3574 | |
| 3575 | /* Any packets being sent? Check the first TCB on the send list */ |
| 3576 | spin_lock_irqsave(&adapter->tcb_send_qlock, flags); |
| 3577 | |
| 3578 | tcb = adapter->tx_ring.send_head; |
| 3579 | |
| 3580 | while (tcb != NULL && freed < NUM_TCB) { |
| 3581 | struct tcb *next = tcb->next; |
| 3582 | |
| 3583 | adapter->tx_ring.send_head = next; |
| 3584 | |
| 3585 | if (next == NULL) |
| 3586 | adapter->tx_ring.send_tail = NULL; |
| 3587 | |
| 3588 | adapter->tx_ring.used--; |
| 3589 | |
| 3590 | spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags); |
| 3591 | |
| 3592 | freed++; |
| 3593 | free_send_packet(adapter, tcb); |
| 3594 | |
| 3595 | spin_lock_irqsave(&adapter->tcb_send_qlock, flags); |
| 3596 | |
| 3597 | tcb = adapter->tx_ring.send_head; |
| 3598 | } |
| 3599 | |
| 3600 | WARN_ON(freed == NUM_TCB); |
| 3601 | |
| 3602 | spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags); |
| 3603 | |
| 3604 | adapter->tx_ring.used = 0; |
| 3605 | } |
| 3606 | |
| 3607 | /** |
| 3608 | * et131x_handle_send_interrupt - Interrupt handler for sending processing |
| 3609 | * @adapter: pointer to our adapter |
| 3610 | * |
| 3611 | * Re-claim the send resources, complete sends and get more to send from |
| 3612 | * the send wait queue. |
| 3613 | * |
| 3614 | * Assumption - Send spinlock has been acquired |
| 3615 | */ |
| 3616 | void et131x_handle_send_interrupt(struct et131x_adapter *adapter) |
| 3617 | { |
| 3618 | unsigned long flags; |
| 3619 | u32 serviced; |
| 3620 | struct tcb *tcb; |
| 3621 | u32 index; |
| 3622 | |
| 3623 | serviced = readl(&adapter->regs->txdma.new_service_complete); |
| 3624 | index = INDEX10(serviced); |
| 3625 | |
| 3626 | /* Has the ring wrapped? Process any descriptors that do not have |
| 3627 | * the same "wrap" indicator as the current completion indicator |
| 3628 | */ |
| 3629 | spin_lock_irqsave(&adapter->tcb_send_qlock, flags); |
| 3630 | |
| 3631 | tcb = adapter->tx_ring.send_head; |
| 3632 | |
| 3633 | while (tcb && |
| 3634 | ((serviced ^ tcb->index) & ET_DMA10_WRAP) && |
| 3635 | index < INDEX10(tcb->index)) { |
| 3636 | adapter->tx_ring.used--; |
| 3637 | adapter->tx_ring.send_head = tcb->next; |
| 3638 | if (tcb->next == NULL) |
| 3639 | adapter->tx_ring.send_tail = NULL; |
| 3640 | |
| 3641 | spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags); |
| 3642 | free_send_packet(adapter, tcb); |
| 3643 | spin_lock_irqsave(&adapter->tcb_send_qlock, flags); |
| 3644 | |
| 3645 | /* Goto the next packet */ |
| 3646 | tcb = adapter->tx_ring.send_head; |
| 3647 | } |
| 3648 | while (tcb && |
| 3649 | !((serviced ^ tcb->index) & ET_DMA10_WRAP) |
| 3650 | && index > (tcb->index & ET_DMA10_MASK)) { |
| 3651 | adapter->tx_ring.used--; |
| 3652 | adapter->tx_ring.send_head = tcb->next; |
| 3653 | if (tcb->next == NULL) |
| 3654 | adapter->tx_ring.send_tail = NULL; |
| 3655 | |
| 3656 | spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags); |
| 3657 | free_send_packet(adapter, tcb); |
| 3658 | spin_lock_irqsave(&adapter->tcb_send_qlock, flags); |
| 3659 | |
| 3660 | /* Goto the next packet */ |
| 3661 | tcb = adapter->tx_ring.send_head; |
| 3662 | } |
| 3663 | |
| 3664 | /* Wake up the queue when we hit a low-water mark */ |
| 3665 | if (adapter->tx_ring.used <= NUM_TCB / 3) |
| 3666 | netif_wake_queue(adapter->netdev); |
| 3667 | |
| 3668 | spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags); |
| 3669 | } |
| 3670 | |
| 3671 | /* ETHTOOL functions */ |
| 3672 | |
| 3673 | static int et131x_get_settings(struct net_device *netdev, |
| 3674 | struct ethtool_cmd *cmd) |
| 3675 | { |
| 3676 | struct et131x_adapter *adapter = netdev_priv(netdev); |
| 3677 | |
| 3678 | return phy_ethtool_gset(adapter->phydev, cmd); |
| 3679 | } |
| 3680 | |
| 3681 | static int et131x_set_settings(struct net_device *netdev, |
| 3682 | struct ethtool_cmd *cmd) |
| 3683 | { |
| 3684 | struct et131x_adapter *adapter = netdev_priv(netdev); |
| 3685 | |
| 3686 | return phy_ethtool_sset(adapter->phydev, cmd); |
| 3687 | } |
| 3688 | |
| 3689 | static int et131x_get_regs_len(struct net_device *netdev) |
| 3690 | { |
| 3691 | #define ET131X_REGS_LEN 256 |
| 3692 | return ET131X_REGS_LEN * sizeof(u32); |
| 3693 | } |
| 3694 | |
| 3695 | static void et131x_get_regs(struct net_device *netdev, |
| 3696 | struct ethtool_regs *regs, void *regs_data) |
| 3697 | { |
| 3698 | struct et131x_adapter *adapter = netdev_priv(netdev); |
| 3699 | struct address_map __iomem *aregs = adapter->regs; |
| 3700 | u32 *regs_buff = regs_data; |
| 3701 | u32 num = 0; |
| 3702 | |
| 3703 | memset(regs_data, 0, et131x_get_regs_len(netdev)); |
| 3704 | |
| 3705 | regs->version = (1 << 24) | (adapter->pdev->revision << 16) | |
| 3706 | adapter->pdev->device; |
| 3707 | |
| 3708 | /* PHY regs */ |
| 3709 | et131x_mii_read(adapter, MII_BMCR, (u16 *)®s_buff[num++]); |
| 3710 | et131x_mii_read(adapter, MII_BMSR, (u16 *)®s_buff[num++]); |
| 3711 | et131x_mii_read(adapter, MII_PHYSID1, (u16 *)®s_buff[num++]); |
| 3712 | et131x_mii_read(adapter, MII_PHYSID2, (u16 *)®s_buff[num++]); |
| 3713 | et131x_mii_read(adapter, MII_ADVERTISE, (u16 *)®s_buff[num++]); |
| 3714 | et131x_mii_read(adapter, MII_LPA, (u16 *)®s_buff[num++]); |
| 3715 | et131x_mii_read(adapter, MII_EXPANSION, (u16 *)®s_buff[num++]); |
| 3716 | /* Autoneg next page transmit reg */ |
| 3717 | et131x_mii_read(adapter, 0x07, (u16 *)®s_buff[num++]); |
| 3718 | /* Link partner next page reg */ |
| 3719 | et131x_mii_read(adapter, 0x08, (u16 *)®s_buff[num++]); |
| 3720 | et131x_mii_read(adapter, MII_CTRL1000, (u16 *)®s_buff[num++]); |
| 3721 | et131x_mii_read(adapter, MII_STAT1000, (u16 *)®s_buff[num++]); |
| 3722 | et131x_mii_read(adapter, MII_ESTATUS, (u16 *)®s_buff[num++]); |
| 3723 | et131x_mii_read(adapter, PHY_INDEX_REG, (u16 *)®s_buff[num++]); |
| 3724 | et131x_mii_read(adapter, PHY_DATA_REG, (u16 *)®s_buff[num++]); |
| 3725 | et131x_mii_read(adapter, PHY_MPHY_CONTROL_REG, |
| 3726 | (u16 *)®s_buff[num++]); |
| 3727 | et131x_mii_read(adapter, PHY_LOOPBACK_CONTROL, |
| 3728 | (u16 *)®s_buff[num++]); |
| 3729 | et131x_mii_read(adapter, PHY_LOOPBACK_CONTROL+1, |
| 3730 | (u16 *)®s_buff[num++]); |
| 3731 | et131x_mii_read(adapter, PHY_REGISTER_MGMT_CONTROL, |
| 3732 | (u16 *)®s_buff[num++]); |
| 3733 | et131x_mii_read(adapter, PHY_CONFIG, (u16 *)®s_buff[num++]); |
| 3734 | et131x_mii_read(adapter, PHY_PHY_CONTROL, (u16 *)®s_buff[num++]); |
| 3735 | et131x_mii_read(adapter, PHY_INTERRUPT_MASK, (u16 *)®s_buff[num++]); |
| 3736 | et131x_mii_read(adapter, PHY_INTERRUPT_STATUS, |
| 3737 | (u16 *)®s_buff[num++]); |
| 3738 | et131x_mii_read(adapter, PHY_PHY_STATUS, (u16 *)®s_buff[num++]); |
| 3739 | et131x_mii_read(adapter, PHY_LED_1, (u16 *)®s_buff[num++]); |
| 3740 | et131x_mii_read(adapter, PHY_LED_2, (u16 *)®s_buff[num++]); |
| 3741 | |
| 3742 | /* Global regs */ |
| 3743 | regs_buff[num++] = readl(&aregs->global.txq_start_addr); |
| 3744 | regs_buff[num++] = readl(&aregs->global.txq_end_addr); |
| 3745 | regs_buff[num++] = readl(&aregs->global.rxq_start_addr); |
| 3746 | regs_buff[num++] = readl(&aregs->global.rxq_end_addr); |
| 3747 | regs_buff[num++] = readl(&aregs->global.pm_csr); |
| 3748 | regs_buff[num++] = adapter->stats.interrupt_status; |
| 3749 | regs_buff[num++] = readl(&aregs->global.int_mask); |
| 3750 | regs_buff[num++] = readl(&aregs->global.int_alias_clr_en); |
| 3751 | regs_buff[num++] = readl(&aregs->global.int_status_alias); |
| 3752 | regs_buff[num++] = readl(&aregs->global.sw_reset); |
| 3753 | regs_buff[num++] = readl(&aregs->global.slv_timer); |
| 3754 | regs_buff[num++] = readl(&aregs->global.msi_config); |
| 3755 | regs_buff[num++] = readl(&aregs->global.loopback); |
| 3756 | regs_buff[num++] = readl(&aregs->global.watchdog_timer); |
| 3757 | |
| 3758 | /* TXDMA regs */ |
| 3759 | regs_buff[num++] = readl(&aregs->txdma.csr); |
| 3760 | regs_buff[num++] = readl(&aregs->txdma.pr_base_hi); |
| 3761 | regs_buff[num++] = readl(&aregs->txdma.pr_base_lo); |
| 3762 | regs_buff[num++] = readl(&aregs->txdma.pr_num_des); |
| 3763 | regs_buff[num++] = readl(&aregs->txdma.txq_wr_addr); |
| 3764 | regs_buff[num++] = readl(&aregs->txdma.txq_wr_addr_ext); |
| 3765 | regs_buff[num++] = readl(&aregs->txdma.txq_rd_addr); |
| 3766 | regs_buff[num++] = readl(&aregs->txdma.dma_wb_base_hi); |
| 3767 | regs_buff[num++] = readl(&aregs->txdma.dma_wb_base_lo); |
| 3768 | regs_buff[num++] = readl(&aregs->txdma.service_request); |
| 3769 | regs_buff[num++] = readl(&aregs->txdma.service_complete); |
| 3770 | regs_buff[num++] = readl(&aregs->txdma.cache_rd_index); |
| 3771 | regs_buff[num++] = readl(&aregs->txdma.cache_wr_index); |
| 3772 | regs_buff[num++] = readl(&aregs->txdma.tx_dma_error); |
| 3773 | regs_buff[num++] = readl(&aregs->txdma.desc_abort_cnt); |
| 3774 | regs_buff[num++] = readl(&aregs->txdma.payload_abort_cnt); |
| 3775 | regs_buff[num++] = readl(&aregs->txdma.writeback_abort_cnt); |
| 3776 | regs_buff[num++] = readl(&aregs->txdma.desc_timeout_cnt); |
| 3777 | regs_buff[num++] = readl(&aregs->txdma.payload_timeout_cnt); |
| 3778 | regs_buff[num++] = readl(&aregs->txdma.writeback_timeout_cnt); |
| 3779 | regs_buff[num++] = readl(&aregs->txdma.desc_error_cnt); |
| 3780 | regs_buff[num++] = readl(&aregs->txdma.payload_error_cnt); |
| 3781 | regs_buff[num++] = readl(&aregs->txdma.writeback_error_cnt); |
| 3782 | regs_buff[num++] = readl(&aregs->txdma.dropped_tlp_cnt); |
| 3783 | regs_buff[num++] = readl(&aregs->txdma.new_service_complete); |
| 3784 | regs_buff[num++] = readl(&aregs->txdma.ethernet_packet_cnt); |
| 3785 | |
| 3786 | /* RXDMA regs */ |
| 3787 | regs_buff[num++] = readl(&aregs->rxdma.csr); |
| 3788 | regs_buff[num++] = readl(&aregs->rxdma.dma_wb_base_hi); |
| 3789 | regs_buff[num++] = readl(&aregs->rxdma.dma_wb_base_lo); |
| 3790 | regs_buff[num++] = readl(&aregs->rxdma.num_pkt_done); |
| 3791 | regs_buff[num++] = readl(&aregs->rxdma.max_pkt_time); |
| 3792 | regs_buff[num++] = readl(&aregs->rxdma.rxq_rd_addr); |
| 3793 | regs_buff[num++] = readl(&aregs->rxdma.rxq_rd_addr_ext); |
| 3794 | regs_buff[num++] = readl(&aregs->rxdma.rxq_wr_addr); |
| 3795 | regs_buff[num++] = readl(&aregs->rxdma.psr_base_hi); |
| 3796 | regs_buff[num++] = readl(&aregs->rxdma.psr_base_lo); |
| 3797 | regs_buff[num++] = readl(&aregs->rxdma.psr_num_des); |
| 3798 | regs_buff[num++] = readl(&aregs->rxdma.psr_avail_offset); |
| 3799 | regs_buff[num++] = readl(&aregs->rxdma.psr_full_offset); |
| 3800 | regs_buff[num++] = readl(&aregs->rxdma.psr_access_index); |
| 3801 | regs_buff[num++] = readl(&aregs->rxdma.psr_min_des); |
| 3802 | regs_buff[num++] = readl(&aregs->rxdma.fbr0_base_lo); |
| 3803 | regs_buff[num++] = readl(&aregs->rxdma.fbr0_base_hi); |
| 3804 | regs_buff[num++] = readl(&aregs->rxdma.fbr0_num_des); |
| 3805 | regs_buff[num++] = readl(&aregs->rxdma.fbr0_avail_offset); |
| 3806 | regs_buff[num++] = readl(&aregs->rxdma.fbr0_full_offset); |
| 3807 | regs_buff[num++] = readl(&aregs->rxdma.fbr0_rd_index); |
| 3808 | regs_buff[num++] = readl(&aregs->rxdma.fbr0_min_des); |
| 3809 | regs_buff[num++] = readl(&aregs->rxdma.fbr1_base_lo); |
| 3810 | regs_buff[num++] = readl(&aregs->rxdma.fbr1_base_hi); |
| 3811 | regs_buff[num++] = readl(&aregs->rxdma.fbr1_num_des); |
| 3812 | regs_buff[num++] = readl(&aregs->rxdma.fbr1_avail_offset); |
| 3813 | regs_buff[num++] = readl(&aregs->rxdma.fbr1_full_offset); |
| 3814 | regs_buff[num++] = readl(&aregs->rxdma.fbr1_rd_index); |
| 3815 | regs_buff[num++] = readl(&aregs->rxdma.fbr1_min_des); |
| 3816 | } |
| 3817 | |
| 3818 | #define ET131X_DRVINFO_LEN 32 /* value from ethtool.h */ |
| 3819 | static void et131x_get_drvinfo(struct net_device *netdev, |
| 3820 | struct ethtool_drvinfo *info) |
| 3821 | { |
| 3822 | struct et131x_adapter *adapter = netdev_priv(netdev); |
| 3823 | |
| 3824 | strncpy(info->driver, DRIVER_NAME, ET131X_DRVINFO_LEN); |
| 3825 | strncpy(info->version, DRIVER_VERSION, ET131X_DRVINFO_LEN); |
| 3826 | strncpy(info->bus_info, pci_name(adapter->pdev), ET131X_DRVINFO_LEN); |
| 3827 | } |
| 3828 | |
| 3829 | static struct ethtool_ops et131x_ethtool_ops = { |
| 3830 | .get_settings = et131x_get_settings, |
| 3831 | .set_settings = et131x_set_settings, |
| 3832 | .get_drvinfo = et131x_get_drvinfo, |
| 3833 | .get_regs_len = et131x_get_regs_len, |
| 3834 | .get_regs = et131x_get_regs, |
| 3835 | .get_link = ethtool_op_get_link, |
| 3836 | }; |
| 3837 | |
| 3838 | void et131x_set_ethtool_ops(struct net_device *netdev) |
| 3839 | { |
| 3840 | SET_ETHTOOL_OPS(netdev, &et131x_ethtool_ops); |
| 3841 | } |
| 3842 | |
| 3843 | /* PCI functions */ |
| 3844 | |
| 3845 | /** |
| 3846 | * et131x_hwaddr_init - set up the MAC Address on the ET1310 |
| 3847 | * @adapter: pointer to our private adapter structure |
| 3848 | */ |
| 3849 | void et131x_hwaddr_init(struct et131x_adapter *adapter) |
| 3850 | { |
| 3851 | /* If have our default mac from init and no mac address from |
| 3852 | * EEPROM then we need to generate the last octet and set it on the |
| 3853 | * device |
| 3854 | */ |
| 3855 | if (adapter->rom_addr[0] == 0x00 && |
| 3856 | adapter->rom_addr[1] == 0x00 && |
| 3857 | adapter->rom_addr[2] == 0x00 && |
| 3858 | adapter->rom_addr[3] == 0x00 && |
| 3859 | adapter->rom_addr[4] == 0x00 && |
| 3860 | adapter->rom_addr[5] == 0x00) { |
| 3861 | /* |
| 3862 | * We need to randomly generate the last octet so we |
| 3863 | * decrease our chances of setting the mac address to |
| 3864 | * same as another one of our cards in the system |
| 3865 | */ |
| 3866 | get_random_bytes(&adapter->addr[5], 1); |
| 3867 | /* |
| 3868 | * We have the default value in the register we are |
| 3869 | * working with so we need to copy the current |
| 3870 | * address into the permanent address |
| 3871 | */ |
| 3872 | memcpy(adapter->rom_addr, |
| 3873 | adapter->addr, ETH_ALEN); |
| 3874 | } else { |
| 3875 | /* We do not have an override address, so set the |
| 3876 | * current address to the permanent address and add |
| 3877 | * it to the device |
| 3878 | */ |
| 3879 | memcpy(adapter->addr, |
| 3880 | adapter->rom_addr, ETH_ALEN); |
| 3881 | } |
| 3882 | } |
| 3883 | |
| 3884 | /** |
| 3885 | * et131x_pci_init - initial PCI setup |
| 3886 | * @adapter: pointer to our private adapter structure |
| 3887 | * @pdev: our PCI device |
| 3888 | * |
| 3889 | * Perform the initial setup of PCI registers and if possible initialise |
| 3890 | * the MAC address. At this point the I/O registers have yet to be mapped |
| 3891 | */ |
| 3892 | static int et131x_pci_init(struct et131x_adapter *adapter, |
| 3893 | struct pci_dev *pdev) |
| 3894 | { |
| 3895 | int i; |
| 3896 | u8 max_payload; |
| 3897 | u8 read_size_reg; |
| 3898 | |
| 3899 | if (et131x_init_eeprom(adapter) < 0) |
| 3900 | return -EIO; |
| 3901 | |
| 3902 | /* Let's set up the PORT LOGIC Register. First we need to know what |
| 3903 | * the max_payload_size is |
| 3904 | */ |
| 3905 | if (pci_read_config_byte(pdev, ET1310_PCI_MAX_PYLD, &max_payload)) { |
| 3906 | dev_err(&pdev->dev, |
| 3907 | "Could not read PCI config space for Max Payload Size\n"); |
| 3908 | return -EIO; |
| 3909 | } |
| 3910 | |
| 3911 | /* Program the Ack/Nak latency and replay timers */ |
| 3912 | max_payload &= 0x07; /* Only the lower 3 bits are valid */ |
| 3913 | |
| 3914 | if (max_payload < 2) { |
| 3915 | static const u16 acknak[2] = { 0x76, 0xD0 }; |
| 3916 | static const u16 replay[2] = { 0x1E0, 0x2ED }; |
| 3917 | |
| 3918 | if (pci_write_config_word(pdev, ET1310_PCI_ACK_NACK, |
| 3919 | acknak[max_payload])) { |
| 3920 | dev_err(&pdev->dev, |
| 3921 | "Could not write PCI config space for ACK/NAK\n"); |
| 3922 | return -EIO; |
| 3923 | } |
| 3924 | if (pci_write_config_word(pdev, ET1310_PCI_REPLAY, |
| 3925 | replay[max_payload])) { |
| 3926 | dev_err(&pdev->dev, |
| 3927 | "Could not write PCI config space for Replay Timer\n"); |
| 3928 | return -EIO; |
| 3929 | } |
| 3930 | } |
| 3931 | |
| 3932 | /* l0s and l1 latency timers. We are using default values. |
| 3933 | * Representing 001 for L0s and 010 for L1 |
| 3934 | */ |
| 3935 | if (pci_write_config_byte(pdev, ET1310_PCI_L0L1LATENCY, 0x11)) { |
| 3936 | dev_err(&pdev->dev, |
| 3937 | "Could not write PCI config space for Latency Timers\n"); |
| 3938 | return -EIO; |
| 3939 | } |
| 3940 | |
| 3941 | /* Change the max read size to 2k */ |
| 3942 | if (pci_read_config_byte(pdev, 0x51, &read_size_reg)) { |
| 3943 | dev_err(&pdev->dev, |
| 3944 | "Could not read PCI config space for Max read size\n"); |
| 3945 | return -EIO; |
| 3946 | } |
| 3947 | |
| 3948 | read_size_reg &= 0x8f; |
| 3949 | read_size_reg |= 0x40; |
| 3950 | |
| 3951 | if (pci_write_config_byte(pdev, 0x51, read_size_reg)) { |
| 3952 | dev_err(&pdev->dev, |
| 3953 | "Could not write PCI config space for Max read size\n"); |
| 3954 | return -EIO; |
| 3955 | } |
| 3956 | |
| 3957 | /* Get MAC address from config space if an eeprom exists, otherwise |
| 3958 | * the MAC address there will not be valid |
| 3959 | */ |
| 3960 | if (!adapter->has_eeprom) { |
| 3961 | et131x_hwaddr_init(adapter); |
| 3962 | return 0; |
| 3963 | } |
| 3964 | |
| 3965 | for (i = 0; i < ETH_ALEN; i++) { |
| 3966 | if (pci_read_config_byte(pdev, ET1310_PCI_MAC_ADDRESS + i, |
| 3967 | adapter->rom_addr + i)) { |
| 3968 | dev_err(&pdev->dev, "Could not read PCI config space for MAC address\n"); |
| 3969 | return -EIO; |
| 3970 | } |
| 3971 | } |
| 3972 | memcpy(adapter->addr, adapter->rom_addr, ETH_ALEN); |
| 3973 | return 0; |
| 3974 | } |
| 3975 | |
| 3976 | /** |
| 3977 | * et131x_error_timer_handler |
| 3978 | * @data: timer-specific variable; here a pointer to our adapter structure |
| 3979 | * |
| 3980 | * The routine called when the error timer expires, to track the number of |
| 3981 | * recurring errors. |
| 3982 | */ |
| 3983 | void et131x_error_timer_handler(unsigned long data) |
| 3984 | { |
| 3985 | struct et131x_adapter *adapter = (struct et131x_adapter *) data; |
| 3986 | struct phy_device *phydev = adapter->phydev; |
| 3987 | |
| 3988 | if (et1310_in_phy_coma(adapter)) { |
| 3989 | /* Bring the device immediately out of coma, to |
| 3990 | * prevent it from sleeping indefinitely, this |
| 3991 | * mechanism could be improved! */ |
| 3992 | et1310_disable_phy_coma(adapter); |
| 3993 | adapter->boot_coma = 20; |
| 3994 | } else { |
| 3995 | et1310_update_macstat_host_counters(adapter); |
| 3996 | } |
| 3997 | |
| 3998 | if (!phydev->link && adapter->boot_coma < 11) |
| 3999 | adapter->boot_coma++; |
| 4000 | |
| 4001 | if (adapter->boot_coma == 10) { |
| 4002 | if (!phydev->link) { |
| 4003 | if (!et1310_in_phy_coma(adapter)) { |
| 4004 | /* NOTE - This was originally a 'sync with |
| 4005 | * interrupt'. How to do that under Linux? |
| 4006 | */ |
| 4007 | et131x_enable_interrupts(adapter); |
| 4008 | et1310_enable_phy_coma(adapter); |
| 4009 | } |
| 4010 | } |
| 4011 | } |
| 4012 | |
| 4013 | /* This is a periodic timer, so reschedule */ |
| 4014 | mod_timer(&adapter->error_timer, jiffies + |
| 4015 | TX_ERROR_PERIOD * HZ / 1000); |
| 4016 | } |
| 4017 | |
| 4018 | /** |
| 4019 | * et131x_configure_global_regs - configure JAGCore global regs |
| 4020 | * @adapter: pointer to our adapter structure |
| 4021 | * |
| 4022 | * Used to configure the global registers on the JAGCore |
| 4023 | */ |
| 4024 | void et131x_configure_global_regs(struct et131x_adapter *adapter) |
| 4025 | { |
| 4026 | struct global_regs __iomem *regs = &adapter->regs->global; |
| 4027 | |
| 4028 | writel(0, ®s->rxq_start_addr); |
| 4029 | writel(INTERNAL_MEM_SIZE - 1, ®s->txq_end_addr); |
| 4030 | |
| 4031 | if (adapter->registry_jumbo_packet < 2048) { |
| 4032 | /* Tx / RxDMA and Tx/Rx MAC interfaces have a 1k word |
| 4033 | * block of RAM that the driver can split between Tx |
| 4034 | * and Rx as it desires. Our default is to split it |
| 4035 | * 50/50: |
| 4036 | */ |
| 4037 | writel(PARM_RX_MEM_END_DEF, ®s->rxq_end_addr); |
| 4038 | writel(PARM_RX_MEM_END_DEF + 1, ®s->txq_start_addr); |
| 4039 | } else if (adapter->registry_jumbo_packet < 8192) { |
| 4040 | /* For jumbo packets > 2k but < 8k, split 50-50. */ |
| 4041 | writel(INTERNAL_MEM_RX_OFFSET, ®s->rxq_end_addr); |
| 4042 | writel(INTERNAL_MEM_RX_OFFSET + 1, ®s->txq_start_addr); |
| 4043 | } else { |
| 4044 | /* 9216 is the only packet size greater than 8k that |
| 4045 | * is available. The Tx buffer has to be big enough |
| 4046 | * for one whole packet on the Tx side. We'll make |
| 4047 | * the Tx 9408, and give the rest to Rx |
| 4048 | */ |
| 4049 | writel(0x01b3, ®s->rxq_end_addr); |
| 4050 | writel(0x01b4, ®s->txq_start_addr); |
| 4051 | } |
| 4052 | |
| 4053 | /* Initialize the loopback register. Disable all loopbacks. */ |
| 4054 | writel(0, ®s->loopback); |
| 4055 | |
| 4056 | /* MSI Register */ |
| 4057 | writel(0, ®s->msi_config); |
| 4058 | |
| 4059 | /* By default, disable the watchdog timer. It will be enabled when |
| 4060 | * a packet is queued. |
| 4061 | */ |
| 4062 | writel(0, ®s->watchdog_timer); |
| 4063 | } |
| 4064 | |
| 4065 | /** |
| 4066 | * et131x_adapter_setup - Set the adapter up as per cassini+ documentation |
| 4067 | * @adapter: pointer to our private adapter structure |
| 4068 | * |
| 4069 | * Returns 0 on success, errno on failure (as defined in errno.h) |
| 4070 | */ |
| 4071 | void et131x_adapter_setup(struct et131x_adapter *adapter) |
| 4072 | { |
| 4073 | /* Configure the JAGCore */ |
| 4074 | et131x_configure_global_regs(adapter); |
| 4075 | |
| 4076 | et1310_config_mac_regs1(adapter); |
| 4077 | |
| 4078 | /* Configure the MMC registers */ |
| 4079 | /* All we need to do is initialize the Memory Control Register */ |
| 4080 | writel(ET_MMC_ENABLE, &adapter->regs->mmc.mmc_ctrl); |
| 4081 | |
| 4082 | et1310_config_rxmac_regs(adapter); |
| 4083 | et1310_config_txmac_regs(adapter); |
| 4084 | |
| 4085 | et131x_config_rx_dma_regs(adapter); |
| 4086 | et131x_config_tx_dma_regs(adapter); |
| 4087 | |
| 4088 | et1310_config_macstat_regs(adapter); |
| 4089 | |
| 4090 | et1310_phy_power_down(adapter, 0); |
| 4091 | et131x_xcvr_init(adapter); |
| 4092 | } |
| 4093 | |
| 4094 | /** |
| 4095 | * et131x_soft_reset - Issue a soft reset to the hardware, complete for ET1310 |
| 4096 | * @adapter: pointer to our private adapter structure |
| 4097 | */ |
| 4098 | void et131x_soft_reset(struct et131x_adapter *adapter) |
| 4099 | { |
| 4100 | /* Disable MAC Core */ |
| 4101 | writel(0xc00f0000, &adapter->regs->mac.cfg1); |
| 4102 | |
| 4103 | /* Set everything to a reset value */ |
| 4104 | writel(0x7F, &adapter->regs->global.sw_reset); |
| 4105 | writel(0x000f0000, &adapter->regs->mac.cfg1); |
| 4106 | writel(0x00000000, &adapter->regs->mac.cfg1); |
| 4107 | } |
| 4108 | |
| 4109 | /** |
| 4110 | * et131x_align_allocated_memory - Align allocated memory on a given boundary |
| 4111 | * @adapter: pointer to our adapter structure |
| 4112 | * @phys_addr: pointer to Physical address |
| 4113 | * @offset: pointer to the offset variable |
| 4114 | * @mask: correct mask |
| 4115 | */ |
| 4116 | void et131x_align_allocated_memory(struct et131x_adapter *adapter, |
| 4117 | uint64_t *phys_addr, |
| 4118 | uint64_t *offset, uint64_t mask) |
| 4119 | { |
| 4120 | uint64_t new_addr; |
| 4121 | |
| 4122 | *offset = 0; |
| 4123 | |
| 4124 | new_addr = *phys_addr & ~mask; |
| 4125 | |
| 4126 | if (new_addr != *phys_addr) { |
| 4127 | /* Move to next aligned block */ |
| 4128 | new_addr += mask + 1; |
| 4129 | /* Return offset for adjusting virt addr */ |
| 4130 | *offset = new_addr - *phys_addr; |
| 4131 | /* Return new physical address */ |
| 4132 | *phys_addr = new_addr; |
| 4133 | } |
| 4134 | } |
| 4135 | |
| 4136 | /** |
| 4137 | * et131x_adapter_memory_alloc |
| 4138 | * @adapter: pointer to our private adapter structure |
| 4139 | * |
| 4140 | * Returns 0 on success, errno on failure (as defined in errno.h). |
| 4141 | * |
| 4142 | * Allocate all the memory blocks for send, receive and others. |
| 4143 | */ |
| 4144 | int et131x_adapter_memory_alloc(struct et131x_adapter *adapter) |
| 4145 | { |
| 4146 | int status; |
| 4147 | |
| 4148 | /* Allocate memory for the Tx Ring */ |
| 4149 | status = et131x_tx_dma_memory_alloc(adapter); |
| 4150 | if (status != 0) { |
| 4151 | dev_err(&adapter->pdev->dev, |
| 4152 | "et131x_tx_dma_memory_alloc FAILED\n"); |
| 4153 | return status; |
| 4154 | } |
| 4155 | /* Receive buffer memory allocation */ |
| 4156 | status = et131x_rx_dma_memory_alloc(adapter); |
| 4157 | if (status != 0) { |
| 4158 | dev_err(&adapter->pdev->dev, |
| 4159 | "et131x_rx_dma_memory_alloc FAILED\n"); |
| 4160 | et131x_tx_dma_memory_free(adapter); |
| 4161 | return status; |
| 4162 | } |
| 4163 | |
| 4164 | /* Init receive data structures */ |
| 4165 | status = et131x_init_recv(adapter); |
| 4166 | if (status != 0) { |
| 4167 | dev_err(&adapter->pdev->dev, |
| 4168 | "et131x_init_recv FAILED\n"); |
| 4169 | et131x_tx_dma_memory_free(adapter); |
| 4170 | et131x_rx_dma_memory_free(adapter); |
| 4171 | } |
| 4172 | return status; |
| 4173 | } |
| 4174 | |
| 4175 | /** |
| 4176 | * et131x_adapter_memory_free - Free all memory allocated for use by Tx & Rx |
| 4177 | * @adapter: pointer to our private adapter structure |
| 4178 | */ |
| 4179 | void et131x_adapter_memory_free(struct et131x_adapter *adapter) |
| 4180 | { |
| 4181 | /* Free DMA memory */ |
| 4182 | et131x_tx_dma_memory_free(adapter); |
| 4183 | et131x_rx_dma_memory_free(adapter); |
| 4184 | } |
| 4185 | |
| 4186 | static void et131x_adjust_link(struct net_device *netdev) |
| 4187 | { |
| 4188 | struct et131x_adapter *adapter = netdev_priv(netdev); |
| 4189 | struct phy_device *phydev = adapter->phydev; |
| 4190 | |
| 4191 | if (netif_carrier_ok(netdev)) { |
| 4192 | adapter->boot_coma = 20; |
| 4193 | |
| 4194 | if (phydev && phydev->speed == SPEED_10) { |
| 4195 | /* |
| 4196 | * NOTE - Is there a way to query this without |
| 4197 | * TruePHY? |
| 4198 | * && TRU_QueryCoreType(adapter->hTruePhy, 0)== |
| 4199 | * EMI_TRUEPHY_A13O) { |
| 4200 | */ |
| 4201 | u16 register18; |
| 4202 | |
| 4203 | et131x_mii_read(adapter, PHY_MPHY_CONTROL_REG, |
| 4204 | ®ister18); |
| 4205 | et131x_mii_write(adapter, PHY_MPHY_CONTROL_REG, |
| 4206 | register18 | 0x4); |
| 4207 | et131x_mii_write(adapter, PHY_INDEX_REG, |
| 4208 | register18 | 0x8402); |
| 4209 | et131x_mii_write(adapter, PHY_DATA_REG, |
| 4210 | register18 | 511); |
| 4211 | et131x_mii_write(adapter, PHY_MPHY_CONTROL_REG, |
| 4212 | register18); |
| 4213 | } |
| 4214 | |
| 4215 | et1310_config_flow_control(adapter); |
| 4216 | |
| 4217 | if (phydev && phydev->speed == SPEED_1000 && |
| 4218 | adapter->registry_jumbo_packet > 2048) { |
| 4219 | u16 reg; |
| 4220 | |
| 4221 | et131x_mii_read(adapter, PHY_CONFIG, ®); |
| 4222 | reg &= ~ET_PHY_CONFIG_TX_FIFO_DEPTH; |
| 4223 | reg |= ET_PHY_CONFIG_FIFO_DEPTH_32; |
| 4224 | et131x_mii_write(adapter, PHY_CONFIG, reg); |
| 4225 | } |
| 4226 | |
| 4227 | et131x_set_rx_dma_timer(adapter); |
| 4228 | et1310_config_mac_regs2(adapter); |
| 4229 | } |
| 4230 | |
| 4231 | if (phydev && phydev->link != adapter->link) { |
| 4232 | /* |
| 4233 | * Check to see if we are in coma mode and if |
| 4234 | * so, disable it because we will not be able |
| 4235 | * to read PHY values until we are out. |
| 4236 | */ |
| 4237 | if (et1310_in_phy_coma(adapter)) |
| 4238 | et1310_disable_phy_coma(adapter); |
| 4239 | |
| 4240 | if (phydev->link) { |
| 4241 | adapter->boot_coma = 20; |
| 4242 | } else { |
| 4243 | dev_warn(&adapter->pdev->dev, |
| 4244 | "Link down - cable problem ?\n"); |
| 4245 | adapter->boot_coma = 0; |
| 4246 | |
| 4247 | if (phydev->speed == SPEED_10) { |
| 4248 | /* NOTE - Is there a way to query this without |
| 4249 | * TruePHY? |
| 4250 | * && TRU_QueryCoreType(adapter->hTruePhy, 0) == |
| 4251 | * EMI_TRUEPHY_A13O) |
| 4252 | */ |
| 4253 | u16 register18; |
| 4254 | |
| 4255 | et131x_mii_read(adapter, PHY_MPHY_CONTROL_REG, |
| 4256 | ®ister18); |
| 4257 | et131x_mii_write(adapter, PHY_MPHY_CONTROL_REG, |
| 4258 | register18 | 0x4); |
| 4259 | et131x_mii_write(adapter, PHY_INDEX_REG, |
| 4260 | register18 | 0x8402); |
| 4261 | et131x_mii_write(adapter, PHY_DATA_REG, |
| 4262 | register18 | 511); |
| 4263 | et131x_mii_write(adapter, PHY_MPHY_CONTROL_REG, |
| 4264 | register18); |
| 4265 | } |
| 4266 | |
| 4267 | /* Free the packets being actively sent & stopped */ |
| 4268 | et131x_free_busy_send_packets(adapter); |
| 4269 | |
| 4270 | /* Re-initialize the send structures */ |
| 4271 | et131x_init_send(adapter); |
| 4272 | |
| 4273 | /* Reset the RFD list and re-start RU */ |
| 4274 | et131x_reset_recv(adapter); |
| 4275 | |
| 4276 | /* |
| 4277 | * Bring the device back to the state it was during |
| 4278 | * init prior to autonegotiation being complete. This |
| 4279 | * way, when we get the auto-neg complete interrupt, |
| 4280 | * we can complete init by calling config_mac_regs2. |
| 4281 | */ |
| 4282 | et131x_soft_reset(adapter); |
| 4283 | |
| 4284 | /* Setup ET1310 as per the documentation */ |
| 4285 | et131x_adapter_setup(adapter); |
| 4286 | |
| 4287 | /* perform reset of tx/rx */ |
| 4288 | et131x_disable_txrx(netdev); |
| 4289 | et131x_enable_txrx(netdev); |
| 4290 | } |
| 4291 | |
| 4292 | adapter->link = phydev->link; |
| 4293 | |
| 4294 | phy_print_status(phydev); |
| 4295 | } |
| 4296 | } |
| 4297 | |
| 4298 | static int et131x_mii_probe(struct net_device *netdev) |
| 4299 | { |
| 4300 | struct et131x_adapter *adapter = netdev_priv(netdev); |
| 4301 | struct phy_device *phydev = NULL; |
| 4302 | |
| 4303 | phydev = phy_find_first(adapter->mii_bus); |
| 4304 | if (!phydev) { |
| 4305 | dev_err(&adapter->pdev->dev, "no PHY found\n"); |
| 4306 | return -ENODEV; |
| 4307 | } |
| 4308 | |
| 4309 | phydev = phy_connect(netdev, dev_name(&phydev->dev), |
| 4310 | &et131x_adjust_link, 0, PHY_INTERFACE_MODE_MII); |
| 4311 | |
| 4312 | if (IS_ERR(phydev)) { |
| 4313 | dev_err(&adapter->pdev->dev, "Could not attach to PHY\n"); |
| 4314 | return PTR_ERR(phydev); |
| 4315 | } |
| 4316 | |
| 4317 | phydev->supported &= (SUPPORTED_10baseT_Half |
| 4318 | | SUPPORTED_10baseT_Full |
| 4319 | | SUPPORTED_100baseT_Half |
| 4320 | | SUPPORTED_100baseT_Full |
| 4321 | | SUPPORTED_Autoneg |
| 4322 | | SUPPORTED_MII |
| 4323 | | SUPPORTED_TP); |
| 4324 | |
| 4325 | if (adapter->pdev->device != ET131X_PCI_DEVICE_ID_FAST) |
| 4326 | phydev->supported |= SUPPORTED_1000baseT_Full; |
| 4327 | |
| 4328 | phydev->advertising = phydev->supported; |
| 4329 | adapter->phydev = phydev; |
| 4330 | |
| 4331 | dev_info(&adapter->pdev->dev, "attached PHY driver [%s] " |
| 4332 | "(mii_bus:phy_addr=%s)\n", |
| 4333 | phydev->drv->name, dev_name(&phydev->dev)); |
| 4334 | |
| 4335 | return 0; |
| 4336 | } |
| 4337 | |
| 4338 | /** |
| 4339 | * et131x_adapter_init |
| 4340 | * @adapter: pointer to the private adapter struct |
| 4341 | * @pdev: pointer to the PCI device |
| 4342 | * |
| 4343 | * Initialize the data structures for the et131x_adapter object and link |
| 4344 | * them together with the platform provided device structures. |
| 4345 | */ |
| 4346 | static struct et131x_adapter *et131x_adapter_init(struct net_device *netdev, |
| 4347 | struct pci_dev *pdev) |
| 4348 | { |
| 4349 | static const u8 default_mac[] = { 0x00, 0x05, 0x3d, 0x00, 0x02, 0x00 }; |
| 4350 | |
| 4351 | struct et131x_adapter *adapter; |
| 4352 | |
| 4353 | /* Allocate private adapter struct and copy in relevant information */ |
| 4354 | adapter = netdev_priv(netdev); |
| 4355 | adapter->pdev = pci_dev_get(pdev); |
| 4356 | adapter->netdev = netdev; |
| 4357 | |
| 4358 | /* Do the same for the netdev struct */ |
| 4359 | netdev->irq = pdev->irq; |
| 4360 | netdev->base_addr = pci_resource_start(pdev, 0); |
| 4361 | |
| 4362 | /* Initialize spinlocks here */ |
| 4363 | spin_lock_init(&adapter->lock); |
| 4364 | spin_lock_init(&adapter->tcb_send_qlock); |
| 4365 | spin_lock_init(&adapter->tcb_ready_qlock); |
| 4366 | spin_lock_init(&adapter->send_hw_lock); |
| 4367 | spin_lock_init(&adapter->rcv_lock); |
| 4368 | spin_lock_init(&adapter->rcv_pend_lock); |
| 4369 | spin_lock_init(&adapter->fbr_lock); |
| 4370 | spin_lock_init(&adapter->phy_lock); |
| 4371 | |
| 4372 | adapter->registry_jumbo_packet = 1514; /* 1514-9216 */ |
| 4373 | |
| 4374 | /* Set the MAC address to a default */ |
| 4375 | memcpy(adapter->addr, default_mac, ETH_ALEN); |
| 4376 | |
| 4377 | return adapter; |
| 4378 | } |
| 4379 | |
| 4380 | /** |
| 4381 | * et131x_pci_setup - Perform device initialization |
| 4382 | * @pdev: a pointer to the device's pci_dev structure |
| 4383 | * @ent: this device's entry in the pci_device_id table |
| 4384 | * |
| 4385 | * Returns 0 on success, errno on failure (as defined in errno.h) |
| 4386 | * |
| 4387 | * Registered in the pci_driver structure, this function is called when the |
| 4388 | * PCI subsystem finds a new PCI device which matches the information |
| 4389 | * contained in the pci_device_id table. This routine is the equivalent to |
| 4390 | * a device insertion routine. |
| 4391 | */ |
| 4392 | static int __devinit et131x_pci_setup(struct pci_dev *pdev, |
| 4393 | const struct pci_device_id *ent) |
| 4394 | { |
| 4395 | int result; |
| 4396 | int pm_cap; |
| 4397 | struct net_device *netdev; |
| 4398 | struct et131x_adapter *adapter; |
| 4399 | int ii; |
| 4400 | |
| 4401 | result = pci_enable_device(pdev); |
| 4402 | if (result) { |
| 4403 | dev_err(&pdev->dev, "pci_enable_device() failed\n"); |
| 4404 | goto err_out; |
| 4405 | } |
| 4406 | |
| 4407 | /* Perform some basic PCI checks */ |
| 4408 | if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { |
| 4409 | dev_err(&pdev->dev, "Can't find PCI device's base address\n"); |
| 4410 | goto err_disable; |
| 4411 | } |
| 4412 | |
| 4413 | if (pci_request_regions(pdev, DRIVER_NAME)) { |
| 4414 | dev_err(&pdev->dev, "Can't get PCI resources\n"); |
| 4415 | goto err_disable; |
| 4416 | } |
| 4417 | |
| 4418 | pci_set_master(pdev); |
| 4419 | |
| 4420 | /* Query PCI for Power Mgmt Capabilities |
| 4421 | * |
| 4422 | * NOTE: Now reading PowerMgmt in another location; is this still |
| 4423 | * needed? |
| 4424 | */ |
| 4425 | pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); |
| 4426 | if (!pm_cap) { |
| 4427 | dev_err(&pdev->dev, |
| 4428 | "Cannot find Power Management capabilities\n"); |
| 4429 | result = -EIO; |
| 4430 | goto err_release_res; |
| 4431 | } |
| 4432 | |
| 4433 | /* Check the DMA addressing support of this device */ |
| 4434 | if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) { |
| 4435 | result = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); |
| 4436 | if (result) { |
| 4437 | dev_err(&pdev->dev, |
| 4438 | "Unable to obtain 64 bit DMA for consistent allocations\n"); |
| 4439 | goto err_release_res; |
| 4440 | } |
| 4441 | } else if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) { |
| 4442 | result = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); |
| 4443 | if (result) { |
| 4444 | dev_err(&pdev->dev, |
| 4445 | "Unable to obtain 32 bit DMA for consistent allocations\n"); |
| 4446 | goto err_release_res; |
| 4447 | } |
| 4448 | } else { |
| 4449 | dev_err(&pdev->dev, "No usable DMA addressing method\n"); |
| 4450 | result = -EIO; |
| 4451 | goto err_release_res; |
| 4452 | } |
| 4453 | |
| 4454 | /* Allocate netdev and private adapter structs */ |
| 4455 | netdev = et131x_device_alloc(); |
| 4456 | if (!netdev) { |
| 4457 | dev_err(&pdev->dev, "Couldn't alloc netdev struct\n"); |
| 4458 | result = -ENOMEM; |
| 4459 | goto err_release_res; |
| 4460 | } |
| 4461 | |
| 4462 | SET_NETDEV_DEV(netdev, &pdev->dev); |
| 4463 | et131x_set_ethtool_ops(netdev); |
| 4464 | |
| 4465 | adapter = et131x_adapter_init(netdev, pdev); |
| 4466 | |
| 4467 | /* Initialise the PCI setup for the device */ |
| 4468 | et131x_pci_init(adapter, pdev); |
| 4469 | |
| 4470 | /* Map the bus-relative registers to system virtual memory */ |
| 4471 | adapter->regs = pci_ioremap_bar(pdev, 0); |
| 4472 | if (!adapter->regs) { |
| 4473 | dev_err(&pdev->dev, "Cannot map device registers\n"); |
| 4474 | result = -ENOMEM; |
| 4475 | goto err_free_dev; |
| 4476 | } |
| 4477 | |
| 4478 | /* If Phy COMA mode was enabled when we went down, disable it here. */ |
| 4479 | writel(ET_PMCSR_INIT, &adapter->regs->global.pm_csr); |
| 4480 | |
| 4481 | /* Issue a global reset to the et1310 */ |
| 4482 | et131x_soft_reset(adapter); |
| 4483 | |
| 4484 | /* Disable all interrupts (paranoid) */ |
| 4485 | et131x_disable_interrupts(adapter); |
| 4486 | |
| 4487 | /* Allocate DMA memory */ |
| 4488 | result = et131x_adapter_memory_alloc(adapter); |
| 4489 | if (result) { |
| 4490 | dev_err(&pdev->dev, "Could not alloc adapater memory (DMA)\n"); |
| 4491 | goto err_iounmap; |
| 4492 | } |
| 4493 | |
| 4494 | /* Init send data structures */ |
| 4495 | et131x_init_send(adapter); |
| 4496 | |
| 4497 | /* Set up the task structure for the ISR's deferred handler */ |
| 4498 | INIT_WORK(&adapter->task, et131x_isr_handler); |
| 4499 | |
| 4500 | /* Copy address into the net_device struct */ |
| 4501 | memcpy(netdev->dev_addr, adapter->addr, ETH_ALEN); |
| 4502 | |
| 4503 | /* Init variable for counting how long we do not have link status */ |
| 4504 | adapter->boot_coma = 0; |
| 4505 | et1310_disable_phy_coma(adapter); |
| 4506 | |
| 4507 | /* Setup the mii_bus struct */ |
| 4508 | adapter->mii_bus = mdiobus_alloc(); |
| 4509 | if (!adapter->mii_bus) { |
| 4510 | dev_err(&pdev->dev, "Alloc of mii_bus struct failed\n"); |
| 4511 | goto err_mem_free; |
| 4512 | } |
| 4513 | |
| 4514 | adapter->mii_bus->name = "et131x_eth_mii"; |
| 4515 | snprintf(adapter->mii_bus->id, MII_BUS_ID_SIZE, "%x", |
| 4516 | (adapter->pdev->bus->number << 8) | adapter->pdev->devfn); |
| 4517 | adapter->mii_bus->priv = netdev; |
| 4518 | adapter->mii_bus->read = et131x_mdio_read; |
| 4519 | adapter->mii_bus->write = et131x_mdio_write; |
| 4520 | adapter->mii_bus->reset = et131x_mdio_reset; |
| 4521 | adapter->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL); |
| 4522 | if (!adapter->mii_bus->irq) { |
| 4523 | dev_err(&pdev->dev, "mii_bus irq allocation failed\n"); |
| 4524 | goto err_mdio_free; |
| 4525 | } |
| 4526 | |
| 4527 | for (ii = 0; ii < PHY_MAX_ADDR; ii++) |
| 4528 | adapter->mii_bus->irq[ii] = PHY_POLL; |
| 4529 | |
| 4530 | if (mdiobus_register(adapter->mii_bus)) { |
| 4531 | dev_err(&pdev->dev, "failed to register MII bus\n"); |
| 4532 | mdiobus_free(adapter->mii_bus); |
| 4533 | goto err_mdio_free_irq; |
| 4534 | } |
| 4535 | |
| 4536 | if (et131x_mii_probe(netdev)) { |
| 4537 | dev_err(&pdev->dev, "failed to probe MII bus\n"); |
| 4538 | goto err_mdio_unregister; |
| 4539 | } |
| 4540 | |
| 4541 | /* Setup et1310 as per the documentation */ |
| 4542 | et131x_adapter_setup(adapter); |
| 4543 | |
| 4544 | /* We can enable interrupts now |
| 4545 | * |
| 4546 | * NOTE - Because registration of interrupt handler is done in the |
| 4547 | * device's open(), defer enabling device interrupts to that |
| 4548 | * point |
| 4549 | */ |
| 4550 | |
| 4551 | /* Register the net_device struct with the Linux network layer */ |
| 4552 | result = register_netdev(netdev); |
| 4553 | if (result != 0) { |
| 4554 | dev_err(&pdev->dev, "register_netdev() failed\n"); |
| 4555 | goto err_mdio_unregister; |
| 4556 | } |
| 4557 | |
| 4558 | /* Register the net_device struct with the PCI subsystem. Save a copy |
| 4559 | * of the PCI config space for this device now that the device has |
| 4560 | * been initialized, just in case it needs to be quickly restored. |
| 4561 | */ |
| 4562 | pci_set_drvdata(pdev, netdev); |
| 4563 | pci_save_state(adapter->pdev); |
| 4564 | |
| 4565 | return result; |
| 4566 | |
| 4567 | err_mdio_unregister: |
| 4568 | mdiobus_unregister(adapter->mii_bus); |
| 4569 | err_mdio_free_irq: |
| 4570 | kfree(adapter->mii_bus->irq); |
| 4571 | err_mdio_free: |
| 4572 | mdiobus_free(adapter->mii_bus); |
| 4573 | err_mem_free: |
| 4574 | et131x_adapter_memory_free(adapter); |
| 4575 | err_iounmap: |
| 4576 | iounmap(adapter->regs); |
| 4577 | err_free_dev: |
| 4578 | pci_dev_put(pdev); |
| 4579 | free_netdev(netdev); |
| 4580 | err_release_res: |
| 4581 | pci_release_regions(pdev); |
| 4582 | err_disable: |
| 4583 | pci_disable_device(pdev); |
| 4584 | err_out: |
| 4585 | return result; |
| 4586 | } |
| 4587 | |
| 4588 | /** |
| 4589 | * et131x_pci_remove |
| 4590 | * @pdev: a pointer to the device's pci_dev structure |
| 4591 | * |
| 4592 | * Registered in the pci_driver structure, this function is called when the |
| 4593 | * PCI subsystem detects that a PCI device which matches the information |
| 4594 | * contained in the pci_device_id table has been removed. |
| 4595 | */ |
| 4596 | static void __devexit et131x_pci_remove(struct pci_dev *pdev) |
| 4597 | { |
| 4598 | struct net_device *netdev = pci_get_drvdata(pdev); |
| 4599 | struct et131x_adapter *adapter = netdev_priv(netdev); |
| 4600 | |
| 4601 | unregister_netdev(netdev); |
| 4602 | mdiobus_unregister(adapter->mii_bus); |
| 4603 | kfree(adapter->mii_bus->irq); |
| 4604 | mdiobus_free(adapter->mii_bus); |
| 4605 | |
| 4606 | et131x_adapter_memory_free(adapter); |
| 4607 | iounmap(adapter->regs); |
| 4608 | pci_dev_put(pdev); |
| 4609 | |
| 4610 | free_netdev(netdev); |
| 4611 | pci_release_regions(pdev); |
| 4612 | pci_disable_device(pdev); |
| 4613 | } |
| 4614 | |
| 4615 | #ifdef CONFIG_PM_SLEEP |
| 4616 | static int et131x_suspend(struct device *dev) |
| 4617 | { |
| 4618 | struct pci_dev *pdev = to_pci_dev(dev); |
| 4619 | struct net_device *netdev = pci_get_drvdata(pdev); |
| 4620 | |
| 4621 | if (netif_running(netdev)) { |
| 4622 | netif_device_detach(netdev); |
| 4623 | et131x_down(netdev); |
| 4624 | pci_save_state(pdev); |
| 4625 | } |
| 4626 | |
| 4627 | return 0; |
| 4628 | } |
| 4629 | |
| 4630 | static int et131x_resume(struct device *dev) |
| 4631 | { |
| 4632 | struct pci_dev *pdev = to_pci_dev(dev); |
| 4633 | struct net_device *netdev = pci_get_drvdata(pdev); |
| 4634 | |
| 4635 | if (netif_running(netdev)) { |
| 4636 | pci_restore_state(pdev); |
| 4637 | et131x_up(netdev); |
| 4638 | netif_device_attach(netdev); |
| 4639 | } |
| 4640 | |
| 4641 | return 0; |
| 4642 | } |
| 4643 | |
| 4644 | static SIMPLE_DEV_PM_OPS(et131x_pm_ops, et131x_suspend, et131x_resume); |
| 4645 | #define ET131X_PM_OPS (&et131x_pm_ops) |
| 4646 | #else |
| 4647 | #define ET131X_PM_OPS NULL |
| 4648 | #endif |
| 4649 | |
| 4650 | static struct pci_device_id et131x_pci_table[] __devinitdata = { |
| 4651 | {ET131X_PCI_VENDOR_ID, ET131X_PCI_DEVICE_ID_GIG, PCI_ANY_ID, |
| 4652 | PCI_ANY_ID, 0, 0, 0UL}, |
| 4653 | {ET131X_PCI_VENDOR_ID, ET131X_PCI_DEVICE_ID_FAST, PCI_ANY_ID, |
| 4654 | PCI_ANY_ID, 0, 0, 0UL}, |
| 4655 | {0,} |
| 4656 | }; |
| 4657 | |
| 4658 | MODULE_DEVICE_TABLE(pci, et131x_pci_table); |
| 4659 | |
| 4660 | static struct pci_driver et131x_driver = { |
| 4661 | .name = DRIVER_NAME, |
| 4662 | .id_table = et131x_pci_table, |
| 4663 | .probe = et131x_pci_setup, |
| 4664 | .remove = __devexit_p(et131x_pci_remove), |
| 4665 | .driver.pm = ET131X_PM_OPS, |
| 4666 | }; |
| 4667 | |
| 4668 | /** |
| 4669 | * et131x_init_module - The "main" entry point called on driver initialization |
| 4670 | * |
| 4671 | * Returns 0 on success, errno on failure (as defined in errno.h) |
| 4672 | */ |
| 4673 | static int __init et131x_init_module(void) |
| 4674 | { |
| 4675 | return pci_register_driver(&et131x_driver); |
| 4676 | } |
| 4677 | |
| 4678 | /** |
| 4679 | * et131x_cleanup_module - The entry point called on driver cleanup |
| 4680 | */ |
| 4681 | static void __exit et131x_cleanup_module(void) |
| 4682 | { |
| 4683 | pci_unregister_driver(&et131x_driver); |
| 4684 | } |
| 4685 | |
| 4686 | module_init(et131x_init_module); |
| 4687 | module_exit(et131x_cleanup_module); |
| 4688 | |
| 4689 | /* ISR functions */ |
| 4690 | |
| 4691 | /** |
| 4692 | * et131x_enable_interrupts - enable interrupt |
| 4693 | * @adapter: et131x device |
| 4694 | * |
| 4695 | * Enable the appropriate interrupts on the ET131x according to our |
| 4696 | * configuration |
| 4697 | */ |
| 4698 | void et131x_enable_interrupts(struct et131x_adapter *adapter) |
| 4699 | { |
| 4700 | u32 mask; |
| 4701 | |
| 4702 | /* Enable all global interrupts */ |
| 4703 | if (adapter->flowcontrol == FLOW_TXONLY || |
| 4704 | adapter->flowcontrol == FLOW_BOTH) |
| 4705 | mask = INT_MASK_ENABLE; |
| 4706 | else |
| 4707 | mask = INT_MASK_ENABLE_NO_FLOW; |
| 4708 | |
| 4709 | writel(mask, &adapter->regs->global.int_mask); |
| 4710 | } |
| 4711 | |
| 4712 | /** |
| 4713 | * et131x_disable_interrupts - interrupt disable |
| 4714 | * @adapter: et131x device |
| 4715 | * |
| 4716 | * Block all interrupts from the et131x device at the device itself |
| 4717 | */ |
| 4718 | void et131x_disable_interrupts(struct et131x_adapter *adapter) |
| 4719 | { |
| 4720 | /* Disable all global interrupts */ |
| 4721 | writel(INT_MASK_DISABLE, &adapter->regs->global.int_mask); |
| 4722 | } |
| 4723 | |
| 4724 | |
| 4725 | /** |
| 4726 | * et131x_isr - The Interrupt Service Routine for the driver. |
| 4727 | * @irq: the IRQ on which the interrupt was received. |
| 4728 | * @dev_id: device-specific info (here a pointer to a net_device struct) |
| 4729 | * |
| 4730 | * Returns a value indicating if the interrupt was handled. |
| 4731 | */ |
| 4732 | irqreturn_t et131x_isr(int irq, void *dev_id) |
| 4733 | { |
| 4734 | bool handled = true; |
| 4735 | struct net_device *netdev = (struct net_device *)dev_id; |
| 4736 | struct et131x_adapter *adapter = NULL; |
| 4737 | u32 status; |
| 4738 | |
| 4739 | if (!netif_device_present(netdev)) { |
| 4740 | handled = false; |
| 4741 | goto out; |
| 4742 | } |
| 4743 | |
| 4744 | adapter = netdev_priv(netdev); |
| 4745 | |
| 4746 | /* If the adapter is in low power state, then it should not |
| 4747 | * recognize any interrupt |
| 4748 | */ |
| 4749 | |
| 4750 | /* Disable Device Interrupts */ |
| 4751 | et131x_disable_interrupts(adapter); |
| 4752 | |
| 4753 | /* Get a copy of the value in the interrupt status register |
| 4754 | * so we can process the interrupting section |
| 4755 | */ |
| 4756 | status = readl(&adapter->regs->global.int_status); |
| 4757 | |
| 4758 | if (adapter->flowcontrol == FLOW_TXONLY || |
| 4759 | adapter->flowcontrol == FLOW_BOTH) { |
| 4760 | status &= ~INT_MASK_ENABLE; |
| 4761 | } else { |
| 4762 | status &= ~INT_MASK_ENABLE_NO_FLOW; |
| 4763 | } |
| 4764 | |
| 4765 | /* Make sure this is our interrupt */ |
| 4766 | if (!status) { |
| 4767 | handled = false; |
| 4768 | et131x_enable_interrupts(adapter); |
| 4769 | goto out; |
| 4770 | } |
| 4771 | |
| 4772 | /* This is our interrupt, so process accordingly */ |
| 4773 | |
| 4774 | if (status & ET_INTR_WATCHDOG) { |
| 4775 | struct tcb *tcb = adapter->tx_ring.send_head; |
| 4776 | |
| 4777 | if (tcb) |
| 4778 | if (++tcb->stale > 1) |
| 4779 | status |= ET_INTR_TXDMA_ISR; |
| 4780 | |
| 4781 | if (adapter->rx_ring.unfinished_receives) |
| 4782 | status |= ET_INTR_RXDMA_XFR_DONE; |
| 4783 | else if (tcb == NULL) |
| 4784 | writel(0, &adapter->regs->global.watchdog_timer); |
| 4785 | |
| 4786 | status &= ~ET_INTR_WATCHDOG; |
| 4787 | } |
| 4788 | |
| 4789 | if (status == 0) { |
| 4790 | /* This interrupt has in some way been "handled" by |
| 4791 | * the ISR. Either it was a spurious Rx interrupt, or |
| 4792 | * it was a Tx interrupt that has been filtered by |
| 4793 | * the ISR. |
| 4794 | */ |
| 4795 | et131x_enable_interrupts(adapter); |
| 4796 | goto out; |
| 4797 | } |
| 4798 | |
| 4799 | /* We need to save the interrupt status value for use in our |
| 4800 | * DPC. We will clear the software copy of that in that |
| 4801 | * routine. |
| 4802 | */ |
| 4803 | adapter->stats.interrupt_status = status; |
| 4804 | |
| 4805 | /* Schedule the ISR handler as a bottom-half task in the |
| 4806 | * kernel's tq_immediate queue, and mark the queue for |
| 4807 | * execution |
| 4808 | */ |
| 4809 | schedule_work(&adapter->task); |
| 4810 | out: |
| 4811 | return IRQ_RETVAL(handled); |
| 4812 | } |
| 4813 | |
| 4814 | /** |
| 4815 | * et131x_isr_handler - The ISR handler |
| 4816 | * @p_adapter, a pointer to the device's private adapter structure |
| 4817 | * |
| 4818 | * scheduled to run in a deferred context by the ISR. This is where the ISR's |
| 4819 | * work actually gets done. |
| 4820 | */ |
| 4821 | void et131x_isr_handler(struct work_struct *work) |
| 4822 | { |
| 4823 | struct et131x_adapter *adapter = |
| 4824 | container_of(work, struct et131x_adapter, task); |
| 4825 | u32 status = adapter->stats.interrupt_status; |
| 4826 | struct address_map __iomem *iomem = adapter->regs; |
| 4827 | |
| 4828 | /* |
| 4829 | * These first two are by far the most common. Once handled, we clear |
| 4830 | * their two bits in the status word. If the word is now zero, we |
| 4831 | * exit. |
| 4832 | */ |
| 4833 | /* Handle all the completed Transmit interrupts */ |
| 4834 | if (status & ET_INTR_TXDMA_ISR) |
| 4835 | et131x_handle_send_interrupt(adapter); |
| 4836 | |
| 4837 | /* Handle all the completed Receives interrupts */ |
| 4838 | if (status & ET_INTR_RXDMA_XFR_DONE) |
| 4839 | et131x_handle_recv_interrupt(adapter); |
| 4840 | |
| 4841 | status &= 0xffffffd7; |
| 4842 | |
| 4843 | if (status) { |
| 4844 | /* Handle the TXDMA Error interrupt */ |
| 4845 | if (status & ET_INTR_TXDMA_ERR) { |
| 4846 | u32 txdma_err; |
| 4847 | |
| 4848 | /* Following read also clears the register (COR) */ |
| 4849 | txdma_err = readl(&iomem->txdma.tx_dma_error); |
| 4850 | |
| 4851 | dev_warn(&adapter->pdev->dev, |
| 4852 | "TXDMA_ERR interrupt, error = %d\n", |
| 4853 | txdma_err); |
| 4854 | } |
| 4855 | |
| 4856 | /* Handle Free Buffer Ring 0 and 1 Low interrupt */ |
| 4857 | if (status & |
| 4858 | (ET_INTR_RXDMA_FB_R0_LOW | ET_INTR_RXDMA_FB_R1_LOW)) { |
| 4859 | /* |
| 4860 | * This indicates the number of unused buffers in |
| 4861 | * RXDMA free buffer ring 0 is <= the limit you |
| 4862 | * programmed. Free buffer resources need to be |
| 4863 | * returned. Free buffers are consumed as packets |
| 4864 | * are passed from the network to the host. The host |
| 4865 | * becomes aware of the packets from the contents of |
| 4866 | * the packet status ring. This ring is queried when |
| 4867 | * the packet done interrupt occurs. Packets are then |
| 4868 | * passed to the OS. When the OS is done with the |
| 4869 | * packets the resources can be returned to the |
| 4870 | * ET1310 for re-use. This interrupt is one method of |
| 4871 | * returning resources. |
| 4872 | */ |
| 4873 | |
| 4874 | /* If the user has flow control on, then we will |
| 4875 | * send a pause packet, otherwise just exit |
| 4876 | */ |
| 4877 | if (adapter->flowcontrol == FLOW_TXONLY || |
| 4878 | adapter->flowcontrol == FLOW_BOTH) { |
| 4879 | u32 pm_csr; |
| 4880 | |
| 4881 | /* Tell the device to send a pause packet via |
| 4882 | * the back pressure register (bp req and |
| 4883 | * bp xon/xoff) |
| 4884 | */ |
| 4885 | pm_csr = readl(&iomem->global.pm_csr); |
| 4886 | if (!et1310_in_phy_coma(adapter)) |
| 4887 | writel(3, &iomem->txmac.bp_ctrl); |
| 4888 | } |
| 4889 | } |
| 4890 | |
| 4891 | /* Handle Packet Status Ring Low Interrupt */ |
| 4892 | if (status & ET_INTR_RXDMA_STAT_LOW) { |
| 4893 | |
| 4894 | /* |
| 4895 | * Same idea as with the two Free Buffer Rings. |
| 4896 | * Packets going from the network to the host each |
| 4897 | * consume a free buffer resource and a packet status |
| 4898 | * resource. These resoures are passed to the OS. |
| 4899 | * When the OS is done with the resources, they need |
| 4900 | * to be returned to the ET1310. This is one method |
| 4901 | * of returning the resources. |
| 4902 | */ |
| 4903 | } |
| 4904 | |
| 4905 | /* Handle RXDMA Error Interrupt */ |
| 4906 | if (status & ET_INTR_RXDMA_ERR) { |
| 4907 | /* |
| 4908 | * The rxdma_error interrupt is sent when a time-out |
| 4909 | * on a request issued by the JAGCore has occurred or |
| 4910 | * a completion is returned with an un-successful |
| 4911 | * status. In both cases the request is considered |
| 4912 | * complete. The JAGCore will automatically re-try the |
| 4913 | * request in question. Normally information on events |
| 4914 | * like these are sent to the host using the "Advanced |
| 4915 | * Error Reporting" capability. This interrupt is |
| 4916 | * another way of getting similar information. The |
| 4917 | * only thing required is to clear the interrupt by |
| 4918 | * reading the ISR in the global resources. The |
| 4919 | * JAGCore will do a re-try on the request. Normally |
| 4920 | * you should never see this interrupt. If you start |
| 4921 | * to see this interrupt occurring frequently then |
| 4922 | * something bad has occurred. A reset might be the |
| 4923 | * thing to do. |
| 4924 | */ |
| 4925 | /* TRAP();*/ |
| 4926 | |
| 4927 | dev_warn(&adapter->pdev->dev, |
| 4928 | "RxDMA_ERR interrupt, error %x\n", |
| 4929 | readl(&iomem->txmac.tx_test)); |
| 4930 | } |
| 4931 | |
| 4932 | /* Handle the Wake on LAN Event */ |
| 4933 | if (status & ET_INTR_WOL) { |
| 4934 | /* |
| 4935 | * This is a secondary interrupt for wake on LAN. |
| 4936 | * The driver should never see this, if it does, |
| 4937 | * something serious is wrong. We will TRAP the |
| 4938 | * message when we are in DBG mode, otherwise we |
| 4939 | * will ignore it. |
| 4940 | */ |
| 4941 | dev_err(&adapter->pdev->dev, "WAKE_ON_LAN interrupt\n"); |
| 4942 | } |
| 4943 | |
| 4944 | /* Let's move on to the TxMac */ |
| 4945 | if (status & ET_INTR_TXMAC) { |
| 4946 | u32 err = readl(&iomem->txmac.err); |
| 4947 | |
| 4948 | /* |
| 4949 | * When any of the errors occur and TXMAC generates |
| 4950 | * an interrupt to report these errors, it usually |
| 4951 | * means that TXMAC has detected an error in the data |
| 4952 | * stream retrieved from the on-chip Tx Q. All of |
| 4953 | * these errors are catastrophic and TXMAC won't be |
| 4954 | * able to recover data when these errors occur. In |
| 4955 | * a nutshell, the whole Tx path will have to be reset |
| 4956 | * and re-configured afterwards. |
| 4957 | */ |
| 4958 | dev_warn(&adapter->pdev->dev, |
| 4959 | "TXMAC interrupt, error 0x%08x\n", |
| 4960 | err); |
| 4961 | |
| 4962 | /* If we are debugging, we want to see this error, |
| 4963 | * otherwise we just want the device to be reset and |
| 4964 | * continue |
| 4965 | */ |
| 4966 | } |
| 4967 | |
| 4968 | /* Handle RXMAC Interrupt */ |
| 4969 | if (status & ET_INTR_RXMAC) { |
| 4970 | /* |
| 4971 | * These interrupts are catastrophic to the device, |
| 4972 | * what we need to do is disable the interrupts and |
| 4973 | * set the flag to cause us to reset so we can solve |
| 4974 | * this issue. |
| 4975 | */ |
| 4976 | /* MP_SET_FLAG( adapter, |
| 4977 | fMP_ADAPTER_HARDWARE_ERROR); */ |
| 4978 | |
| 4979 | dev_warn(&adapter->pdev->dev, |
| 4980 | "RXMAC interrupt, error 0x%08x. Requesting reset\n", |
| 4981 | readl(&iomem->rxmac.err_reg)); |
| 4982 | |
| 4983 | dev_warn(&adapter->pdev->dev, |
| 4984 | "Enable 0x%08x, Diag 0x%08x\n", |
| 4985 | readl(&iomem->rxmac.ctrl), |
| 4986 | readl(&iomem->rxmac.rxq_diag)); |
| 4987 | |
| 4988 | /* |
| 4989 | * If we are debugging, we want to see this error, |
| 4990 | * otherwise we just want the device to be reset and |
| 4991 | * continue |
| 4992 | */ |
| 4993 | } |
| 4994 | |
| 4995 | /* Handle MAC_STAT Interrupt */ |
| 4996 | if (status & ET_INTR_MAC_STAT) { |
| 4997 | /* |
| 4998 | * This means at least one of the un-masked counters |
| 4999 | * in the MAC_STAT block has rolled over. Use this |
| 5000 | * to maintain the top, software managed bits of the |
| 5001 | * counter(s). |
| 5002 | */ |
| 5003 | et1310_handle_macstat_interrupt(adapter); |
| 5004 | } |
| 5005 | |
| 5006 | /* Handle SLV Timeout Interrupt */ |
| 5007 | if (status & ET_INTR_SLV_TIMEOUT) { |
| 5008 | /* |
| 5009 | * This means a timeout has occurred on a read or |
| 5010 | * write request to one of the JAGCore registers. The |
| 5011 | * Global Resources block has terminated the request |
| 5012 | * and on a read request, returned a "fake" value. |
| 5013 | * The most likely reasons are: Bad Address or the |
| 5014 | * addressed module is in a power-down state and |
| 5015 | * can't respond. |
| 5016 | */ |
| 5017 | } |
| 5018 | } |
| 5019 | et131x_enable_interrupts(adapter); |
| 5020 | } |
| 5021 | |
| 5022 | /* NETDEV functions */ |
| 5023 | |
| 5024 | /** |
| 5025 | * et131x_stats - Return the current device statistics. |
| 5026 | * @netdev: device whose stats are being queried |
| 5027 | * |
| 5028 | * Returns 0 on success, errno on failure (as defined in errno.h) |
| 5029 | */ |
| 5030 | static struct net_device_stats *et131x_stats(struct net_device *netdev) |
| 5031 | { |
| 5032 | struct et131x_adapter *adapter = netdev_priv(netdev); |
| 5033 | struct net_device_stats *stats = &adapter->net_stats; |
| 5034 | struct ce_stats *devstat = &adapter->stats; |
| 5035 | |
| 5036 | stats->rx_errors = devstat->rx_length_errs + |
| 5037 | devstat->rx_align_errs + |
| 5038 | devstat->rx_crc_errs + |
| 5039 | devstat->rx_code_violations + |
| 5040 | devstat->rx_other_errs; |
| 5041 | stats->tx_errors = devstat->tx_max_pkt_errs; |
| 5042 | stats->multicast = devstat->multicast_pkts_rcvd; |
| 5043 | stats->collisions = devstat->tx_collisions; |
| 5044 | |
| 5045 | stats->rx_length_errors = devstat->rx_length_errs; |
| 5046 | stats->rx_over_errors = devstat->rx_overflows; |
| 5047 | stats->rx_crc_errors = devstat->rx_crc_errs; |
| 5048 | |
| 5049 | /* NOTE: These stats don't have corresponding values in CE_STATS, |
| 5050 | * so we're going to have to update these directly from within the |
| 5051 | * TX/RX code |
| 5052 | */ |
| 5053 | /* stats->rx_bytes = 20; devstat->; */ |
| 5054 | /* stats->tx_bytes = 20; devstat->; */ |
| 5055 | /* stats->rx_dropped = devstat->; */ |
| 5056 | /* stats->tx_dropped = devstat->; */ |
| 5057 | |
| 5058 | /* NOTE: Not used, can't find analogous statistics */ |
| 5059 | /* stats->rx_frame_errors = devstat->; */ |
| 5060 | /* stats->rx_fifo_errors = devstat->; */ |
| 5061 | /* stats->rx_missed_errors = devstat->; */ |
| 5062 | |
| 5063 | /* stats->tx_aborted_errors = devstat->; */ |
| 5064 | /* stats->tx_carrier_errors = devstat->; */ |
| 5065 | /* stats->tx_fifo_errors = devstat->; */ |
| 5066 | /* stats->tx_heartbeat_errors = devstat->; */ |
| 5067 | /* stats->tx_window_errors = devstat->; */ |
| 5068 | return stats; |
| 5069 | } |
| 5070 | |
| 5071 | /** |
| 5072 | * et131x_enable_txrx - Enable tx/rx queues |
| 5073 | * @netdev: device to be enabled |
| 5074 | */ |
| 5075 | void et131x_enable_txrx(struct net_device *netdev) |
| 5076 | { |
| 5077 | struct et131x_adapter *adapter = netdev_priv(netdev); |
| 5078 | |
| 5079 | /* Enable the Tx and Rx DMA engines (if not already enabled) */ |
| 5080 | et131x_rx_dma_enable(adapter); |
| 5081 | et131x_tx_dma_enable(adapter); |
| 5082 | |
| 5083 | /* Enable device interrupts */ |
| 5084 | if (adapter->flags & fMP_ADAPTER_INTERRUPT_IN_USE) |
| 5085 | et131x_enable_interrupts(adapter); |
| 5086 | |
| 5087 | /* We're ready to move some data, so start the queue */ |
| 5088 | netif_start_queue(netdev); |
| 5089 | } |
| 5090 | |
| 5091 | /** |
| 5092 | * et131x_disable_txrx - Disable tx/rx queues |
| 5093 | * @netdev: device to be disabled |
| 5094 | */ |
| 5095 | void et131x_disable_txrx(struct net_device *netdev) |
| 5096 | { |
| 5097 | struct et131x_adapter *adapter = netdev_priv(netdev); |
| 5098 | |
| 5099 | /* First thing is to stop the queue */ |
| 5100 | netif_stop_queue(netdev); |
| 5101 | |
| 5102 | /* Stop the Tx and Rx DMA engines */ |
| 5103 | et131x_rx_dma_disable(adapter); |
| 5104 | et131x_tx_dma_disable(adapter); |
| 5105 | |
| 5106 | /* Disable device interrupts */ |
| 5107 | et131x_disable_interrupts(adapter); |
| 5108 | } |
| 5109 | |
| 5110 | /** |
| 5111 | * et131x_up - Bring up a device for use. |
| 5112 | * @netdev: device to be opened |
| 5113 | */ |
| 5114 | void et131x_up(struct net_device *netdev) |
| 5115 | { |
| 5116 | struct et131x_adapter *adapter = netdev_priv(netdev); |
| 5117 | |
| 5118 | et131x_enable_txrx(netdev); |
| 5119 | phy_start(adapter->phydev); |
| 5120 | } |
| 5121 | |
| 5122 | /** |
| 5123 | * et131x_open - Open the device for use. |
| 5124 | * @netdev: device to be opened |
| 5125 | * |
| 5126 | * Returns 0 on success, errno on failure (as defined in errno.h) |
| 5127 | */ |
| 5128 | int et131x_open(struct net_device *netdev) |
| 5129 | { |
| 5130 | int result = 0; |
| 5131 | struct et131x_adapter *adapter = netdev_priv(netdev); |
| 5132 | |
| 5133 | /* Start the timer to track NIC errors */ |
| 5134 | init_timer(&adapter->error_timer); |
| 5135 | adapter->error_timer.expires = jiffies + TX_ERROR_PERIOD * HZ / 1000; |
| 5136 | adapter->error_timer.function = et131x_error_timer_handler; |
| 5137 | adapter->error_timer.data = (unsigned long)adapter; |
| 5138 | add_timer(&adapter->error_timer); |
| 5139 | |
| 5140 | /* Register our IRQ */ |
| 5141 | result = request_irq(netdev->irq, et131x_isr, IRQF_SHARED, |
| 5142 | netdev->name, netdev); |
| 5143 | if (result) { |
| 5144 | dev_err(&adapter->pdev->dev, "could not register IRQ %d\n", |
| 5145 | netdev->irq); |
| 5146 | return result; |
| 5147 | } |
| 5148 | |
| 5149 | adapter->flags |= fMP_ADAPTER_INTERRUPT_IN_USE; |
| 5150 | |
| 5151 | et131x_up(netdev); |
| 5152 | |
| 5153 | return result; |
| 5154 | } |
| 5155 | |
| 5156 | /** |
| 5157 | * et131x_down - Bring down the device |
| 5158 | * @netdev: device to be broght down |
| 5159 | */ |
| 5160 | void et131x_down(struct net_device *netdev) |
| 5161 | { |
| 5162 | struct et131x_adapter *adapter = netdev_priv(netdev); |
| 5163 | |
| 5164 | /* Save the timestamp for the TX watchdog, prevent a timeout */ |
| 5165 | netdev->trans_start = jiffies; |
| 5166 | |
| 5167 | phy_stop(adapter->phydev); |
| 5168 | et131x_disable_txrx(netdev); |
| 5169 | } |
| 5170 | |
| 5171 | /** |
| 5172 | * et131x_close - Close the device |
| 5173 | * @netdev: device to be closed |
| 5174 | * |
| 5175 | * Returns 0 on success, errno on failure (as defined in errno.h) |
| 5176 | */ |
| 5177 | int et131x_close(struct net_device *netdev) |
| 5178 | { |
| 5179 | struct et131x_adapter *adapter = netdev_priv(netdev); |
| 5180 | |
| 5181 | et131x_down(netdev); |
| 5182 | |
| 5183 | adapter->flags &= ~fMP_ADAPTER_INTERRUPT_IN_USE; |
| 5184 | free_irq(netdev->irq, netdev); |
| 5185 | |
| 5186 | /* Stop the error timer */ |
| 5187 | return del_timer_sync(&adapter->error_timer); |
| 5188 | } |
| 5189 | |
| 5190 | /** |
| 5191 | * et131x_ioctl - The I/O Control handler for the driver |
| 5192 | * @netdev: device on which the control request is being made |
| 5193 | * @reqbuf: a pointer to the IOCTL request buffer |
| 5194 | * @cmd: the IOCTL command code |
| 5195 | * |
| 5196 | * Returns 0 on success, errno on failure (as defined in errno.h) |
| 5197 | */ |
| 5198 | static int et131x_ioctl(struct net_device *netdev, struct ifreq *reqbuf, int cmd) |
| 5199 | { |
| 5200 | struct et131x_adapter *adapter = netdev_priv(netdev); |
| 5201 | |
| 5202 | if (!adapter->phydev) |
| 5203 | return -EINVAL; |
| 5204 | |
| 5205 | return phy_mii_ioctl(adapter->phydev, reqbuf, cmd); |
| 5206 | } |
| 5207 | |
| 5208 | /** |
| 5209 | * et131x_set_packet_filter - Configures the Rx Packet filtering on the device |
| 5210 | * @adapter: pointer to our private adapter structure |
| 5211 | * |
| 5212 | * FIXME: lot of dups with MAC code |
| 5213 | * |
| 5214 | * Returns 0 on success, errno on failure |
| 5215 | */ |
| 5216 | static int et131x_set_packet_filter(struct et131x_adapter *adapter) |
| 5217 | { |
| 5218 | int status = 0; |
| 5219 | uint32_t filter = adapter->packet_filter; |
| 5220 | u32 ctrl; |
| 5221 | u32 pf_ctrl; |
| 5222 | |
| 5223 | ctrl = readl(&adapter->regs->rxmac.ctrl); |
| 5224 | pf_ctrl = readl(&adapter->regs->rxmac.pf_ctrl); |
| 5225 | |
| 5226 | /* Default to disabled packet filtering. Enable it in the individual |
| 5227 | * case statements that require the device to filter something |
| 5228 | */ |
| 5229 | ctrl |= 0x04; |
| 5230 | |
| 5231 | /* Set us to be in promiscuous mode so we receive everything, this |
| 5232 | * is also true when we get a packet filter of 0 |
| 5233 | */ |
| 5234 | if ((filter & ET131X_PACKET_TYPE_PROMISCUOUS) || filter == 0) |
| 5235 | pf_ctrl &= ~7; /* Clear filter bits */ |
| 5236 | else { |
| 5237 | /* |
| 5238 | * Set us up with Multicast packet filtering. Three cases are |
| 5239 | * possible - (1) we have a multi-cast list, (2) we receive ALL |
| 5240 | * multicast entries or (3) we receive none. |
| 5241 | */ |
| 5242 | if (filter & ET131X_PACKET_TYPE_ALL_MULTICAST) |
| 5243 | pf_ctrl &= ~2; /* Multicast filter bit */ |
| 5244 | else { |
| 5245 | et1310_setup_device_for_multicast(adapter); |
| 5246 | pf_ctrl |= 2; |
| 5247 | ctrl &= ~0x04; |
| 5248 | } |
| 5249 | |
| 5250 | /* Set us up with Unicast packet filtering */ |
| 5251 | if (filter & ET131X_PACKET_TYPE_DIRECTED) { |
| 5252 | et1310_setup_device_for_unicast(adapter); |
| 5253 | pf_ctrl |= 4; |
| 5254 | ctrl &= ~0x04; |
| 5255 | } |
| 5256 | |
| 5257 | /* Set us up with Broadcast packet filtering */ |
| 5258 | if (filter & ET131X_PACKET_TYPE_BROADCAST) { |
| 5259 | pf_ctrl |= 1; /* Broadcast filter bit */ |
| 5260 | ctrl &= ~0x04; |
| 5261 | } else |
| 5262 | pf_ctrl &= ~1; |
| 5263 | |
| 5264 | /* Setup the receive mac configuration registers - Packet |
| 5265 | * Filter control + the enable / disable for packet filter |
| 5266 | * in the control reg. |
| 5267 | */ |
| 5268 | writel(pf_ctrl, &adapter->regs->rxmac.pf_ctrl); |
| 5269 | writel(ctrl, &adapter->regs->rxmac.ctrl); |
| 5270 | } |
| 5271 | return status; |
| 5272 | } |
| 5273 | |
| 5274 | /** |
| 5275 | * et131x_multicast - The handler to configure multicasting on the interface |
| 5276 | * @netdev: a pointer to a net_device struct representing the device |
| 5277 | */ |
| 5278 | static void et131x_multicast(struct net_device *netdev) |
| 5279 | { |
| 5280 | struct et131x_adapter *adapter = netdev_priv(netdev); |
| 5281 | uint32_t packet_filter = 0; |
| 5282 | unsigned long flags; |
| 5283 | struct netdev_hw_addr *ha; |
| 5284 | int i; |
| 5285 | |
| 5286 | spin_lock_irqsave(&adapter->lock, flags); |
| 5287 | |
| 5288 | /* Before we modify the platform-independent filter flags, store them |
| 5289 | * locally. This allows us to determine if anything's changed and if |
| 5290 | * we even need to bother the hardware |
| 5291 | */ |
| 5292 | packet_filter = adapter->packet_filter; |
| 5293 | |
| 5294 | /* Clear the 'multicast' flag locally; because we only have a single |
| 5295 | * flag to check multicast, and multiple multicast addresses can be |
| 5296 | * set, this is the easiest way to determine if more than one |
| 5297 | * multicast address is being set. |
| 5298 | */ |
| 5299 | packet_filter &= ~ET131X_PACKET_TYPE_MULTICAST; |
| 5300 | |
| 5301 | /* Check the net_device flags and set the device independent flags |
| 5302 | * accordingly |
| 5303 | */ |
| 5304 | |
| 5305 | if (netdev->flags & IFF_PROMISC) |
| 5306 | adapter->packet_filter |= ET131X_PACKET_TYPE_PROMISCUOUS; |
| 5307 | else |
| 5308 | adapter->packet_filter &= ~ET131X_PACKET_TYPE_PROMISCUOUS; |
| 5309 | |
| 5310 | if (netdev->flags & IFF_ALLMULTI) |
| 5311 | adapter->packet_filter |= ET131X_PACKET_TYPE_ALL_MULTICAST; |
| 5312 | |
| 5313 | if (netdev_mc_count(netdev) > NIC_MAX_MCAST_LIST) |
| 5314 | adapter->packet_filter |= ET131X_PACKET_TYPE_ALL_MULTICAST; |
| 5315 | |
| 5316 | if (netdev_mc_count(netdev) < 1) { |
| 5317 | adapter->packet_filter &= ~ET131X_PACKET_TYPE_ALL_MULTICAST; |
| 5318 | adapter->packet_filter &= ~ET131X_PACKET_TYPE_MULTICAST; |
| 5319 | } else |
| 5320 | adapter->packet_filter |= ET131X_PACKET_TYPE_MULTICAST; |
| 5321 | |
| 5322 | /* Set values in the private adapter struct */ |
| 5323 | i = 0; |
| 5324 | netdev_for_each_mc_addr(ha, netdev) { |
| 5325 | if (i == NIC_MAX_MCAST_LIST) |
| 5326 | break; |
| 5327 | memcpy(adapter->multicast_list[i++], ha->addr, ETH_ALEN); |
| 5328 | } |
| 5329 | adapter->multicast_addr_count = i; |
| 5330 | |
| 5331 | /* Are the new flags different from the previous ones? If not, then no |
| 5332 | * action is required |
| 5333 | * |
| 5334 | * NOTE - This block will always update the multicast_list with the |
| 5335 | * hardware, even if the addresses aren't the same. |
| 5336 | */ |
| 5337 | if (packet_filter != adapter->packet_filter) { |
| 5338 | /* Call the device's filter function */ |
| 5339 | et131x_set_packet_filter(adapter); |
| 5340 | } |
| 5341 | spin_unlock_irqrestore(&adapter->lock, flags); |
| 5342 | } |
| 5343 | |
| 5344 | /** |
| 5345 | * et131x_tx - The handler to tx a packet on the device |
| 5346 | * @skb: data to be Tx'd |
| 5347 | * @netdev: device on which data is to be Tx'd |
| 5348 | * |
| 5349 | * Returns 0 on success, errno on failure (as defined in errno.h) |
| 5350 | */ |
| 5351 | static int et131x_tx(struct sk_buff *skb, struct net_device *netdev) |
| 5352 | { |
| 5353 | int status = 0; |
| 5354 | |
| 5355 | /* Save the timestamp for the TX timeout watchdog */ |
| 5356 | netdev->trans_start = jiffies; |
| 5357 | |
| 5358 | /* Call the device-specific data Tx routine */ |
| 5359 | status = et131x_send_packets(skb, netdev); |
| 5360 | |
| 5361 | /* Check status and manage the netif queue if necessary */ |
| 5362 | if (status != 0) { |
| 5363 | if (status == -ENOMEM) { |
| 5364 | /* Put the queue to sleep until resources are |
| 5365 | * available |
| 5366 | */ |
| 5367 | netif_stop_queue(netdev); |
| 5368 | status = NETDEV_TX_BUSY; |
| 5369 | } else { |
| 5370 | status = NETDEV_TX_OK; |
| 5371 | } |
| 5372 | } |
| 5373 | return status; |
| 5374 | } |
| 5375 | |
| 5376 | /** |
| 5377 | * et131x_tx_timeout - Timeout handler |
| 5378 | * @netdev: a pointer to a net_device struct representing the device |
| 5379 | * |
| 5380 | * The handler called when a Tx request times out. The timeout period is |
| 5381 | * specified by the 'tx_timeo" element in the net_device structure (see |
| 5382 | * et131x_alloc_device() to see how this value is set). |
| 5383 | */ |
| 5384 | static void et131x_tx_timeout(struct net_device *netdev) |
| 5385 | { |
| 5386 | struct et131x_adapter *adapter = netdev_priv(netdev); |
| 5387 | struct tcb *tcb; |
| 5388 | unsigned long flags; |
| 5389 | |
| 5390 | /* If the device is closed, ignore the timeout */ |
| 5391 | if (~(adapter->flags & fMP_ADAPTER_INTERRUPT_IN_USE)) |
| 5392 | return; |
| 5393 | |
| 5394 | /* Any nonrecoverable hardware error? |
| 5395 | * Checks adapter->flags for any failure in phy reading |
| 5396 | */ |
| 5397 | if (adapter->flags & fMP_ADAPTER_NON_RECOVER_ERROR) |
| 5398 | return; |
| 5399 | |
| 5400 | /* Hardware failure? */ |
| 5401 | if (adapter->flags & fMP_ADAPTER_HARDWARE_ERROR) { |
| 5402 | dev_err(&adapter->pdev->dev, "hardware error - reset\n"); |
| 5403 | return; |
| 5404 | } |
| 5405 | |
| 5406 | /* Is send stuck? */ |
| 5407 | spin_lock_irqsave(&adapter->tcb_send_qlock, flags); |
| 5408 | |
| 5409 | tcb = adapter->tx_ring.send_head; |
| 5410 | |
| 5411 | if (tcb != NULL) { |
| 5412 | tcb->count++; |
| 5413 | |
| 5414 | if (tcb->count > NIC_SEND_HANG_THRESHOLD) { |
| 5415 | spin_unlock_irqrestore(&adapter->tcb_send_qlock, |
| 5416 | flags); |
| 5417 | |
| 5418 | dev_warn(&adapter->pdev->dev, |
| 5419 | "Send stuck - reset. tcb->WrIndex %x, flags 0x%08x\n", |
| 5420 | tcb->index, |
| 5421 | tcb->flags); |
| 5422 | |
| 5423 | adapter->net_stats.tx_errors++; |
| 5424 | |
| 5425 | /* perform reset of tx/rx */ |
| 5426 | et131x_disable_txrx(netdev); |
| 5427 | et131x_enable_txrx(netdev); |
| 5428 | return; |
| 5429 | } |
| 5430 | } |
| 5431 | |
| 5432 | spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags); |
| 5433 | } |
| 5434 | |
| 5435 | /** |
| 5436 | * et131x_change_mtu - The handler called to change the MTU for the device |
| 5437 | * @netdev: device whose MTU is to be changed |
| 5438 | * @new_mtu: the desired MTU |
| 5439 | * |
| 5440 | * Returns 0 on success, errno on failure (as defined in errno.h) |
| 5441 | */ |
| 5442 | static int et131x_change_mtu(struct net_device *netdev, int new_mtu) |
| 5443 | { |
| 5444 | int result = 0; |
| 5445 | struct et131x_adapter *adapter = netdev_priv(netdev); |
| 5446 | |
| 5447 | /* Make sure the requested MTU is valid */ |
| 5448 | if (new_mtu < 64 || new_mtu > 9216) |
| 5449 | return -EINVAL; |
| 5450 | |
| 5451 | et131x_disable_txrx(netdev); |
| 5452 | et131x_handle_send_interrupt(adapter); |
| 5453 | et131x_handle_recv_interrupt(adapter); |
| 5454 | |
| 5455 | /* Set the new MTU */ |
| 5456 | netdev->mtu = new_mtu; |
| 5457 | |
| 5458 | /* Free Rx DMA memory */ |
| 5459 | et131x_adapter_memory_free(adapter); |
| 5460 | |
| 5461 | /* Set the config parameter for Jumbo Packet support */ |
| 5462 | adapter->registry_jumbo_packet = new_mtu + 14; |
| 5463 | et131x_soft_reset(adapter); |
| 5464 | |
| 5465 | /* Alloc and init Rx DMA memory */ |
| 5466 | result = et131x_adapter_memory_alloc(adapter); |
| 5467 | if (result != 0) { |
| 5468 | dev_warn(&adapter->pdev->dev, |
| 5469 | "Change MTU failed; couldn't re-alloc DMA memory\n"); |
| 5470 | return result; |
| 5471 | } |
| 5472 | |
| 5473 | et131x_init_send(adapter); |
| 5474 | |
| 5475 | et131x_hwaddr_init(adapter); |
| 5476 | memcpy(netdev->dev_addr, adapter->addr, ETH_ALEN); |
| 5477 | |
| 5478 | /* Init the device with the new settings */ |
| 5479 | et131x_adapter_setup(adapter); |
| 5480 | |
| 5481 | et131x_enable_txrx(netdev); |
| 5482 | |
| 5483 | return result; |
| 5484 | } |
| 5485 | |
| 5486 | /** |
| 5487 | * et131x_set_mac_addr - handler to change the MAC address for the device |
| 5488 | * @netdev: device whose MAC is to be changed |
| 5489 | * @new_mac: the desired MAC address |
| 5490 | * |
| 5491 | * Returns 0 on success, errno on failure (as defined in errno.h) |
| 5492 | * |
| 5493 | * IMPLEMENTED BY : blux http://berndlux.de 22.01.2007 21:14 |
| 5494 | */ |
| 5495 | static int et131x_set_mac_addr(struct net_device *netdev, void *new_mac) |
| 5496 | { |
| 5497 | int result = 0; |
| 5498 | struct et131x_adapter *adapter = netdev_priv(netdev); |
| 5499 | struct sockaddr *address = new_mac; |
| 5500 | |
| 5501 | /* begin blux */ |
| 5502 | |
| 5503 | if (adapter == NULL) |
| 5504 | return -ENODEV; |
| 5505 | |
| 5506 | /* Make sure the requested MAC is valid */ |
| 5507 | if (!is_valid_ether_addr(address->sa_data)) |
| 5508 | return -EINVAL; |
| 5509 | |
| 5510 | et131x_disable_txrx(netdev); |
| 5511 | et131x_handle_send_interrupt(adapter); |
| 5512 | et131x_handle_recv_interrupt(adapter); |
| 5513 | |
| 5514 | /* Set the new MAC */ |
| 5515 | /* netdev->set_mac_address = &new_mac; */ |
| 5516 | |
| 5517 | memcpy(netdev->dev_addr, address->sa_data, netdev->addr_len); |
| 5518 | |
| 5519 | printk(KERN_INFO "%s: Setting MAC address to %pM\n", |
| 5520 | netdev->name, netdev->dev_addr); |
| 5521 | |
| 5522 | /* Free Rx DMA memory */ |
| 5523 | et131x_adapter_memory_free(adapter); |
| 5524 | |
| 5525 | et131x_soft_reset(adapter); |
| 5526 | |
| 5527 | /* Alloc and init Rx DMA memory */ |
| 5528 | result = et131x_adapter_memory_alloc(adapter); |
| 5529 | if (result != 0) { |
| 5530 | dev_err(&adapter->pdev->dev, |
| 5531 | "Change MAC failed; couldn't re-alloc DMA memory\n"); |
| 5532 | return result; |
| 5533 | } |
| 5534 | |
| 5535 | et131x_init_send(adapter); |
| 5536 | |
| 5537 | et131x_hwaddr_init(adapter); |
| 5538 | |
| 5539 | /* Init the device with the new settings */ |
| 5540 | et131x_adapter_setup(adapter); |
| 5541 | |
| 5542 | et131x_enable_txrx(netdev); |
| 5543 | |
| 5544 | return result; |
| 5545 | } |
| 5546 | |
| 5547 | static const struct net_device_ops et131x_netdev_ops = { |
| 5548 | .ndo_open = et131x_open, |
| 5549 | .ndo_stop = et131x_close, |
| 5550 | .ndo_start_xmit = et131x_tx, |
| 5551 | .ndo_set_multicast_list = et131x_multicast, |
| 5552 | .ndo_tx_timeout = et131x_tx_timeout, |
| 5553 | .ndo_change_mtu = et131x_change_mtu, |
| 5554 | .ndo_set_mac_address = et131x_set_mac_addr, |
| 5555 | .ndo_validate_addr = eth_validate_addr, |
| 5556 | .ndo_get_stats = et131x_stats, |
| 5557 | .ndo_do_ioctl = et131x_ioctl, |
| 5558 | }; |
| 5559 | |
| 5560 | /** |
| 5561 | * et131x_device_alloc |
| 5562 | * |
| 5563 | * Returns pointer to the allocated and initialized net_device struct for |
| 5564 | * this device. |
| 5565 | * |
| 5566 | * Create instances of net_device and wl_private for the new adapter and |
| 5567 | * register the device's entry points in the net_device structure. |
| 5568 | */ |
| 5569 | struct net_device *et131x_device_alloc(void) |
| 5570 | { |
| 5571 | struct net_device *netdev; |
| 5572 | |
| 5573 | /* Alloc net_device and adapter structs */ |
| 5574 | netdev = alloc_etherdev(sizeof(struct et131x_adapter)); |
| 5575 | |
| 5576 | if (!netdev) { |
| 5577 | printk(KERN_ERR "et131x: Alloc of net_device struct failed\n"); |
| 5578 | return NULL; |
| 5579 | } |
| 5580 | |
| 5581 | /* |
| 5582 | * Setup the function registration table (and other data) for a |
| 5583 | * net_device |
| 5584 | */ |
| 5585 | netdev->watchdog_timeo = ET131X_TX_TIMEOUT; |
| 5586 | netdev->netdev_ops = &et131x_netdev_ops; |
| 5587 | |
| 5588 | /* Poll? */ |
| 5589 | /* netdev->poll = &et131x_poll; */ |
| 5590 | /* netdev->poll_controller = &et131x_poll_controller; */ |
| 5591 | return netdev; |
| 5592 | } |
| 5593 | |