Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (c) 2017, The Linux Foundation. All rights reserved. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 and |
| 6 | * only version 2 as published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | * |
| 13 | */ |
| 14 | |
| 15 | #include <asm/dma-iommu.h> |
| 16 | #include <linux/clk.h> |
| 17 | #include <linux/dma-mapping.h> |
| 18 | #include <linux/ipc_logging.h> |
| 19 | #include <linux/io.h> |
| 20 | #include <linux/list.h> |
| 21 | #include <linux/module.h> |
| 22 | #include <linux/msm-bus.h> |
| 23 | #include <linux/msm-bus-board.h> |
| 24 | #include <linux/of.h> |
| 25 | #include <linux/of_platform.h> |
| 26 | #include <linux/pm_runtime.h> |
| 27 | #include <linux/qcom-geni-se.h> |
| 28 | #include <linux/spinlock.h> |
| 29 | |
| 30 | #define GENI_SE_IOMMU_VA_START (0x40000000) |
| 31 | #define GENI_SE_IOMMU_VA_SIZE (0xC0000000) |
| 32 | |
| 33 | #define NUM_LOG_PAGES 2 |
| 34 | |
| 35 | static unsigned long default_bus_bw_set[] = {0, 19200000, 50000000, 100000000}; |
| 36 | |
| 37 | /** |
| 38 | * @struct geni_se_device - Data structure to represent the QUPv3 Core |
| 39 | * @dev: Device pointer of the QUPv3 core. |
| 40 | * @cb_dev: Device pointer of the context bank in the IOMMU. |
| 41 | * @iommu_lock: Lock to protect IOMMU Mapping & attachment. |
| 42 | * @iommu_map: IOMMU map of the memory space supported by this core. |
| 43 | * @iommu_s1_bypass: Bypass IOMMU stage 1 translation. |
| 44 | * @base: Base address of this instance of QUPv3 core. |
| 45 | * @bus_bw: Client handle to the bus bandwidth request. |
| 46 | * @bus_mas_id: Master Endpoint ID for bus BW request. |
| 47 | * @bus_slv_id: Slave Endpoint ID for bus BW request. |
| 48 | * @ab_ib_lock: Lock to protect the bus ab & ib values, list. |
| 49 | * @ab_list_head: Sorted resource list based on average bus BW. |
| 50 | * @ib_list_head: Sorted resource list based on instantaneous bus BW. |
| 51 | * @cur_ab: Current Bus Average BW request value. |
| 52 | * @cur_ib: Current Bus Instantaneous BW request value. |
| 53 | * @bus_bw_set: Clock plan for the bus driver. |
| 54 | * @cur_bus_bw_idx: Current index within the bus clock plan. |
| 55 | * @log_ctx: Logging context to hold the debug information |
| 56 | */ |
| 57 | struct geni_se_device { |
| 58 | struct device *dev; |
| 59 | struct device *cb_dev; |
| 60 | struct mutex iommu_lock; |
| 61 | struct dma_iommu_mapping *iommu_map; |
| 62 | bool iommu_s1_bypass; |
| 63 | void __iomem *base; |
| 64 | struct msm_bus_client_handle *bus_bw; |
| 65 | u32 bus_mas_id; |
| 66 | u32 bus_slv_id; |
| 67 | spinlock_t ab_ib_lock; |
| 68 | struct list_head ab_list_head; |
| 69 | struct list_head ib_list_head; |
| 70 | unsigned long cur_ab; |
| 71 | unsigned long cur_ib; |
| 72 | int bus_bw_set_size; |
| 73 | unsigned long *bus_bw_set; |
| 74 | int cur_bus_bw_idx; |
| 75 | void *log_ctx; |
| 76 | }; |
| 77 | |
| 78 | /* Offset of QUPV3 Hardware Version Register */ |
| 79 | #define QUPV3_HW_VER (0x4) |
| 80 | |
| 81 | #define HW_VER_MAJOR_MASK GENMASK(31, 28) |
| 82 | #define HW_VER_MAJOR_SHFT 28 |
| 83 | #define HW_VER_MINOR_MASK GENMASK(27, 16) |
| 84 | #define HW_VER_MINOR_SHFT 16 |
| 85 | #define HW_VER_STEP_MASK GENMASK(15, 0) |
| 86 | |
| 87 | static int geni_se_iommu_map_and_attach(struct geni_se_device *geni_se_dev); |
| 88 | |
| 89 | /** |
| 90 | * geni_read_reg_nolog() - Helper function to read from a GENI register |
| 91 | * @base: Base address of the serial engine's register block. |
| 92 | * @offset: Offset within the serial engine's register block. |
| 93 | * |
| 94 | * Return: Return the contents of the register. |
| 95 | */ |
| 96 | unsigned int geni_read_reg_nolog(void __iomem *base, int offset) |
| 97 | { |
| 98 | return readl_relaxed_no_log(base + offset); |
| 99 | } |
| 100 | EXPORT_SYMBOL(geni_read_reg_nolog); |
| 101 | |
| 102 | /** |
| 103 | * geni_write_reg_nolog() - Helper function to write into a GENI register |
| 104 | * @value: Value to be written into the register. |
| 105 | * @base: Base address of the serial engine's register block. |
| 106 | * @offset: Offset within the serial engine's register block. |
| 107 | */ |
| 108 | void geni_write_reg_nolog(unsigned int value, void __iomem *base, int offset) |
| 109 | { |
| 110 | return writel_relaxed_no_log(value, (base + offset)); |
| 111 | } |
| 112 | EXPORT_SYMBOL(geni_write_reg_nolog); |
| 113 | |
| 114 | /** |
| 115 | * geni_read_reg() - Helper function to read from a GENI register |
| 116 | * @base: Base address of the serial engine's register block. |
| 117 | * @offset: Offset within the serial engine's register block. |
| 118 | * |
| 119 | * Return: Return the contents of the register. |
| 120 | */ |
| 121 | unsigned int geni_read_reg(void __iomem *base, int offset) |
| 122 | { |
| 123 | return readl_relaxed(base + offset); |
| 124 | } |
| 125 | EXPORT_SYMBOL(geni_read_reg); |
| 126 | |
| 127 | /** |
| 128 | * geni_write_reg() - Helper function to write into a GENI register |
| 129 | * @value: Value to be written into the register. |
| 130 | * @base: Base address of the serial engine's register block. |
| 131 | * @offset: Offset within the serial engine's register block. |
| 132 | */ |
| 133 | void geni_write_reg(unsigned int value, void __iomem *base, int offset) |
| 134 | { |
| 135 | return writel_relaxed(value, (base + offset)); |
| 136 | } |
| 137 | EXPORT_SYMBOL(geni_write_reg); |
| 138 | |
| 139 | /** |
| 140 | * get_se_proto() - Read the protocol configured for a serial engine |
| 141 | * @base: Base address of the serial engine's register block. |
| 142 | * |
| 143 | * Return: Protocol value as configured in the serial engine. |
| 144 | */ |
| 145 | int get_se_proto(void __iomem *base) |
| 146 | { |
| 147 | int proto; |
| 148 | |
| 149 | proto = ((geni_read_reg(base, GENI_FW_REVISION_RO) |
| 150 | & FW_REV_PROTOCOL_MSK) >> FW_REV_PROTOCOL_SHFT); |
| 151 | return proto; |
| 152 | } |
| 153 | EXPORT_SYMBOL(get_se_proto); |
| 154 | |
| 155 | static int se_geni_irq_en(void __iomem *base) |
| 156 | { |
| 157 | unsigned int common_geni_m_irq_en; |
| 158 | unsigned int common_geni_s_irq_en; |
| 159 | |
| 160 | common_geni_m_irq_en = geni_read_reg(base, SE_GENI_M_IRQ_EN); |
| 161 | common_geni_s_irq_en = geni_read_reg(base, SE_GENI_S_IRQ_EN); |
| 162 | /* Common to all modes */ |
| 163 | common_geni_m_irq_en |= M_COMMON_GENI_M_IRQ_EN; |
| 164 | common_geni_s_irq_en |= S_COMMON_GENI_S_IRQ_EN; |
| 165 | |
| 166 | geni_write_reg(common_geni_m_irq_en, base, SE_GENI_M_IRQ_EN); |
| 167 | geni_write_reg(common_geni_s_irq_en, base, SE_GENI_S_IRQ_EN); |
| 168 | return 0; |
| 169 | } |
| 170 | |
| 171 | |
| 172 | static void se_set_rx_rfr_wm(void __iomem *base, unsigned int rx_wm, |
| 173 | unsigned int rx_rfr) |
| 174 | { |
| 175 | geni_write_reg(rx_wm, base, SE_GENI_RX_WATERMARK_REG); |
| 176 | geni_write_reg(rx_rfr, base, SE_GENI_RX_RFR_WATERMARK_REG); |
| 177 | } |
| 178 | |
| 179 | static int se_io_set_mode(void __iomem *base) |
| 180 | { |
| 181 | unsigned int io_mode; |
| 182 | unsigned int geni_dma_mode; |
| 183 | |
| 184 | io_mode = geni_read_reg(base, SE_IRQ_EN); |
| 185 | geni_dma_mode = geni_read_reg(base, SE_GENI_DMA_MODE_EN); |
| 186 | |
| 187 | io_mode |= (GENI_M_IRQ_EN | GENI_S_IRQ_EN); |
| 188 | io_mode |= (DMA_TX_IRQ_EN | DMA_RX_IRQ_EN); |
| 189 | geni_dma_mode &= ~GENI_DMA_MODE_EN; |
| 190 | |
| 191 | geni_write_reg(io_mode, base, SE_IRQ_EN); |
| 192 | geni_write_reg(geni_dma_mode, base, SE_GENI_DMA_MODE_EN); |
| 193 | geni_write_reg(0, base, SE_GSI_EVENT_EN); |
| 194 | return 0; |
| 195 | } |
| 196 | |
| 197 | static void se_io_init(void __iomem *base) |
| 198 | { |
| 199 | unsigned int io_op_ctrl; |
| 200 | unsigned int geni_cgc_ctrl; |
| 201 | unsigned int dma_general_cfg; |
| 202 | |
| 203 | geni_cgc_ctrl = geni_read_reg(base, GENI_CGC_CTRL); |
| 204 | dma_general_cfg = geni_read_reg(base, SE_DMA_GENERAL_CFG); |
| 205 | geni_cgc_ctrl |= DEFAULT_CGC_EN; |
| 206 | dma_general_cfg |= (AHB_SEC_SLV_CLK_CGC_ON | DMA_AHB_SLV_CFG_ON | |
| 207 | DMA_TX_CLK_CGC_ON | DMA_RX_CLK_CGC_ON); |
| 208 | io_op_ctrl = DEFAULT_IO_OUTPUT_CTRL_MSK; |
| 209 | geni_write_reg(geni_cgc_ctrl, base, GENI_CGC_CTRL); |
| 210 | geni_write_reg(dma_general_cfg, base, SE_DMA_GENERAL_CFG); |
| 211 | |
| 212 | geni_write_reg(io_op_ctrl, base, GENI_OUTPUT_CTRL); |
| 213 | geni_write_reg(FORCE_DEFAULT, base, GENI_FORCE_DEFAULT_REG); |
| 214 | } |
| 215 | |
| 216 | /** |
| 217 | * geni_se_init() - Initialize the GENI Serial Engine |
| 218 | * @base: Base address of the serial engine's register block. |
| 219 | * @rx_wm: Receive watermark to be configured. |
| 220 | * @rx_rfr_wm: Ready-for-receive watermark to be configured. |
| 221 | * |
| 222 | * This function is used to initialize the GENI serial engine, configure |
| 223 | * receive watermark and ready-for-receive watermarks. |
| 224 | * |
| 225 | * Return: 0 on success, standard Linux error codes on failure/error. |
| 226 | */ |
| 227 | int geni_se_init(void __iomem *base, unsigned int rx_wm, unsigned int rx_rfr) |
| 228 | { |
| 229 | int ret; |
| 230 | |
| 231 | se_io_init(base); |
| 232 | ret = se_io_set_mode(base); |
| 233 | if (ret) |
| 234 | return ret; |
| 235 | |
| 236 | se_set_rx_rfr_wm(base, rx_wm, rx_rfr); |
| 237 | ret = se_geni_irq_en(base); |
| 238 | return ret; |
| 239 | } |
| 240 | EXPORT_SYMBOL(geni_se_init); |
| 241 | |
| 242 | static int geni_se_select_fifo_mode(void __iomem *base) |
| 243 | { |
| 244 | int proto = get_se_proto(base); |
| 245 | unsigned int common_geni_m_irq_en; |
| 246 | unsigned int common_geni_s_irq_en; |
| 247 | unsigned int geni_dma_mode; |
| 248 | |
| 249 | geni_write_reg(0, base, SE_GSI_EVENT_EN); |
| 250 | geni_write_reg(0xFFFFFFFF, base, SE_GENI_M_IRQ_CLEAR); |
| 251 | geni_write_reg(0xFFFFFFFF, base, SE_GENI_S_IRQ_CLEAR); |
| 252 | geni_write_reg(0xFFFFFFFF, base, SE_DMA_TX_IRQ_CLR); |
| 253 | geni_write_reg(0xFFFFFFFF, base, SE_DMA_RX_IRQ_CLR); |
| 254 | geni_write_reg(0xFFFFFFFF, base, SE_IRQ_EN); |
| 255 | |
| 256 | common_geni_m_irq_en = geni_read_reg(base, SE_GENI_M_IRQ_EN); |
| 257 | common_geni_s_irq_en = geni_read_reg(base, SE_GENI_S_IRQ_EN); |
| 258 | geni_dma_mode = geni_read_reg(base, SE_GENI_DMA_MODE_EN); |
| 259 | if (proto != UART) { |
| 260 | common_geni_m_irq_en |= |
| 261 | (M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN | |
| 262 | M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN); |
| 263 | common_geni_s_irq_en |= S_CMD_DONE_EN; |
| 264 | } |
| 265 | geni_dma_mode &= ~GENI_DMA_MODE_EN; |
| 266 | |
| 267 | geni_write_reg(common_geni_m_irq_en, base, SE_GENI_M_IRQ_EN); |
| 268 | geni_write_reg(common_geni_s_irq_en, base, SE_GENI_S_IRQ_EN); |
| 269 | geni_write_reg(geni_dma_mode, base, SE_GENI_DMA_MODE_EN); |
| 270 | return 0; |
| 271 | } |
| 272 | |
| 273 | static int geni_se_select_dma_mode(void __iomem *base) |
| 274 | { |
| 275 | unsigned int geni_dma_mode = 0; |
| 276 | |
| 277 | geni_write_reg(0, base, SE_GSI_EVENT_EN); |
| 278 | geni_write_reg(0xFFFFFFFF, base, SE_GENI_M_IRQ_CLEAR); |
| 279 | geni_write_reg(0xFFFFFFFF, base, SE_GENI_S_IRQ_CLEAR); |
| 280 | geni_write_reg(0xFFFFFFFF, base, SE_DMA_TX_IRQ_CLR); |
| 281 | geni_write_reg(0xFFFFFFFF, base, SE_DMA_RX_IRQ_CLR); |
| 282 | geni_write_reg(0xFFFFFFFF, base, SE_IRQ_EN); |
| 283 | |
| 284 | geni_dma_mode = geni_read_reg(base, SE_GENI_DMA_MODE_EN); |
| 285 | geni_dma_mode |= GENI_DMA_MODE_EN; |
| 286 | geni_write_reg(geni_dma_mode, base, SE_GENI_DMA_MODE_EN); |
| 287 | return 0; |
| 288 | } |
| 289 | |
| 290 | static int geni_se_select_gsi_mode(void __iomem *base) |
| 291 | { |
| 292 | unsigned int io_mode = 0; |
| 293 | unsigned int geni_dma_mode = 0; |
| 294 | unsigned int gsi_event_en = 0; |
| 295 | |
| 296 | geni_dma_mode = geni_read_reg(base, SE_GENI_DMA_MODE_EN); |
| 297 | gsi_event_en = geni_read_reg(base, SE_GSI_EVENT_EN); |
| 298 | io_mode = geni_read_reg(base, SE_IRQ_EN); |
| 299 | |
| 300 | geni_dma_mode |= GENI_DMA_MODE_EN; |
| 301 | io_mode &= ~(DMA_TX_IRQ_EN | DMA_RX_IRQ_EN); |
| 302 | gsi_event_en |= (DMA_RX_EVENT_EN | DMA_TX_EVENT_EN | |
| 303 | GENI_M_EVENT_EN | GENI_S_EVENT_EN); |
| 304 | |
| 305 | geni_write_reg(io_mode, base, SE_IRQ_EN); |
| 306 | geni_write_reg(geni_dma_mode, base, SE_GENI_DMA_MODE_EN); |
| 307 | geni_write_reg(gsi_event_en, base, SE_GSI_EVENT_EN); |
| 308 | return 0; |
| 309 | |
| 310 | } |
| 311 | |
| 312 | /** |
| 313 | * geni_se_select_mode() - Select the serial engine transfer mode |
| 314 | * @base: Base address of the serial engine's register block. |
| 315 | * @mode: Transfer mode to be selected. |
| 316 | * |
| 317 | * Return: 0 on success, standard Linux error codes on failure. |
| 318 | */ |
| 319 | int geni_se_select_mode(void __iomem *base, int mode) |
| 320 | { |
| 321 | int ret = 0; |
| 322 | |
| 323 | switch (mode) { |
| 324 | case FIFO_MODE: |
| 325 | geni_se_select_fifo_mode(base); |
| 326 | break; |
| 327 | case SE_DMA: |
| 328 | geni_se_select_dma_mode(base); |
| 329 | break; |
| 330 | case GSI_DMA: |
| 331 | geni_se_select_gsi_mode(base); |
| 332 | break; |
| 333 | default: |
| 334 | ret = -EINVAL; |
| 335 | break; |
| 336 | } |
| 337 | |
| 338 | return ret; |
| 339 | } |
| 340 | EXPORT_SYMBOL(geni_se_select_mode); |
| 341 | |
| 342 | /** |
| 343 | * geni_setup_m_cmd() - Setup the primary sequencer |
| 344 | * @base: Base address of the serial engine's register block. |
| 345 | * @cmd: Command/Operation to setup in the primary sequencer. |
| 346 | * @params: Parameter for the sequencer command. |
| 347 | * |
| 348 | * This function is used to configure the primary sequencer with the |
| 349 | * command and its assoicated parameters. |
| 350 | */ |
| 351 | void geni_setup_m_cmd(void __iomem *base, u32 cmd, u32 params) |
| 352 | { |
| 353 | u32 m_cmd = (cmd << M_OPCODE_SHFT); |
| 354 | |
| 355 | m_cmd |= (params & M_PARAMS_MSK); |
| 356 | geni_write_reg(m_cmd, base, SE_GENI_M_CMD0); |
| 357 | } |
| 358 | EXPORT_SYMBOL(geni_setup_m_cmd); |
| 359 | |
| 360 | /** |
| 361 | * geni_setup_s_cmd() - Setup the secondary sequencer |
| 362 | * @base: Base address of the serial engine's register block. |
| 363 | * @cmd: Command/Operation to setup in the secondary sequencer. |
| 364 | * @params: Parameter for the sequencer command. |
| 365 | * |
| 366 | * This function is used to configure the secondary sequencer with the |
| 367 | * command and its assoicated parameters. |
| 368 | */ |
| 369 | void geni_setup_s_cmd(void __iomem *base, u32 cmd, u32 params) |
| 370 | { |
| 371 | u32 s_cmd = geni_read_reg(base, SE_GENI_S_CMD0); |
| 372 | |
| 373 | s_cmd &= ~(S_OPCODE_MSK | S_PARAMS_MSK); |
| 374 | s_cmd |= (cmd << S_OPCODE_SHFT); |
| 375 | s_cmd |= (params & S_PARAMS_MSK); |
| 376 | geni_write_reg(s_cmd, base, SE_GENI_S_CMD0); |
| 377 | } |
| 378 | EXPORT_SYMBOL(geni_setup_s_cmd); |
| 379 | |
| 380 | /** |
| 381 | * geni_cancel_m_cmd() - Cancel the command configured in the primary sequencer |
| 382 | * @base: Base address of the serial engine's register block. |
| 383 | * |
| 384 | * This function is used to cancel the currently configured command in the |
| 385 | * primary sequencer. |
| 386 | */ |
| 387 | void geni_cancel_m_cmd(void __iomem *base) |
| 388 | { |
| 389 | geni_write_reg(M_GENI_CMD_CANCEL, base, SE_GENI_S_CMD_CTRL_REG); |
| 390 | } |
| 391 | EXPORT_SYMBOL(geni_cancel_m_cmd); |
| 392 | |
| 393 | /** |
| 394 | * geni_cancel_s_cmd() - Cancel the command configured in the secondary |
| 395 | * sequencer |
| 396 | * @base: Base address of the serial engine's register block. |
| 397 | * |
| 398 | * This function is used to cancel the currently configured command in the |
| 399 | * secondary sequencer. |
| 400 | */ |
| 401 | void geni_cancel_s_cmd(void __iomem *base) |
| 402 | { |
| 403 | geni_write_reg(S_GENI_CMD_CANCEL, base, SE_GENI_S_CMD_CTRL_REG); |
| 404 | } |
| 405 | EXPORT_SYMBOL(geni_cancel_s_cmd); |
| 406 | |
| 407 | /** |
| 408 | * geni_abort_m_cmd() - Abort the command configured in the primary sequencer |
| 409 | * @base: Base address of the serial engine's register block. |
| 410 | * |
| 411 | * This function is used to force abort the currently configured command in the |
| 412 | * primary sequencer. |
| 413 | */ |
| 414 | void geni_abort_m_cmd(void __iomem *base) |
| 415 | { |
| 416 | geni_write_reg(M_GENI_CMD_ABORT, base, SE_GENI_M_CMD_CTRL_REG); |
| 417 | } |
| 418 | EXPORT_SYMBOL(geni_abort_m_cmd); |
| 419 | |
| 420 | /** |
| 421 | * geni_abort_s_cmd() - Abort the command configured in the secondary |
| 422 | * sequencer |
| 423 | * @base: Base address of the serial engine's register block. |
| 424 | * |
| 425 | * This function is used to force abort the currently configured command in the |
| 426 | * secondary sequencer. |
| 427 | */ |
| 428 | void geni_abort_s_cmd(void __iomem *base) |
| 429 | { |
| 430 | geni_write_reg(S_GENI_CMD_ABORT, base, SE_GENI_S_CMD_CTRL_REG); |
| 431 | } |
| 432 | EXPORT_SYMBOL(geni_abort_s_cmd); |
| 433 | |
| 434 | /** |
| 435 | * get_tx_fifo_depth() - Get the TX fifo depth of the serial engine |
| 436 | * @base: Base address of the serial engine's register block. |
| 437 | * |
| 438 | * This function is used to get the depth i.e. number of elements in the |
| 439 | * TX fifo of the serial engine. |
| 440 | * |
| 441 | * Return: TX fifo depth in units of FIFO words. |
| 442 | */ |
| 443 | int get_tx_fifo_depth(void __iomem *base) |
| 444 | { |
| 445 | int tx_fifo_depth; |
| 446 | |
| 447 | tx_fifo_depth = ((geni_read_reg(base, SE_HW_PARAM_0) |
| 448 | & TX_FIFO_DEPTH_MSK) >> TX_FIFO_DEPTH_SHFT); |
| 449 | return tx_fifo_depth; |
| 450 | } |
| 451 | EXPORT_SYMBOL(get_tx_fifo_depth); |
| 452 | |
| 453 | /** |
| 454 | * get_tx_fifo_width() - Get the TX fifo width of the serial engine |
| 455 | * @base: Base address of the serial engine's register block. |
| 456 | * |
| 457 | * This function is used to get the width i.e. word size per element in the |
| 458 | * TX fifo of the serial engine. |
| 459 | * |
| 460 | * Return: TX fifo width in bits |
| 461 | */ |
| 462 | int get_tx_fifo_width(void __iomem *base) |
| 463 | { |
| 464 | int tx_fifo_width; |
| 465 | |
| 466 | tx_fifo_width = ((geni_read_reg(base, SE_HW_PARAM_0) |
| 467 | & TX_FIFO_WIDTH_MSK) >> TX_FIFO_WIDTH_SHFT); |
| 468 | return tx_fifo_width; |
| 469 | } |
| 470 | EXPORT_SYMBOL(get_tx_fifo_width); |
| 471 | |
| 472 | /** |
| 473 | * get_rx_fifo_depth() - Get the RX fifo depth of the serial engine |
| 474 | * @base: Base address of the serial engine's register block. |
| 475 | * |
| 476 | * This function is used to get the depth i.e. number of elements in the |
| 477 | * RX fifo of the serial engine. |
| 478 | * |
| 479 | * Return: RX fifo depth in units of FIFO words |
| 480 | */ |
| 481 | int get_rx_fifo_depth(void __iomem *base) |
| 482 | { |
| 483 | int rx_fifo_depth; |
| 484 | |
| 485 | rx_fifo_depth = ((geni_read_reg(base, SE_HW_PARAM_1) |
| 486 | & RX_FIFO_DEPTH_MSK) >> RX_FIFO_DEPTH_SHFT); |
| 487 | return rx_fifo_depth; |
| 488 | } |
| 489 | EXPORT_SYMBOL(get_rx_fifo_depth); |
| 490 | |
| 491 | /** |
| 492 | * se_get_packing_config() - Get the packing configuration based on input |
| 493 | * @bpw: Bits of data per transfer word. |
| 494 | * @pack_words: Number of words per fifo element. |
| 495 | * @msb_to_lsb: Transfer from MSB to LSB or vice-versa. |
| 496 | * @cfg0: Output buffer to hold the first half of configuration. |
| 497 | * @cfg1: Output buffer to hold the second half of configuration. |
| 498 | * |
| 499 | * This function is used to calculate the packing configuration based on |
| 500 | * the input packing requirement and the configuration logic. |
| 501 | */ |
| 502 | void se_get_packing_config(int bpw, int pack_words, bool msb_to_lsb, |
| 503 | unsigned long *cfg0, unsigned long *cfg1) |
| 504 | { |
| 505 | u32 cfg[4] = {0}; |
| 506 | int len; |
| 507 | int temp_bpw = bpw; |
| 508 | int idx_start = (msb_to_lsb ? (bpw - 1) : 0); |
| 509 | int idx = idx_start; |
| 510 | int idx_delta = (msb_to_lsb ? -BITS_PER_BYTE : BITS_PER_BYTE); |
| 511 | int ceil_bpw = ((bpw & (BITS_PER_BYTE - 1)) ? |
| 512 | ((bpw & ~(BITS_PER_BYTE - 1)) + BITS_PER_BYTE) : bpw); |
| 513 | int iter = (ceil_bpw * pack_words) >> 3; |
| 514 | int i; |
| 515 | |
| 516 | if (unlikely(iter <= 0 || iter > 4)) { |
| 517 | *cfg0 = 0; |
| 518 | *cfg1 = 0; |
| 519 | return; |
| 520 | } |
| 521 | |
| 522 | for (i = 0; i < iter; i++) { |
| 523 | len = (temp_bpw < BITS_PER_BYTE) ? |
| 524 | (temp_bpw - 1) : BITS_PER_BYTE - 1; |
| 525 | cfg[i] = ((idx << 5) | (msb_to_lsb << 4) | (len << 1)); |
| 526 | idx = ((temp_bpw - BITS_PER_BYTE) <= 0) ? |
| 527 | ((i + 1) * BITS_PER_BYTE) + idx_start : |
| 528 | idx + idx_delta; |
| 529 | temp_bpw = ((temp_bpw - BITS_PER_BYTE) <= 0) ? |
| 530 | bpw : (temp_bpw - BITS_PER_BYTE); |
| 531 | } |
| 532 | cfg[iter - 1] |= 1; |
| 533 | *cfg0 = cfg[0] | (cfg[1] << 10); |
| 534 | *cfg1 = cfg[2] | (cfg[3] << 10); |
| 535 | } |
| 536 | EXPORT_SYMBOL(se_get_packing_config); |
| 537 | |
| 538 | /** |
| 539 | * se_config_packing() - Packing configuration of the serial engine |
| 540 | * @base: Base address of the serial engine's register block. |
| 541 | * @bpw: Bits of data per transfer word. |
| 542 | * @pack_words: Number of words per fifo element. |
| 543 | * @msb_to_lsb: Transfer from MSB to LSB or vice-versa. |
| 544 | * |
| 545 | * This function is used to configure the packing rules for the current |
| 546 | * transfer. |
| 547 | */ |
| 548 | void se_config_packing(void __iomem *base, int bpw, |
| 549 | int pack_words, bool msb_to_lsb) |
| 550 | { |
| 551 | unsigned long cfg0, cfg1; |
| 552 | |
| 553 | se_get_packing_config(bpw, pack_words, msb_to_lsb, &cfg0, &cfg1); |
| 554 | geni_write_reg(cfg0, base, SE_GENI_TX_PACKING_CFG0); |
| 555 | geni_write_reg(cfg1, base, SE_GENI_TX_PACKING_CFG1); |
| 556 | geni_write_reg(cfg0, base, SE_GENI_RX_PACKING_CFG0); |
| 557 | geni_write_reg(cfg1, base, SE_GENI_RX_PACKING_CFG1); |
| 558 | if (pack_words || bpw == 32) |
| 559 | geni_write_reg((bpw >> 4), base, SE_GENI_BYTE_GRAN); |
| 560 | } |
| 561 | EXPORT_SYMBOL(se_config_packing); |
| 562 | |
| 563 | static void se_geni_clks_off(struct se_geni_rsc *rsc) |
| 564 | { |
| 565 | clk_disable_unprepare(rsc->se_clk); |
| 566 | clk_disable_unprepare(rsc->s_ahb_clk); |
| 567 | clk_disable_unprepare(rsc->m_ahb_clk); |
| 568 | } |
| 569 | |
| 570 | static bool geni_se_check_bus_bw(struct geni_se_device *geni_se_dev) |
| 571 | { |
| 572 | int i; |
| 573 | int new_bus_bw_idx = geni_se_dev->bus_bw_set_size - 1; |
| 574 | unsigned long new_bus_bw; |
| 575 | bool bus_bw_update = false; |
| 576 | |
| 577 | new_bus_bw = max(geni_se_dev->cur_ib, geni_se_dev->cur_ab) / |
| 578 | DEFAULT_BUS_WIDTH; |
| 579 | for (i = 0; i < geni_se_dev->bus_bw_set_size; i++) { |
| 580 | if (geni_se_dev->bus_bw_set[i] >= new_bus_bw) { |
| 581 | new_bus_bw_idx = i; |
| 582 | break; |
| 583 | } |
| 584 | } |
| 585 | |
| 586 | if (geni_se_dev->cur_bus_bw_idx != new_bus_bw_idx) { |
| 587 | geni_se_dev->cur_bus_bw_idx = new_bus_bw_idx; |
| 588 | bus_bw_update = true; |
| 589 | } |
| 590 | return bus_bw_update; |
| 591 | } |
| 592 | |
| 593 | static int geni_se_rmv_ab_ib(struct geni_se_device *geni_se_dev, |
| 594 | struct se_geni_rsc *rsc) |
| 595 | { |
| 596 | unsigned long flags; |
| 597 | struct se_geni_rsc *tmp; |
| 598 | bool bus_bw_update = false; |
| 599 | int ret = 0; |
| 600 | |
| 601 | if (unlikely(list_empty(&rsc->ab_list) || list_empty(&rsc->ib_list))) |
| 602 | return -EINVAL; |
| 603 | |
| 604 | spin_lock_irqsave(&geni_se_dev->ab_ib_lock, flags); |
| 605 | list_del_init(&rsc->ab_list); |
| 606 | geni_se_dev->cur_ab -= rsc->ab; |
| 607 | |
| 608 | list_del_init(&rsc->ib_list); |
| 609 | tmp = list_first_entry_or_null(&geni_se_dev->ib_list_head, |
| 610 | struct se_geni_rsc, ib_list); |
| 611 | if (tmp && tmp->ib != geni_se_dev->cur_ib) |
| 612 | geni_se_dev->cur_ib = tmp->ib; |
| 613 | else if (!tmp && geni_se_dev->cur_ib) |
| 614 | geni_se_dev->cur_ib = 0; |
| 615 | |
| 616 | bus_bw_update = geni_se_check_bus_bw(geni_se_dev); |
| 617 | spin_unlock_irqrestore(&geni_se_dev->ab_ib_lock, flags); |
| 618 | |
| 619 | if (bus_bw_update) |
| 620 | ret = msm_bus_scale_update_bw(geni_se_dev->bus_bw, |
| 621 | geni_se_dev->cur_ab, |
| 622 | geni_se_dev->cur_ib); |
| 623 | GENI_SE_DBG(geni_se_dev->log_ctx, false, NULL, |
| 624 | "%s: %lu:%lu (%lu:%lu) %d\n", __func__, |
| 625 | geni_se_dev->cur_ab, geni_se_dev->cur_ib, |
| 626 | rsc->ab, rsc->ib, bus_bw_update); |
| 627 | return ret; |
| 628 | } |
| 629 | |
| 630 | /** |
| 631 | * se_geni_resources_off() - Turn off resources associated with the serial |
| 632 | * engine |
| 633 | * @rsc: Handle to resources associated with the serial engine. |
| 634 | * |
| 635 | * Return: 0 on success, standard Linux error codes on failure/error. |
| 636 | */ |
| 637 | int se_geni_resources_off(struct se_geni_rsc *rsc) |
| 638 | { |
| 639 | int ret = 0; |
| 640 | struct geni_se_device *geni_se_dev; |
| 641 | |
| 642 | if (unlikely(!rsc || !rsc->wrapper_dev)) |
| 643 | return -EINVAL; |
| 644 | |
| 645 | geni_se_dev = dev_get_drvdata(rsc->wrapper_dev); |
| 646 | if (unlikely(!geni_se_dev || !geni_se_dev->bus_bw)) |
| 647 | return -ENODEV; |
| 648 | |
| 649 | ret = pinctrl_select_state(rsc->geni_pinctrl, rsc->geni_gpio_sleep); |
| 650 | if (ret) { |
| 651 | GENI_SE_ERR(geni_se_dev->log_ctx, false, NULL, |
| 652 | "%s: Error %d pinctrl_select_state\n", __func__, ret); |
| 653 | return ret; |
| 654 | } |
| 655 | se_geni_clks_off(rsc); |
| 656 | ret = geni_se_rmv_ab_ib(geni_se_dev, rsc); |
| 657 | if (ret) |
| 658 | GENI_SE_ERR(geni_se_dev->log_ctx, false, NULL, |
| 659 | "%s: Error %d during bus_bw_update\n", __func__, ret); |
| 660 | return ret; |
| 661 | } |
| 662 | EXPORT_SYMBOL(se_geni_resources_off); |
| 663 | |
| 664 | static int se_geni_clks_on(struct se_geni_rsc *rsc) |
| 665 | { |
| 666 | int ret; |
| 667 | |
| 668 | ret = clk_prepare_enable(rsc->m_ahb_clk); |
| 669 | if (ret) |
| 670 | return ret; |
| 671 | |
| 672 | ret = clk_prepare_enable(rsc->s_ahb_clk); |
| 673 | if (ret) { |
| 674 | clk_disable_unprepare(rsc->m_ahb_clk); |
| 675 | return ret; |
| 676 | } |
| 677 | |
| 678 | ret = clk_prepare_enable(rsc->se_clk); |
| 679 | if (ret) { |
| 680 | clk_disable_unprepare(rsc->s_ahb_clk); |
| 681 | clk_disable_unprepare(rsc->m_ahb_clk); |
| 682 | } |
| 683 | return ret; |
| 684 | } |
| 685 | |
| 686 | static int geni_se_add_ab_ib(struct geni_se_device *geni_se_dev, |
| 687 | struct se_geni_rsc *rsc) |
| 688 | { |
| 689 | unsigned long flags; |
| 690 | struct se_geni_rsc *tmp; |
| 691 | struct list_head *ins_list_head; |
| 692 | bool bus_bw_update = false; |
| 693 | int ret = 0; |
| 694 | |
| 695 | spin_lock_irqsave(&geni_se_dev->ab_ib_lock, flags); |
| 696 | list_add(&rsc->ab_list, &geni_se_dev->ab_list_head); |
| 697 | geni_se_dev->cur_ab += rsc->ab; |
| 698 | |
| 699 | ins_list_head = &geni_se_dev->ib_list_head; |
| 700 | list_for_each_entry(tmp, &geni_se_dev->ib_list_head, ib_list) { |
| 701 | if (tmp->ib < rsc->ib) |
| 702 | break; |
| 703 | ins_list_head = &tmp->ib_list; |
| 704 | } |
| 705 | list_add(&rsc->ib_list, ins_list_head); |
| 706 | /* Currently inserted node has greater average BW value */ |
| 707 | if (ins_list_head == &geni_se_dev->ib_list_head) |
| 708 | geni_se_dev->cur_ib = tmp->ib; |
| 709 | |
| 710 | bus_bw_update = geni_se_check_bus_bw(geni_se_dev); |
| 711 | spin_unlock_irqrestore(&geni_se_dev->ab_ib_lock, flags); |
| 712 | |
| 713 | if (bus_bw_update) |
| 714 | ret = msm_bus_scale_update_bw(geni_se_dev->bus_bw, |
| 715 | geni_se_dev->cur_ab, |
| 716 | geni_se_dev->cur_ib); |
| 717 | GENI_SE_DBG(geni_se_dev->log_ctx, false, NULL, |
| 718 | "%s: %lu:%lu (%lu:%lu) %d\n", __func__, |
| 719 | geni_se_dev->cur_ab, geni_se_dev->cur_ib, |
| 720 | rsc->ab, rsc->ib, bus_bw_update); |
| 721 | return ret; |
| 722 | } |
| 723 | |
| 724 | /** |
| 725 | * se_geni_resources_on() - Turn on resources associated with the serial |
| 726 | * engine |
| 727 | * @rsc: Handle to resources associated with the serial engine. |
| 728 | * |
| 729 | * Return: 0 on success, standard Linux error codes on failure/error. |
| 730 | */ |
| 731 | int se_geni_resources_on(struct se_geni_rsc *rsc) |
| 732 | { |
| 733 | int ret = 0; |
| 734 | struct geni_se_device *geni_se_dev; |
| 735 | |
| 736 | if (unlikely(!rsc || !rsc->wrapper_dev)) |
| 737 | return -EINVAL; |
| 738 | |
| 739 | geni_se_dev = dev_get_drvdata(rsc->wrapper_dev); |
| 740 | if (unlikely(!geni_se_dev)) |
| 741 | return -EPROBE_DEFER; |
| 742 | |
| 743 | ret = geni_se_add_ab_ib(geni_se_dev, rsc); |
| 744 | if (ret) { |
| 745 | GENI_SE_ERR(geni_se_dev->log_ctx, false, NULL, |
| 746 | "%s: Error %d during bus_bw_update\n", __func__, ret); |
| 747 | return ret; |
| 748 | } |
| 749 | |
| 750 | ret = se_geni_clks_on(rsc); |
| 751 | if (ret) { |
| 752 | GENI_SE_ERR(geni_se_dev->log_ctx, false, NULL, |
| 753 | "%s: Error %d during clks_on\n", __func__, ret); |
| 754 | geni_se_rmv_ab_ib(geni_se_dev, rsc); |
| 755 | return ret; |
| 756 | } |
| 757 | |
| 758 | ret = pinctrl_select_state(rsc->geni_pinctrl, rsc->geni_gpio_active); |
| 759 | if (ret) { |
| 760 | GENI_SE_ERR(geni_se_dev->log_ctx, false, NULL, |
| 761 | "%s: Error %d pinctrl_select_state\n", __func__, ret); |
| 762 | se_geni_clks_off(rsc); |
| 763 | geni_se_rmv_ab_ib(geni_se_dev, rsc); |
| 764 | } |
| 765 | return ret; |
| 766 | } |
| 767 | EXPORT_SYMBOL(se_geni_resources_on); |
| 768 | |
| 769 | /** |
| 770 | * geni_se_resources_init() - Init the SE resource structure |
| 771 | * @rsc: SE resource structure to be initialized. |
| 772 | * @ab: Initial Average bus bandwidth request value. |
| 773 | * @ib: Initial Instantaneous bus bandwidth request value. |
| 774 | * |
| 775 | * Return: 0 on success, standard Linux error codes on failure. |
| 776 | */ |
| 777 | int geni_se_resources_init(struct se_geni_rsc *rsc, |
| 778 | unsigned long ab, unsigned long ib) |
| 779 | { |
| 780 | struct geni_se_device *geni_se_dev; |
| 781 | |
| 782 | if (unlikely(!rsc || !rsc->wrapper_dev)) |
| 783 | return -EINVAL; |
| 784 | |
| 785 | geni_se_dev = dev_get_drvdata(rsc->wrapper_dev); |
| 786 | if (unlikely(!geni_se_dev)) |
| 787 | return -EPROBE_DEFER; |
| 788 | |
| 789 | if (unlikely(IS_ERR_OR_NULL(geni_se_dev->bus_bw))) { |
| 790 | geni_se_dev->bus_bw = msm_bus_scale_register( |
| 791 | geni_se_dev->bus_mas_id, |
| 792 | geni_se_dev->bus_slv_id, |
| 793 | (char *)dev_name(geni_se_dev->dev), |
| 794 | false); |
| 795 | if (IS_ERR_OR_NULL(geni_se_dev->bus_bw)) { |
| 796 | GENI_SE_ERR(geni_se_dev->log_ctx, false, NULL, |
| 797 | "%s: Error creating bus client\n", __func__); |
| 798 | return (int)PTR_ERR(geni_se_dev->bus_bw); |
| 799 | } |
| 800 | } |
| 801 | |
| 802 | rsc->ab = ab; |
| 803 | rsc->ib = ib; |
| 804 | INIT_LIST_HEAD(&rsc->ab_list); |
| 805 | INIT_LIST_HEAD(&rsc->ib_list); |
| 806 | geni_se_iommu_map_and_attach(geni_se_dev); |
| 807 | return 0; |
| 808 | } |
| 809 | EXPORT_SYMBOL(geni_se_resources_init); |
| 810 | |
| 811 | /** |
| 812 | * geni_se_tx_dma_prep() - Prepare the Serial Engine for TX DMA transfer |
| 813 | * @wrapper_dev: QUPv3 Wrapper Device to which the TX buffer is mapped. |
| 814 | * @base: Base address of the SE register block. |
| 815 | * @tx_buf: Pointer to the TX buffer. |
| 816 | * @tx_len: Length of the TX buffer. |
| 817 | * @tx_dma: Pointer to store the mapped DMA address. |
| 818 | * |
| 819 | * This function is used to prepare the buffers for DMA TX. |
| 820 | * |
| 821 | * Return: 0 on success, standard Linux error codes on error/failure. |
| 822 | */ |
| 823 | int geni_se_tx_dma_prep(struct device *wrapper_dev, void __iomem *base, |
| 824 | void *tx_buf, int tx_len, dma_addr_t *tx_dma) |
| 825 | { |
| 826 | int ret; |
| 827 | |
| 828 | if (unlikely(!wrapper_dev || !base || !tx_buf || !tx_len || !tx_dma)) |
| 829 | return -EINVAL; |
| 830 | |
| 831 | ret = geni_se_iommu_map_buf(wrapper_dev, tx_dma, tx_buf, tx_len, |
| 832 | DMA_TO_DEVICE); |
| 833 | if (ret) |
| 834 | return ret; |
| 835 | |
| 836 | geni_write_reg(7, base, SE_DMA_TX_IRQ_EN_SET); |
| 837 | geni_write_reg((u32)(*tx_dma), base, SE_DMA_TX_PTR_L); |
| 838 | geni_write_reg((u32)((*tx_dma) >> 32), base, SE_DMA_TX_PTR_H); |
| 839 | geni_write_reg(1, base, SE_DMA_TX_ATTR); |
| 840 | geni_write_reg(tx_len, base, SE_DMA_TX_LEN); |
| 841 | return 0; |
| 842 | } |
| 843 | EXPORT_SYMBOL(geni_se_tx_dma_prep); |
| 844 | |
| 845 | /** |
| 846 | * geni_se_rx_dma_prep() - Prepare the Serial Engine for RX DMA transfer |
| 847 | * @wrapper_dev: QUPv3 Wrapper Device to which the RX buffer is mapped. |
| 848 | * @base: Base address of the SE register block. |
| 849 | * @rx_buf: Pointer to the RX buffer. |
| 850 | * @rx_len: Length of the RX buffer. |
| 851 | * @rx_dma: Pointer to store the mapped DMA address. |
| 852 | * |
| 853 | * This function is used to prepare the buffers for DMA RX. |
| 854 | * |
| 855 | * Return: 0 on success, standard Linux error codes on error/failure. |
| 856 | */ |
| 857 | int geni_se_rx_dma_prep(struct device *wrapper_dev, void __iomem *base, |
| 858 | void *rx_buf, int rx_len, dma_addr_t *rx_dma) |
| 859 | { |
| 860 | int ret; |
| 861 | |
| 862 | if (unlikely(!wrapper_dev || !base || !rx_buf || !rx_len || !rx_dma)) |
| 863 | return -EINVAL; |
| 864 | |
| 865 | ret = geni_se_iommu_map_buf(wrapper_dev, rx_dma, rx_buf, rx_len, |
| 866 | DMA_FROM_DEVICE); |
| 867 | if (ret) |
| 868 | return ret; |
| 869 | |
| 870 | geni_write_reg(7, base, SE_DMA_RX_IRQ_EN_SET); |
| 871 | geni_write_reg((u32)(*rx_dma), base, SE_DMA_RX_PTR_L); |
| 872 | geni_write_reg((u32)((*rx_dma) >> 32), base, SE_DMA_RX_PTR_H); |
| 873 | /* RX does not have EOT bit */ |
| 874 | geni_write_reg(0, base, SE_DMA_RX_ATTR); |
| 875 | geni_write_reg(rx_len, base, SE_DMA_RX_LEN); |
| 876 | return 0; |
| 877 | } |
| 878 | EXPORT_SYMBOL(geni_se_rx_dma_prep); |
| 879 | |
| 880 | /** |
| 881 | * geni_se_tx_dma_unprep() - Unprepare the Serial Engine after TX DMA transfer |
| 882 | * @wrapper_dev: QUPv3 Wrapper Device to which the RX buffer is mapped. |
| 883 | * @tx_dma: DMA address of the TX buffer. |
| 884 | * @tx_len: Length of the TX buffer. |
| 885 | * |
| 886 | * This function is used to unprepare the DMA buffers after DMA TX. |
| 887 | */ |
| 888 | void geni_se_tx_dma_unprep(struct device *wrapper_dev, |
| 889 | dma_addr_t tx_dma, int tx_len) |
| 890 | { |
| 891 | if (tx_dma) |
| 892 | geni_se_iommu_unmap_buf(wrapper_dev, &tx_dma, tx_len, |
| 893 | DMA_TO_DEVICE); |
| 894 | } |
| 895 | EXPORT_SYMBOL(geni_se_tx_dma_unprep); |
| 896 | |
| 897 | /** |
| 898 | * geni_se_rx_dma_unprep() - Unprepare the Serial Engine after RX DMA transfer |
| 899 | * @wrapper_dev: QUPv3 Wrapper Device to which the RX buffer is mapped. |
| 900 | * @rx_dma: DMA address of the RX buffer. |
| 901 | * @rx_len: Length of the RX buffer. |
| 902 | * |
| 903 | * This function is used to unprepare the DMA buffers after DMA RX. |
| 904 | */ |
| 905 | void geni_se_rx_dma_unprep(struct device *wrapper_dev, |
| 906 | dma_addr_t rx_dma, int rx_len) |
| 907 | { |
| 908 | if (rx_dma) |
| 909 | geni_se_iommu_unmap_buf(wrapper_dev, &rx_dma, rx_len, |
| 910 | DMA_FROM_DEVICE); |
| 911 | } |
| 912 | EXPORT_SYMBOL(geni_se_rx_dma_unprep); |
| 913 | |
| 914 | /** |
| 915 | * geni_se_qupv3_hw_version() - Read the QUPv3 Hardware version |
| 916 | * @wrapper_dev: Pointer to the corresponding QUPv3 wrapper core. |
| 917 | * @major: Buffer for Major Version field. |
| 918 | * @minor: Buffer for Minor Version field. |
| 919 | * @step: Buffer for Step Version field. |
| 920 | * |
| 921 | * Return: 0 on success, standard Linux error codes on failure/error. |
| 922 | */ |
| 923 | int geni_se_qupv3_hw_version(struct device *wrapper_dev, unsigned int *major, |
| 924 | unsigned int *minor, unsigned int *step) |
| 925 | { |
| 926 | unsigned int version; |
| 927 | struct geni_se_device *geni_se_dev; |
| 928 | |
| 929 | if (!wrapper_dev || !major || !minor || !step) |
| 930 | return -EINVAL; |
| 931 | |
| 932 | geni_se_dev = dev_get_drvdata(wrapper_dev); |
| 933 | if (unlikely(!geni_se_dev)) |
| 934 | return -ENODEV; |
| 935 | |
| 936 | version = geni_read_reg(geni_se_dev->base, QUPV3_HW_VER); |
| 937 | *major = (version & HW_VER_MAJOR_MASK) >> HW_VER_MAJOR_SHFT; |
| 938 | *minor = (version & HW_VER_MINOR_MASK) >> HW_VER_MINOR_SHFT; |
| 939 | *step = version & HW_VER_STEP_MASK; |
| 940 | return 0; |
| 941 | } |
| 942 | EXPORT_SYMBOL(geni_se_qupv3_hw_version); |
| 943 | |
| 944 | static int geni_se_iommu_map_and_attach(struct geni_se_device *geni_se_dev) |
| 945 | { |
| 946 | dma_addr_t va_start = GENI_SE_IOMMU_VA_START; |
| 947 | size_t va_size = GENI_SE_IOMMU_VA_SIZE; |
| 948 | int bypass = 1; |
| 949 | struct device *cb_dev = geni_se_dev->cb_dev; |
| 950 | |
| 951 | mutex_lock(&geni_se_dev->iommu_lock); |
| 952 | if (likely(geni_se_dev->iommu_map)) { |
| 953 | mutex_unlock(&geni_se_dev->iommu_lock); |
| 954 | return 0; |
| 955 | } |
| 956 | |
| 957 | geni_se_dev->iommu_map = arm_iommu_create_mapping(&platform_bus_type, |
| 958 | va_start, va_size); |
| 959 | if (IS_ERR(geni_se_dev->iommu_map)) { |
| 960 | GENI_SE_ERR(geni_se_dev->log_ctx, false, NULL, |
| 961 | "%s:%s iommu_create_mapping failure\n", |
| 962 | __func__, dev_name(cb_dev)); |
| 963 | mutex_unlock(&geni_se_dev->iommu_lock); |
| 964 | return PTR_ERR(geni_se_dev->iommu_map); |
| 965 | } |
| 966 | |
| 967 | if (geni_se_dev->iommu_s1_bypass) { |
| 968 | if (iommu_domain_set_attr(geni_se_dev->iommu_map->domain, |
| 969 | DOMAIN_ATTR_S1_BYPASS, &bypass)) { |
| 970 | GENI_SE_ERR(geni_se_dev->log_ctx, false, NULL, |
| 971 | "%s:%s Couldn't bypass s1 translation\n", |
| 972 | __func__, dev_name(cb_dev)); |
| 973 | arm_iommu_release_mapping(geni_se_dev->iommu_map); |
| 974 | geni_se_dev->iommu_map = NULL; |
| 975 | mutex_unlock(&geni_se_dev->iommu_lock); |
| 976 | return -EIO; |
| 977 | } |
| 978 | } |
| 979 | |
| 980 | if (arm_iommu_attach_device(cb_dev, geni_se_dev->iommu_map)) { |
| 981 | GENI_SE_ERR(geni_se_dev->log_ctx, false, NULL, |
| 982 | "%s:%s couldn't arm_iommu_attach_device\n", |
| 983 | __func__, dev_name(cb_dev)); |
| 984 | arm_iommu_release_mapping(geni_se_dev->iommu_map); |
| 985 | geni_se_dev->iommu_map = NULL; |
| 986 | mutex_unlock(&geni_se_dev->iommu_lock); |
| 987 | return -EIO; |
| 988 | } |
| 989 | mutex_unlock(&geni_se_dev->iommu_lock); |
| 990 | GENI_SE_DBG(geni_se_dev->log_ctx, false, NULL, "%s:%s successful\n", |
| 991 | __func__, dev_name(cb_dev)); |
| 992 | return 0; |
| 993 | } |
| 994 | |
| 995 | /** |
| 996 | * geni_se_iommu_map_buf() - Map a single buffer into QUPv3 context bank |
| 997 | * @wrapper_dev: Pointer to the corresponding QUPv3 wrapper core. |
| 998 | * @iova: Pointer in which the mapped virtual address is stored. |
| 999 | * @buf: Address of the buffer that needs to be mapped. |
| 1000 | * @size: Size of the buffer. |
| 1001 | * @dir: Direction of the DMA transfer. |
| 1002 | * |
| 1003 | * This function is used to map an already allocated buffer into the |
| 1004 | * QUPv3 context bank device space. |
| 1005 | * |
| 1006 | * Return: 0 on success, standard Linux error codes on failure/error. |
| 1007 | */ |
| 1008 | int geni_se_iommu_map_buf(struct device *wrapper_dev, dma_addr_t *iova, |
| 1009 | void *buf, size_t size, enum dma_data_direction dir) |
| 1010 | { |
| 1011 | struct device *cb_dev; |
| 1012 | struct geni_se_device *geni_se_dev; |
| 1013 | |
| 1014 | if (!wrapper_dev || !iova || !buf || !size) |
| 1015 | return -EINVAL; |
| 1016 | |
| 1017 | *iova = DMA_ERROR_CODE; |
| 1018 | geni_se_dev = dev_get_drvdata(wrapper_dev); |
| 1019 | if (!geni_se_dev || !geni_se_dev->cb_dev) |
| 1020 | return -ENODEV; |
| 1021 | |
| 1022 | cb_dev = geni_se_dev->cb_dev; |
| 1023 | |
| 1024 | *iova = dma_map_single(cb_dev, buf, size, dir); |
| 1025 | if (dma_mapping_error(cb_dev, *iova)) |
| 1026 | return -EIO; |
| 1027 | return 0; |
| 1028 | } |
| 1029 | EXPORT_SYMBOL(geni_se_iommu_map_buf); |
| 1030 | |
| 1031 | /** |
| 1032 | * geni_se_iommu_alloc_buf() - Allocate & map a single buffer into QUPv3 |
| 1033 | * context bank |
| 1034 | * @wrapper_dev: Pointer to the corresponding QUPv3 wrapper core. |
| 1035 | * @iova: Pointer in which the mapped virtual address is stored. |
| 1036 | * @size: Size of the buffer. |
| 1037 | * |
| 1038 | * This function is used to allocate a buffer and map it into the |
| 1039 | * QUPv3 context bank device space. |
| 1040 | * |
| 1041 | * Return: address of the buffer on success, NULL or ERR_PTR on |
| 1042 | * failure/error. |
| 1043 | */ |
| 1044 | void *geni_se_iommu_alloc_buf(struct device *wrapper_dev, dma_addr_t *iova, |
| 1045 | size_t size) |
| 1046 | { |
| 1047 | struct device *cb_dev; |
| 1048 | struct geni_se_device *geni_se_dev; |
| 1049 | void *buf = NULL; |
| 1050 | |
| 1051 | if (!wrapper_dev || !iova || !size) |
| 1052 | return ERR_PTR(-EINVAL); |
| 1053 | |
| 1054 | *iova = DMA_ERROR_CODE; |
| 1055 | geni_se_dev = dev_get_drvdata(wrapper_dev); |
| 1056 | if (!geni_se_dev || !geni_se_dev->cb_dev) |
| 1057 | return ERR_PTR(-ENODEV); |
| 1058 | |
| 1059 | cb_dev = geni_se_dev->cb_dev; |
| 1060 | |
| 1061 | buf = dma_alloc_coherent(cb_dev, size, iova, GFP_KERNEL); |
| 1062 | if (!buf) |
| 1063 | GENI_SE_ERR(geni_se_dev->log_ctx, false, NULL, |
| 1064 | "%s: Failed dma_alloc_coherent\n", __func__); |
| 1065 | return buf; |
| 1066 | } |
| 1067 | EXPORT_SYMBOL(geni_se_iommu_alloc_buf); |
| 1068 | |
| 1069 | /** |
| 1070 | * geni_se_iommu_unmap_buf() - Unmap a single buffer from QUPv3 context bank |
| 1071 | * @wrapper_dev: Pointer to the corresponding QUPv3 wrapper core. |
| 1072 | * @iova: Pointer in which the mapped virtual address is stored. |
| 1073 | * @size: Size of the buffer. |
| 1074 | * @dir: Direction of the DMA transfer. |
| 1075 | * |
| 1076 | * This function is used to unmap an already mapped buffer from the |
| 1077 | * QUPv3 context bank device space. |
| 1078 | * |
| 1079 | * Return: 0 on success, standard Linux error codes on failure/error. |
| 1080 | */ |
| 1081 | int geni_se_iommu_unmap_buf(struct device *wrapper_dev, dma_addr_t *iova, |
| 1082 | size_t size, enum dma_data_direction dir) |
| 1083 | { |
| 1084 | struct device *cb_dev; |
| 1085 | struct geni_se_device *geni_se_dev; |
| 1086 | |
| 1087 | if (!wrapper_dev || !iova || !size) |
| 1088 | return -EINVAL; |
| 1089 | |
| 1090 | geni_se_dev = dev_get_drvdata(wrapper_dev); |
| 1091 | if (!geni_se_dev || !geni_se_dev->cb_dev) |
| 1092 | return -ENODEV; |
| 1093 | |
| 1094 | cb_dev = geni_se_dev->cb_dev; |
| 1095 | |
| 1096 | dma_unmap_single(cb_dev, *iova, size, dir); |
| 1097 | return 0; |
| 1098 | } |
| 1099 | EXPORT_SYMBOL(geni_se_iommu_unmap_buf); |
| 1100 | |
| 1101 | /** |
| 1102 | * geni_se_iommu_free_buf() - Unmap & free a single buffer from QUPv3 |
| 1103 | * context bank |
| 1104 | * @wrapper_dev: Pointer to the corresponding QUPv3 wrapper core. |
| 1105 | * @iova: Pointer in which the mapped virtual address is stored. |
| 1106 | * @buf: Address of the buffer. |
| 1107 | * @size: Size of the buffer. |
| 1108 | * |
| 1109 | * This function is used to unmap and free a buffer from the |
| 1110 | * QUPv3 context bank device space. |
| 1111 | * |
| 1112 | * Return: 0 on success, standard Linux error codes on failure/error. |
| 1113 | */ |
| 1114 | int geni_se_iommu_free_buf(struct device *wrapper_dev, dma_addr_t *iova, |
| 1115 | void *buf, size_t size) |
| 1116 | { |
| 1117 | struct device *cb_dev; |
| 1118 | struct geni_se_device *geni_se_dev; |
| 1119 | |
| 1120 | if (!wrapper_dev || !iova || !buf || !size) |
| 1121 | return -EINVAL; |
| 1122 | |
| 1123 | geni_se_dev = dev_get_drvdata(wrapper_dev); |
| 1124 | if (!geni_se_dev || !geni_se_dev->cb_dev) |
| 1125 | return -ENODEV; |
| 1126 | |
| 1127 | cb_dev = geni_se_dev->cb_dev; |
| 1128 | |
| 1129 | dma_free_coherent(cb_dev, size, buf, *iova); |
| 1130 | return 0; |
| 1131 | } |
| 1132 | EXPORT_SYMBOL(geni_se_iommu_free_buf); |
| 1133 | |
| 1134 | static const struct of_device_id geni_se_dt_match[] = { |
| 1135 | { .compatible = "qcom,qupv3-geni-se", }, |
| 1136 | { .compatible = "qcom,qupv3-geni-se-cb", }, |
| 1137 | {} |
| 1138 | }; |
| 1139 | |
| 1140 | static int geni_se_iommu_probe(struct device *dev) |
| 1141 | { |
| 1142 | struct geni_se_device *geni_se_dev; |
| 1143 | |
| 1144 | if (unlikely(!dev->parent)) { |
| 1145 | dev_err(dev, "%s no parent for this device\n", __func__); |
| 1146 | return -EINVAL; |
| 1147 | } |
| 1148 | |
| 1149 | geni_se_dev = dev_get_drvdata(dev->parent); |
| 1150 | if (unlikely(!geni_se_dev)) { |
| 1151 | dev_err(dev, "%s geni_se_dev not found\n", __func__); |
| 1152 | return -EINVAL; |
| 1153 | } |
| 1154 | geni_se_dev->cb_dev = dev; |
| 1155 | |
| 1156 | GENI_SE_DBG(geni_se_dev->log_ctx, false, NULL, |
| 1157 | "%s: Probe successful\n", __func__); |
| 1158 | return 0; |
| 1159 | } |
| 1160 | |
| 1161 | static int geni_se_probe(struct platform_device *pdev) |
| 1162 | { |
| 1163 | int ret; |
| 1164 | struct device *dev = &pdev->dev; |
| 1165 | struct resource *res; |
| 1166 | struct geni_se_device *geni_se_dev; |
| 1167 | |
| 1168 | if (of_device_is_compatible(dev->of_node, "qcom,qupv3-geni-se-cb")) |
| 1169 | return geni_se_iommu_probe(dev); |
| 1170 | |
| 1171 | geni_se_dev = devm_kzalloc(dev, sizeof(*geni_se_dev), GFP_KERNEL); |
| 1172 | if (!geni_se_dev) |
| 1173 | return -ENOMEM; |
| 1174 | |
| 1175 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 1176 | if (!res) { |
| 1177 | dev_err(dev, "%s: Mandatory resource info not found\n", |
| 1178 | __func__); |
| 1179 | devm_kfree(dev, geni_se_dev); |
| 1180 | return -EINVAL; |
| 1181 | } |
| 1182 | |
| 1183 | geni_se_dev->base = devm_ioremap_resource(dev, res); |
| 1184 | if (IS_ERR_OR_NULL(geni_se_dev->base)) { |
| 1185 | dev_err(dev, "%s: Error mapping the resource\n", __func__); |
| 1186 | devm_kfree(dev, geni_se_dev); |
| 1187 | return -EFAULT; |
| 1188 | } |
| 1189 | |
| 1190 | geni_se_dev->dev = dev; |
| 1191 | ret = of_property_read_u32(dev->of_node, "qcom,bus-mas-id", |
| 1192 | &geni_se_dev->bus_mas_id); |
| 1193 | if (ret) { |
| 1194 | dev_err(dev, "%s: Error missing bus master id\n", __func__); |
| 1195 | devm_iounmap(dev, geni_se_dev->base); |
| 1196 | devm_kfree(dev, geni_se_dev); |
| 1197 | } |
| 1198 | ret = of_property_read_u32(dev->of_node, "qcom,bus-slv-id", |
| 1199 | &geni_se_dev->bus_slv_id); |
| 1200 | if (ret) { |
| 1201 | dev_err(dev, "%s: Error missing bus slave id\n", __func__); |
| 1202 | devm_iounmap(dev, geni_se_dev->base); |
| 1203 | devm_kfree(dev, geni_se_dev); |
| 1204 | } |
| 1205 | |
| 1206 | geni_se_dev->iommu_s1_bypass = of_property_read_bool(dev->of_node, |
| 1207 | "qcom,iommu-s1-bypass"); |
| 1208 | geni_se_dev->bus_bw_set = default_bus_bw_set; |
| 1209 | geni_se_dev->bus_bw_set_size = ARRAY_SIZE(default_bus_bw_set); |
| 1210 | mutex_init(&geni_se_dev->iommu_lock); |
| 1211 | INIT_LIST_HEAD(&geni_se_dev->ab_list_head); |
| 1212 | INIT_LIST_HEAD(&geni_se_dev->ib_list_head); |
| 1213 | spin_lock_init(&geni_se_dev->ab_ib_lock); |
| 1214 | geni_se_dev->log_ctx = ipc_log_context_create(NUM_LOG_PAGES, |
| 1215 | dev_name(geni_se_dev->dev), 0); |
| 1216 | if (!geni_se_dev->log_ctx) |
| 1217 | dev_err(dev, "%s Failed to allocate log context\n", __func__); |
| 1218 | dev_set_drvdata(dev, geni_se_dev); |
| 1219 | |
| 1220 | ret = of_platform_populate(dev->of_node, geni_se_dt_match, NULL, dev); |
| 1221 | if (ret) { |
| 1222 | dev_err(dev, "%s: Error populating children\n", __func__); |
| 1223 | devm_iounmap(dev, geni_se_dev->base); |
| 1224 | devm_kfree(dev, geni_se_dev); |
| 1225 | } |
| 1226 | |
| 1227 | GENI_SE_DBG(geni_se_dev->log_ctx, false, NULL, |
| 1228 | "%s: Probe successful\n", __func__); |
| 1229 | return ret; |
| 1230 | } |
| 1231 | |
| 1232 | static int geni_se_remove(struct platform_device *pdev) |
| 1233 | { |
| 1234 | struct device *dev = &pdev->dev; |
| 1235 | struct geni_se_device *geni_se_dev = dev_get_drvdata(dev); |
| 1236 | |
| 1237 | if (likely(!IS_ERR_OR_NULL(geni_se_dev->iommu_map))) { |
| 1238 | arm_iommu_detach_device(geni_se_dev->cb_dev); |
| 1239 | arm_iommu_release_mapping(geni_se_dev->iommu_map); |
| 1240 | } |
| 1241 | ipc_log_context_destroy(geni_se_dev->log_ctx); |
| 1242 | devm_iounmap(dev, geni_se_dev->base); |
| 1243 | devm_kfree(dev, geni_se_dev); |
| 1244 | return 0; |
| 1245 | } |
| 1246 | |
| 1247 | static struct platform_driver geni_se_driver = { |
| 1248 | .driver = { |
| 1249 | .name = "qupv3_geni_se", |
| 1250 | .of_match_table = geni_se_dt_match, |
| 1251 | }, |
| 1252 | .probe = geni_se_probe, |
| 1253 | .remove = geni_se_remove, |
| 1254 | }; |
| 1255 | |
| 1256 | static int __init geni_se_driver_init(void) |
| 1257 | { |
| 1258 | return platform_driver_register(&geni_se_driver); |
| 1259 | } |
| 1260 | arch_initcall(geni_se_driver_init); |
| 1261 | |
| 1262 | static void __exit geni_se_driver_exit(void) |
| 1263 | { |
| 1264 | platform_driver_unregister(&geni_se_driver); |
| 1265 | } |
| 1266 | module_exit(geni_se_driver_exit); |
| 1267 | |
| 1268 | MODULE_DESCRIPTION("GENI Serial Engine Driver"); |
| 1269 | MODULE_LICENSE("GPL v2"); |