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Peter Ujfalusifd26f942011-11-28 15:45:40 +02001/*
2 * omap-dmic.h -- OMAP Digital Microphone Controller
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#ifndef _OMAP_DMIC_H
10#define _OMAP_DMIC_H
11
12#define OMAP_DMIC_REVISION_REG 0x00
13#define OMAP_DMIC_SYSCONFIG_REG 0x10
14#define OMAP_DMIC_IRQSTATUS_RAW_REG 0x24
15#define OMAP_DMIC_IRQSTATUS_REG 0x28
16#define OMAP_DMIC_IRQENABLE_SET_REG 0x2C
17#define OMAP_DMIC_IRQENABLE_CLR_REG 0x30
18#define OMAP_DMIC_IRQWAKE_EN_REG 0x34
19#define OMAP_DMIC_DMAENABLE_SET_REG 0x38
20#define OMAP_DMIC_DMAENABLE_CLR_REG 0x3C
21#define OMAP_DMIC_DMAWAKEEN_REG 0x40
22#define OMAP_DMIC_CTRL_REG 0x44
23#define OMAP_DMIC_DATA_REG 0x48
24#define OMAP_DMIC_FIFO_CTRL_REG 0x4C
25#define OMAP_DMIC_FIFO_DMIC1R_DATA_REG 0x50
26#define OMAP_DMIC_FIFO_DMIC1L_DATA_REG 0x54
27#define OMAP_DMIC_FIFO_DMIC2R_DATA_REG 0x58
28#define OMAP_DMIC_FIFO_DMIC2L_DATA_REG 0x5C
29#define OMAP_DMIC_FIFO_DMIC3R_DATA_REG 0x60
30#define OMAP_DMIC_FIFO_DMIC3L_DATA_REG 0x64
31
32/* IRQSTATUS_RAW, IRQSTATUS, IRQENABLE_SET, IRQENABLE_CLR bit fields */
33#define OMAP_DMIC_IRQ (1 << 0)
34#define OMAP_DMIC_IRQ_FULL (1 << 1)
35#define OMAP_DMIC_IRQ_ALMST_EMPTY (1 << 2)
36#define OMAP_DMIC_IRQ_EMPTY (1 << 3)
37#define OMAP_DMIC_IRQ_MASK 0x07
38
39/* DMIC_DMAENABLE bit fields */
40#define OMAP_DMIC_DMA_ENABLE 0x1
41
42/* DMIC_CTRL bit fields */
43#define OMAP_DMIC_UP1_ENABLE (1 << 0)
44#define OMAP_DMIC_UP2_ENABLE (1 << 1)
45#define OMAP_DMIC_UP3_ENABLE (1 << 2)
46#define OMAP_DMIC_UP_ENABLE_MASK 0x7
47#define OMAP_DMIC_FORMAT (1 << 3)
48#define OMAP_DMIC_POLAR1 (1 << 4)
49#define OMAP_DMIC_POLAR2 (1 << 5)
50#define OMAP_DMIC_POLAR3 (1 << 6)
51#define OMAP_DMIC_POLAR_MASK (0x7 << 4)
52#define OMAP_DMIC_CLK_DIV(x) (((x) & 0x7) << 7)
53#define OMAP_DMIC_CLK_DIV_MASK (0x7 << 7)
54#define OMAP_DMIC_RESET (1 << 10)
55
56#define OMAP_DMICOUTFORMAT_LJUST (0 << 3)
57#define OMAP_DMICOUTFORMAT_RJUST (1 << 3)
58
59/* DMIC_FIFO_CTRL bit fields */
60#define OMAP_DMIC_THRES_MAX 0xF
61
62enum omap_dmic_clk {
63 OMAP_DMIC_SYSCLK_PAD_CLKS, /* PAD_CLKS */
64 OMAP_DMIC_SYSCLK_SLIMBLUS_CLKS, /* SLIMBUS_CLK */
65 OMAP_DMIC_SYSCLK_SYNC_MUX_CLKS, /* DMIC_SYNC_MUX_CLK */
66 OMAP_DMIC_ABE_DMIC_CLK, /* abe_dmic_clk */
67};
68
69#endif