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Zhang, Yanmin6c2b3742006-07-31 15:21:33 +08001/*
2 * Copyright (C) 2006 Intel Corp.
3 * Tom Long Nguyen (tom.l.nguyen@intel.com)
4 * Zhang Yanmin (yanmin.zhang@intel.com)
5 *
6 */
7
8#ifndef _AERDRV_H_
9#define _AERDRV_H_
10
Alexey Dobriyane8edc6e2007-05-21 01:22:52 +040011#include <linux/workqueue.h>
Zhang, Yanmin6c2b3742006-07-31 15:21:33 +080012#include <linux/pcieport_if.h>
13#include <linux/aer.h>
Huang Ying634deb02009-04-24 10:45:23 +080014#include <linux/interrupt.h>
Zhang, Yanmin6c2b3742006-07-31 15:21:33 +080015
16#define AER_NONFATAL 0
17#define AER_FATAL 1
18#define AER_CORRECTABLE 2
19#define AER_UNCORRECTABLE 4
20#define AER_ERROR_MASK 0x001fffff
21#define AER_ERROR(d) (d & AER_ERROR_MASK)
22
Zhang, Yanmin6c2b3742006-07-31 15:21:33 +080023/* Root Error Status Register Bits */
Hidetoshi Setoc9a91882009-09-07 17:07:29 +090024#define ROOT_ERR_STATUS_MASKS 0x0f
Zhang, Yanmin6c2b3742006-07-31 15:21:33 +080025
26#define SYSTEM_ERROR_INTR_ON_MESG_MASK (PCI_EXP_RTCTL_SECEE| \
27 PCI_EXP_RTCTL_SENFEE| \
28 PCI_EXP_RTCTL_SEFEE)
29#define ROOT_PORT_INTR_ON_MESG_MASK (PCI_ERR_ROOT_CMD_COR_EN| \
30 PCI_ERR_ROOT_CMD_NONFATAL_EN| \
31 PCI_ERR_ROOT_CMD_FATAL_EN)
32#define ERR_COR_ID(d) (d & 0xffff)
33#define ERR_UNCOR_ID(d) (d >> 16)
34
35#define AER_SUCCESS 0
36#define AER_UNSUCCESS 1
37#define AER_ERROR_SOURCES_MAX 100
38
39#define AER_LOG_TLP_MASKS (PCI_ERR_UNC_POISON_TLP| \
40 PCI_ERR_UNC_ECRC| \
41 PCI_ERR_UNC_UNSUP| \
42 PCI_ERR_UNC_COMP_ABORT| \
43 PCI_ERR_UNC_UNX_COMP| \
44 PCI_ERR_UNC_MALF_TLP)
45
46/* AER Error Info Flags */
47#define AER_TLP_HEADER_VALID_FLAG 0x00000001
48#define AER_MULTI_ERROR_VALID_FLAG 0x00000002
49
Zhang, Yanmin6c2b3742006-07-31 15:21:33 +080050struct header_log_regs {
51 unsigned int dw0;
52 unsigned int dw1;
53 unsigned int dw2;
54 unsigned int dw3;
55};
56
Zhang, Yanmin3d5505c2009-06-16 13:35:16 +080057#define AER_MAX_MULTI_ERR_DEVICES 5 /* Not likely to have more */
Zhang, Yanmin6c2b3742006-07-31 15:21:33 +080058struct aer_err_info {
Zhang, Yanmin3d5505c2009-06-16 13:35:16 +080059 struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES];
60 int error_dev_num;
Zhang, Yanmin28eb27c2009-06-16 13:35:11 +080061 u16 id;
Zhang, Yanmin6c2b3742006-07-31 15:21:33 +080062 int severity; /* 0:NONFATAL | 1:FATAL | 2:COR */
63 int flags;
64 unsigned int status; /* COR/UNCOR Error Status */
Hidetoshi Seto0d90c3a2009-09-07 17:12:25 +090065 unsigned int mask; /* COR/UNCOR Error Mask */
Hidetoshi Setoc9a91882009-09-07 17:07:29 +090066 struct header_log_regs tlp; /* TLP Header */
Zhang, Yanmin6c2b3742006-07-31 15:21:33 +080067};
68
69struct aer_err_source {
70 unsigned int status;
71 unsigned int id;
72};
73
74struct aer_rpc {
75 struct pcie_device *rpd; /* Root Port device */
76 struct work_struct dpc_handler;
77 struct aer_err_source e_sources[AER_ERROR_SOURCES_MAX];
78 unsigned short prod_idx; /* Error Producer Index */
79 unsigned short cons_idx; /* Error Consumer Index */
80 int isr;
81 spinlock_t e_lock; /*
82 * Lock access to Error Status/ID Regs
83 * and error producer/consumer index
84 */
85 struct mutex rpc_mutex; /*
86 * only one thread could do
87 * recovery on the same
Uwe Kleine-König1b3c3712007-02-17 19:23:03 +010088 * root port hierarchy
Zhang, Yanmin6c2b3742006-07-31 15:21:33 +080089 */
90 wait_queue_head_t wait_release;
91};
92
93struct aer_broadcast_data {
94 enum pci_channel_state state;
95 enum pci_ers_result result;
96};
97
98static inline pci_ers_result_t merge_result(enum pci_ers_result orig,
99 enum pci_ers_result new)
100{
Zhang, Yanmin029091d2009-04-30 14:48:29 +0800101 if (new == PCI_ERS_RESULT_NONE)
102 return orig;
103
Zhang, Yanmin6c2b3742006-07-31 15:21:33 +0800104 switch (orig) {
105 case PCI_ERS_RESULT_CAN_RECOVER:
106 case PCI_ERS_RESULT_RECOVERED:
107 orig = new;
108 break;
109 case PCI_ERS_RESULT_DISCONNECT:
110 if (new == PCI_ERS_RESULT_NEED_RESET)
111 orig = new;
112 break;
113 default:
114 break;
115 }
116
117 return orig;
118}
119
120extern struct bus_type pcie_port_bus_type;
121extern void aer_enable_rootport(struct aer_rpc *rpc);
122extern void aer_delete_rootport(struct aer_rpc *rpc);
123extern int aer_init(struct pcie_device *dev);
David Howells65f27f32006-11-22 14:55:48 +0000124extern void aer_isr(struct work_struct *work);
Zhang, Yanmin6c2b3742006-07-31 15:21:33 +0800125extern void aer_print_error(struct pci_dev *dev, struct aer_err_info *info);
Huang Ying634deb02009-04-24 10:45:23 +0800126extern irqreturn_t aer_irq(int irq, void *context);
Zhang, Yanmin8d29bfb2007-06-06 11:44:16 +0800127
128#ifdef CONFIG_ACPI
129extern int aer_osc_setup(struct pcie_device *pciedev);
130#else
131static inline int aer_osc_setup(struct pcie_device *pciedev)
132{
133 return 0;
134}
135#endif
Zhang, Yanmin6c2b3742006-07-31 15:21:33 +0800136
Hidetoshi Setoc9a91882009-09-07 17:07:29 +0900137#endif /* _AERDRV_H_ */