Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2013 Red Hat |
| 3 | * Author: Rob Clark <robdclark@gmail.com> |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify it |
| 6 | * under the terms of the GNU General Public License version 2 as published by |
| 7 | * the Free Software Foundation. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 12 | * more details. |
| 13 | * |
| 14 | * You should have received a copy of the GNU General Public License along with |
| 15 | * this program. If not, see <http://www.gnu.org/licenses/>. |
| 16 | */ |
| 17 | |
| 18 | #include "mdp4_kms.h" |
| 19 | |
| 20 | #include <drm/drm_mode.h> |
| 21 | #include "drm_crtc.h" |
| 22 | #include "drm_crtc_helper.h" |
| 23 | #include "drm_flip_work.h" |
| 24 | |
| 25 | struct mdp4_crtc { |
| 26 | struct drm_crtc base; |
| 27 | char name[8]; |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 28 | int id; |
| 29 | int ovlp; |
| 30 | enum mdp4_dma dma; |
| 31 | bool enabled; |
| 32 | |
| 33 | /* which mixer/encoder we route output to: */ |
| 34 | int mixer; |
| 35 | |
| 36 | struct { |
| 37 | spinlock_t lock; |
| 38 | bool stale; |
| 39 | uint32_t width, height; |
Rob Clark | aa1b0e5 | 2013-12-13 10:49:25 -0500 | [diff] [blame] | 40 | uint32_t x, y; |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 41 | |
| 42 | /* next cursor to scan-out: */ |
| 43 | uint32_t next_iova; |
| 44 | struct drm_gem_object *next_bo; |
| 45 | |
| 46 | /* current cursor being scanned out: */ |
| 47 | struct drm_gem_object *scanout_bo; |
| 48 | } cursor; |
| 49 | |
| 50 | |
| 51 | /* if there is a pending flip, these will be non-null: */ |
| 52 | struct drm_pending_vblank_event *event; |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 53 | |
Rob Clark | 2a2b8fa | 2013-10-29 12:05:20 -0400 | [diff] [blame] | 54 | #define PENDING_CURSOR 0x1 |
| 55 | #define PENDING_FLIP 0x2 |
| 56 | atomic_t pending; |
| 57 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 58 | /* for unref'ing cursor bo's after scanout completes: */ |
| 59 | struct drm_flip_work unref_cursor_work; |
| 60 | |
Rob Clark | 9e0efa6 | 2013-11-30 17:24:22 -0500 | [diff] [blame] | 61 | struct mdp_irq vblank; |
| 62 | struct mdp_irq err; |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 63 | }; |
| 64 | #define to_mdp4_crtc(x) container_of(x, struct mdp4_crtc, base) |
| 65 | |
| 66 | static struct mdp4_kms *get_kms(struct drm_crtc *crtc) |
| 67 | { |
| 68 | struct msm_drm_private *priv = crtc->dev->dev_private; |
Rob Clark | 9e0efa6 | 2013-11-30 17:24:22 -0500 | [diff] [blame] | 69 | return to_mdp4_kms(to_mdp_kms(priv->kms)); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 70 | } |
| 71 | |
Rob Clark | b69720c | 2013-12-13 10:41:07 -0500 | [diff] [blame] | 72 | static void request_pending(struct drm_crtc *crtc, uint32_t pending) |
| 73 | { |
| 74 | struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc); |
| 75 | |
| 76 | atomic_or(pending, &mdp4_crtc->pending); |
| 77 | mdp_irq_register(&get_kms(crtc)->base, &mdp4_crtc->vblank); |
| 78 | } |
| 79 | |
| 80 | static void crtc_flush(struct drm_crtc *crtc) |
| 81 | { |
| 82 | struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc); |
| 83 | struct mdp4_kms *mdp4_kms = get_kms(crtc); |
Rob Clark | bb6c018 | 2014-11-07 13:20:50 -0500 | [diff] [blame] | 84 | struct drm_plane *plane; |
| 85 | uint32_t flush = 0; |
Rob Clark | b69720c | 2013-12-13 10:41:07 -0500 | [diff] [blame] | 86 | |
Rob Clark | 93b02be | 2014-11-25 20:29:47 -0500 | [diff] [blame] | 87 | drm_atomic_crtc_for_each_plane(plane, crtc) { |
Rob Clark | bb6c018 | 2014-11-07 13:20:50 -0500 | [diff] [blame] | 88 | enum mdp4_pipe pipe_id = mdp4_plane_pipe(plane); |
| 89 | flush |= pipe2flush(pipe_id); |
Rob Clark | b69720c | 2013-12-13 10:41:07 -0500 | [diff] [blame] | 90 | } |
Rob Clark | bb6c018 | 2014-11-07 13:20:50 -0500 | [diff] [blame] | 91 | |
Rob Clark | b69720c | 2013-12-13 10:41:07 -0500 | [diff] [blame] | 92 | flush |= ovlp2flush(mdp4_crtc->ovlp); |
| 93 | |
| 94 | DBG("%s: flush=%08x", mdp4_crtc->name, flush); |
| 95 | |
| 96 | mdp4_write(mdp4_kms, REG_MDP4_OVERLAY_FLUSH, flush); |
| 97 | } |
| 98 | |
Rob Clark | 2a2b8fa | 2013-10-29 12:05:20 -0400 | [diff] [blame] | 99 | /* if file!=NULL, this is preclose potential cancel-flip path */ |
| 100 | static void complete_flip(struct drm_crtc *crtc, struct drm_file *file) |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 101 | { |
| 102 | struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc); |
| 103 | struct drm_device *dev = crtc->dev; |
| 104 | struct drm_pending_vblank_event *event; |
| 105 | unsigned long flags; |
| 106 | |
| 107 | spin_lock_irqsave(&dev->event_lock, flags); |
| 108 | event = mdp4_crtc->event; |
| 109 | if (event) { |
Rob Clark | 2a2b8fa | 2013-10-29 12:05:20 -0400 | [diff] [blame] | 110 | /* if regular vblank case (!file) or if cancel-flip from |
| 111 | * preclose on file that requested flip, then send the |
| 112 | * event: |
| 113 | */ |
| 114 | if (!file || (event->base.file_priv == file)) { |
| 115 | mdp4_crtc->event = NULL; |
Rob Clark | e27c54f | 2014-11-08 13:24:08 -0500 | [diff] [blame] | 116 | DBG("%s: send event: %p", mdp4_crtc->name, event); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 117 | drm_send_vblank_event(dev, mdp4_crtc->id, event); |
Rob Clark | 2a2b8fa | 2013-10-29 12:05:20 -0400 | [diff] [blame] | 118 | } |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 119 | } |
| 120 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 121 | } |
| 122 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 123 | static void unref_cursor_worker(struct drm_flip_work *work, void *val) |
| 124 | { |
| 125 | struct mdp4_crtc *mdp4_crtc = |
| 126 | container_of(work, struct mdp4_crtc, unref_cursor_work); |
| 127 | struct mdp4_kms *mdp4_kms = get_kms(&mdp4_crtc->base); |
| 128 | |
| 129 | msm_gem_put_iova(val, mdp4_kms->id); |
| 130 | drm_gem_object_unreference_unlocked(val); |
| 131 | } |
| 132 | |
| 133 | static void mdp4_crtc_destroy(struct drm_crtc *crtc) |
| 134 | { |
| 135 | struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc); |
| 136 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 137 | drm_crtc_cleanup(crtc); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 138 | drm_flip_work_cleanup(&mdp4_crtc->unref_cursor_work); |
| 139 | |
| 140 | kfree(mdp4_crtc); |
| 141 | } |
| 142 | |
| 143 | static void mdp4_crtc_dpms(struct drm_crtc *crtc, int mode) |
| 144 | { |
| 145 | struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc); |
| 146 | struct mdp4_kms *mdp4_kms = get_kms(crtc); |
| 147 | bool enabled = (mode == DRM_MODE_DPMS_ON); |
| 148 | |
| 149 | DBG("%s: mode=%d", mdp4_crtc->name, mode); |
| 150 | |
| 151 | if (enabled != mdp4_crtc->enabled) { |
| 152 | if (enabled) { |
| 153 | mdp4_enable(mdp4_kms); |
Rob Clark | 9e0efa6 | 2013-11-30 17:24:22 -0500 | [diff] [blame] | 154 | mdp_irq_register(&mdp4_kms->base, &mdp4_crtc->err); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 155 | } else { |
Rob Clark | 9e0efa6 | 2013-11-30 17:24:22 -0500 | [diff] [blame] | 156 | mdp_irq_unregister(&mdp4_kms->base, &mdp4_crtc->err); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 157 | mdp4_disable(mdp4_kms); |
| 158 | } |
| 159 | mdp4_crtc->enabled = enabled; |
| 160 | } |
| 161 | } |
| 162 | |
| 163 | static bool mdp4_crtc_mode_fixup(struct drm_crtc *crtc, |
| 164 | const struct drm_display_mode *mode, |
| 165 | struct drm_display_mode *adjusted_mode) |
| 166 | { |
| 167 | return true; |
| 168 | } |
| 169 | |
Rob Clark | 4dd14fe | 2014-11-21 11:18:01 -0500 | [diff] [blame] | 170 | /* statically (for now) map planes to mixer stage (z-order): */ |
| 171 | static const int idxs[] = { |
| 172 | [VG1] = 1, |
| 173 | [VG2] = 2, |
| 174 | [RGB1] = 0, |
| 175 | [RGB2] = 0, |
| 176 | [RGB3] = 0, |
| 177 | [VG3] = 3, |
| 178 | [VG4] = 4, |
| 179 | |
| 180 | }; |
| 181 | |
| 182 | /* setup mixer config, for which we need to consider all crtc's and |
| 183 | * the planes attached to them |
| 184 | * |
| 185 | * TODO may possibly need some extra locking here |
| 186 | */ |
| 187 | static void setup_mixer(struct mdp4_kms *mdp4_kms) |
| 188 | { |
| 189 | struct drm_mode_config *config = &mdp4_kms->dev->mode_config; |
| 190 | struct drm_crtc *crtc; |
| 191 | uint32_t mixer_cfg = 0; |
| 192 | static const enum mdp_mixer_stage_id stages[] = { |
| 193 | STAGE_BASE, STAGE0, STAGE1, STAGE2, STAGE3, |
| 194 | }; |
| 195 | |
| 196 | list_for_each_entry(crtc, &config->crtc_list, head) { |
| 197 | struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc); |
| 198 | struct drm_plane *plane; |
| 199 | |
Rob Clark | 93b02be | 2014-11-25 20:29:47 -0500 | [diff] [blame] | 200 | drm_atomic_crtc_for_each_plane(plane, crtc) { |
Rob Clark | 4dd14fe | 2014-11-21 11:18:01 -0500 | [diff] [blame] | 201 | enum mdp4_pipe pipe_id = mdp4_plane_pipe(plane); |
| 202 | int idx = idxs[pipe_id]; |
| 203 | mixer_cfg = mixercfg(mixer_cfg, mdp4_crtc->mixer, |
| 204 | pipe_id, stages[idx]); |
| 205 | } |
| 206 | } |
| 207 | |
| 208 | mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG, mixer_cfg); |
| 209 | } |
| 210 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 211 | static void blend_setup(struct drm_crtc *crtc) |
| 212 | { |
| 213 | struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc); |
| 214 | struct mdp4_kms *mdp4_kms = get_kms(crtc); |
Rob Clark | bb6c018 | 2014-11-07 13:20:50 -0500 | [diff] [blame] | 215 | struct drm_plane *plane; |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 216 | int i, ovlp = mdp4_crtc->ovlp; |
Rob Clark | a862391 | 2013-10-08 12:57:48 -0400 | [diff] [blame] | 217 | bool alpha[4]= { false, false, false, false }; |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 218 | |
| 219 | mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_LOW0(ovlp), 0); |
| 220 | mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_LOW1(ovlp), 0); |
| 221 | mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_HIGH0(ovlp), 0); |
| 222 | mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_HIGH1(ovlp), 0); |
| 223 | |
Rob Clark | 93b02be | 2014-11-25 20:29:47 -0500 | [diff] [blame] | 224 | drm_atomic_crtc_for_each_plane(plane, crtc) { |
Rob Clark | bb6c018 | 2014-11-07 13:20:50 -0500 | [diff] [blame] | 225 | enum mdp4_pipe pipe_id = mdp4_plane_pipe(plane); |
| 226 | int idx = idxs[pipe_id]; |
| 227 | if (idx > 0) { |
| 228 | const struct mdp_format *format = |
Rob Clark | 10a02eb | 2013-11-30 14:58:23 -0500 | [diff] [blame] | 229 | to_mdp_format(msm_framebuffer_format(plane->fb)); |
Rob Clark | bb6c018 | 2014-11-07 13:20:50 -0500 | [diff] [blame] | 230 | alpha[idx-1] = format->alpha_enable; |
Rob Clark | a862391 | 2013-10-08 12:57:48 -0400 | [diff] [blame] | 231 | } |
| 232 | } |
| 233 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 234 | for (i = 0; i < 4; i++) { |
Rob Clark | a862391 | 2013-10-08 12:57:48 -0400 | [diff] [blame] | 235 | uint32_t op; |
| 236 | |
| 237 | if (alpha[i]) { |
| 238 | op = MDP4_OVLP_STAGE_OP_FG_ALPHA(FG_PIXEL) | |
| 239 | MDP4_OVLP_STAGE_OP_BG_ALPHA(FG_PIXEL) | |
| 240 | MDP4_OVLP_STAGE_OP_BG_INV_ALPHA; |
| 241 | } else { |
| 242 | op = MDP4_OVLP_STAGE_OP_FG_ALPHA(FG_CONST) | |
| 243 | MDP4_OVLP_STAGE_OP_BG_ALPHA(BG_CONST); |
| 244 | } |
| 245 | |
| 246 | mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_FG_ALPHA(ovlp, i), 0xff); |
| 247 | mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_BG_ALPHA(ovlp, i), 0x00); |
| 248 | mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_OP(ovlp, i), op); |
| 249 | mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_CO3(ovlp, i), 1); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 250 | mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_LOW0(ovlp, i), 0); |
| 251 | mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_LOW1(ovlp, i), 0); |
| 252 | mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_HIGH0(ovlp, i), 0); |
| 253 | mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_HIGH1(ovlp, i), 0); |
| 254 | } |
| 255 | |
Rob Clark | 4dd14fe | 2014-11-21 11:18:01 -0500 | [diff] [blame] | 256 | setup_mixer(mdp4_kms); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 257 | } |
| 258 | |
Rob Clark | e27c54f | 2014-11-08 13:24:08 -0500 | [diff] [blame] | 259 | static void mdp4_crtc_mode_set_nofb(struct drm_crtc *crtc) |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 260 | { |
| 261 | struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc); |
| 262 | struct mdp4_kms *mdp4_kms = get_kms(crtc); |
| 263 | enum mdp4_dma dma = mdp4_crtc->dma; |
Rob Clark | e27c54f | 2014-11-08 13:24:08 -0500 | [diff] [blame] | 264 | int ovlp = mdp4_crtc->ovlp; |
| 265 | struct drm_display_mode *mode; |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 266 | |
Rob Clark | e27c54f | 2014-11-08 13:24:08 -0500 | [diff] [blame] | 267 | if (WARN_ON(!crtc->state)) |
| 268 | return; |
| 269 | |
| 270 | mode = &crtc->state->adjusted_mode; |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 271 | |
| 272 | DBG("%s: set mode: %d:\"%s\" %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x", |
| 273 | mdp4_crtc->name, mode->base.id, mode->name, |
| 274 | mode->vrefresh, mode->clock, |
| 275 | mode->hdisplay, mode->hsync_start, |
| 276 | mode->hsync_end, mode->htotal, |
| 277 | mode->vdisplay, mode->vsync_start, |
| 278 | mode->vsync_end, mode->vtotal, |
| 279 | mode->type, mode->flags); |
| 280 | |
| 281 | mdp4_write(mdp4_kms, REG_MDP4_DMA_SRC_SIZE(dma), |
| 282 | MDP4_DMA_SRC_SIZE_WIDTH(mode->hdisplay) | |
| 283 | MDP4_DMA_SRC_SIZE_HEIGHT(mode->vdisplay)); |
| 284 | |
| 285 | /* take data from pipe: */ |
| 286 | mdp4_write(mdp4_kms, REG_MDP4_DMA_SRC_BASE(dma), 0); |
Rob Clark | 88ff1c2 | 2014-11-07 13:06:54 -0500 | [diff] [blame] | 287 | mdp4_write(mdp4_kms, REG_MDP4_DMA_SRC_STRIDE(dma), 0); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 288 | mdp4_write(mdp4_kms, REG_MDP4_DMA_DST_SIZE(dma), |
| 289 | MDP4_DMA_DST_SIZE_WIDTH(0) | |
| 290 | MDP4_DMA_DST_SIZE_HEIGHT(0)); |
| 291 | |
| 292 | mdp4_write(mdp4_kms, REG_MDP4_OVLP_BASE(ovlp), 0); |
| 293 | mdp4_write(mdp4_kms, REG_MDP4_OVLP_SIZE(ovlp), |
| 294 | MDP4_OVLP_SIZE_WIDTH(mode->hdisplay) | |
| 295 | MDP4_OVLP_SIZE_HEIGHT(mode->vdisplay)); |
Rob Clark | 88ff1c2 | 2014-11-07 13:06:54 -0500 | [diff] [blame] | 296 | mdp4_write(mdp4_kms, REG_MDP4_OVLP_STRIDE(ovlp), 0); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 297 | |
| 298 | mdp4_write(mdp4_kms, REG_MDP4_OVLP_CFG(ovlp), 1); |
| 299 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 300 | if (dma == DMA_E) { |
| 301 | mdp4_write(mdp4_kms, REG_MDP4_DMA_E_QUANT(0), 0x00ff0000); |
| 302 | mdp4_write(mdp4_kms, REG_MDP4_DMA_E_QUANT(1), 0x00ff0000); |
| 303 | mdp4_write(mdp4_kms, REG_MDP4_DMA_E_QUANT(2), 0x00ff0000); |
| 304 | } |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 305 | } |
| 306 | |
| 307 | static void mdp4_crtc_prepare(struct drm_crtc *crtc) |
| 308 | { |
| 309 | struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc); |
| 310 | DBG("%s", mdp4_crtc->name); |
| 311 | /* make sure we hold a ref to mdp clks while setting up mode: */ |
Rob Clark | 119ecb7 | 2014-08-04 10:44:53 -0400 | [diff] [blame] | 312 | drm_crtc_vblank_get(crtc); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 313 | mdp4_enable(get_kms(crtc)); |
| 314 | mdp4_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); |
| 315 | } |
| 316 | |
| 317 | static void mdp4_crtc_commit(struct drm_crtc *crtc) |
| 318 | { |
| 319 | mdp4_crtc_dpms(crtc, DRM_MODE_DPMS_ON); |
| 320 | crtc_flush(crtc); |
| 321 | /* drop the ref to mdp clk's that we got in prepare: */ |
| 322 | mdp4_disable(get_kms(crtc)); |
Rob Clark | 119ecb7 | 2014-08-04 10:44:53 -0400 | [diff] [blame] | 323 | drm_crtc_vblank_put(crtc); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 324 | } |
| 325 | |
Rob Clark | e27c54f | 2014-11-08 13:24:08 -0500 | [diff] [blame] | 326 | static int mdp4_crtc_atomic_check(struct drm_crtc *crtc, |
| 327 | struct drm_crtc_state *state) |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 328 | { |
| 329 | struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc); |
Rob Clark | e27c54f | 2014-11-08 13:24:08 -0500 | [diff] [blame] | 330 | DBG("%s: check", mdp4_crtc->name); |
Rob Clark | e27c54f | 2014-11-08 13:24:08 -0500 | [diff] [blame] | 331 | // TODO anything else to check? |
Rob Clark | e27c54f | 2014-11-08 13:24:08 -0500 | [diff] [blame] | 332 | return 0; |
| 333 | } |
| 334 | |
| 335 | static void mdp4_crtc_atomic_begin(struct drm_crtc *crtc) |
| 336 | { |
| 337 | struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc); |
| 338 | DBG("%s: begin", mdp4_crtc->name); |
| 339 | } |
| 340 | |
| 341 | static void mdp4_crtc_atomic_flush(struct drm_crtc *crtc) |
| 342 | { |
| 343 | struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc); |
| 344 | struct drm_device *dev = crtc->dev; |
| 345 | unsigned long flags; |
| 346 | |
Rob Clark | f86afec | 2014-11-25 12:41:18 -0500 | [diff] [blame] | 347 | DBG("%s: event: %p", mdp4_crtc->name, crtc->state->event); |
Rob Clark | e27c54f | 2014-11-08 13:24:08 -0500 | [diff] [blame] | 348 | |
| 349 | WARN_ON(mdp4_crtc->event); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 350 | |
Rob Clark | 2a2b8fa | 2013-10-29 12:05:20 -0400 | [diff] [blame] | 351 | spin_lock_irqsave(&dev->event_lock, flags); |
Rob Clark | e27c54f | 2014-11-08 13:24:08 -0500 | [diff] [blame] | 352 | mdp4_crtc->event = crtc->state->event; |
Rob Clark | 2a2b8fa | 2013-10-29 12:05:20 -0400 | [diff] [blame] | 353 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 354 | |
Rob Clark | e27c54f | 2014-11-08 13:24:08 -0500 | [diff] [blame] | 355 | blend_setup(crtc); |
| 356 | crtc_flush(crtc); |
| 357 | request_pending(crtc, PENDING_FLIP); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 358 | } |
| 359 | |
| 360 | static int mdp4_crtc_set_property(struct drm_crtc *crtc, |
| 361 | struct drm_property *property, uint64_t val) |
| 362 | { |
| 363 | // XXX |
| 364 | return -EINVAL; |
| 365 | } |
| 366 | |
| 367 | #define CURSOR_WIDTH 64 |
| 368 | #define CURSOR_HEIGHT 64 |
| 369 | |
| 370 | /* called from IRQ to update cursor related registers (if needed). The |
| 371 | * cursor registers, other than x/y position, appear not to be double |
| 372 | * buffered, and changing them other than from vblank seems to trigger |
| 373 | * underflow. |
| 374 | */ |
| 375 | static void update_cursor(struct drm_crtc *crtc) |
| 376 | { |
| 377 | struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc); |
Rob Clark | aa1b0e5 | 2013-12-13 10:49:25 -0500 | [diff] [blame] | 378 | struct mdp4_kms *mdp4_kms = get_kms(crtc); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 379 | enum mdp4_dma dma = mdp4_crtc->dma; |
| 380 | unsigned long flags; |
| 381 | |
| 382 | spin_lock_irqsave(&mdp4_crtc->cursor.lock, flags); |
| 383 | if (mdp4_crtc->cursor.stale) { |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 384 | struct drm_gem_object *next_bo = mdp4_crtc->cursor.next_bo; |
| 385 | struct drm_gem_object *prev_bo = mdp4_crtc->cursor.scanout_bo; |
| 386 | uint32_t iova = mdp4_crtc->cursor.next_iova; |
| 387 | |
| 388 | if (next_bo) { |
| 389 | /* take a obj ref + iova ref when we start scanning out: */ |
| 390 | drm_gem_object_reference(next_bo); |
| 391 | msm_gem_get_iova_locked(next_bo, mdp4_kms->id, &iova); |
| 392 | |
| 393 | /* enable cursor: */ |
| 394 | mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_SIZE(dma), |
| 395 | MDP4_DMA_CURSOR_SIZE_WIDTH(mdp4_crtc->cursor.width) | |
| 396 | MDP4_DMA_CURSOR_SIZE_HEIGHT(mdp4_crtc->cursor.height)); |
| 397 | mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_BASE(dma), iova); |
| 398 | mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_BLEND_CONFIG(dma), |
| 399 | MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT(CURSOR_ARGB) | |
| 400 | MDP4_DMA_CURSOR_BLEND_CONFIG_CURSOR_EN); |
| 401 | } else { |
| 402 | /* disable cursor: */ |
Rob Clark | 7d8d9f6 | 2014-04-22 12:27:28 -0400 | [diff] [blame] | 403 | mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_BASE(dma), |
| 404 | mdp4_kms->blank_cursor_iova); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 405 | } |
| 406 | |
| 407 | /* and drop the iova ref + obj rev when done scanning out: */ |
| 408 | if (prev_bo) |
| 409 | drm_flip_work_queue(&mdp4_crtc->unref_cursor_work, prev_bo); |
| 410 | |
| 411 | mdp4_crtc->cursor.scanout_bo = next_bo; |
| 412 | mdp4_crtc->cursor.stale = false; |
| 413 | } |
Rob Clark | aa1b0e5 | 2013-12-13 10:49:25 -0500 | [diff] [blame] | 414 | |
| 415 | mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_POS(dma), |
| 416 | MDP4_DMA_CURSOR_POS_X(mdp4_crtc->cursor.x) | |
| 417 | MDP4_DMA_CURSOR_POS_Y(mdp4_crtc->cursor.y)); |
| 418 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 419 | spin_unlock_irqrestore(&mdp4_crtc->cursor.lock, flags); |
| 420 | } |
| 421 | |
| 422 | static int mdp4_crtc_cursor_set(struct drm_crtc *crtc, |
| 423 | struct drm_file *file_priv, uint32_t handle, |
| 424 | uint32_t width, uint32_t height) |
| 425 | { |
| 426 | struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc); |
| 427 | struct mdp4_kms *mdp4_kms = get_kms(crtc); |
| 428 | struct drm_device *dev = crtc->dev; |
| 429 | struct drm_gem_object *cursor_bo, *old_bo; |
| 430 | unsigned long flags; |
| 431 | uint32_t iova; |
| 432 | int ret; |
| 433 | |
| 434 | if ((width > CURSOR_WIDTH) || (height > CURSOR_HEIGHT)) { |
| 435 | dev_err(dev->dev, "bad cursor size: %dx%d\n", width, height); |
| 436 | return -EINVAL; |
| 437 | } |
| 438 | |
| 439 | if (handle) { |
| 440 | cursor_bo = drm_gem_object_lookup(dev, file_priv, handle); |
| 441 | if (!cursor_bo) |
| 442 | return -ENOENT; |
| 443 | } else { |
| 444 | cursor_bo = NULL; |
| 445 | } |
| 446 | |
| 447 | if (cursor_bo) { |
| 448 | ret = msm_gem_get_iova(cursor_bo, mdp4_kms->id, &iova); |
| 449 | if (ret) |
| 450 | goto fail; |
| 451 | } else { |
| 452 | iova = 0; |
| 453 | } |
| 454 | |
| 455 | spin_lock_irqsave(&mdp4_crtc->cursor.lock, flags); |
| 456 | old_bo = mdp4_crtc->cursor.next_bo; |
| 457 | mdp4_crtc->cursor.next_bo = cursor_bo; |
| 458 | mdp4_crtc->cursor.next_iova = iova; |
| 459 | mdp4_crtc->cursor.width = width; |
| 460 | mdp4_crtc->cursor.height = height; |
| 461 | mdp4_crtc->cursor.stale = true; |
| 462 | spin_unlock_irqrestore(&mdp4_crtc->cursor.lock, flags); |
| 463 | |
| 464 | if (old_bo) { |
| 465 | /* drop our previous reference: */ |
Rob Clark | 7d8d9f6 | 2014-04-22 12:27:28 -0400 | [diff] [blame] | 466 | drm_flip_work_queue(&mdp4_crtc->unref_cursor_work, old_bo); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 467 | } |
| 468 | |
Rob Clark | 2a2b8fa | 2013-10-29 12:05:20 -0400 | [diff] [blame] | 469 | request_pending(crtc, PENDING_CURSOR); |
| 470 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 471 | return 0; |
| 472 | |
| 473 | fail: |
| 474 | drm_gem_object_unreference_unlocked(cursor_bo); |
| 475 | return ret; |
| 476 | } |
| 477 | |
| 478 | static int mdp4_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) |
| 479 | { |
| 480 | struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc); |
Rob Clark | aa1b0e5 | 2013-12-13 10:49:25 -0500 | [diff] [blame] | 481 | unsigned long flags; |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 482 | |
Rob Clark | aa1b0e5 | 2013-12-13 10:49:25 -0500 | [diff] [blame] | 483 | spin_lock_irqsave(&mdp4_crtc->cursor.lock, flags); |
| 484 | mdp4_crtc->cursor.x = x; |
| 485 | mdp4_crtc->cursor.y = y; |
| 486 | spin_unlock_irqrestore(&mdp4_crtc->cursor.lock, flags); |
| 487 | |
| 488 | crtc_flush(crtc); |
| 489 | request_pending(crtc, PENDING_CURSOR); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 490 | |
| 491 | return 0; |
| 492 | } |
| 493 | |
| 494 | static const struct drm_crtc_funcs mdp4_crtc_funcs = { |
Rob Clark | e27c54f | 2014-11-08 13:24:08 -0500 | [diff] [blame] | 495 | .set_config = drm_atomic_helper_set_config, |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 496 | .destroy = mdp4_crtc_destroy, |
Rob Clark | e27c54f | 2014-11-08 13:24:08 -0500 | [diff] [blame] | 497 | .page_flip = drm_atomic_helper_page_flip, |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 498 | .set_property = mdp4_crtc_set_property, |
| 499 | .cursor_set = mdp4_crtc_cursor_set, |
| 500 | .cursor_move = mdp4_crtc_cursor_move, |
Rob Clark | e27c54f | 2014-11-08 13:24:08 -0500 | [diff] [blame] | 501 | .reset = drm_atomic_helper_crtc_reset, |
| 502 | .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, |
| 503 | .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 504 | }; |
| 505 | |
| 506 | static const struct drm_crtc_helper_funcs mdp4_crtc_helper_funcs = { |
| 507 | .dpms = mdp4_crtc_dpms, |
| 508 | .mode_fixup = mdp4_crtc_mode_fixup, |
Rob Clark | e27c54f | 2014-11-08 13:24:08 -0500 | [diff] [blame] | 509 | .mode_set_nofb = mdp4_crtc_mode_set_nofb, |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 510 | .prepare = mdp4_crtc_prepare, |
| 511 | .commit = mdp4_crtc_commit, |
Rob Clark | e27c54f | 2014-11-08 13:24:08 -0500 | [diff] [blame] | 512 | .atomic_check = mdp4_crtc_atomic_check, |
| 513 | .atomic_begin = mdp4_crtc_atomic_begin, |
| 514 | .atomic_flush = mdp4_crtc_atomic_flush, |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 515 | }; |
| 516 | |
Rob Clark | 9e0efa6 | 2013-11-30 17:24:22 -0500 | [diff] [blame] | 517 | static void mdp4_crtc_vblank_irq(struct mdp_irq *irq, uint32_t irqstatus) |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 518 | { |
| 519 | struct mdp4_crtc *mdp4_crtc = container_of(irq, struct mdp4_crtc, vblank); |
| 520 | struct drm_crtc *crtc = &mdp4_crtc->base; |
| 521 | struct msm_drm_private *priv = crtc->dev->dev_private; |
Rob Clark | 2a2b8fa | 2013-10-29 12:05:20 -0400 | [diff] [blame] | 522 | unsigned pending; |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 523 | |
Rob Clark | 9e0efa6 | 2013-11-30 17:24:22 -0500 | [diff] [blame] | 524 | mdp_irq_unregister(&get_kms(crtc)->base, &mdp4_crtc->vblank); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 525 | |
Rob Clark | 2a2b8fa | 2013-10-29 12:05:20 -0400 | [diff] [blame] | 526 | pending = atomic_xchg(&mdp4_crtc->pending, 0); |
| 527 | |
| 528 | if (pending & PENDING_FLIP) { |
| 529 | complete_flip(crtc, NULL); |
Rob Clark | 2a2b8fa | 2013-10-29 12:05:20 -0400 | [diff] [blame] | 530 | } |
| 531 | |
| 532 | if (pending & PENDING_CURSOR) { |
| 533 | update_cursor(crtc); |
| 534 | drm_flip_work_commit(&mdp4_crtc->unref_cursor_work, priv->wq); |
| 535 | } |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 536 | } |
| 537 | |
Rob Clark | 9e0efa6 | 2013-11-30 17:24:22 -0500 | [diff] [blame] | 538 | static void mdp4_crtc_err_irq(struct mdp_irq *irq, uint32_t irqstatus) |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 539 | { |
| 540 | struct mdp4_crtc *mdp4_crtc = container_of(irq, struct mdp4_crtc, err); |
| 541 | struct drm_crtc *crtc = &mdp4_crtc->base; |
| 542 | DBG("%s: error: %08x", mdp4_crtc->name, irqstatus); |
| 543 | crtc_flush(crtc); |
| 544 | } |
| 545 | |
| 546 | uint32_t mdp4_crtc_vblank(struct drm_crtc *crtc) |
| 547 | { |
| 548 | struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc); |
| 549 | return mdp4_crtc->vblank.irqmask; |
| 550 | } |
| 551 | |
Rob Clark | 2a2b8fa | 2013-10-29 12:05:20 -0400 | [diff] [blame] | 552 | void mdp4_crtc_cancel_pending_flip(struct drm_crtc *crtc, struct drm_file *file) |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 553 | { |
Rob Clark | e27c54f | 2014-11-08 13:24:08 -0500 | [diff] [blame] | 554 | struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc); |
| 555 | DBG("%s: cancel: %p", mdp4_crtc->name, file); |
Rob Clark | 2a2b8fa | 2013-10-29 12:05:20 -0400 | [diff] [blame] | 556 | complete_flip(crtc, file); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 557 | } |
| 558 | |
| 559 | /* set dma config, ie. the format the encoder wants. */ |
| 560 | void mdp4_crtc_set_config(struct drm_crtc *crtc, uint32_t config) |
| 561 | { |
| 562 | struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc); |
| 563 | struct mdp4_kms *mdp4_kms = get_kms(crtc); |
| 564 | |
| 565 | mdp4_write(mdp4_kms, REG_MDP4_DMA_CONFIG(mdp4_crtc->dma), config); |
| 566 | } |
| 567 | |
| 568 | /* set interface for routing crtc->encoder: */ |
Rob Clark | d65bd0e | 2014-08-06 07:43:12 -0400 | [diff] [blame] | 569 | void mdp4_crtc_set_intf(struct drm_crtc *crtc, enum mdp4_intf intf, int mixer) |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 570 | { |
| 571 | struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc); |
| 572 | struct mdp4_kms *mdp4_kms = get_kms(crtc); |
| 573 | uint32_t intf_sel; |
| 574 | |
| 575 | intf_sel = mdp4_read(mdp4_kms, REG_MDP4_DISP_INTF_SEL); |
| 576 | |
| 577 | switch (mdp4_crtc->dma) { |
| 578 | case DMA_P: |
| 579 | intf_sel &= ~MDP4_DISP_INTF_SEL_PRIM__MASK; |
| 580 | intf_sel |= MDP4_DISP_INTF_SEL_PRIM(intf); |
| 581 | break; |
| 582 | case DMA_S: |
| 583 | intf_sel &= ~MDP4_DISP_INTF_SEL_SEC__MASK; |
| 584 | intf_sel |= MDP4_DISP_INTF_SEL_SEC(intf); |
| 585 | break; |
| 586 | case DMA_E: |
| 587 | intf_sel &= ~MDP4_DISP_INTF_SEL_EXT__MASK; |
| 588 | intf_sel |= MDP4_DISP_INTF_SEL_EXT(intf); |
| 589 | break; |
| 590 | } |
| 591 | |
| 592 | if (intf == INTF_DSI_VIDEO) { |
| 593 | intf_sel &= ~MDP4_DISP_INTF_SEL_DSI_CMD; |
| 594 | intf_sel |= MDP4_DISP_INTF_SEL_DSI_VIDEO; |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 595 | } else if (intf == INTF_DSI_CMD) { |
| 596 | intf_sel &= ~MDP4_DISP_INTF_SEL_DSI_VIDEO; |
| 597 | intf_sel |= MDP4_DISP_INTF_SEL_DSI_CMD; |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 598 | } |
| 599 | |
Rob Clark | d65bd0e | 2014-08-06 07:43:12 -0400 | [diff] [blame] | 600 | mdp4_crtc->mixer = mixer; |
| 601 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 602 | blend_setup(crtc); |
| 603 | |
| 604 | DBG("%s: intf_sel=%08x", mdp4_crtc->name, intf_sel); |
| 605 | |
| 606 | mdp4_write(mdp4_kms, REG_MDP4_DISP_INTF_SEL, intf_sel); |
| 607 | } |
| 608 | |
| 609 | static const char *dma_names[] = { |
| 610 | "DMA_P", "DMA_S", "DMA_E", |
| 611 | }; |
| 612 | |
| 613 | /* initialize crtc */ |
| 614 | struct drm_crtc *mdp4_crtc_init(struct drm_device *dev, |
| 615 | struct drm_plane *plane, int id, int ovlp_id, |
| 616 | enum mdp4_dma dma_id) |
| 617 | { |
| 618 | struct drm_crtc *crtc = NULL; |
| 619 | struct mdp4_crtc *mdp4_crtc; |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 620 | |
| 621 | mdp4_crtc = kzalloc(sizeof(*mdp4_crtc), GFP_KERNEL); |
Boris BREZILLON | d7f8db5 | 2014-11-14 19:30:30 +0100 | [diff] [blame] | 622 | if (!mdp4_crtc) |
| 623 | return ERR_PTR(-ENOMEM); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 624 | |
| 625 | crtc = &mdp4_crtc->base; |
| 626 | |
Rob Clark | b69720c | 2013-12-13 10:41:07 -0500 | [diff] [blame] | 627 | mdp4_crtc->id = id; |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 628 | |
| 629 | mdp4_crtc->ovlp = ovlp_id; |
| 630 | mdp4_crtc->dma = dma_id; |
| 631 | |
| 632 | mdp4_crtc->vblank.irqmask = dma2irq(mdp4_crtc->dma); |
| 633 | mdp4_crtc->vblank.irq = mdp4_crtc_vblank_irq; |
| 634 | |
| 635 | mdp4_crtc->err.irqmask = dma2err(mdp4_crtc->dma); |
| 636 | mdp4_crtc->err.irq = mdp4_crtc_err_irq; |
| 637 | |
| 638 | snprintf(mdp4_crtc->name, sizeof(mdp4_crtc->name), "%s:%d", |
| 639 | dma_names[dma_id], ovlp_id); |
| 640 | |
| 641 | spin_lock_init(&mdp4_crtc->cursor.lock); |
| 642 | |
Boris BREZILLON | d7f8db5 | 2014-11-14 19:30:30 +0100 | [diff] [blame] | 643 | drm_flip_work_init(&mdp4_crtc->unref_cursor_work, |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 644 | "unref cursor", unref_cursor_worker); |
| 645 | |
Matt Roper | 2d82d18 | 2014-04-01 15:22:39 -0700 | [diff] [blame] | 646 | drm_crtc_init_with_planes(dev, crtc, plane, NULL, &mdp4_crtc_funcs); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 647 | drm_crtc_helper_add(crtc, &mdp4_crtc_helper_funcs); |
Rob Clark | bb6c018 | 2014-11-07 13:20:50 -0500 | [diff] [blame] | 648 | plane->crtc = crtc; |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 649 | |
Rob Clark | 466c268 | 2014-11-07 13:04:51 -0500 | [diff] [blame] | 650 | mdp4_plane_install_properties(plane, &crtc->base); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 651 | |
| 652 | return crtc; |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 653 | } |