Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2014 IBM Corp. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or |
| 5 | * modify it under the terms of the GNU General Public License |
| 6 | * as published by the Free Software Foundation; either version |
| 7 | * 2 of the License, or (at your option) any later version. |
| 8 | */ |
| 9 | |
| 10 | #include <linux/spinlock.h> |
| 11 | #include <linux/sched.h> |
| 12 | #include <linux/slab.h> |
| 13 | #include <linux/sched.h> |
| 14 | #include <linux/mutex.h> |
| 15 | #include <linux/mm.h> |
| 16 | #include <linux/uaccess.h> |
| 17 | #include <asm/synch.h> |
Michael Neuling | ec249dd | 2015-05-27 16:07:16 +1000 | [diff] [blame] | 18 | #include <misc/cxl-base.h> |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 19 | |
| 20 | #include "cxl.h" |
Ian Munsie | 9bcf28c | 2015-01-09 20:34:36 +1100 | [diff] [blame] | 21 | #include "trace.h" |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 22 | |
| 23 | static int afu_control(struct cxl_afu *afu, u64 command, |
| 24 | u64 result, u64 mask, bool enabled) |
| 25 | { |
| 26 | u64 AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An); |
| 27 | unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT); |
Ian Munsie | 9bcf28c | 2015-01-09 20:34:36 +1100 | [diff] [blame] | 28 | int rc = 0; |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 29 | |
| 30 | spin_lock(&afu->afu_cntl_lock); |
| 31 | pr_devel("AFU command starting: %llx\n", command); |
| 32 | |
Ian Munsie | 9bcf28c | 2015-01-09 20:34:36 +1100 | [diff] [blame] | 33 | trace_cxl_afu_ctrl(afu, command); |
| 34 | |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 35 | cxl_p2n_write(afu, CXL_AFU_Cntl_An, AFU_Cntl | command); |
| 36 | |
| 37 | AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An); |
| 38 | while ((AFU_Cntl & mask) != result) { |
| 39 | if (time_after_eq(jiffies, timeout)) { |
| 40 | dev_warn(&afu->dev, "WARNING: AFU control timed out!\n"); |
Ian Munsie | 9bcf28c | 2015-01-09 20:34:36 +1100 | [diff] [blame] | 41 | rc = -EBUSY; |
| 42 | goto out; |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 43 | } |
Daniel Axtens | 0b3f9c7 | 2015-08-14 17:41:18 +1000 | [diff] [blame] | 44 | |
| 45 | if (!cxl_adapter_link_ok(afu->adapter)) { |
| 46 | afu->enabled = enabled; |
| 47 | rc = -EIO; |
| 48 | goto out; |
| 49 | } |
| 50 | |
Rasmus Villemoes | de36953 | 2015-06-11 13:27:52 +0200 | [diff] [blame] | 51 | pr_devel_ratelimited("AFU control... (0x%016llx)\n", |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 52 | AFU_Cntl | command); |
| 53 | cpu_relax(); |
| 54 | AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An); |
| 55 | }; |
| 56 | pr_devel("AFU command complete: %llx\n", command); |
| 57 | afu->enabled = enabled; |
Ian Munsie | 9bcf28c | 2015-01-09 20:34:36 +1100 | [diff] [blame] | 58 | out: |
| 59 | trace_cxl_afu_ctrl_done(afu, command, rc); |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 60 | spin_unlock(&afu->afu_cntl_lock); |
| 61 | |
Ian Munsie | 9bcf28c | 2015-01-09 20:34:36 +1100 | [diff] [blame] | 62 | return rc; |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 63 | } |
| 64 | |
| 65 | static int afu_enable(struct cxl_afu *afu) |
| 66 | { |
| 67 | pr_devel("AFU enable request\n"); |
| 68 | |
| 69 | return afu_control(afu, CXL_AFU_Cntl_An_E, |
| 70 | CXL_AFU_Cntl_An_ES_Enabled, |
| 71 | CXL_AFU_Cntl_An_ES_MASK, true); |
| 72 | } |
| 73 | |
| 74 | int cxl_afu_disable(struct cxl_afu *afu) |
| 75 | { |
| 76 | pr_devel("AFU disable request\n"); |
| 77 | |
| 78 | return afu_control(afu, 0, CXL_AFU_Cntl_An_ES_Disabled, |
| 79 | CXL_AFU_Cntl_An_ES_MASK, false); |
| 80 | } |
| 81 | |
| 82 | /* This will disable as well as reset */ |
Michael Neuling | b12994f | 2015-05-27 16:07:09 +1000 | [diff] [blame] | 83 | int __cxl_afu_reset(struct cxl_afu *afu) |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 84 | { |
| 85 | pr_devel("AFU reset request\n"); |
| 86 | |
| 87 | return afu_control(afu, CXL_AFU_Cntl_An_RA, |
| 88 | CXL_AFU_Cntl_An_RS_Complete | CXL_AFU_Cntl_An_ES_Disabled, |
| 89 | CXL_AFU_Cntl_An_RS_MASK | CXL_AFU_Cntl_An_ES_MASK, |
| 90 | false); |
| 91 | } |
| 92 | |
Michael Neuling | 1a1a94b | 2015-05-27 16:07:10 +1000 | [diff] [blame] | 93 | int cxl_afu_check_and_enable(struct cxl_afu *afu) |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 94 | { |
Daniel Axtens | 0b3f9c7 | 2015-08-14 17:41:18 +1000 | [diff] [blame] | 95 | if (!cxl_adapter_link_ok(afu->adapter)) { |
| 96 | WARN(1, "Refusing to enable afu while link down!\n"); |
| 97 | return -EIO; |
| 98 | } |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 99 | if (afu->enabled) |
| 100 | return 0; |
| 101 | return afu_enable(afu); |
| 102 | } |
| 103 | |
| 104 | int cxl_psl_purge(struct cxl_afu *afu) |
| 105 | { |
| 106 | u64 PSL_CNTL = cxl_p1n_read(afu, CXL_PSL_SCNTL_An); |
| 107 | u64 AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An); |
| 108 | u64 dsisr, dar; |
| 109 | u64 start, end; |
| 110 | unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT); |
Ian Munsie | 9bcf28c | 2015-01-09 20:34:36 +1100 | [diff] [blame] | 111 | int rc = 0; |
| 112 | |
| 113 | trace_cxl_psl_ctrl(afu, CXL_PSL_SCNTL_An_Pc); |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 114 | |
| 115 | pr_devel("PSL purge request\n"); |
| 116 | |
Daniel Axtens | 0b3f9c7 | 2015-08-14 17:41:18 +1000 | [diff] [blame] | 117 | if (!cxl_adapter_link_ok(afu->adapter)) { |
| 118 | dev_warn(&afu->dev, "PSL Purge called with link down, ignoring\n"); |
| 119 | rc = -EIO; |
| 120 | goto out; |
| 121 | } |
| 122 | |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 123 | if ((AFU_Cntl & CXL_AFU_Cntl_An_ES_MASK) != CXL_AFU_Cntl_An_ES_Disabled) { |
| 124 | WARN(1, "psl_purge request while AFU not disabled!\n"); |
| 125 | cxl_afu_disable(afu); |
| 126 | } |
| 127 | |
| 128 | cxl_p1n_write(afu, CXL_PSL_SCNTL_An, |
| 129 | PSL_CNTL | CXL_PSL_SCNTL_An_Pc); |
| 130 | start = local_clock(); |
| 131 | PSL_CNTL = cxl_p1n_read(afu, CXL_PSL_SCNTL_An); |
| 132 | while ((PSL_CNTL & CXL_PSL_SCNTL_An_Ps_MASK) |
| 133 | == CXL_PSL_SCNTL_An_Ps_Pending) { |
| 134 | if (time_after_eq(jiffies, timeout)) { |
| 135 | dev_warn(&afu->dev, "WARNING: PSL Purge timed out!\n"); |
Ian Munsie | 9bcf28c | 2015-01-09 20:34:36 +1100 | [diff] [blame] | 136 | rc = -EBUSY; |
| 137 | goto out; |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 138 | } |
Daniel Axtens | 0b3f9c7 | 2015-08-14 17:41:18 +1000 | [diff] [blame] | 139 | if (!cxl_adapter_link_ok(afu->adapter)) { |
| 140 | rc = -EIO; |
| 141 | goto out; |
| 142 | } |
| 143 | |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 144 | dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An); |
Rasmus Villemoes | de36953 | 2015-06-11 13:27:52 +0200 | [diff] [blame] | 145 | pr_devel_ratelimited("PSL purging... PSL_CNTL: 0x%016llx PSL_DSISR: 0x%016llx\n", PSL_CNTL, dsisr); |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 146 | if (dsisr & CXL_PSL_DSISR_TRANS) { |
| 147 | dar = cxl_p2n_read(afu, CXL_PSL_DAR_An); |
Rasmus Villemoes | de36953 | 2015-06-11 13:27:52 +0200 | [diff] [blame] | 148 | dev_notice(&afu->dev, "PSL purge terminating pending translation, DSISR: 0x%016llx, DAR: 0x%016llx\n", dsisr, dar); |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 149 | cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE); |
| 150 | } else if (dsisr) { |
Rasmus Villemoes | de36953 | 2015-06-11 13:27:52 +0200 | [diff] [blame] | 151 | dev_notice(&afu->dev, "PSL purge acknowledging pending non-translation fault, DSISR: 0x%016llx\n", dsisr); |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 152 | cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A); |
| 153 | } else { |
| 154 | cpu_relax(); |
| 155 | } |
| 156 | PSL_CNTL = cxl_p1n_read(afu, CXL_PSL_SCNTL_An); |
| 157 | }; |
| 158 | end = local_clock(); |
| 159 | pr_devel("PSL purged in %lld ns\n", end - start); |
| 160 | |
| 161 | cxl_p1n_write(afu, CXL_PSL_SCNTL_An, |
| 162 | PSL_CNTL & ~CXL_PSL_SCNTL_An_Pc); |
Ian Munsie | 9bcf28c | 2015-01-09 20:34:36 +1100 | [diff] [blame] | 163 | out: |
| 164 | trace_cxl_psl_ctrl_done(afu, CXL_PSL_SCNTL_An_Pc, rc); |
| 165 | return rc; |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 166 | } |
| 167 | |
| 168 | static int spa_max_procs(int spa_size) |
| 169 | { |
| 170 | /* |
| 171 | * From the CAIA: |
| 172 | * end_of_SPA_area = SPA_Base + ((n+4) * 128) + (( ((n*8) + 127) >> 7) * 128) + 255 |
| 173 | * Most of that junk is really just an overly-complicated way of saying |
| 174 | * the last 256 bytes are __aligned(128), so it's really: |
| 175 | * end_of_SPA_area = end_of_PSL_queue_area + __aligned(128) 255 |
| 176 | * and |
| 177 | * end_of_PSL_queue_area = SPA_Base + ((n+4) * 128) + (n*8) - 1 |
| 178 | * so |
| 179 | * sizeof(SPA) = ((n+4) * 128) + (n*8) + __aligned(128) 256 |
| 180 | * Ignore the alignment (which is safe in this case as long as we are |
| 181 | * careful with our rounding) and solve for n: |
| 182 | */ |
| 183 | return ((spa_size / 8) - 96) / 17; |
| 184 | } |
| 185 | |
Daniel Axtens | 05155772 | 2015-08-14 17:41:19 +1000 | [diff] [blame] | 186 | int cxl_alloc_spa(struct cxl_afu *afu) |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 187 | { |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 188 | /* Work out how many pages to allocate */ |
| 189 | afu->spa_order = 0; |
| 190 | do { |
| 191 | afu->spa_order++; |
| 192 | afu->spa_size = (1 << afu->spa_order) * PAGE_SIZE; |
| 193 | afu->spa_max_procs = spa_max_procs(afu->spa_size); |
| 194 | } while (afu->spa_max_procs < afu->num_procs); |
| 195 | |
| 196 | WARN_ON(afu->spa_size > 0x100000); /* Max size supported by the hardware */ |
| 197 | |
| 198 | if (!(afu->spa = (struct cxl_process_element *) |
| 199 | __get_free_pages(GFP_KERNEL | __GFP_ZERO, afu->spa_order))) { |
| 200 | pr_err("cxl_alloc_spa: Unable to allocate scheduled process area\n"); |
| 201 | return -ENOMEM; |
| 202 | } |
| 203 | pr_devel("spa pages: %i afu->spa_max_procs: %i afu->num_procs: %i\n", |
| 204 | 1<<afu->spa_order, afu->spa_max_procs, afu->num_procs); |
| 205 | |
Daniel Axtens | 05155772 | 2015-08-14 17:41:19 +1000 | [diff] [blame] | 206 | return 0; |
| 207 | } |
| 208 | |
| 209 | static void attach_spa(struct cxl_afu *afu) |
| 210 | { |
| 211 | u64 spap; |
| 212 | |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 213 | afu->sw_command_status = (__be64 *)((char *)afu->spa + |
| 214 | ((afu->spa_max_procs + 3) * 128)); |
| 215 | |
| 216 | spap = virt_to_phys(afu->spa) & CXL_PSL_SPAP_Addr; |
| 217 | spap |= ((afu->spa_size >> (12 - CXL_PSL_SPAP_Size_Shift)) - 1) & CXL_PSL_SPAP_Size; |
| 218 | spap |= CXL_PSL_SPAP_V; |
| 219 | pr_devel("cxl: SPA allocated at 0x%p. Max processes: %i, sw_command_status: 0x%p CXL_PSL_SPAP_An=0x%016llx\n", afu->spa, afu->spa_max_procs, afu->sw_command_status, spap); |
| 220 | cxl_p1n_write(afu, CXL_PSL_SPAP_An, spap); |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 221 | } |
| 222 | |
Daniel Axtens | 05155772 | 2015-08-14 17:41:19 +1000 | [diff] [blame] | 223 | static inline void detach_spa(struct cxl_afu *afu) |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 224 | { |
Ian Munsie | db7933f | 2014-12-08 19:18:00 +1100 | [diff] [blame] | 225 | cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0); |
Daniel Axtens | 05155772 | 2015-08-14 17:41:19 +1000 | [diff] [blame] | 226 | } |
| 227 | |
| 228 | void cxl_release_spa(struct cxl_afu *afu) |
| 229 | { |
| 230 | if (afu->spa) { |
| 231 | free_pages((unsigned long) afu->spa, afu->spa_order); |
| 232 | afu->spa = NULL; |
| 233 | } |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 234 | } |
| 235 | |
| 236 | int cxl_tlb_slb_invalidate(struct cxl *adapter) |
| 237 | { |
| 238 | unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT); |
| 239 | |
| 240 | pr_devel("CXL adapter wide TLBIA & SLBIA\n"); |
| 241 | |
| 242 | cxl_p1_write(adapter, CXL_PSL_AFUSEL, CXL_PSL_AFUSEL_A); |
| 243 | |
| 244 | cxl_p1_write(adapter, CXL_PSL_TLBIA, CXL_TLB_SLB_IQ_ALL); |
| 245 | while (cxl_p1_read(adapter, CXL_PSL_TLBIA) & CXL_TLB_SLB_P) { |
| 246 | if (time_after_eq(jiffies, timeout)) { |
| 247 | dev_warn(&adapter->dev, "WARNING: CXL adapter wide TLBIA timed out!\n"); |
| 248 | return -EBUSY; |
| 249 | } |
Daniel Axtens | 0b3f9c7 | 2015-08-14 17:41:18 +1000 | [diff] [blame] | 250 | if (!cxl_adapter_link_ok(adapter)) |
| 251 | return -EIO; |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 252 | cpu_relax(); |
| 253 | } |
| 254 | |
| 255 | cxl_p1_write(adapter, CXL_PSL_SLBIA, CXL_TLB_SLB_IQ_ALL); |
| 256 | while (cxl_p1_read(adapter, CXL_PSL_SLBIA) & CXL_TLB_SLB_P) { |
| 257 | if (time_after_eq(jiffies, timeout)) { |
| 258 | dev_warn(&adapter->dev, "WARNING: CXL adapter wide SLBIA timed out!\n"); |
| 259 | return -EBUSY; |
| 260 | } |
Daniel Axtens | 0b3f9c7 | 2015-08-14 17:41:18 +1000 | [diff] [blame] | 261 | if (!cxl_adapter_link_ok(adapter)) |
| 262 | return -EIO; |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 263 | cpu_relax(); |
| 264 | } |
| 265 | return 0; |
| 266 | } |
| 267 | |
| 268 | int cxl_afu_slbia(struct cxl_afu *afu) |
| 269 | { |
| 270 | unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT); |
| 271 | |
| 272 | pr_devel("cxl_afu_slbia issuing SLBIA command\n"); |
| 273 | cxl_p2n_write(afu, CXL_SLBIA_An, CXL_TLB_SLB_IQ_ALL); |
| 274 | while (cxl_p2n_read(afu, CXL_SLBIA_An) & CXL_TLB_SLB_P) { |
| 275 | if (time_after_eq(jiffies, timeout)) { |
| 276 | dev_warn(&afu->dev, "WARNING: CXL AFU SLBIA timed out!\n"); |
| 277 | return -EBUSY; |
| 278 | } |
Daniel Axtens | 0b3f9c7 | 2015-08-14 17:41:18 +1000 | [diff] [blame] | 279 | /* If the adapter has gone down, we can assume that we |
| 280 | * will PERST it and that will invalidate everything. |
| 281 | */ |
| 282 | if (!cxl_adapter_link_ok(afu->adapter)) |
| 283 | return -EIO; |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 284 | cpu_relax(); |
| 285 | } |
| 286 | return 0; |
| 287 | } |
| 288 | |
| 289 | static int cxl_write_sstp(struct cxl_afu *afu, u64 sstp0, u64 sstp1) |
| 290 | { |
| 291 | int rc; |
| 292 | |
| 293 | /* 1. Disable SSTP by writing 0 to SSTP1[V] */ |
| 294 | cxl_p2n_write(afu, CXL_SSTP1_An, 0); |
| 295 | |
| 296 | /* 2. Invalidate all SLB entries */ |
| 297 | if ((rc = cxl_afu_slbia(afu))) |
| 298 | return rc; |
| 299 | |
| 300 | /* 3. Set SSTP0_An */ |
| 301 | cxl_p2n_write(afu, CXL_SSTP0_An, sstp0); |
| 302 | |
| 303 | /* 4. Set SSTP1_An */ |
| 304 | cxl_p2n_write(afu, CXL_SSTP1_An, sstp1); |
| 305 | |
| 306 | return 0; |
| 307 | } |
| 308 | |
| 309 | /* Using per slice version may improve performance here. (ie. SLBIA_An) */ |
| 310 | static void slb_invalid(struct cxl_context *ctx) |
| 311 | { |
| 312 | struct cxl *adapter = ctx->afu->adapter; |
| 313 | u64 slbia; |
| 314 | |
| 315 | WARN_ON(!mutex_is_locked(&ctx->afu->spa_mutex)); |
| 316 | |
| 317 | cxl_p1_write(adapter, CXL_PSL_LBISEL, |
| 318 | ((u64)be32_to_cpu(ctx->elem->common.pid) << 32) | |
| 319 | be32_to_cpu(ctx->elem->lpid)); |
| 320 | cxl_p1_write(adapter, CXL_PSL_SLBIA, CXL_TLB_SLB_IQ_LPIDPID); |
| 321 | |
| 322 | while (1) { |
Daniel Axtens | 0b3f9c7 | 2015-08-14 17:41:18 +1000 | [diff] [blame] | 323 | if (!cxl_adapter_link_ok(adapter)) |
| 324 | break; |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 325 | slbia = cxl_p1_read(adapter, CXL_PSL_SLBIA); |
| 326 | if (!(slbia & CXL_TLB_SLB_P)) |
| 327 | break; |
| 328 | cpu_relax(); |
| 329 | } |
| 330 | } |
| 331 | |
| 332 | static int do_process_element_cmd(struct cxl_context *ctx, |
| 333 | u64 cmd, u64 pe_state) |
| 334 | { |
| 335 | u64 state; |
Ian Munsie | a98e6e9 | 2014-12-08 19:17:56 +1100 | [diff] [blame] | 336 | unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT); |
Ian Munsie | 9bcf28c | 2015-01-09 20:34:36 +1100 | [diff] [blame] | 337 | int rc = 0; |
| 338 | |
| 339 | trace_cxl_llcmd(ctx, cmd); |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 340 | |
| 341 | WARN_ON(!ctx->afu->enabled); |
| 342 | |
| 343 | ctx->elem->software_state = cpu_to_be32(pe_state); |
| 344 | smp_wmb(); |
| 345 | *(ctx->afu->sw_command_status) = cpu_to_be64(cmd | 0 | ctx->pe); |
| 346 | smp_mb(); |
| 347 | cxl_p1n_write(ctx->afu, CXL_PSL_LLCMD_An, cmd | ctx->pe); |
| 348 | while (1) { |
Ian Munsie | a98e6e9 | 2014-12-08 19:17:56 +1100 | [diff] [blame] | 349 | if (time_after_eq(jiffies, timeout)) { |
| 350 | dev_warn(&ctx->afu->dev, "WARNING: Process Element Command timed out!\n"); |
Ian Munsie | 9bcf28c | 2015-01-09 20:34:36 +1100 | [diff] [blame] | 351 | rc = -EBUSY; |
| 352 | goto out; |
Ian Munsie | a98e6e9 | 2014-12-08 19:17:56 +1100 | [diff] [blame] | 353 | } |
Daniel Axtens | 0b3f9c7 | 2015-08-14 17:41:18 +1000 | [diff] [blame] | 354 | if (!cxl_adapter_link_ok(ctx->afu->adapter)) { |
| 355 | dev_warn(&ctx->afu->dev, "WARNING: Device link down, aborting Process Element Command!\n"); |
| 356 | rc = -EIO; |
| 357 | goto out; |
| 358 | } |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 359 | state = be64_to_cpup(ctx->afu->sw_command_status); |
| 360 | if (state == ~0ULL) { |
| 361 | pr_err("cxl: Error adding process element to AFU\n"); |
Ian Munsie | 9bcf28c | 2015-01-09 20:34:36 +1100 | [diff] [blame] | 362 | rc = -1; |
| 363 | goto out; |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 364 | } |
| 365 | if ((state & (CXL_SPA_SW_CMD_MASK | CXL_SPA_SW_STATE_MASK | CXL_SPA_SW_LINK_MASK)) == |
| 366 | (cmd | (cmd >> 16) | ctx->pe)) |
| 367 | break; |
| 368 | /* |
| 369 | * The command won't finish in the PSL if there are |
| 370 | * outstanding DSIs. Hence we need to yield here in |
| 371 | * case there are outstanding DSIs that we need to |
| 372 | * service. Tuning possiblity: we could wait for a |
| 373 | * while before sched |
| 374 | */ |
| 375 | schedule(); |
| 376 | |
| 377 | } |
Ian Munsie | 9bcf28c | 2015-01-09 20:34:36 +1100 | [diff] [blame] | 378 | out: |
| 379 | trace_cxl_llcmd_done(ctx, cmd, rc); |
| 380 | return rc; |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 381 | } |
| 382 | |
| 383 | static int add_process_element(struct cxl_context *ctx) |
| 384 | { |
| 385 | int rc = 0; |
| 386 | |
| 387 | mutex_lock(&ctx->afu->spa_mutex); |
| 388 | pr_devel("%s Adding pe: %i started\n", __func__, ctx->pe); |
| 389 | if (!(rc = do_process_element_cmd(ctx, CXL_SPA_SW_CMD_ADD, CXL_PE_SOFTWARE_STATE_V))) |
| 390 | ctx->pe_inserted = true; |
| 391 | pr_devel("%s Adding pe: %i finished\n", __func__, ctx->pe); |
| 392 | mutex_unlock(&ctx->afu->spa_mutex); |
| 393 | return rc; |
| 394 | } |
| 395 | |
| 396 | static int terminate_process_element(struct cxl_context *ctx) |
| 397 | { |
| 398 | int rc = 0; |
| 399 | |
| 400 | /* fast path terminate if it's already invalid */ |
| 401 | if (!(ctx->elem->software_state & cpu_to_be32(CXL_PE_SOFTWARE_STATE_V))) |
| 402 | return rc; |
| 403 | |
| 404 | mutex_lock(&ctx->afu->spa_mutex); |
| 405 | pr_devel("%s Terminate pe: %i started\n", __func__, ctx->pe); |
Daniel Axtens | 0b3f9c7 | 2015-08-14 17:41:18 +1000 | [diff] [blame] | 406 | /* We could be asked to terminate when the hw is down. That |
| 407 | * should always succeed: it's not running if the hw has gone |
| 408 | * away and is being reset. |
| 409 | */ |
| 410 | if (cxl_adapter_link_ok(ctx->afu->adapter)) |
| 411 | rc = do_process_element_cmd(ctx, CXL_SPA_SW_CMD_TERMINATE, |
| 412 | CXL_PE_SOFTWARE_STATE_V | CXL_PE_SOFTWARE_STATE_T); |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 413 | ctx->elem->software_state = 0; /* Remove Valid bit */ |
| 414 | pr_devel("%s Terminate pe: %i finished\n", __func__, ctx->pe); |
| 415 | mutex_unlock(&ctx->afu->spa_mutex); |
| 416 | return rc; |
| 417 | } |
| 418 | |
| 419 | static int remove_process_element(struct cxl_context *ctx) |
| 420 | { |
| 421 | int rc = 0; |
| 422 | |
| 423 | mutex_lock(&ctx->afu->spa_mutex); |
| 424 | pr_devel("%s Remove pe: %i started\n", __func__, ctx->pe); |
Daniel Axtens | 0b3f9c7 | 2015-08-14 17:41:18 +1000 | [diff] [blame] | 425 | |
| 426 | /* We could be asked to remove when the hw is down. Again, if |
| 427 | * the hw is down, the PE is gone, so we succeed. |
| 428 | */ |
| 429 | if (cxl_adapter_link_ok(ctx->afu->adapter)) |
| 430 | rc = do_process_element_cmd(ctx, CXL_SPA_SW_CMD_REMOVE, 0); |
| 431 | |
| 432 | if (!rc) |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 433 | ctx->pe_inserted = false; |
| 434 | slb_invalid(ctx); |
| 435 | pr_devel("%s Remove pe: %i finished\n", __func__, ctx->pe); |
| 436 | mutex_unlock(&ctx->afu->spa_mutex); |
| 437 | |
| 438 | return rc; |
| 439 | } |
| 440 | |
| 441 | |
Michael Neuling | 1a1a94b | 2015-05-27 16:07:10 +1000 | [diff] [blame] | 442 | void cxl_assign_psn_space(struct cxl_context *ctx) |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 443 | { |
| 444 | if (!ctx->afu->pp_size || ctx->master) { |
| 445 | ctx->psn_phys = ctx->afu->psn_phys; |
| 446 | ctx->psn_size = ctx->afu->adapter->ps_size; |
| 447 | } else { |
| 448 | ctx->psn_phys = ctx->afu->psn_phys + |
| 449 | (ctx->afu->pp_offset + ctx->afu->pp_size * ctx->pe); |
| 450 | ctx->psn_size = ctx->afu->pp_size; |
| 451 | } |
| 452 | } |
| 453 | |
| 454 | static int activate_afu_directed(struct cxl_afu *afu) |
| 455 | { |
| 456 | int rc; |
| 457 | |
| 458 | dev_info(&afu->dev, "Activating AFU directed mode\n"); |
| 459 | |
Christophe Lombard | 4108efb | 2015-10-07 16:07:40 +1100 | [diff] [blame] | 460 | afu->num_procs = afu->max_procs_virtualised; |
Daniel Axtens | 05155772 | 2015-08-14 17:41:19 +1000 | [diff] [blame] | 461 | if (afu->spa == NULL) { |
| 462 | if (cxl_alloc_spa(afu)) |
| 463 | return -ENOMEM; |
| 464 | } |
| 465 | attach_spa(afu); |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 466 | |
| 467 | cxl_p1n_write(afu, CXL_PSL_SCNTL_An, CXL_PSL_SCNTL_An_PM_AFU); |
| 468 | cxl_p1n_write(afu, CXL_PSL_AMOR_An, 0xFFFFFFFFFFFFFFFFULL); |
| 469 | cxl_p1n_write(afu, CXL_PSL_ID_An, CXL_PSL_ID_An_F | CXL_PSL_ID_An_L); |
| 470 | |
| 471 | afu->current_mode = CXL_MODE_DIRECTED; |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 472 | |
| 473 | if ((rc = cxl_chardev_m_afu_add(afu))) |
| 474 | return rc; |
| 475 | |
| 476 | if ((rc = cxl_sysfs_afu_m_add(afu))) |
| 477 | goto err; |
| 478 | |
| 479 | if ((rc = cxl_chardev_s_afu_add(afu))) |
| 480 | goto err1; |
| 481 | |
| 482 | return 0; |
| 483 | err1: |
| 484 | cxl_sysfs_afu_m_remove(afu); |
| 485 | err: |
| 486 | cxl_chardev_afu_remove(afu); |
| 487 | return rc; |
| 488 | } |
| 489 | |
| 490 | #ifdef CONFIG_CPU_LITTLE_ENDIAN |
| 491 | #define set_endian(sr) ((sr) |= CXL_PSL_SR_An_LE) |
| 492 | #else |
| 493 | #define set_endian(sr) ((sr) &= ~(CXL_PSL_SR_An_LE)) |
| 494 | #endif |
| 495 | |
Michael Neuling | 2f66352 | 2015-05-27 16:07:13 +1000 | [diff] [blame] | 496 | static u64 calculate_sr(struct cxl_context *ctx) |
| 497 | { |
| 498 | u64 sr = 0; |
| 499 | |
Frederic Barrat | e606e03 | 2015-12-07 14:34:40 +0100 | [diff] [blame] | 500 | set_endian(sr); |
Michael Neuling | 2f66352 | 2015-05-27 16:07:13 +1000 | [diff] [blame] | 501 | if (ctx->master) |
| 502 | sr |= CXL_PSL_SR_An_MP; |
| 503 | if (mfspr(SPRN_LPCR) & LPCR_TC) |
| 504 | sr |= CXL_PSL_SR_An_TC; |
| 505 | if (ctx->kernel) { |
| 506 | sr |= CXL_PSL_SR_An_R | (mfmsr() & MSR_SF); |
| 507 | sr |= CXL_PSL_SR_An_HV; |
| 508 | } else { |
| 509 | sr |= CXL_PSL_SR_An_PR | CXL_PSL_SR_An_R; |
Michael Neuling | 2f66352 | 2015-05-27 16:07:13 +1000 | [diff] [blame] | 510 | sr &= ~(CXL_PSL_SR_An_HV); |
| 511 | if (!test_tsk_thread_flag(current, TIF_32BIT)) |
| 512 | sr |= CXL_PSL_SR_An_SF; |
| 513 | } |
| 514 | return sr; |
| 515 | } |
| 516 | |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 517 | static int attach_afu_directed(struct cxl_context *ctx, u64 wed, u64 amr) |
| 518 | { |
Michael Neuling | 2f66352 | 2015-05-27 16:07:13 +1000 | [diff] [blame] | 519 | u32 pid; |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 520 | int r, result; |
| 521 | |
Michael Neuling | 1a1a94b | 2015-05-27 16:07:10 +1000 | [diff] [blame] | 522 | cxl_assign_psn_space(ctx); |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 523 | |
| 524 | ctx->elem->ctxtime = 0; /* disable */ |
| 525 | ctx->elem->lpid = cpu_to_be32(mfspr(SPRN_LPID)); |
| 526 | ctx->elem->haurp = 0; /* disable */ |
| 527 | ctx->elem->sdr = cpu_to_be64(mfspr(SPRN_SDR1)); |
| 528 | |
Michael Neuling | 2f66352 | 2015-05-27 16:07:13 +1000 | [diff] [blame] | 529 | pid = current->pid; |
| 530 | if (ctx->kernel) |
| 531 | pid = 0; |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 532 | ctx->elem->common.tid = 0; |
Michael Neuling | 2f66352 | 2015-05-27 16:07:13 +1000 | [diff] [blame] | 533 | ctx->elem->common.pid = cpu_to_be32(pid); |
| 534 | |
| 535 | ctx->elem->sr = cpu_to_be64(calculate_sr(ctx)); |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 536 | |
| 537 | ctx->elem->common.csrp = 0; /* disable */ |
| 538 | ctx->elem->common.aurp0 = 0; /* disable */ |
| 539 | ctx->elem->common.aurp1 = 0; /* disable */ |
| 540 | |
| 541 | cxl_prefault(ctx, wed); |
| 542 | |
| 543 | ctx->elem->common.sstp0 = cpu_to_be64(ctx->sstp0); |
| 544 | ctx->elem->common.sstp1 = cpu_to_be64(ctx->sstp1); |
| 545 | |
| 546 | for (r = 0; r < CXL_IRQ_RANGES; r++) { |
| 547 | ctx->elem->ivte_offsets[r] = cpu_to_be16(ctx->irqs.offset[r]); |
| 548 | ctx->elem->ivte_ranges[r] = cpu_to_be16(ctx->irqs.range[r]); |
| 549 | } |
| 550 | |
| 551 | ctx->elem->common.amr = cpu_to_be64(amr); |
| 552 | ctx->elem->common.wed = cpu_to_be64(wed); |
| 553 | |
| 554 | /* first guy needs to enable */ |
Michael Neuling | 1a1a94b | 2015-05-27 16:07:10 +1000 | [diff] [blame] | 555 | if ((result = cxl_afu_check_and_enable(ctx->afu))) |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 556 | return result; |
| 557 | |
Daniel Axtens | 368857c | 2015-07-29 14:07:22 +1000 | [diff] [blame] | 558 | return add_process_element(ctx); |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 559 | } |
| 560 | |
| 561 | static int deactivate_afu_directed(struct cxl_afu *afu) |
| 562 | { |
| 563 | dev_info(&afu->dev, "Deactivating AFU directed mode\n"); |
| 564 | |
| 565 | afu->current_mode = 0; |
| 566 | afu->num_procs = 0; |
| 567 | |
| 568 | cxl_sysfs_afu_m_remove(afu); |
| 569 | cxl_chardev_afu_remove(afu); |
| 570 | |
Michael Neuling | b12994f | 2015-05-27 16:07:09 +1000 | [diff] [blame] | 571 | __cxl_afu_reset(afu); |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 572 | cxl_afu_disable(afu); |
| 573 | cxl_psl_purge(afu); |
| 574 | |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 575 | return 0; |
| 576 | } |
| 577 | |
| 578 | static int activate_dedicated_process(struct cxl_afu *afu) |
| 579 | { |
| 580 | dev_info(&afu->dev, "Activating dedicated process mode\n"); |
| 581 | |
| 582 | cxl_p1n_write(afu, CXL_PSL_SCNTL_An, CXL_PSL_SCNTL_An_PM_Process); |
| 583 | |
| 584 | cxl_p1n_write(afu, CXL_PSL_CtxTime_An, 0); /* disable */ |
| 585 | cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0); /* disable */ |
| 586 | cxl_p1n_write(afu, CXL_PSL_AMOR_An, 0xFFFFFFFFFFFFFFFFULL); |
| 587 | cxl_p1n_write(afu, CXL_PSL_LPID_An, mfspr(SPRN_LPID)); |
| 588 | cxl_p1n_write(afu, CXL_HAURP_An, 0); /* disable */ |
| 589 | cxl_p1n_write(afu, CXL_PSL_SDR_An, mfspr(SPRN_SDR1)); |
| 590 | |
| 591 | cxl_p2n_write(afu, CXL_CSRP_An, 0); /* disable */ |
| 592 | cxl_p2n_write(afu, CXL_AURP0_An, 0); /* disable */ |
| 593 | cxl_p2n_write(afu, CXL_AURP1_An, 0); /* disable */ |
| 594 | |
| 595 | afu->current_mode = CXL_MODE_DEDICATED; |
| 596 | afu->num_procs = 1; |
| 597 | |
| 598 | return cxl_chardev_d_afu_add(afu); |
| 599 | } |
| 600 | |
| 601 | static int attach_dedicated(struct cxl_context *ctx, u64 wed, u64 amr) |
| 602 | { |
| 603 | struct cxl_afu *afu = ctx->afu; |
Michael Neuling | 2f66352 | 2015-05-27 16:07:13 +1000 | [diff] [blame] | 604 | u64 pid; |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 605 | int rc; |
| 606 | |
Michael Neuling | 2f66352 | 2015-05-27 16:07:13 +1000 | [diff] [blame] | 607 | pid = (u64)current->pid << 32; |
| 608 | if (ctx->kernel) |
| 609 | pid = 0; |
| 610 | cxl_p2n_write(afu, CXL_PSL_PID_TID_An, pid); |
| 611 | |
| 612 | cxl_p1n_write(afu, CXL_PSL_SR_An, calculate_sr(ctx)); |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 613 | |
| 614 | if ((rc = cxl_write_sstp(afu, ctx->sstp0, ctx->sstp1))) |
| 615 | return rc; |
| 616 | |
| 617 | cxl_prefault(ctx, wed); |
| 618 | |
| 619 | cxl_p1n_write(afu, CXL_PSL_IVTE_Offset_An, |
| 620 | (((u64)ctx->irqs.offset[0] & 0xffff) << 48) | |
| 621 | (((u64)ctx->irqs.offset[1] & 0xffff) << 32) | |
| 622 | (((u64)ctx->irqs.offset[2] & 0xffff) << 16) | |
| 623 | ((u64)ctx->irqs.offset[3] & 0xffff)); |
| 624 | cxl_p1n_write(afu, CXL_PSL_IVTE_Limit_An, (u64) |
| 625 | (((u64)ctx->irqs.range[0] & 0xffff) << 48) | |
| 626 | (((u64)ctx->irqs.range[1] & 0xffff) << 32) | |
| 627 | (((u64)ctx->irqs.range[2] & 0xffff) << 16) | |
| 628 | ((u64)ctx->irqs.range[3] & 0xffff)); |
| 629 | |
| 630 | cxl_p2n_write(afu, CXL_PSL_AMR_An, amr); |
| 631 | |
| 632 | /* master only context for dedicated */ |
Michael Neuling | 1a1a94b | 2015-05-27 16:07:10 +1000 | [diff] [blame] | 633 | cxl_assign_psn_space(ctx); |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 634 | |
Michael Neuling | b12994f | 2015-05-27 16:07:09 +1000 | [diff] [blame] | 635 | if ((rc = __cxl_afu_reset(afu))) |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 636 | return rc; |
| 637 | |
| 638 | cxl_p2n_write(afu, CXL_PSL_WED_An, wed); |
| 639 | |
| 640 | return afu_enable(afu); |
| 641 | } |
| 642 | |
| 643 | static int deactivate_dedicated_process(struct cxl_afu *afu) |
| 644 | { |
| 645 | dev_info(&afu->dev, "Deactivating dedicated process mode\n"); |
| 646 | |
| 647 | afu->current_mode = 0; |
| 648 | afu->num_procs = 0; |
| 649 | |
| 650 | cxl_chardev_afu_remove(afu); |
| 651 | |
| 652 | return 0; |
| 653 | } |
| 654 | |
| 655 | int _cxl_afu_deactivate_mode(struct cxl_afu *afu, int mode) |
| 656 | { |
| 657 | if (mode == CXL_MODE_DIRECTED) |
| 658 | return deactivate_afu_directed(afu); |
| 659 | if (mode == CXL_MODE_DEDICATED) |
| 660 | return deactivate_dedicated_process(afu); |
| 661 | return 0; |
| 662 | } |
| 663 | |
| 664 | int cxl_afu_deactivate_mode(struct cxl_afu *afu) |
| 665 | { |
| 666 | return _cxl_afu_deactivate_mode(afu, afu->current_mode); |
| 667 | } |
| 668 | |
| 669 | int cxl_afu_activate_mode(struct cxl_afu *afu, int mode) |
| 670 | { |
| 671 | if (!mode) |
| 672 | return 0; |
| 673 | if (!(mode & afu->modes_supported)) |
| 674 | return -EINVAL; |
| 675 | |
Daniel Axtens | 0b3f9c7 | 2015-08-14 17:41:18 +1000 | [diff] [blame] | 676 | if (!cxl_adapter_link_ok(afu->adapter)) { |
| 677 | WARN(1, "Device link is down, refusing to activate!\n"); |
| 678 | return -EIO; |
| 679 | } |
| 680 | |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 681 | if (mode == CXL_MODE_DIRECTED) |
| 682 | return activate_afu_directed(afu); |
| 683 | if (mode == CXL_MODE_DEDICATED) |
| 684 | return activate_dedicated_process(afu); |
| 685 | |
| 686 | return -EINVAL; |
| 687 | } |
| 688 | |
| 689 | int cxl_attach_process(struct cxl_context *ctx, bool kernel, u64 wed, u64 amr) |
| 690 | { |
Daniel Axtens | 0b3f9c7 | 2015-08-14 17:41:18 +1000 | [diff] [blame] | 691 | if (!cxl_adapter_link_ok(ctx->afu->adapter)) { |
| 692 | WARN(1, "Device link is down, refusing to attach process!\n"); |
| 693 | return -EIO; |
| 694 | } |
| 695 | |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 696 | ctx->kernel = kernel; |
| 697 | if (ctx->afu->current_mode == CXL_MODE_DIRECTED) |
| 698 | return attach_afu_directed(ctx, wed, amr); |
| 699 | |
| 700 | if (ctx->afu->current_mode == CXL_MODE_DEDICATED) |
| 701 | return attach_dedicated(ctx, wed, amr); |
| 702 | |
| 703 | return -EINVAL; |
| 704 | } |
| 705 | |
| 706 | static inline int detach_process_native_dedicated(struct cxl_context *ctx) |
| 707 | { |
Michael Neuling | b12994f | 2015-05-27 16:07:09 +1000 | [diff] [blame] | 708 | __cxl_afu_reset(ctx->afu); |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 709 | cxl_afu_disable(ctx->afu); |
| 710 | cxl_psl_purge(ctx->afu); |
| 711 | return 0; |
| 712 | } |
| 713 | |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 714 | static inline int detach_process_native_afu_directed(struct cxl_context *ctx) |
| 715 | { |
| 716 | if (!ctx->pe_inserted) |
| 717 | return 0; |
| 718 | if (terminate_process_element(ctx)) |
| 719 | return -1; |
| 720 | if (remove_process_element(ctx)) |
| 721 | return -1; |
| 722 | |
| 723 | return 0; |
| 724 | } |
| 725 | |
| 726 | int cxl_detach_process(struct cxl_context *ctx) |
| 727 | { |
Ian Munsie | 9bcf28c | 2015-01-09 20:34:36 +1100 | [diff] [blame] | 728 | trace_cxl_detach(ctx); |
| 729 | |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 730 | if (ctx->afu->current_mode == CXL_MODE_DEDICATED) |
| 731 | return detach_process_native_dedicated(ctx); |
| 732 | |
| 733 | return detach_process_native_afu_directed(ctx); |
| 734 | } |
| 735 | |
Ian Munsie | bc78b05 | 2014-11-14 17:37:50 +1100 | [diff] [blame] | 736 | int cxl_get_irq(struct cxl_afu *afu, struct cxl_irq_info *info) |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 737 | { |
| 738 | u64 pidtid; |
| 739 | |
Daniel Axtens | 0b3f9c7 | 2015-08-14 17:41:18 +1000 | [diff] [blame] | 740 | /* If the adapter has gone away, we can't get any meaningful |
| 741 | * information. |
| 742 | */ |
| 743 | if (!cxl_adapter_link_ok(afu->adapter)) |
| 744 | return -EIO; |
| 745 | |
Ian Munsie | bc78b05 | 2014-11-14 17:37:50 +1100 | [diff] [blame] | 746 | info->dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An); |
| 747 | info->dar = cxl_p2n_read(afu, CXL_PSL_DAR_An); |
| 748 | info->dsr = cxl_p2n_read(afu, CXL_PSL_DSR_An); |
| 749 | pidtid = cxl_p2n_read(afu, CXL_PSL_PID_TID_An); |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 750 | info->pid = pidtid >> 32; |
| 751 | info->tid = pidtid & 0xffffffff; |
Ian Munsie | bc78b05 | 2014-11-14 17:37:50 +1100 | [diff] [blame] | 752 | info->afu_err = cxl_p2n_read(afu, CXL_AFU_ERR_An); |
| 753 | info->errstat = cxl_p2n_read(afu, CXL_PSL_ErrStat_An); |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 754 | |
| 755 | return 0; |
| 756 | } |
| 757 | |
| 758 | static void recover_psl_err(struct cxl_afu *afu, u64 errstat) |
| 759 | { |
| 760 | u64 dsisr; |
| 761 | |
Rasmus Villemoes | de36953 | 2015-06-11 13:27:52 +0200 | [diff] [blame] | 762 | pr_devel("RECOVERING FROM PSL ERROR... (0x%016llx)\n", errstat); |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 763 | |
| 764 | /* Clear PSL_DSISR[PE] */ |
| 765 | dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An); |
| 766 | cxl_p2n_write(afu, CXL_PSL_DSISR_An, dsisr & ~CXL_PSL_DSISR_An_PE); |
| 767 | |
| 768 | /* Write 1s to clear error status bits */ |
| 769 | cxl_p2n_write(afu, CXL_PSL_ErrStat_An, errstat); |
| 770 | } |
| 771 | |
| 772 | int cxl_ack_irq(struct cxl_context *ctx, u64 tfc, u64 psl_reset_mask) |
| 773 | { |
Ian Munsie | 9bcf28c | 2015-01-09 20:34:36 +1100 | [diff] [blame] | 774 | trace_cxl_psl_irq_ack(ctx, tfc); |
Ian Munsie | f204e0b | 2014-10-08 19:55:02 +1100 | [diff] [blame] | 775 | if (tfc) |
| 776 | cxl_p2n_write(ctx->afu, CXL_PSL_TFC_An, tfc); |
| 777 | if (psl_reset_mask) |
| 778 | recover_psl_err(ctx->afu, psl_reset_mask); |
| 779 | |
| 780 | return 0; |
| 781 | } |
| 782 | |
| 783 | int cxl_check_error(struct cxl_afu *afu) |
| 784 | { |
| 785 | return (cxl_p1n_read(afu, CXL_PSL_SCNTL_An) == ~0ULL); |
| 786 | } |