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gerrit-public.fairphone.software / kernel / msm-4.9 / 0e5bdb3f9fa5c2bd4452c258de78122ef15f62d6 / . / drivers / clk / rockchip / clk-rk3188.c
blob: ceabce5954982f855f67c37bed68a4fa237e1512 [file] [log] [blame]
Heiko Stübner2c14736c2014-07-03 02:01:14 +0200[diff] [blame]1/*
2 * Copyright (c) 2014 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/clk-provider.h>
17#include <linux/of.h>
18#include <linux/of_address.h>
19#include <dt-bindings/clock/rk3188-cru-common.h>
20#include "clk.h"
21
Heiko Stuebner11ff3762014-09-01 23:52:40 +0200[diff] [blame]22#define RK3066_GRF_SOC_STATUS 0x15c
Heiko Stübner2c14736c2014-07-03 02:01:14 +0200[diff] [blame]23#define RK3188_GRF_SOC_STATUS 0xac
24
25enum rk3188_plls {
26 apll, cpll, dpll, gpll,
27};
28
29struct rockchip_pll_rate_table rk3188_pll_rates[] = {
30 RK3066_PLL_RATE(2208000000, 1, 92, 1),
31 RK3066_PLL_RATE(2184000000, 1, 91, 1),
32 RK3066_PLL_RATE(2160000000, 1, 90, 1),
33 RK3066_PLL_RATE(2136000000, 1, 89, 1),
34 RK3066_PLL_RATE(2112000000, 1, 88, 1),
35 RK3066_PLL_RATE(2088000000, 1, 87, 1),
36 RK3066_PLL_RATE(2064000000, 1, 86, 1),
37 RK3066_PLL_RATE(2040000000, 1, 85, 1),
38 RK3066_PLL_RATE(2016000000, 1, 84, 1),
39 RK3066_PLL_RATE(1992000000, 1, 83, 1),
40 RK3066_PLL_RATE(1968000000, 1, 82, 1),
41 RK3066_PLL_RATE(1944000000, 1, 81, 1),
42 RK3066_PLL_RATE(1920000000, 1, 80, 1),
43 RK3066_PLL_RATE(1896000000, 1, 79, 1),
44 RK3066_PLL_RATE(1872000000, 1, 78, 1),
45 RK3066_PLL_RATE(1848000000, 1, 77, 1),
46 RK3066_PLL_RATE(1824000000, 1, 76, 1),
47 RK3066_PLL_RATE(1800000000, 1, 75, 1),
48 RK3066_PLL_RATE(1776000000, 1, 74, 1),
49 RK3066_PLL_RATE(1752000000, 1, 73, 1),
50 RK3066_PLL_RATE(1728000000, 1, 72, 1),
51 RK3066_PLL_RATE(1704000000, 1, 71, 1),
52 RK3066_PLL_RATE(1680000000, 1, 70, 1),
53 RK3066_PLL_RATE(1656000000, 1, 69, 1),
54 RK3066_PLL_RATE(1632000000, 1, 68, 1),
55 RK3066_PLL_RATE(1608000000, 1, 67, 1),
56 RK3066_PLL_RATE(1560000000, 1, 65, 1),
57 RK3066_PLL_RATE(1512000000, 1, 63, 1),
58 RK3066_PLL_RATE(1488000000, 1, 62, 1),
59 RK3066_PLL_RATE(1464000000, 1, 61, 1),
60 RK3066_PLL_RATE(1440000000, 1, 60, 1),
61 RK3066_PLL_RATE(1416000000, 1, 59, 1),
62 RK3066_PLL_RATE(1392000000, 1, 58, 1),
63 RK3066_PLL_RATE(1368000000, 1, 57, 1),
64 RK3066_PLL_RATE(1344000000, 1, 56, 1),
65 RK3066_PLL_RATE(1320000000, 1, 55, 1),
66 RK3066_PLL_RATE(1296000000, 1, 54, 1),
67 RK3066_PLL_RATE(1272000000, 1, 53, 1),
68 RK3066_PLL_RATE(1248000000, 1, 52, 1),
69 RK3066_PLL_RATE(1224000000, 1, 51, 1),
70 RK3066_PLL_RATE(1200000000, 1, 50, 1),
71 RK3066_PLL_RATE(1188000000, 2, 99, 1),
72 RK3066_PLL_RATE(1176000000, 1, 49, 1),
73 RK3066_PLL_RATE(1128000000, 1, 47, 1),
74 RK3066_PLL_RATE(1104000000, 1, 46, 1),
75 RK3066_PLL_RATE(1008000000, 1, 84, 2),
76 RK3066_PLL_RATE( 912000000, 1, 76, 2),
77 RK3066_PLL_RATE( 891000000, 8, 594, 2),
78 RK3066_PLL_RATE( 888000000, 1, 74, 2),
79 RK3066_PLL_RATE( 816000000, 1, 68, 2),
80 RK3066_PLL_RATE( 798000000, 2, 133, 2),
81 RK3066_PLL_RATE( 792000000, 1, 66, 2),
82 RK3066_PLL_RATE( 768000000, 1, 64, 2),
83 RK3066_PLL_RATE( 742500000, 8, 495, 2),
84 RK3066_PLL_RATE( 696000000, 1, 58, 2),
85 RK3066_PLL_RATE( 600000000, 1, 50, 2),
86 RK3066_PLL_RATE( 594000000, 2, 198, 4),
87 RK3066_PLL_RATE( 552000000, 1, 46, 2),
88 RK3066_PLL_RATE( 504000000, 1, 84, 4),
89 RK3066_PLL_RATE( 456000000, 1, 76, 4),
90 RK3066_PLL_RATE( 408000000, 1, 68, 4),
91 RK3066_PLL_RATE( 384000000, 2, 128, 4),
92 RK3066_PLL_RATE( 360000000, 1, 60, 4),
93 RK3066_PLL_RATE( 312000000, 1, 52, 4),
94 RK3066_PLL_RATE( 300000000, 1, 50, 4),
95 RK3066_PLL_RATE( 297000000, 2, 198, 8),
96 RK3066_PLL_RATE( 252000000, 1, 84, 8),
97 RK3066_PLL_RATE( 216000000, 1, 72, 8),
98 RK3066_PLL_RATE( 148500000, 2, 99, 8),
99 RK3066_PLL_RATE( 126000000, 1, 84, 16),
100 RK3066_PLL_RATE( 48000000, 1, 64, 32),
101 { /* sentinel */ },
102};
103
Heiko Stuebner0e5bdb32014-09-05 11:25:03 +0200[diff] [blame^]104#define RK3066_DIV_CORE_PERIPH_MASK 0x3
105#define RK3066_DIV_CORE_PERIPH_SHIFT 6
106#define RK3066_DIV_ACLK_CORE_MASK 0x7
107#define RK3066_DIV_ACLK_CORE_SHIFT 0
108#define RK3066_DIV_ACLK_HCLK_MASK 0x3
109#define RK3066_DIV_ACLK_HCLK_SHIFT 8
110#define RK3066_DIV_ACLK_PCLK_MASK 0x3
111#define RK3066_DIV_ACLK_PCLK_SHIFT 12
112#define RK3066_DIV_AHB2APB_MASK 0x3
113#define RK3066_DIV_AHB2APB_SHIFT 14
114
115#define RK3066_CLKSEL0(_core_peri) \
116 { \
117 .reg = RK2928_CLKSEL_CON(0), \
118 .val = HIWORD_UPDATE(_core_peri, RK3066_DIV_CORE_PERIPH_MASK, \
119 RK3066_DIV_CORE_PERIPH_SHIFT) \
120 }
121#define RK3066_CLKSEL1(_aclk_core, _aclk_hclk, _aclk_pclk, _ahb2apb) \
122 { \
123 .reg = RK2928_CLKSEL_CON(1), \
124 .val = HIWORD_UPDATE(_aclk_core, RK3066_DIV_ACLK_CORE_MASK, \
125 RK3066_DIV_ACLK_CORE_SHIFT) | \
126 HIWORD_UPDATE(_aclk_hclk, RK3066_DIV_ACLK_HCLK_MASK, \
127 RK3066_DIV_ACLK_HCLK_SHIFT) | \
128 HIWORD_UPDATE(_aclk_pclk, RK3066_DIV_ACLK_PCLK_MASK, \
129 RK3066_DIV_ACLK_PCLK_SHIFT) | \
130 HIWORD_UPDATE(_ahb2apb, RK3066_DIV_AHB2APB_MASK, \
131 RK3066_DIV_AHB2APB_SHIFT), \
132 }
133
134#define RK3066_CPUCLK_RATE(_prate, _core_peri, _acore, _ahclk, _apclk, _h2p) \
135 { \
136 .prate = _prate, \
137 .divs = { \
138 RK3066_CLKSEL0(_core_peri), \
139 RK3066_CLKSEL1(_acore, _ahclk, _apclk, _h2p), \
140 }, \
141 }
142
143static struct rockchip_cpuclk_rate_table rk3066_cpuclk_rates[] __initdata = {
144 RK3066_CPUCLK_RATE(1416000000, 2, 3, 1, 2, 1),
145 RK3066_CPUCLK_RATE(1200000000, 2, 3, 1, 2, 1),
146 RK3066_CPUCLK_RATE(1008000000, 2, 2, 1, 2, 1),
147 RK3066_CPUCLK_RATE( 816000000, 2, 2, 1, 2, 1),
148 RK3066_CPUCLK_RATE( 600000000, 1, 2, 1, 2, 1),
149 RK3066_CPUCLK_RATE( 504000000, 1, 1, 1, 2, 1),
150 RK3066_CPUCLK_RATE( 312000000, 0, 1, 1, 1, 0),
151};
152
153static const struct rockchip_cpuclk_reg_data rk3066_cpuclk_data = {
154 .core_reg = RK2928_CLKSEL_CON(0),
155 .div_core_shift = 0,
156 .div_core_mask = 0x1f,
157 .mux_core_shift = 8,
158};
159
160#define RK3188_DIV_ACLK_CORE_MASK 0x7
161#define RK3188_DIV_ACLK_CORE_SHIFT 3
162
163#define RK3188_CLKSEL1(_aclk_core) \
164 { \
165 .reg = RK2928_CLKSEL_CON(1), \
166 .val = HIWORD_UPDATE(_aclk_core, RK3188_DIV_ACLK_CORE_MASK,\
167 RK3188_DIV_ACLK_CORE_SHIFT) \
168 }
169#define RK3188_CPUCLK_RATE(_prate, _core_peri, _aclk_core) \
170 { \
171 .prate = _prate, \
172 .divs = { \
173 RK3066_CLKSEL0(_core_peri), \
174 RK3188_CLKSEL1(_aclk_core), \
175 }, \
176 }
177
178static struct rockchip_cpuclk_rate_table rk3188_cpuclk_rates[] __initdata = {
179 RK3188_CPUCLK_RATE(1608000000, 2, 3),
180 RK3188_CPUCLK_RATE(1416000000, 2, 3),
181 RK3188_CPUCLK_RATE(1200000000, 2, 3),
182 RK3188_CPUCLK_RATE(1008000000, 2, 3),
183 RK3188_CPUCLK_RATE( 816000000, 2, 3),
184 RK3188_CPUCLK_RATE( 600000000, 1, 3),
185 RK3188_CPUCLK_RATE( 504000000, 1, 3),
186 RK3188_CPUCLK_RATE( 312000000, 0, 1),
187};
188
189static const struct rockchip_cpuclk_reg_data rk3188_cpuclk_data = {
190 .core_reg = RK2928_CLKSEL_CON(0),
191 .div_core_shift = 9,
192 .div_core_mask = 0x1f,
193 .mux_core_shift = 8,
194};
195
Heiko Stübner2c14736c2014-07-03 02:01:14 +0200[diff] [blame]196PNAME(mux_pll_p) = { "xin24m", "xin32k" };
197PNAME(mux_armclk_p) = { "apll", "gpll_armclk" };
198PNAME(mux_ddrphy_p) = { "dpll", "gpll_ddr" };
199PNAME(mux_pll_src_gpll_cpll_p) = { "gpll", "cpll" };
200PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" };
201PNAME(mux_aclk_cpu_p) = { "apll", "gpll" };
202PNAME(mux_sclk_cif0_p) = { "cif0_pre", "xin24m" };
203PNAME(mux_sclk_i2s0_p) = { "i2s0_pre", "i2s0_frac", "xin12m" };
204PNAME(mux_sclk_spdif_p) = { "spdif_src", "spdif_frac", "xin12m" };
205PNAME(mux_sclk_uart0_p) = { "uart0_pre", "uart0_frac", "xin24m" };
206PNAME(mux_sclk_uart1_p) = { "uart1_pre", "uart1_frac", "xin24m" };
207PNAME(mux_sclk_uart2_p) = { "uart2_pre", "uart2_frac", "xin24m" };
208PNAME(mux_sclk_uart3_p) = { "uart3_pre", "uart3_frac", "xin24m" };
209PNAME(mux_sclk_hsadc_p) = { "hsadc_src", "hsadc_frac", "ext_hsadc" };
210PNAME(mux_mac_p) = { "gpll", "dpll" };
211PNAME(mux_sclk_macref_p) = { "mac_src", "ext_rmii" };
212
213static struct rockchip_pll_clock rk3188_pll_clks[] __initdata = {
214 [apll] = PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0),
215 RK2928_MODE_CON, 0, 6, rk3188_pll_rates),
216 [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4),
217 RK2928_MODE_CON, 4, 5, NULL),
218 [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(8),
219 RK2928_MODE_CON, 8, 7, rk3188_pll_rates),
220 [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12),
221 RK2928_MODE_CON, 12, 8, rk3188_pll_rates),
222};
223
224#define MFLAGS CLK_MUX_HIWORD_MASK
225#define DFLAGS CLK_DIVIDER_HIWORD_MASK
226#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
227
228/* 2 ^ (val + 1) */
229static struct clk_div_table div_core_peri_t[] = {
230 { .val = 0, .div = 2 },
231 { .val = 1, .div = 4 },
232 { .val = 2, .div = 8 },
233 { .val = 3, .div = 16 },
234 { /* sentinel */ },
235};
236
237static struct rockchip_clk_branch common_clk_branches[] __initdata = {
238 /*
239 * Clock-Architecture Diagram 2
240 */
241
242 GATE(0, "gpll_armclk", "gpll", 0, RK2928_CLKGATE_CON(0), 1, GFLAGS),
243
244 /* these two are set by the cpuclk and should not be changed */
245 COMPOSITE_NOMUX_DIVTBL(CORE_PERI, "core_peri", "armclk", 0,
246 RK2928_CLKSEL_CON(0), 6, 2, DFLAGS | CLK_DIVIDER_READ_ONLY,
247 div_core_peri_t, RK2928_CLKGATE_CON(0), 0, GFLAGS),
248
249 COMPOSITE(0, "aclk_vepu", mux_pll_src_cpll_gpll_p, 0,
250 RK2928_CLKSEL_CON(32), 7, 1, MFLAGS, 0, 5, DFLAGS,
251 RK2928_CLKGATE_CON(3), 9, GFLAGS),
252 GATE(0, "hclk_vepu", "aclk_vepu", 0,
253 RK2928_CLKGATE_CON(3), 10, GFLAGS),
254 COMPOSITE(0, "aclk_vdpu", mux_pll_src_cpll_gpll_p, 0,
255 RK2928_CLKSEL_CON(32), 15, 1, MFLAGS, 8, 5, DFLAGS,
256 RK2928_CLKGATE_CON(3), 11, GFLAGS),
257 GATE(0, "hclk_vdpu", "aclk_vdpu", 0,
258 RK2928_CLKGATE_CON(3), 12, GFLAGS),
259
260 GATE(0, "gpll_ddr", "gpll", 0,
261 RK2928_CLKGATE_CON(1), 7, GFLAGS),
262 COMPOSITE(0, "ddrphy", mux_ddrphy_p, 0,
263 RK2928_CLKSEL_CON(26), 8, 1, MFLAGS, 0, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
264 RK2928_CLKGATE_CON(0), 2, GFLAGS),
265
266 GATE(0, "aclk_cpu", "aclk_cpu_pre", 0,
267 RK2928_CLKGATE_CON(0), 3, GFLAGS),
268
Heiko Stübner2c14736c2014-07-03 02:01:14 +0200[diff] [blame]269 GATE(0, "atclk_cpu", "pclk_cpu_pre", 0,
270 RK2928_CLKGATE_CON(0), 6, GFLAGS),
271 GATE(0, "pclk_cpu", "pclk_cpu_pre", 0,
272 RK2928_CLKGATE_CON(0), 5, GFLAGS),
Heiko Stübner2c14736c2014-07-03 02:01:14 +0200[diff] [blame]273 GATE(0, "hclk_cpu", "hclk_cpu_pre", 0,
274 RK2928_CLKGATE_CON(0), 4, GFLAGS),
275
276 COMPOSITE(0, "aclk_lcdc0_pre", mux_pll_src_cpll_gpll_p, 0,
277 RK2928_CLKSEL_CON(31), 7, 1, MFLAGS, 0, 5, DFLAGS,
278 RK2928_CLKGATE_CON(3), 0, GFLAGS),
279 COMPOSITE(0, "aclk_lcdc1_pre", mux_pll_src_cpll_gpll_p, 0,
280 RK2928_CLKSEL_CON(31), 15, 1, MFLAGS, 8, 5, DFLAGS,
281 RK2928_CLKGATE_CON(1), 4, GFLAGS),
282
283 GATE(0, "aclk_peri", "aclk_peri_pre", 0,
284 RK2928_CLKGATE_CON(2), 1, GFLAGS),
285 COMPOSITE_NOMUX(0, "hclk_peri", "aclk_peri_pre", 0,
286 RK2928_CLKSEL_CON(10), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
287 RK2928_CLKGATE_CON(2), 2, GFLAGS),
288 COMPOSITE_NOMUX(0, "pclk_peri", "aclk_peri_pre", 0,
289 RK2928_CLKSEL_CON(10), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
290 RK2928_CLKGATE_CON(2), 3, GFLAGS),
291
292 MUX(0, "cif_src", mux_pll_src_cpll_gpll_p, 0,
293 RK2928_CLKSEL_CON(29), 0, 1, MFLAGS),
294 COMPOSITE_NOMUX(0, "cif0_pre", "cif_src", 0,
295 RK2928_CLKSEL_CON(29), 1, 5, DFLAGS,
296 RK2928_CLKGATE_CON(3), 7, GFLAGS),
297 MUX(SCLK_CIF0, "sclk_cif0", mux_sclk_cif0_p, 0,
298 RK2928_CLKSEL_CON(29), 7, 1, MFLAGS),
299
300 GATE(0, "pclkin_cif0", "ext_cif0", 0,
301 RK2928_CLKGATE_CON(3), 3, GFLAGS),
302
303 /*
304 * the 480m are generated inside the usb block from these clocks,
305 * but they are also a source for the hsicphy clock.
306 */
307 GATE(SCLK_OTGPHY0, "sclk_otgphy0", "usb480m", 0,
308 RK2928_CLKGATE_CON(1), 5, GFLAGS),
309 GATE(SCLK_OTGPHY1, "sclk_otgphy1", "usb480m", 0,
310 RK2928_CLKGATE_CON(1), 6, GFLAGS),
311
312 COMPOSITE(0, "mac_src", mux_mac_p, 0,
313 RK2928_CLKSEL_CON(21), 0, 1, MFLAGS, 8, 5, DFLAGS,
314 RK2928_CLKGATE_CON(2), 5, GFLAGS),
315 MUX(SCLK_MAC, "sclk_macref", mux_sclk_macref_p, CLK_SET_RATE_PARENT,
316 RK2928_CLKSEL_CON(21), 4, 1, MFLAGS),
317 GATE(0, "sclk_mac_lbtest", "sclk_macref",
318 RK2928_CLKGATE_CON(2), 12, 0, GFLAGS),
319
320 COMPOSITE(0, "hsadc_src", mux_pll_src_gpll_cpll_p, 0,
321 RK2928_CLKSEL_CON(22), 0, 1, MFLAGS, 8, 8, DFLAGS,
322 RK2928_CLKGATE_CON(2), 6, GFLAGS),
323 COMPOSITE_FRAC(0, "hsadc_frac", "hsadc_src",
324 RK2928_CLKSEL_CON(23), 0,
325 RK2928_CLKGATE_CON(2), 7, 0, GFLAGS),
326 MUX(SCLK_HSADC, "sclk_hsadc", mux_sclk_hsadc_p, 0,
327 RK2928_CLKSEL_CON(22), 4, 2, MFLAGS),
328
329 COMPOSITE_NOMUX(SCLK_SARADC, "sclk_saradc", "xin24m", 0,
330 RK2928_CLKSEL_CON(24), 8, 8, DFLAGS,
331 RK2928_CLKGATE_CON(2), 8, GFLAGS),
332
333 /*
334 * Clock-Architecture Diagram 4
335 */
336
337 GATE(SCLK_SMC, "sclk_smc", "hclk_peri",
338 RK2928_CLKGATE_CON(2), 4, 0, GFLAGS),
339
340 COMPOSITE_NOMUX(SCLK_SPI0, "sclk_spi0", "pclk_peri", 0,
341 RK2928_CLKSEL_CON(25), 0, 7, DFLAGS,
342 RK2928_CLKGATE_CON(2), 9, GFLAGS),
343 COMPOSITE_NOMUX(SCLK_SPI1, "sclk_spi1", "pclk_peri", 0,
344 RK2928_CLKSEL_CON(25), 8, 7, DFLAGS,
345 RK2928_CLKGATE_CON(2), 10, GFLAGS),
346
347 COMPOSITE_NOMUX(SCLK_SDMMC, "sclk_sdmmc", "hclk_peri", 0,
348 RK2928_CLKSEL_CON(11), 0, 6, DFLAGS,
349 RK2928_CLKGATE_CON(2), 11, GFLAGS),
350 COMPOSITE_NOMUX(SCLK_SDIO, "sclk_sdio", "hclk_peri", 0,
351 RK2928_CLKSEL_CON(12), 0, 6, DFLAGS,
352 RK2928_CLKGATE_CON(2), 13, GFLAGS),
353 COMPOSITE_NOMUX(SCLK_EMMC, "sclk_emmc", "hclk_peri", 0,
354 RK2928_CLKSEL_CON(12), 8, 6, DFLAGS,
355 RK2928_CLKGATE_CON(2), 14, GFLAGS),
356
357 MUX(0, "uart_src", mux_pll_src_gpll_cpll_p, 0,
358 RK2928_CLKSEL_CON(12), 15, 1, MFLAGS),
359 COMPOSITE_NOMUX(0, "uart0_pre", "uart_src", 0,
360 RK2928_CLKSEL_CON(13), 0, 7, DFLAGS,
361 RK2928_CLKGATE_CON(1), 8, GFLAGS),
362 COMPOSITE_FRAC(0, "uart0_frac", "uart0_pre", 0,
363 RK2928_CLKSEL_CON(17), 0,
364 RK2928_CLKGATE_CON(1), 9, GFLAGS),
365 MUX(SCLK_UART0, "sclk_uart0", mux_sclk_uart0_p, 0,
366 RK2928_CLKSEL_CON(13), 8, 2, MFLAGS),
367 COMPOSITE_NOMUX(0, "uart1_pre", "uart_src", 0,
368 RK2928_CLKSEL_CON(14), 0, 7, DFLAGS,
369 RK2928_CLKGATE_CON(1), 10, GFLAGS),
370 COMPOSITE_FRAC(0, "uart1_frac", "uart1_pre", 0,
371 RK2928_CLKSEL_CON(18), 0,
372 RK2928_CLKGATE_CON(1), 11, GFLAGS),
373 MUX(SCLK_UART1, "sclk_uart1", mux_sclk_uart1_p, 0,
374 RK2928_CLKSEL_CON(14), 8, 2, MFLAGS),
375 COMPOSITE_NOMUX(0, "uart2_pre", "uart_src", 0,
376 RK2928_CLKSEL_CON(15), 0, 7, DFLAGS,
377 RK2928_CLKGATE_CON(1), 12, GFLAGS),
378 COMPOSITE_FRAC(0, "uart2_frac", "uart2_pre", 0,
379 RK2928_CLKSEL_CON(19), 0,
380 RK2928_CLKGATE_CON(1), 13, GFLAGS),
381 MUX(SCLK_UART2, "sclk_uart2", mux_sclk_uart2_p, 0,
382 RK2928_CLKSEL_CON(15), 8, 2, MFLAGS),
383 COMPOSITE_NOMUX(0, "uart3_pre", "uart_src", 0,
384 RK2928_CLKSEL_CON(16), 0, 7, DFLAGS,
385 RK2928_CLKGATE_CON(1), 14, GFLAGS),
386 COMPOSITE_FRAC(0, "uart3_frac", "uart3_pre", 0,
387 RK2928_CLKSEL_CON(20), 0,
388 RK2928_CLKGATE_CON(1), 15, GFLAGS),
389 MUX(SCLK_UART3, "sclk_uart3", mux_sclk_uart3_p, 0,
390 RK2928_CLKSEL_CON(16), 8, 2, MFLAGS),
391
392 GATE(SCLK_JTAG, "jtag", "ext_jtag", 0, RK2928_CLKGATE_CON(1), 3, GFLAGS),
393
394 GATE(SCLK_TIMER0, "timer0", "xin24m", 0, RK2928_CLKGATE_CON(1), 0, GFLAGS),
395 GATE(SCLK_TIMER1, "timer1", "xin24m", 0, RK2928_CLKGATE_CON(1), 1, GFLAGS),
396
397 /* clk_core_pre gates */
398 GATE(0, "core_dbg", "armclk", 0, RK2928_CLKGATE_CON(9), 0, GFLAGS),
399
400 /* aclk_cpu gates */
401 GATE(ACLK_DMA1, "aclk_dma1", "aclk_cpu", 0, RK2928_CLKGATE_CON(5), 0, GFLAGS),
402 GATE(0, "aclk_intmem", "aclk_cpu", 0, RK2928_CLKGATE_CON(4), 12, GFLAGS),
403 GATE(0, "aclk_strc_sys", "aclk_cpu", 0, RK2928_CLKGATE_CON(4), 10, GFLAGS),
404
405 /* hclk_cpu gates */
406 GATE(HCLK_ROM, "hclk_rom", "hclk_cpu", 0, RK2928_CLKGATE_CON(5), 6, GFLAGS),
407 GATE(HCLK_I2S0, "hclk_i2s0", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 2, GFLAGS),
408 GATE(HCLK_SPDIF, "hclk_spdif", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 1, GFLAGS),
409 GATE(0, "hclk_cpubus", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 8, GFLAGS),
410 /* hclk_ahb2apb is part of a clk branch */
411 GATE(0, "hclk_vio_bus", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 12, GFLAGS),
412 GATE(HCLK_LCDC0, "hclk_lcdc0", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 1, GFLAGS),
413 GATE(HCLK_LCDC1, "hclk_lcdc1", "aclk_cpu", 0, RK2928_CLKGATE_CON(6), 2, GFLAGS),
414 GATE(HCLK_CIF0, "hclk_cif0", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 4, GFLAGS),
415 GATE(HCLK_IPP, "hclk_ipp", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 9, GFLAGS),
416 GATE(HCLK_RGA, "hclk_rga", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 10, GFLAGS),
417
418 /* hclk_peri gates */
419 GATE(0, "hclk_peri_axi_matrix", "hclk_peri", 0, RK2928_CLKGATE_CON(4), 0, GFLAGS),
420 GATE(0, "hclk_peri_ahb_arbi", "hclk_peri", 0, RK2928_CLKGATE_CON(4), 6, GFLAGS),
421 GATE(0, "hclk_emem_peri", "hclk_peri", 0, RK2928_CLKGATE_CON(4), 7, GFLAGS),
422 GATE(HCLK_EMAC, "hclk_emac", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 0, GFLAGS),
423 GATE(HCLK_NANDC0, "hclk_nandc0", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 9, GFLAGS),
424 GATE(0, "hclk_usb_peri", "hclk_peri", 0, RK2928_CLKGATE_CON(4), 5, GFLAGS),
425 GATE(HCLK_OTG0, "hclk_usbotg0", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 13, GFLAGS),
426 GATE(HCLK_HSADC, "hclk_hsadc", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 5, GFLAGS),
427 GATE(HCLK_PIDF, "hclk_pidfilter", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 6, GFLAGS),
428 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 10, GFLAGS),
429 GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 11, GFLAGS),
430 GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 12, GFLAGS),
431
432 /* aclk_lcdc0_pre gates */
433 GATE(0, "aclk_vio0", "aclk_lcdc0_pre", 0, RK2928_CLKGATE_CON(6), 13, GFLAGS),
434 GATE(ACLK_LCDC0, "aclk_lcdc0", "aclk_vio0", 0, RK2928_CLKGATE_CON(6), 0, GFLAGS),
435 GATE(ACLK_CIF0, "aclk_cif0", "aclk_vio0", 0, RK2928_CLKGATE_CON(6), 5, GFLAGS),
436 GATE(ACLK_IPP, "aclk_ipp", "aclk_vio0", 0, RK2928_CLKGATE_CON(6), 8, GFLAGS),
437
438 /* aclk_lcdc1_pre gates */
439 GATE(0, "aclk_vio1", "aclk_lcdc1_pre", 0, RK2928_CLKGATE_CON(9), 5, GFLAGS),
440 GATE(ACLK_LCDC1, "aclk_lcdc1", "aclk_vio1", 0, RK2928_CLKGATE_CON(6), 3, GFLAGS),
441 GATE(ACLK_RGA, "aclk_rga", "aclk_vio1", 0, RK2928_CLKGATE_CON(6), 11, GFLAGS),
442
443 /* atclk_cpu gates */
444 GATE(0, "atclk", "atclk_cpu", 0, RK2928_CLKGATE_CON(9), 3, GFLAGS),
445 GATE(0, "trace", "atclk_cpu", 0, RK2928_CLKGATE_CON(9), 2, GFLAGS),
446
447 /* pclk_cpu gates */
448 GATE(PCLK_PWM01, "pclk_pwm01", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 10, GFLAGS),
449 GATE(PCLK_TIMER0, "pclk_timer0", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 7, GFLAGS),
450 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 4, GFLAGS),
451 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 5, GFLAGS),
452 GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 9, GFLAGS),
453 GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 10, GFLAGS),
454 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 11, GFLAGS),
455 GATE(PCLK_EFUSE, "pclk_efuse", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 2, GFLAGS),
456 GATE(PCLK_TZPC, "pclk_tzpc", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 3, GFLAGS),
457 GATE(0, "pclk_ddrupctl", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 7, GFLAGS),
458 GATE(0, "pclk_ddrpubl", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 6, GFLAGS),
459 GATE(0, "pclk_dbg", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 1, GFLAGS),
460 GATE(PCLK_GRF, "pclk_grf", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 4, GFLAGS),
461 GATE(PCLK_PMU, "pclk_pmu", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 5, GFLAGS),
462
463 /* aclk_peri */
464 GATE(ACLK_DMA2, "aclk_dma2", "aclk_peri", 0, RK2928_CLKGATE_CON(5), 1, GFLAGS),
465 GATE(ACLK_SMC, "aclk_smc", "aclk_peri", 0, RK2928_CLKGATE_CON(5), 8, GFLAGS),
466 GATE(0, "aclk_peri_niu", "aclk_peri", 0, RK2928_CLKGATE_CON(4), 4, GFLAGS),
467 GATE(0, "aclk_cpu_peri", "aclk_peri", 0, RK2928_CLKGATE_CON(4), 2, GFLAGS),
468 GATE(0, "aclk_peri_axi_matrix", "aclk_peri", 0, RK2928_CLKGATE_CON(4), 3, GFLAGS),
469
470 /* pclk_peri gates */
471 GATE(0, "pclk_peri_axi_matrix", "pclk_peri", 0, RK2928_CLKGATE_CON(4), 1, GFLAGS),
472 GATE(PCLK_PWM23, "pclk_pwm23", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 11, GFLAGS),
473 GATE(PCLK_WDT, "pclk_wdt", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 15, GFLAGS),
474 GATE(PCLK_SPI0, "pclk_spi0", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 12, GFLAGS),
475 GATE(PCLK_SPI1, "pclk_spi1", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 13, GFLAGS),
476 GATE(PCLK_UART2, "pclk_uart2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 2, GFLAGS),
477 GATE(PCLK_UART3, "pclk_uart3", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 3, GFLAGS),
478 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 6, GFLAGS),
479 GATE(PCLK_I2C3, "pclk_i2c3", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 7, GFLAGS),
480 GATE(PCLK_I2C4, "pclk_i2c4", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 8, GFLAGS),
481 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 12, GFLAGS),
482 GATE(PCLK_SARADC, "pclk_saradc", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 14, GFLAGS),
483};
484
485PNAME(mux_rk3066_lcdc0_p) = { "dclk_lcdc0_src", "xin27m" };
486PNAME(mux_rk3066_lcdc1_p) = { "dclk_lcdc1_src", "xin27m" };
487PNAME(mux_sclk_cif1_p) = { "cif1_pre", "xin24m" };
488PNAME(mux_sclk_i2s1_p) = { "i2s1_pre", "i2s1_frac", "xin12m" };
489PNAME(mux_sclk_i2s2_p) = { "i2s2_pre", "i2s2_frac", "xin12m" };
490
491static struct clk_div_table div_aclk_cpu_t[] = {
492 { .val = 0, .div = 1 },
493 { .val = 1, .div = 2 },
494 { .val = 2, .div = 3 },
495 { .val = 3, .div = 4 },
496 { .val = 4, .div = 8 },
497 { /* sentinel */ },
498};
499
500static struct rockchip_clk_branch rk3066a_clk_branches[] __initdata = {
Heiko Stübner2c14736c2014-07-03 02:01:14 +0200[diff] [blame]501 DIVTBL(0, "aclk_cpu_pre", "armclk", 0,
Heiko Stuebner2b9bcee2014-09-04 21:43:17 +0200[diff] [blame]502 RK2928_CLKSEL_CON(1), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY, div_aclk_cpu_t),
503 DIV(0, "pclk_cpu_pre", "aclk_cpu_pre", 0,
504 RK2928_CLKSEL_CON(1), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO
505 | CLK_DIVIDER_READ_ONLY),
506 DIV(0, "hclk_cpu_pre", "aclk_cpu_pre", 0,
507 RK2928_CLKSEL_CON(1), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO
508 | CLK_DIVIDER_READ_ONLY),
509 COMPOSITE_NOMUX(0, "hclk_ahb2apb", "hclk_cpu_pre", 0,
510 RK2928_CLKSEL_CON(1), 14, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO
511 | CLK_DIVIDER_READ_ONLY,
512 RK2928_CLKGATE_CON(4), 9, GFLAGS),
Heiko Stübner2c14736c2014-07-03 02:01:14 +0200[diff] [blame]513
514 GATE(CORE_L2C, "core_l2c", "aclk_cpu", 0,
515 RK2928_CLKGATE_CON(9), 4, GFLAGS),
516
517 COMPOSITE(0, "aclk_peri_pre", mux_pll_src_gpll_cpll_p, 0,
518 RK2928_CLKSEL_CON(10), 15, 1, MFLAGS, 0, 5, DFLAGS,
519 RK2928_CLKGATE_CON(2), 0, GFLAGS),
520
521 COMPOSITE(0, "dclk_lcdc0_src", mux_pll_src_cpll_gpll_p, 0,
522 RK2928_CLKSEL_CON(27), 0, 1, MFLAGS, 8, 8, DFLAGS,
523 RK2928_CLKGATE_CON(3), 1, GFLAGS),
524 MUX(DCLK_LCDC0, "dclk_lcdc0", mux_rk3066_lcdc0_p, 0,
525 RK2928_CLKSEL_CON(27), 4, 1, MFLAGS),
526 COMPOSITE(0, "dclk_lcdc1_src", mux_pll_src_cpll_gpll_p, 0,
527 RK2928_CLKSEL_CON(28), 0, 1, MFLAGS, 8, 8, DFLAGS,
528 RK2928_CLKGATE_CON(3), 2, GFLAGS),
529 MUX(DCLK_LCDC1, "dclk_lcdc1", mux_rk3066_lcdc1_p, 0,
530 RK2928_CLKSEL_CON(28), 4, 1, MFLAGS),
531
532 COMPOSITE_NOMUX(0, "cif1_pre", "cif_src", 0,
533 RK2928_CLKSEL_CON(29), 8, 5, DFLAGS,
534 RK2928_CLKGATE_CON(3), 8, GFLAGS),
535 MUX(SCLK_CIF1, "sclk_cif1", mux_sclk_cif1_p, 0,
536 RK2928_CLKSEL_CON(29), 15, 1, MFLAGS),
537
538 GATE(0, "pclkin_cif1", "ext_cif1", 0,
539 RK2928_CLKGATE_CON(3), 4, GFLAGS),
540
541 COMPOSITE(0, "aclk_gpu_src", mux_pll_src_cpll_gpll_p, 0,
542 RK2928_CLKSEL_CON(33), 8, 1, MFLAGS, 0, 5, DFLAGS,
543 RK2928_CLKGATE_CON(3), 13, GFLAGS),
544 GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_src", 0,
545 RK2928_CLKGATE_CON(5), 15, GFLAGS),
546
547 GATE(SCLK_TIMER2, "timer2", "xin24m", 0,
548 RK2928_CLKGATE_CON(3), 2, GFLAGS),
549
550 COMPOSITE_NOMUX(0, "sclk_tsadc", "xin24m", 0,
551 RK2928_CLKSEL_CON(34), 0, 16, DFLAGS,
552 RK2928_CLKGATE_CON(2), 15, GFLAGS),
553
554 MUX(0, "i2s_src", mux_pll_src_gpll_cpll_p, 0,
555 RK2928_CLKSEL_CON(2), 15, 1, MFLAGS),
556 COMPOSITE_NOMUX(0, "i2s0_pre", "i2s_src", 0,
557 RK2928_CLKSEL_CON(2), 0, 7, DFLAGS,
558 RK2928_CLKGATE_CON(0), 7, GFLAGS),
559 COMPOSITE_FRAC(0, "i2s0_frac", "i2s0_pre", 0,
560 RK2928_CLKSEL_CON(6), 0,
561 RK2928_CLKGATE_CON(0), 8, GFLAGS),
562 MUX(SCLK_I2S0, "sclk_i2s0", mux_sclk_i2s0_p, 0,
563 RK2928_CLKSEL_CON(2), 8, 2, MFLAGS),
564 COMPOSITE_NOMUX(0, "i2s1_pre", "i2s_src", 0,
565 RK2928_CLKSEL_CON(3), 0, 7, DFLAGS,
566 RK2928_CLKGATE_CON(0), 9, GFLAGS),
567 COMPOSITE_FRAC(0, "i2s1_frac", "i2s1_pre", 0,
568 RK2928_CLKSEL_CON(7), 0,
569 RK2928_CLKGATE_CON(0), 10, GFLAGS),
570 MUX(SCLK_I2S1, "sclk_i2s1", mux_sclk_i2s1_p, 0,
571 RK2928_CLKSEL_CON(3), 8, 2, MFLAGS),
572 COMPOSITE_NOMUX(0, "i2s2_pre", "i2s_src", 0,
573 RK2928_CLKSEL_CON(4), 0, 7, DFLAGS,
574 RK2928_CLKGATE_CON(0), 11, GFLAGS),
575 COMPOSITE_FRAC(0, "i2s2_frac", "i2s2_pre", 0,
576 RK2928_CLKSEL_CON(8), 0,
577 RK2928_CLKGATE_CON(0), 12, GFLAGS),
578 MUX(SCLK_I2S2, "sclk_i2s2", mux_sclk_i2s2_p, 0,
579 RK2928_CLKSEL_CON(4), 8, 2, MFLAGS),
580 COMPOSITE_NOMUX(0, "spdif_pre", "i2s_src", 0,
581 RK2928_CLKSEL_CON(5), 0, 7, DFLAGS,
582 RK2928_CLKGATE_CON(0), 13, GFLAGS),
583 COMPOSITE_FRAC(0, "spdif_frac", "spdif_pll", 0,
584 RK2928_CLKSEL_CON(9), 0,
585 RK2928_CLKGATE_CON(0), 14, GFLAGS),
586 MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, 0,
587 RK2928_CLKSEL_CON(5), 8, 2, MFLAGS),
588
589 GATE(HCLK_I2S1, "hclk_i2s1", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 3, GFLAGS),
590 GATE(HCLK_I2S2, "hclk_i2s2", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 4, GFLAGS),
591 GATE(0, "hclk_cif1", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 6, GFLAGS),
592 GATE(0, "hclk_hdmi", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 14, GFLAGS),
593
594 GATE(HCLK_OTG1, "hclk_usbotg1", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 14, GFLAGS),
595
596 GATE(0, "aclk_cif1", "aclk_vio1", 0, RK2928_CLKGATE_CON(6), 7, GFLAGS),
597
598 GATE(PCLK_TIMER1, "pclk_timer1", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 8, GFLAGS),
599 GATE(PCLK_TIMER2, "pclk_timer2", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 9, GFLAGS),
600 GATE(PCLK_GPIO6, "pclk_gpio6", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 15, GFLAGS),
601 GATE(PCLK_UART0, "pclk_uart0", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 0, GFLAGS),
602 GATE(PCLK_UART1, "pclk_uart1", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 1, GFLAGS),
603
604 GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 13, GFLAGS),
605 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_peri", 0, RK2928_CLKGATE_CON(4), 13, GFLAGS),
606};
607
608static struct clk_div_table div_rk3188_aclk_core_t[] = {
609 { .val = 0, .div = 1 },
610 { .val = 1, .div = 2 },
611 { .val = 2, .div = 3 },
612 { .val = 3, .div = 4 },
613 { .val = 4, .div = 8 },
614 { /* sentinel */ },
615};
616
617PNAME(mux_hsicphy_p) = { "sclk_otgphy0", "sclk_otgphy1",
618 "gpll", "cpll" };
619
620static struct rockchip_clk_branch rk3188_clk_branches[] __initdata = {
Heiko Stübner2c14736c2014-07-03 02:01:14 +0200[diff] [blame]621 COMPOSITE_NOMUX_DIVTBL(0, "aclk_core", "armclk", 0,
622 RK2928_CLKSEL_CON(1), 3, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
623 div_rk3188_aclk_core_t, RK2928_CLKGATE_CON(0), 7, GFLAGS),
624
625 /* do not source aclk_cpu_pre from the apll, to keep complexity down */
626 COMPOSITE_NOGATE(0, "aclk_cpu_pre", mux_aclk_cpu_p, CLK_SET_RATE_NO_REPARENT,
627 RK2928_CLKSEL_CON(0), 5, 1, MFLAGS, 0, 5, DFLAGS),
Heiko Stuebner2b9bcee2014-09-04 21:43:17 +0200[diff] [blame]628 DIV(0, "pclk_cpu_pre", "aclk_cpu_pre", 0,
629 RK2928_CLKSEL_CON(1), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
630 DIV(0, "hclk_cpu_pre", "aclk_cpu_pre", 0,
631 RK2928_CLKSEL_CON(1), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
632 COMPOSITE_NOMUX(0, "hclk_ahb2apb", "hclk_cpu_pre", 0,
633 RK2928_CLKSEL_CON(1), 14, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
634 RK2928_CLKGATE_CON(4), 9, GFLAGS),
Heiko Stübner2c14736c2014-07-03 02:01:14 +0200[diff] [blame]635
636 GATE(CORE_L2C, "core_l2c", "armclk", 0,
637 RK2928_CLKGATE_CON(9), 4, GFLAGS),
638
639 COMPOSITE(0, "aclk_peri_pre", mux_pll_src_cpll_gpll_p, 0,
640 RK2928_CLKSEL_CON(10), 15, 1, MFLAGS, 0, 5, DFLAGS,
641 RK2928_CLKGATE_CON(2), 0, GFLAGS),
642
643 COMPOSITE(DCLK_LCDC0, "dclk_lcdc0", mux_pll_src_cpll_gpll_p, 0,
644 RK2928_CLKSEL_CON(27), 0, 1, MFLAGS, 8, 8, DFLAGS,
645 RK2928_CLKGATE_CON(3), 1, GFLAGS),
646 COMPOSITE(DCLK_LCDC1, "dclk_lcdc1", mux_pll_src_cpll_gpll_p, 0,
647 RK2928_CLKSEL_CON(28), 0, 1, MFLAGS, 8, 8, DFLAGS,
648 RK2928_CLKGATE_CON(3), 2, GFLAGS),
649
650 COMPOSITE(0, "aclk_gpu_src", mux_pll_src_cpll_gpll_p, 0,
651 RK2928_CLKSEL_CON(34), 7, 1, MFLAGS, 0, 5, DFLAGS,
652 RK2928_CLKGATE_CON(3), 15, GFLAGS),
653 GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_src", 0,
654 RK2928_CLKGATE_CON(9), 7, GFLAGS),
655
656 GATE(SCLK_TIMER2, "timer2", "xin24m", 0, RK2928_CLKGATE_CON(3), 4, GFLAGS),
657 GATE(SCLK_TIMER3, "timer3", "xin24m", 0, RK2928_CLKGATE_CON(1), 2, GFLAGS),
658 GATE(SCLK_TIMER4, "timer4", "xin24m", 0, RK2928_CLKGATE_CON(3), 5, GFLAGS),
659 GATE(SCLK_TIMER5, "timer5", "xin24m", 0, RK2928_CLKGATE_CON(3), 8, GFLAGS),
660 GATE(SCLK_TIMER6, "timer6", "xin24m", 0, RK2928_CLKGATE_CON(3), 14, GFLAGS),
661
662 COMPOSITE_NODIV(0, "sclk_hsicphy_480m", mux_hsicphy_p, 0,
663 RK2928_CLKSEL_CON(30), 0, 2, DFLAGS,
664 RK2928_CLKGATE_CON(3), 6, GFLAGS),
665 DIV(0, "sclk_hsicphy_12m", "sclk_hsicphy_480m", 0,
666 RK2928_CLKGATE_CON(11), 8, 6, DFLAGS),
667
668 MUX(0, "i2s_src", mux_pll_src_gpll_cpll_p, 0,
669 RK2928_CLKSEL_CON(2), 15, 1, MFLAGS),
670 COMPOSITE_NOMUX(0, "i2s0_pre", "i2s_src", 0,
671 RK2928_CLKSEL_CON(3), 0, 7, DFLAGS,
672 RK2928_CLKGATE_CON(0), 9, GFLAGS),
673 COMPOSITE_FRAC(0, "i2s0_frac", "i2s0_pre", 0,
674 RK2928_CLKSEL_CON(7), 0,
675 RK2928_CLKGATE_CON(0), 10, GFLAGS),
676 MUX(SCLK_I2S0, "sclk_i2s0", mux_sclk_i2s0_p, 0,
677 RK2928_CLKSEL_CON(3), 8, 2, MFLAGS),
678 COMPOSITE_NOMUX(0, "spdif_pre", "i2s_src", 0,
679 RK2928_CLKSEL_CON(5), 0, 7, DFLAGS,
680 RK2928_CLKGATE_CON(13), 13, GFLAGS),
681 COMPOSITE_FRAC(0, "spdif_frac", "spdif_pll", 0,
682 RK2928_CLKSEL_CON(9), 0,
683 RK2928_CLKGATE_CON(0), 14, GFLAGS),
684 MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, 0,
685 RK2928_CLKSEL_CON(5), 8, 2, MFLAGS),
686
687 GATE(0, "hclk_imem0", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 14, GFLAGS),
688 GATE(0, "hclk_imem1", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 15, GFLAGS),
689
690 GATE(HCLK_OTG1, "hclk_usbotg1", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 3, GFLAGS),
691 GATE(HCLK_HSIC, "hclk_hsic", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 4, GFLAGS),
692
693 GATE(PCLK_TIMER3, "pclk_timer3", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 9, GFLAGS),
694
695 GATE(PCLK_UART0, "pclk_uart0", "hclk_ahb2apb", 0, RK2928_CLKGATE_CON(8), 0, GFLAGS),
696 GATE(PCLK_UART1, "pclk_uart1", "hclk_ahb2apb", 0, RK2928_CLKGATE_CON(8), 1, GFLAGS),
697
698 GATE(ACLK_GPS, "aclk_gps", "aclk_peri", 0, RK2928_CLKGATE_CON(8), 13, GFLAGS),
699};
700
Heiko Stübnerfe94f972014-08-14 23:00:26 +0200[diff] [blame]701static const char *rk3188_critical_clocks[] __initconst = {
702 "aclk_cpu",
703 "aclk_peri",
Heiko Stübner2fed71e2014-09-10 17:52:02 +0200[diff] [blame]704 "hclk_peri",
Heiko Stübnerfe94f972014-08-14 23:00:26 +0200[diff] [blame]705};
706
Heiko Stübner2c14736c2014-07-03 02:01:14 +0200[diff] [blame]707static void __init rk3188_common_clk_init(struct device_node *np)
708{
709 void __iomem *reg_base;
710 struct clk *clk;
711
712 reg_base = of_iomap(np, 0);
713 if (!reg_base) {
714 pr_err("%s: could not map cru region\n", __func__);
715 return;
716 }
717
718 rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
719
720 /* xin12m is created by an cru-internal divider */
721 clk = clk_register_fixed_factor(NULL, "xin12m", "xin24m", 0, 1, 2);
722 if (IS_ERR(clk))
723 pr_warn("%s: could not register clock xin12m: %ld\n",
724 __func__, PTR_ERR(clk));
725
726 clk = clk_register_fixed_factor(NULL, "usb480m", "xin24m", 0, 20, 1);
727 if (IS_ERR(clk))
728 pr_warn("%s: could not register clock usb480m: %ld\n",
729 __func__, PTR_ERR(clk));
730
Heiko Stübner2c14736c2014-07-03 02:01:14 +0200[diff] [blame]731 rockchip_clk_register_branches(common_clk_branches,
732 ARRAY_SIZE(common_clk_branches));
Heiko Stübnerfe94f972014-08-14 23:00:26 +0200[diff] [blame]733 rockchip_clk_protect_critical(rk3188_critical_clocks,
734 ARRAY_SIZE(rk3188_critical_clocks));
Heiko Stübner2c14736c2014-07-03 02:01:14 +0200[diff] [blame]735
736 rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0),
737 ROCKCHIP_SOFTRST_HIWORD_MASK);
738}
739
740static void __init rk3066a_clk_init(struct device_node *np)
741{
742 rk3188_common_clk_init(np);
Heiko Stuebner11ff3762014-09-01 23:52:40 +0200[diff] [blame]743 rockchip_clk_register_plls(rk3188_pll_clks,
744 ARRAY_SIZE(rk3188_pll_clks),
745 RK3066_GRF_SOC_STATUS);
Heiko Stübner2c14736c2014-07-03 02:01:14 +0200[diff] [blame]746 rockchip_clk_register_branches(rk3066a_clk_branches,
747 ARRAY_SIZE(rk3066a_clk_branches));
Heiko Stuebner0e5bdb32014-09-05 11:25:03 +0200[diff] [blame^]748 rockchip_clk_register_armclk(ARMCLK, "armclk",
749 mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
750 &rk3066_cpuclk_data, rk3066_cpuclk_rates,
751 ARRAY_SIZE(rk3066_cpuclk_rates));
Heiko Stübner2c14736c2014-07-03 02:01:14 +0200[diff] [blame]752}
753CLK_OF_DECLARE(rk3066a_cru, "rockchip,rk3066a-cru", rk3066a_clk_init);
754
755static void __init rk3188a_clk_init(struct device_node *np)
756{
Heiko Stuebnerf5f70042014-09-04 21:24:45 +0200[diff] [blame]757 struct clk *clk1, *clk2;
758 unsigned long rate;
759 int ret;
760
Heiko Stübner2c14736c2014-07-03 02:01:14 +0200[diff] [blame]761 rk3188_common_clk_init(np);
Heiko Stuebner11ff3762014-09-01 23:52:40 +0200[diff] [blame]762 rockchip_clk_register_plls(rk3188_pll_clks,
763 ARRAY_SIZE(rk3188_pll_clks),
764 RK3188_GRF_SOC_STATUS);
Heiko Stübner2c14736c2014-07-03 02:01:14 +0200[diff] [blame]765 rockchip_clk_register_branches(rk3188_clk_branches,
766 ARRAY_SIZE(rk3188_clk_branches));
Heiko Stuebner0e5bdb32014-09-05 11:25:03 +0200[diff] [blame^]767 rockchip_clk_register_armclk(ARMCLK, "armclk",
768 mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
769 &rk3188_cpuclk_data, rk3188_cpuclk_rates,
770 ARRAY_SIZE(rk3188_cpuclk_rates));
Heiko Stuebnerf5f70042014-09-04 21:24:45 +0200[diff] [blame]771
772 /* reparent aclk_cpu_pre from apll */
773 clk1 = __clk_lookup("aclk_cpu_pre");
774 clk2 = __clk_lookup("gpll");
775 if (clk1 && clk2) {
776 rate = clk_get_rate(clk1);
777
778 ret = clk_set_parent(clk1, clk2);
779 if (ret < 0)
780 pr_warn("%s: could not reparent aclk_cpu_pre to gpll\n",
781 __func__);
782
783 clk_set_rate(clk1, rate);
784 } else {
785 pr_warn("%s: missing clocks to reparent aclk_cpu_pre to gpll\n",
786 __func__);
787 }
Heiko Stübner2c14736c2014-07-03 02:01:14 +0200[diff] [blame]788}
789CLK_OF_DECLARE(rk3188a_cru, "rockchip,rk3188a-cru", rk3188a_clk_init);
790
791static void __init rk3188_clk_init(struct device_node *np)
792{
793 int i;
794
795 for (i = 0; i < ARRAY_SIZE(rk3188_pll_clks); i++) {
796 struct rockchip_pll_clock *pll = &rk3188_pll_clks[i];
797 struct rockchip_pll_rate_table *rate;
798
799 if (!pll->rate_table)
800 continue;
801
802 rate = pll->rate_table;
803 while (rate->rate > 0) {
804 rate->bwadj = 0;
805 rate++;
806 }
807 }
808
809 rk3188a_clk_init(np);
810}
811CLK_OF_DECLARE(rk3188_cru, "rockchip,rk3188-cru", rk3188_clk_init);