Gitiles
Code Review Sign In
gerrit-public.fairphone.software / kernel / msm-4.9 / 0e87e0436c0cc3954eb62181a96d7217ca955a4f / . / arch / arm / boot / dts / imx6q.dtsi
blob: 925da33420e2d0c405a77defcdde8b096994f494 [file] [log] [blame]
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/include/ "skeleton.dtsi"
14
15/ {
16 aliases {
Richard Zhao8f9ffec2011-12-14 09:26:45 +0800[diff] [blame]17 serial0 = &uart1;
18 serial1 = &uart2;
19 serial2 = &uart3;
20 serial3 = &uart4;
21 serial4 = &uart5;
Shawn Guo5230f8f2012-08-05 14:01:28 +0800[diff] [blame]22 gpio0 = &gpio1;
23 gpio1 = &gpio2;
24 gpio2 = &gpio3;
25 gpio3 = &gpio4;
26 gpio4 = &gpio5;
27 gpio5 = &gpio6;
28 gpio6 = &gpio7;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]29 };
30
31 cpus {
32 #address-cells = <1>;
33 #size-cells = <0>;
34
35 cpu@0 {
36 compatible = "arm,cortex-a9";
37 reg = <0>;
38 next-level-cache = <&L2>;
39 };
40
41 cpu@1 {
42 compatible = "arm,cortex-a9";
43 reg = <1>;
44 next-level-cache = <&L2>;
45 };
46
47 cpu@2 {
48 compatible = "arm,cortex-a9";
49 reg = <2>;
50 next-level-cache = <&L2>;
51 };
52
53 cpu@3 {
54 compatible = "arm,cortex-a9";
55 reg = <3>;
56 next-level-cache = <&L2>;
57 };
58 };
59
60 intc: interrupt-controller@00a01000 {
61 compatible = "arm,cortex-a9-gic";
62 #interrupt-cells = <3>;
63 #address-cells = <1>;
64 #size-cells = <1>;
65 interrupt-controller;
66 reg = <0x00a01000 0x1000>,
67 <0x00a00100 0x100>;
68 };
69
70 clocks {
71 #address-cells = <1>;
72 #size-cells = <0>;
73
74 ckil {
75 compatible = "fsl,imx-ckil", "fixed-clock";
76 clock-frequency = <32768>;
77 };
78
79 ckih1 {
80 compatible = "fsl,imx-ckih1", "fixed-clock";
81 clock-frequency = <0>;
82 };
83
84 osc {
85 compatible = "fsl,imx-osc", "fixed-clock";
86 clock-frequency = <24000000>;
87 };
88 };
89
90 soc {
91 #address-cells = <1>;
92 #size-cells = <1>;
93 compatible = "simple-bus";
94 interrupt-parent = <&intc>;
95 ranges;
96
Huang Shijiee5d0f9f2012-06-06 21:22:57 -0400[diff] [blame]97 dma-apbh@00110000 {
98 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
99 reg = <0x00110000 0x2000>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame^]100 clocks = <&clks 106>;
Huang Shijiee5d0f9f2012-06-06 21:22:57 -0400[diff] [blame]101 };
102
Huang Shijiecf922fa2012-07-01 23:38:46 -0400[diff] [blame]103 gpmi-nand@00112000 {
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame^]104 compatible = "fsl,imx6q-gpmi-nand";
105 #address-cells = <1>;
106 #size-cells = <1>;
107 reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
108 reg-names = "gpmi-nand", "bch";
109 interrupts = <0 13 0x04>, <0 15 0x04>;
110 interrupt-names = "gpmi-dma", "bch";
111 clocks = <&clks 152>, <&clks 153>, <&clks 151>,
112 <&clks 150>, <&clks 149>;
113 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
114 "gpmi_bch_apb", "per1_bch";
115 fsl,gpmi-dma-channel = <0>;
116 status = "disabled";
Huang Shijiecf922fa2012-07-01 23:38:46 -0400[diff] [blame]117 };
118
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]119 timer@00a00600 {
Marc Zyngier58458e02012-01-10 19:44:19 +0000[diff] [blame]120 compatible = "arm,cortex-a9-twd-timer";
121 reg = <0x00a00600 0x20>;
122 interrupts = <1 13 0xf01>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]123 };
124
125 L2: l2-cache@00a02000 {
126 compatible = "arm,pl310-cache";
127 reg = <0x00a02000 0x1000>;
128 interrupts = <0 92 0x04>;
129 cache-unified;
130 cache-level = <2>;
131 };
132
133 aips-bus@02000000 { /* AIPS1 */
134 compatible = "fsl,aips-bus", "simple-bus";
135 #address-cells = <1>;
136 #size-cells = <1>;
137 reg = <0x02000000 0x100000>;
138 ranges;
139
140 spba-bus@02000000 {
141 compatible = "fsl,spba-bus", "simple-bus";
142 #address-cells = <1>;
143 #size-cells = <1>;
144 reg = <0x02000000 0x40000>;
145 ranges;
146
147 spdif@02004000 {
148 reg = <0x02004000 0x4000>;
149 interrupts = <0 52 0x04>;
150 };
151
152 ecspi@02008000 { /* eCSPI1 */
153 #address-cells = <1>;
154 #size-cells = <0>;
155 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
156 reg = <0x02008000 0x4000>;
157 interrupts = <0 31 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame^]158 clocks = <&clks 112>, <&clks 112>;
159 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]160 status = "disabled";
161 };
162
163 ecspi@0200c000 { /* eCSPI2 */
164 #address-cells = <1>;
165 #size-cells = <0>;
166 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
167 reg = <0x0200c000 0x4000>;
168 interrupts = <0 32 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame^]169 clocks = <&clks 113>, <&clks 113>;
170 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]171 status = "disabled";
172 };
173
174 ecspi@02010000 { /* eCSPI3 */
175 #address-cells = <1>;
176 #size-cells = <0>;
177 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
178 reg = <0x02010000 0x4000>;
179 interrupts = <0 33 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame^]180 clocks = <&clks 114>, <&clks 114>;
181 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]182 status = "disabled";
183 };
184
185 ecspi@02014000 { /* eCSPI4 */
186 #address-cells = <1>;
187 #size-cells = <0>;
188 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
189 reg = <0x02014000 0x4000>;
190 interrupts = <0 34 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame^]191 clocks = <&clks 115>, <&clks 115>;
192 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]193 status = "disabled";
194 };
195
196 ecspi@02018000 { /* eCSPI5 */
197 #address-cells = <1>;
198 #size-cells = <0>;
199 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
200 reg = <0x02018000 0x4000>;
201 interrupts = <0 35 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame^]202 clocks = <&clks 116>, <&clks 116>;
203 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]204 status = "disabled";
205 };
206
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]207 uart1: serial@02020000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]208 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
209 reg = <0x02020000 0x4000>;
210 interrupts = <0 26 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame^]211 clocks = <&clks 160>, <&clks 161>;
212 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]213 status = "disabled";
214 };
215
216 esai@02024000 {
217 reg = <0x02024000 0x4000>;
218 interrupts = <0 51 0x04>;
219 };
220
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]221 ssi1: ssi@02028000 {
222 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]223 reg = <0x02028000 0x4000>;
224 interrupts = <0 46 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame^]225 clocks = <&clks 178>;
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]226 fsl,fifo-depth = <15>;
227 fsl,ssi-dma-events = <38 37>;
228 status = "disabled";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]229 };
230
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]231 ssi2: ssi@0202c000 {
232 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]233 reg = <0x0202c000 0x4000>;
234 interrupts = <0 47 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame^]235 clocks = <&clks 179>;
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]236 fsl,fifo-depth = <15>;
237 fsl,ssi-dma-events = <42 41>;
238 status = "disabled";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]239 };
240
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]241 ssi3: ssi@02030000 {
242 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]243 reg = <0x02030000 0x4000>;
244 interrupts = <0 48 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame^]245 clocks = <&clks 180>;
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]246 fsl,fifo-depth = <15>;
247 fsl,ssi-dma-events = <46 45>;
248 status = "disabled";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]249 };
250
251 asrc@02034000 {
252 reg = <0x02034000 0x4000>;
253 interrupts = <0 50 0x04>;
254 };
255
256 spba@0203c000 {
257 reg = <0x0203c000 0x4000>;
258 };
259 };
260
261 vpu@02040000 {
262 reg = <0x02040000 0x3c000>;
263 interrupts = <0 3 0x04 0 12 0x04>;
264 };
265
266 aipstz@0207c000 { /* AIPSTZ1 */
267 reg = <0x0207c000 0x4000>;
268 };
269
270 pwm@02080000 { /* PWM1 */
271 reg = <0x02080000 0x4000>;
272 interrupts = <0 83 0x04>;
273 };
274
275 pwm@02084000 { /* PWM2 */
276 reg = <0x02084000 0x4000>;
277 interrupts = <0 84 0x04>;
278 };
279
280 pwm@02088000 { /* PWM3 */
281 reg = <0x02088000 0x4000>;
282 interrupts = <0 85 0x04>;
283 };
284
285 pwm@0208c000 { /* PWM4 */
286 reg = <0x0208c000 0x4000>;
287 interrupts = <0 86 0x04>;
288 };
289
290 flexcan@02090000 { /* CAN1 */
291 reg = <0x02090000 0x4000>;
292 interrupts = <0 110 0x04>;
293 };
294
295 flexcan@02094000 { /* CAN2 */
296 reg = <0x02094000 0x4000>;
297 interrupts = <0 111 0x04>;
298 };
299
300 gpt@02098000 {
301 compatible = "fsl,imx6q-gpt";
302 reg = <0x02098000 0x4000>;
303 interrupts = <0 55 0x04>;
304 };
305
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]306 gpio1: gpio@0209c000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]307 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]308 reg = <0x0209c000 0x4000>;
309 interrupts = <0 66 0x04 0 67 0x04>;
310 gpio-controller;
311 #gpio-cells = <2>;
312 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]313 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]314 };
315
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]316 gpio2: gpio@020a0000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]317 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]318 reg = <0x020a0000 0x4000>;
319 interrupts = <0 68 0x04 0 69 0x04>;
320 gpio-controller;
321 #gpio-cells = <2>;
322 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]323 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]324 };
325
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]326 gpio3: gpio@020a4000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]327 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]328 reg = <0x020a4000 0x4000>;
329 interrupts = <0 70 0x04 0 71 0x04>;
330 gpio-controller;
331 #gpio-cells = <2>;
332 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]333 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]334 };
335
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]336 gpio4: gpio@020a8000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]337 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]338 reg = <0x020a8000 0x4000>;
339 interrupts = <0 72 0x04 0 73 0x04>;
340 gpio-controller;
341 #gpio-cells = <2>;
342 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]343 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]344 };
345
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]346 gpio5: gpio@020ac000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]347 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]348 reg = <0x020ac000 0x4000>;
349 interrupts = <0 74 0x04 0 75 0x04>;
350 gpio-controller;
351 #gpio-cells = <2>;
352 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]353 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]354 };
355
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]356 gpio6: gpio@020b0000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]357 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]358 reg = <0x020b0000 0x4000>;
359 interrupts = <0 76 0x04 0 77 0x04>;
360 gpio-controller;
361 #gpio-cells = <2>;
362 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]363 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]364 };
365
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]366 gpio7: gpio@020b4000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]367 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]368 reg = <0x020b4000 0x4000>;
369 interrupts = <0 78 0x04 0 79 0x04>;
370 gpio-controller;
371 #gpio-cells = <2>;
372 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]373 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]374 };
375
376 kpp@020b8000 {
377 reg = <0x020b8000 0x4000>;
378 interrupts = <0 82 0x04>;
379 };
380
381 wdog@020bc000 { /* WDOG1 */
382 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
383 reg = <0x020bc000 0x4000>;
384 interrupts = <0 80 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame^]385 clocks = <&clks 0>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]386 status = "disabled";
387 };
388
389 wdog@020c0000 { /* WDOG2 */
390 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
391 reg = <0x020c0000 0x4000>;
392 interrupts = <0 81 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame^]393 clocks = <&clks 0>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]394 status = "disabled";
395 };
396
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame^]397 clks: ccm@020c4000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]398 compatible = "fsl,imx6q-ccm";
399 reg = <0x020c4000 0x4000>;
400 interrupts = <0 87 0x04 0 88 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame^]401 #clock-cells = <1>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]402 };
403
404 anatop@020c8000 {
405 compatible = "fsl,imx6q-anatop";
406 reg = <0x020c8000 0x1000>;
407 interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
Ying-Chun Liu (PaulLiu)a1e327e2012-03-30 21:46:53 +0800[diff] [blame]408
409 regulator-1p1@110 {
410 compatible = "fsl,anatop-regulator";
411 regulator-name = "vdd1p1";
412 regulator-min-microvolt = <800000>;
413 regulator-max-microvolt = <1375000>;
414 regulator-always-on;
415 anatop-reg-offset = <0x110>;
416 anatop-vol-bit-shift = <8>;
417 anatop-vol-bit-width = <5>;
418 anatop-min-bit-val = <4>;
419 anatop-min-voltage = <800000>;
420 anatop-max-voltage = <1375000>;
421 };
422
423 regulator-3p0@120 {
424 compatible = "fsl,anatop-regulator";
425 regulator-name = "vdd3p0";
426 regulator-min-microvolt = <2800000>;
427 regulator-max-microvolt = <3150000>;
428 regulator-always-on;
429 anatop-reg-offset = <0x120>;
430 anatop-vol-bit-shift = <8>;
431 anatop-vol-bit-width = <5>;
432 anatop-min-bit-val = <0>;
433 anatop-min-voltage = <2625000>;
434 anatop-max-voltage = <3400000>;
435 };
436
437 regulator-2p5@130 {
438 compatible = "fsl,anatop-regulator";
439 regulator-name = "vdd2p5";
440 regulator-min-microvolt = <2000000>;
441 regulator-max-microvolt = <2750000>;
442 regulator-always-on;
443 anatop-reg-offset = <0x130>;
444 anatop-vol-bit-shift = <8>;
445 anatop-vol-bit-width = <5>;
446 anatop-min-bit-val = <0>;
447 anatop-min-voltage = <2000000>;
448 anatop-max-voltage = <2750000>;
449 };
450
451 regulator-vddcore@140 {
452 compatible = "fsl,anatop-regulator";
453 regulator-name = "cpu";
454 regulator-min-microvolt = <725000>;
455 regulator-max-microvolt = <1450000>;
456 regulator-always-on;
457 anatop-reg-offset = <0x140>;
458 anatop-vol-bit-shift = <0>;
459 anatop-vol-bit-width = <5>;
460 anatop-min-bit-val = <1>;
461 anatop-min-voltage = <725000>;
462 anatop-max-voltage = <1450000>;
463 };
464
465 regulator-vddpu@140 {
466 compatible = "fsl,anatop-regulator";
467 regulator-name = "vddpu";
468 regulator-min-microvolt = <725000>;
469 regulator-max-microvolt = <1450000>;
470 regulator-always-on;
471 anatop-reg-offset = <0x140>;
472 anatop-vol-bit-shift = <9>;
473 anatop-vol-bit-width = <5>;
474 anatop-min-bit-val = <1>;
475 anatop-min-voltage = <725000>;
476 anatop-max-voltage = <1450000>;
477 };
478
479 regulator-vddsoc@140 {
480 compatible = "fsl,anatop-regulator";
481 regulator-name = "vddsoc";
482 regulator-min-microvolt = <725000>;
483 regulator-max-microvolt = <1450000>;
484 regulator-always-on;
485 anatop-reg-offset = <0x140>;
486 anatop-vol-bit-shift = <18>;
487 anatop-vol-bit-width = <5>;
488 anatop-min-bit-val = <1>;
489 anatop-min-voltage = <725000>;
490 anatop-max-voltage = <1450000>;
491 };
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]492 };
493
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]494 usbphy1: usbphy@020c9000 {
495 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]496 reg = <0x020c9000 0x1000>;
497 interrupts = <0 44 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame^]498 clocks = <&clks 182>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]499 };
500
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]501 usbphy2: usbphy@020ca000 {
502 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]503 reg = <0x020ca000 0x1000>;
504 interrupts = <0 45 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame^]505 clocks = <&clks 183>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]506 };
507
508 snvs@020cc000 {
509 reg = <0x020cc000 0x4000>;
510 interrupts = <0 19 0x04 0 20 0x04>;
511 };
512
513 epit@020d0000 { /* EPIT1 */
514 reg = <0x020d0000 0x4000>;
515 interrupts = <0 56 0x04>;
516 };
517
518 epit@020d4000 { /* EPIT2 */
519 reg = <0x020d4000 0x4000>;
520 interrupts = <0 57 0x04>;
521 };
522
523 src@020d8000 {
524 compatible = "fsl,imx6q-src";
525 reg = <0x020d8000 0x4000>;
526 interrupts = <0 91 0x04 0 96 0x04>;
527 };
528
529 gpc@020dc000 {
530 compatible = "fsl,imx6q-gpc";
531 reg = <0x020dc000 0x4000>;
532 interrupts = <0 89 0x04 0 90 0x04>;
533 };
534
535 iomuxc@020e0000 {
Dong Aisheng551fd202012-05-11 14:58:00 +0800[diff] [blame]536 compatible = "fsl,imx6q-iomuxc";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]537 reg = <0x020e0000 0x4000>;
Dong Aisheng551fd202012-05-11 14:58:00 +0800[diff] [blame]538
539 /* shared pinctrl settings */
Richard Zhao5ca65c12012-05-09 11:21:11 +0800[diff] [blame]540 audmux {
541 pinctrl_audmux_1: audmux-1 {
542 fsl,pins = <18 0x80000000 /* MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */
543 1586 0x80000000 /* MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC */
544 11 0x80000000 /* MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD */
545 3 0x80000000>; /* MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */
546 };
547 };
548
Huang Shijiecf922fa2012-07-01 23:38:46 -0400[diff] [blame]549 gpmi-nand {
550 pinctrl_gpmi_nand_1: gpmi-nand-1 {
551 fsl,pins = <1328 0xb0b1 /* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */
552 1336 0xb0b1 /* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */
553 1344 0xb0b1 /* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */
554 1352 0xb000 /* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */
555 1360 0xb0b1 /* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */
556 1365 0xb0b1 /* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */
557 1371 0xb0b1 /* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */
558 1378 0xb0b1 /* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */
559 1387 0xb0b1 /* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */
560 1393 0xb0b1 /* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */
561 1397 0xb0b1 /* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */
562 1405 0xb0b1 /* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */
563 1413 0xb0b1 /* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */
564 1421 0xb0b1 /* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */
565 1429 0xb0b1 /* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */
566 1437 0xb0b1 /* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */
567 1445 0xb0b1 /* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */
568 1453 0xb0b1 /* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */
569 1463 0x00b1>; /* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */
570 };
571 };
572
Richard Zhaod99a79f2012-05-09 10:47:20 +0800[diff] [blame]573 i2c1 {
574 pinctrl_i2c1_1: i2c1grp-1 {
575 fsl,pins = <137 0x4001b8b1 /* MX6Q_PAD_EIM_D21__I2C1_SCL */
576 196 0x4001b8b1>; /* MX6Q_PAD_EIM_D28__I2C1_SDA */
577 };
578 };
579
Richard Zhaoc3001b22012-05-09 14:44:47 +0800[diff] [blame]580 serial2 {
581 pinctrl_serial2_1: serial2grp-1 {
582 fsl,pins = <183 0x1b0b1 /* MX6Q_PAD_EIM_D26__UART2_TXD */
583 191 0x1b0b1>; /* MX6Q_PAD_EIM_D27__UART2_RXD */
584 };
585 };
586
Dong Aisheng551fd202012-05-11 14:58:00 +0800[diff] [blame]587 usdhc3 {
588 pinctrl_usdhc3_1: usdhc3grp-1 {
589 fsl,pins = <1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
590 1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */
591 1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
592 1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
593 1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
594 1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
595 1265 0x17059 /* MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 */
596 1257 0x17059 /* MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 */
597 1249 0x17059 /* MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 */
598 1241 0x17059>; /* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */
599 };
600 };
601
602 usdhc4 {
603 pinctrl_usdhc4_1: usdhc4grp-1 {
604 fsl,pins = <1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
605 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
606 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
607 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
608 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
609 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
610 1493 0x17059 /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */
611 1501 0x17059 /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */
612 1509 0x17059 /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */
613 1517 0x17059>; /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */
614 };
615 };
Hui Wang8ad7a302012-06-20 14:41:50 +0800[diff] [blame]616
617 ecspi1 {
618 pinctrl_ecspi1_1: ecspi1grp-1 {
619 fsl,pins = <101 0x100b1 /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */
620 109 0x100b1 /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */
621 94 0x100b1>; /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */
622 };
623 };
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]624 };
625
626 dcic@020e4000 { /* DCIC1 */
627 reg = <0x020e4000 0x4000>;
628 interrupts = <0 124 0x04>;
629 };
630
631 dcic@020e8000 { /* DCIC2 */
632 reg = <0x020e8000 0x4000>;
633 interrupts = <0 125 0x04>;
634 };
635
636 sdma@020ec000 {
637 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
638 reg = <0x020ec000 0x4000>;
639 interrupts = <0 2 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame^]640 clocks = <&clks 155>, <&clks 155>;
641 clock-names = "ipg", "ahb";
642 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q-to1.bin";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]643 };
644 };
645
646 aips-bus@02100000 { /* AIPS2 */
647 compatible = "fsl,aips-bus", "simple-bus";
648 #address-cells = <1>;
649 #size-cells = <1>;
650 reg = <0x02100000 0x100000>;
651 ranges;
652
653 caam@02100000 {
654 reg = <0x02100000 0x40000>;
655 interrupts = <0 105 0x04 0 106 0x04>;
656 };
657
658 aipstz@0217c000 { /* AIPSTZ2 */
659 reg = <0x0217c000 0x4000>;
660 };
661
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]662 usb@02184000 { /* USB OTG */
663 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
664 reg = <0x02184000 0x200>;
665 interrupts = <0 43 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame^]666 clocks = <&clks 162>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]667 fsl,usbphy = <&usbphy1>;
668 status = "disabled";
669 };
670
671 usb@02184200 { /* USB1 */
672 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
673 reg = <0x02184200 0x200>;
674 interrupts = <0 40 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame^]675 clocks = <&clks 162>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]676 fsl,usbphy = <&usbphy2>;
677 status = "disabled";
678 };
679
680 usb@02184400 { /* USB2 */
681 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
682 reg = <0x02184400 0x200>;
683 interrupts = <0 41 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame^]684 clocks = <&clks 162>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]685 status = "disabled";
686 };
687
688 usb@02184600 { /* USB3 */
689 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
690 reg = <0x02184600 0x200>;
691 interrupts = <0 42 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame^]692 clocks = <&clks 162>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]693 status = "disabled";
694 };
695
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]696 ethernet@02188000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]697 compatible = "fsl,imx6q-fec";
698 reg = <0x02188000 0x4000>;
699 interrupts = <0 118 0x04 0 119 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame^]700 clocks = <&clks 117>, <&clks 117>;
701 clock-names = "ipg", "ahb";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]702 status = "disabled";
703 };
704
705 mlb@0218c000 {
706 reg = <0x0218c000 0x4000>;
707 interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>;
708 };
709
710 usdhc@02190000 { /* uSDHC1 */
711 compatible = "fsl,imx6q-usdhc";
712 reg = <0x02190000 0x4000>;
713 interrupts = <0 22 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame^]714 clocks = <&clks 163>, <&clks 163>, <&clks 163>;
715 clock-names = "ipg", "ahb", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]716 status = "disabled";
717 };
718
719 usdhc@02194000 { /* uSDHC2 */
720 compatible = "fsl,imx6q-usdhc";
721 reg = <0x02194000 0x4000>;
722 interrupts = <0 23 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame^]723 clocks = <&clks 164>, <&clks 164>, <&clks 164>;
724 clock-names = "ipg", "ahb", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]725 status = "disabled";
726 };
727
728 usdhc@02198000 { /* uSDHC3 */
729 compatible = "fsl,imx6q-usdhc";
730 reg = <0x02198000 0x4000>;
731 interrupts = <0 24 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame^]732 clocks = <&clks 165>, <&clks 165>, <&clks 165>;
733 clock-names = "ipg", "ahb", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]734 status = "disabled";
735 };
736
737 usdhc@0219c000 { /* uSDHC4 */
738 compatible = "fsl,imx6q-usdhc";
739 reg = <0x0219c000 0x4000>;
740 interrupts = <0 25 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame^]741 clocks = <&clks 166>, <&clks 166>, <&clks 166>;
742 clock-names = "ipg", "ahb", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]743 status = "disabled";
744 };
745
746 i2c@021a0000 { /* I2C1 */
747 #address-cells = <1>;
748 #size-cells = <0>;
749 compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
750 reg = <0x021a0000 0x4000>;
751 interrupts = <0 36 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame^]752 clocks = <&clks 125>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]753 status = "disabled";
754 };
755
756 i2c@021a4000 { /* I2C2 */
757 #address-cells = <1>;
758 #size-cells = <0>;
759 compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
760 reg = <0x021a4000 0x4000>;
761 interrupts = <0 37 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame^]762 clocks = <&clks 126>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]763 status = "disabled";
764 };
765
766 i2c@021a8000 { /* I2C3 */
767 #address-cells = <1>;
768 #size-cells = <0>;
769 compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
770 reg = <0x021a8000 0x4000>;
771 interrupts = <0 38 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame^]772 clocks = <&clks 127>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]773 status = "disabled";
774 };
775
776 romcp@021ac000 {
777 reg = <0x021ac000 0x4000>;
778 };
779
780 mmdc@021b0000 { /* MMDC0 */
781 compatible = "fsl,imx6q-mmdc";
782 reg = <0x021b0000 0x4000>;
783 };
784
785 mmdc@021b4000 { /* MMDC1 */
786 reg = <0x021b4000 0x4000>;
787 };
788
789 weim@021b8000 {
790 reg = <0x021b8000 0x4000>;
791 interrupts = <0 14 0x04>;
792 };
793
794 ocotp@021bc000 {
795 reg = <0x021bc000 0x4000>;
796 };
797
798 ocotp@021c0000 {
799 reg = <0x021c0000 0x4000>;
800 interrupts = <0 21 0x04>;
801 };
802
803 tzasc@021d0000 { /* TZASC1 */
804 reg = <0x021d0000 0x4000>;
805 interrupts = <0 108 0x04>;
806 };
807
808 tzasc@021d4000 { /* TZASC2 */
809 reg = <0x021d4000 0x4000>;
810 interrupts = <0 109 0x04>;
811 };
812
813 audmux@021d8000 {
Richard Zhaof965cd52012-05-02 10:32:26 +0800[diff] [blame]814 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]815 reg = <0x021d8000 0x4000>;
Richard Zhaof965cd52012-05-02 10:32:26 +0800[diff] [blame]816 status = "disabled";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]817 };
818
819 mipi@021dc000 { /* MIPI-CSI */
820 reg = <0x021dc000 0x4000>;
821 };
822
823 mipi@021e0000 { /* MIPI-DSI */
824 reg = <0x021e0000 0x4000>;
825 };
826
827 vdoa@021e4000 {
828 reg = <0x021e4000 0x4000>;
829 interrupts = <0 18 0x04>;
830 };
831
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]832 uart2: serial@021e8000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]833 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
834 reg = <0x021e8000 0x4000>;
835 interrupts = <0 27 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame^]836 clocks = <&clks 160>, <&clks 161>;
837 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]838 status = "disabled";
839 };
840
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]841 uart3: serial@021ec000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]842 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
843 reg = <0x021ec000 0x4000>;
844 interrupts = <0 28 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame^]845 clocks = <&clks 160>, <&clks 161>;
846 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]847 status = "disabled";
848 };
849
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]850 uart4: serial@021f0000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]851 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
852 reg = <0x021f0000 0x4000>;
853 interrupts = <0 29 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame^]854 clocks = <&clks 160>, <&clks 161>;
855 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]856 status = "disabled";
857 };
858
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]859 uart5: serial@021f4000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]860 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
861 reg = <0x021f4000 0x4000>;
862 interrupts = <0 30 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame^]863 clocks = <&clks 160>, <&clks 161>;
864 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]865 status = "disabled";
866 };
867 };
868 };
869};