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Catalin Marinasb3901d52012-03-05 11:49:28 +00001/*
2 * Based on arch/arm/kernel/process.c
3 *
4 * Original Copyright (C) 1995 Linus Torvalds
5 * Copyright (C) 1996-2000 Russell King - Converted to ARM.
6 * Copyright (C) 2012 ARM Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21#include <stdarg.h>
22
AKASHI Takahirofd92d4a2014-04-30 10:51:32 +010023#include <linux/compat.h>
Ard Biesheuvel60c0d452015-03-06 15:49:24 +010024#include <linux/efi.h>
Catalin Marinasb3901d52012-03-05 11:49:28 +000025#include <linux/export.h>
26#include <linux/sched.h>
27#include <linux/kernel.h>
28#include <linux/mm.h>
29#include <linux/stddef.h>
30#include <linux/unistd.h>
31#include <linux/user.h>
32#include <linux/delay.h>
33#include <linux/reboot.h>
34#include <linux/interrupt.h>
35#include <linux/kallsyms.h>
36#include <linux/init.h>
37#include <linux/cpu.h>
38#include <linux/elfcore.h>
39#include <linux/pm.h>
40#include <linux/tick.h>
41#include <linux/utsname.h>
42#include <linux/uaccess.h>
43#include <linux/random.h>
44#include <linux/hw_breakpoint.h>
45#include <linux/personality.h>
46#include <linux/notifier.h>
Jisheng Zhang096b3222015-09-16 22:23:21 +080047#include <trace/events/power.h>
Catalin Marinasb3901d52012-03-05 11:49:28 +000048
James Morse57f49592016-02-05 14:58:48 +000049#include <asm/alternative.h>
Catalin Marinasb3901d52012-03-05 11:49:28 +000050#include <asm/compat.h>
51#include <asm/cacheflush.h>
James Morsed0854412016-10-18 11:27:48 +010052#include <asm/exec.h>
Will Deaconec45d1c2013-01-17 12:31:45 +000053#include <asm/fpsimd.h>
54#include <asm/mmu_context.h>
Catalin Marinasb3901d52012-03-05 11:49:28 +000055#include <asm/processor.h>
56#include <asm/stacktrace.h>
Catalin Marinasb3901d52012-03-05 11:49:28 +000057
Laura Abbottc0c264a2014-06-25 23:55:03 +010058#ifdef CONFIG_CC_STACKPROTECTOR
59#include <linux/stackprotector.h>
60unsigned long __stack_chk_guard __read_mostly;
61EXPORT_SYMBOL(__stack_chk_guard);
62#endif
63
Catalin Marinasb3901d52012-03-05 11:49:28 +000064/*
65 * Function pointers to optional machine specific functions
66 */
67void (*pm_power_off)(void);
68EXPORT_SYMBOL_GPL(pm_power_off);
69
Catalin Marinasb0946fc2013-07-23 11:05:10 +010070void (*arm_pm_restart)(enum reboot_mode reboot_mode, const char *cmd);
Catalin Marinasb3901d52012-03-05 11:49:28 +000071
Catalin Marinasb3901d52012-03-05 11:49:28 +000072/*
73 * This is our default idle handler.
74 */
Thomas Gleixner00872982013-03-21 22:49:39 +010075void arch_cpu_idle(void)
Catalin Marinasb3901d52012-03-05 11:49:28 +000076{
77 /*
78 * This should do all the clock switching and wait for interrupt
79 * tricks
80 */
Jisheng Zhang096b3222015-09-16 22:23:21 +080081 trace_cpu_idle_rcuidle(1, smp_processor_id());
Nicolas Pitre69905662014-02-17 10:59:30 -050082 cpu_do_idle();
83 local_irq_enable();
Jisheng Zhang096b3222015-09-16 22:23:21 +080084 trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
Catalin Marinasb3901d52012-03-05 11:49:28 +000085}
86
Mark Rutland9327e2c2013-10-24 20:30:18 +010087#ifdef CONFIG_HOTPLUG_CPU
88void arch_cpu_idle_dead(void)
89{
90 cpu_die();
91}
92#endif
93
Arun KS90f51a02014-05-07 02:41:22 +010094/*
95 * Called by kexec, immediately prior to machine_kexec().
96 *
97 * This must completely disable all secondary CPUs; simply causing those CPUs
98 * to execute e.g. a RAM-based pin loop is not sufficient. This allows the
99 * kexec'd kernel to use any and all RAM as it sees fit, without having to
100 * avoid any code or data used by any SW CPU pin loop. The CPU hotplug
101 * functionality embodied in disable_nonboot_cpus() to achieve this.
102 */
Catalin Marinasb3901d52012-03-05 11:49:28 +0000103void machine_shutdown(void)
104{
Arun KS90f51a02014-05-07 02:41:22 +0100105 disable_nonboot_cpus();
Catalin Marinasb3901d52012-03-05 11:49:28 +0000106}
107
Arun KS90f51a02014-05-07 02:41:22 +0100108/*
109 * Halting simply requires that the secondary CPUs stop performing any
110 * activity (executing tasks, handling interrupts). smp_send_stop()
111 * achieves this.
112 */
Catalin Marinasb3901d52012-03-05 11:49:28 +0000113void machine_halt(void)
114{
Arun KSb9acc492014-05-07 02:41:23 +0100115 local_irq_disable();
Arun KS90f51a02014-05-07 02:41:22 +0100116 smp_send_stop();
Catalin Marinasb3901d52012-03-05 11:49:28 +0000117 while (1);
118}
119
Arun KS90f51a02014-05-07 02:41:22 +0100120/*
121 * Power-off simply requires that the secondary CPUs stop performing any
122 * activity (executing tasks, handling interrupts). smp_send_stop()
123 * achieves this. When the system power is turned off, it will take all CPUs
124 * with it.
125 */
Catalin Marinasb3901d52012-03-05 11:49:28 +0000126void machine_power_off(void)
127{
Arun KSb9acc492014-05-07 02:41:23 +0100128 local_irq_disable();
Arun KS90f51a02014-05-07 02:41:22 +0100129 smp_send_stop();
Catalin Marinasb3901d52012-03-05 11:49:28 +0000130 if (pm_power_off)
131 pm_power_off();
132}
133
Arun KS90f51a02014-05-07 02:41:22 +0100134/*
135 * Restart requires that the secondary CPUs stop performing any activity
Mark Rutland68234df2015-04-20 10:24:35 +0100136 * while the primary CPU resets the system. Systems with multiple CPUs must
Arun KS90f51a02014-05-07 02:41:22 +0100137 * provide a HW restart implementation, to ensure that all CPUs reset at once.
138 * This is required so that any code running after reset on the primary CPU
139 * doesn't have to co-ordinate with other CPUs to ensure they aren't still
140 * executing pre-reset code, and using RAM that the primary CPU's code wishes
141 * to use. Implementing such co-ordination would be essentially impossible.
142 */
Catalin Marinasb3901d52012-03-05 11:49:28 +0000143void machine_restart(char *cmd)
144{
Catalin Marinasb3901d52012-03-05 11:49:28 +0000145 /* Disable interrupts first */
146 local_irq_disable();
Arun KSb9acc492014-05-07 02:41:23 +0100147 smp_send_stop();
Catalin Marinasb3901d52012-03-05 11:49:28 +0000148
Ard Biesheuvel60c0d452015-03-06 15:49:24 +0100149 /*
150 * UpdateCapsule() depends on the system being reset via
151 * ResetSystem().
152 */
153 if (efi_enabled(EFI_RUNTIME_SERVICES))
154 efi_reboot(reboot_mode, NULL);
155
Catalin Marinasb3901d52012-03-05 11:49:28 +0000156 /* Now call the architecture specific reboot code. */
Catalin Marinasaa1e8ec2013-02-28 18:14:37 +0000157 if (arm_pm_restart)
Marc Zyngierff701302013-07-11 12:13:00 +0100158 arm_pm_restart(reboot_mode, cmd);
Guenter Roeck1c7ffc32014-09-26 00:03:16 +0000159 else
160 do_kernel_restart(cmd);
Catalin Marinasb3901d52012-03-05 11:49:28 +0000161
162 /*
163 * Whoops - the architecture was unable to reboot.
164 */
165 printk("Reboot failed -- System halted\n");
166 while (1);
167}
168
169void __show_regs(struct pt_regs *regs)
170{
Catalin Marinas6ca68e82013-09-17 18:49:46 +0100171 int i, top_reg;
172 u64 lr, sp;
173
174 if (compat_user_mode(regs)) {
175 lr = regs->compat_lr;
176 sp = regs->compat_sp;
177 top_reg = 12;
178 } else {
179 lr = regs->regs[30];
180 sp = regs->sp;
181 top_reg = 29;
182 }
Catalin Marinasb3901d52012-03-05 11:49:28 +0000183
Tejun Heoa43cb952013-04-30 15:27:17 -0700184 show_regs_print_info(KERN_DEFAULT);
Catalin Marinasb3901d52012-03-05 11:49:28 +0000185 print_symbol("PC is at %s\n", instruction_pointer(regs));
Catalin Marinas6ca68e82013-09-17 18:49:46 +0100186 print_symbol("LR is at %s\n", lr);
Catalin Marinasb3901d52012-03-05 11:49:28 +0000187 printk("pc : [<%016llx>] lr : [<%016llx>] pstate: %08llx\n",
Catalin Marinas6ca68e82013-09-17 18:49:46 +0100188 regs->pc, lr, regs->pstate);
189 printk("sp : %016llx\n", sp);
Mark Rutlanddb4b0712016-10-20 12:23:16 +0100190
191 i = top_reg;
192
193 while (i >= 0) {
Catalin Marinasb3901d52012-03-05 11:49:28 +0000194 printk("x%-2d: %016llx ", i, regs->regs[i]);
Mark Rutlanddb4b0712016-10-20 12:23:16 +0100195 i--;
196
197 if (i % 2 == 0) {
198 pr_cont("x%-2d: %016llx ", i, regs->regs[i]);
199 i--;
200 }
201
202 pr_cont("\n");
Catalin Marinasb3901d52012-03-05 11:49:28 +0000203 }
204 printk("\n");
205}
206
207void show_regs(struct pt_regs * regs)
208{
209 printk("\n");
Catalin Marinasb3901d52012-03-05 11:49:28 +0000210 __show_regs(regs);
211}
212
Will Deaconeb35bdd2014-09-11 14:38:16 +0100213static void tls_thread_flush(void)
214{
Mark Rutlandadf75892016-09-08 13:55:38 +0100215 write_sysreg(0, tpidr_el0);
Will Deaconeb35bdd2014-09-11 14:38:16 +0100216
217 if (is_compat_task()) {
218 current->thread.tp_value = 0;
219
220 /*
221 * We need to ensure ordering between the shadow state and the
222 * hardware state, so that we don't corrupt the hardware state
223 * with a stale shadow state during context switch.
224 */
225 barrier();
Mark Rutlandadf75892016-09-08 13:55:38 +0100226 write_sysreg(0, tpidrro_el0);
Will Deaconeb35bdd2014-09-11 14:38:16 +0100227 }
228}
229
Catalin Marinasb3901d52012-03-05 11:49:28 +0000230void flush_thread(void)
231{
232 fpsimd_flush_thread();
Will Deaconeb35bdd2014-09-11 14:38:16 +0100233 tls_thread_flush();
Catalin Marinasb3901d52012-03-05 11:49:28 +0000234 flush_ptrace_hw_breakpoint(current);
235}
236
237void release_thread(struct task_struct *dead_task)
238{
239}
240
241int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
242{
Janet Liu6eb6c802015-06-11 12:04:32 +0800243 if (current->mm)
244 fpsimd_preserve_current_state();
Catalin Marinasb3901d52012-03-05 11:49:28 +0000245 *dst = *src;
246 return 0;
247}
248
249asmlinkage void ret_from_fork(void) asm("ret_from_fork");
250
251int copy_thread(unsigned long clone_flags, unsigned long stack_start,
Al Viroafa86fc2012-10-22 22:51:14 -0400252 unsigned long stk_sz, struct task_struct *p)
Catalin Marinasb3901d52012-03-05 11:49:28 +0000253{
254 struct pt_regs *childregs = task_pt_regs(p);
Catalin Marinasb3901d52012-03-05 11:49:28 +0000255
Catalin Marinasb3901d52012-03-05 11:49:28 +0000256 memset(&p->thread.cpu_context, 0, sizeof(struct cpu_context));
Catalin Marinasb3901d52012-03-05 11:49:28 +0000257
Dave Martina3922412017-12-05 14:56:42 +0000258 /*
259 * In case p was allocated the same task_struct pointer as some
260 * other recently-exited task, make sure p is disassociated from
261 * any cpu that may have run that now-exited task recently.
262 * Otherwise we could erroneously skip reloading the FPSIMD
263 * registers for p.
264 */
265 fpsimd_flush_task_state(p);
266
Al Viro9ac08002012-10-21 15:56:52 -0400267 if (likely(!(p->flags & PF_KTHREAD))) {
268 *childregs = *current_pt_regs();
Catalin Marinasc34501d2012-10-05 12:31:20 +0100269 childregs->regs[0] = 0;
Will Deacond00a3812015-05-27 15:39:40 +0100270
271 /*
272 * Read the current TLS pointer from tpidr_el0 as it may be
273 * out-of-sync with the saved value.
274 */
Mark Rutlandadf75892016-09-08 13:55:38 +0100275 *task_user_tls(p) = read_sysreg(tpidr_el0);
Will Deacond00a3812015-05-27 15:39:40 +0100276
277 if (stack_start) {
278 if (is_compat_thread(task_thread_info(p)))
Al Viroe0fd18c2012-10-18 00:55:54 -0400279 childregs->compat_sp = stack_start;
Will Deacond00a3812015-05-27 15:39:40 +0100280 else
Al Viroe0fd18c2012-10-18 00:55:54 -0400281 childregs->sp = stack_start;
Catalin Marinasc34501d2012-10-05 12:31:20 +0100282 }
Will Deacond00a3812015-05-27 15:39:40 +0100283
Catalin Marinasc34501d2012-10-05 12:31:20 +0100284 /*
285 * If a TLS pointer was passed to clone (4th argument), use it
286 * for the new thread.
287 */
288 if (clone_flags & CLONE_SETTLS)
Will Deacond00a3812015-05-27 15:39:40 +0100289 p->thread.tp_value = childregs->regs[3];
Catalin Marinasc34501d2012-10-05 12:31:20 +0100290 } else {
291 memset(childregs, 0, sizeof(struct pt_regs));
292 childregs->pstate = PSR_MODE_EL1h;
James Morse57f49592016-02-05 14:58:48 +0000293 if (IS_ENABLED(CONFIG_ARM64_UAO) &&
Suzuki K Poulosefe64d7d2016-11-08 13:56:20 +0000294 cpus_have_const_cap(ARM64_HAS_UAO))
James Morse57f49592016-02-05 14:58:48 +0000295 childregs->pstate |= PSR_UAO_BIT;
Catalin Marinasc34501d2012-10-05 12:31:20 +0100296 p->thread.cpu_context.x19 = stack_start;
297 p->thread.cpu_context.x20 = stk_sz;
298 }
299 p->thread.cpu_context.pc = (unsigned long)ret_from_fork;
300 p->thread.cpu_context.sp = (unsigned long)childregs;
Catalin Marinasb3901d52012-03-05 11:49:28 +0000301
302 ptrace_hw_copy_thread(p);
303
304 return 0;
305}
306
307static void tls_thread_switch(struct task_struct *next)
308{
Will Deacon6e7fb7c2018-04-03 12:09:08 +0100309 unsigned long tpidr;
Catalin Marinasb3901d52012-03-05 11:49:28 +0000310
Mark Rutlandadf75892016-09-08 13:55:38 +0100311 tpidr = read_sysreg(tpidr_el0);
Will Deacond00a3812015-05-27 15:39:40 +0100312 *task_user_tls(current) = tpidr;
Catalin Marinasb3901d52012-03-05 11:49:28 +0000313
Will Deacon6e7fb7c2018-04-03 12:09:08 +0100314 if (is_compat_thread(task_thread_info(next)))
315 write_sysreg(next->thread.tp_value, tpidrro_el0);
316 else if (!arm64_kernel_unmapped_at_el0())
317 write_sysreg(0, tpidrro_el0);
Catalin Marinasb3901d52012-03-05 11:49:28 +0000318
Will Deacon6e7fb7c2018-04-03 12:09:08 +0100319 write_sysreg(*task_user_tls(next), tpidr_el0);
Catalin Marinasb3901d52012-03-05 11:49:28 +0000320}
321
James Morse57f49592016-02-05 14:58:48 +0000322/* Restore the UAO state depending on next's addr_limit */
James Morsed0854412016-10-18 11:27:48 +0100323void uao_thread_switch(struct task_struct *next)
James Morse57f49592016-02-05 14:58:48 +0000324{
Catalin Marinase9506312016-02-18 15:50:04 +0000325 if (IS_ENABLED(CONFIG_ARM64_UAO)) {
326 if (task_thread_info(next)->addr_limit == KERNEL_DS)
327 asm(ALTERNATIVE("nop", SET_PSTATE_UAO(1), ARM64_HAS_UAO));
328 else
329 asm(ALTERNATIVE("nop", SET_PSTATE_UAO(0), ARM64_HAS_UAO));
330 }
James Morse57f49592016-02-05 14:58:48 +0000331}
332
Catalin Marinasb3901d52012-03-05 11:49:28 +0000333/*
334 * Thread switching.
335 */
336struct task_struct *__switch_to(struct task_struct *prev,
337 struct task_struct *next)
338{
339 struct task_struct *last;
340
341 fpsimd_thread_switch(next);
342 tls_thread_switch(next);
343 hw_breakpoint_thread_switch(next);
Christopher Covington33257322013-04-03 19:01:01 +0100344 contextidr_thread_switch(next);
James Morse57f49592016-02-05 14:58:48 +0000345 uao_thread_switch(next);
Catalin Marinasb3901d52012-03-05 11:49:28 +0000346
Catalin Marinas5108c672013-04-24 14:47:02 +0100347 /*
348 * Complete any pending TLB or cache maintenance on this CPU in case
349 * the thread migrates to a different CPU.
350 */
Will Deacon98f76852014-05-02 16:24:10 +0100351 dsb(ish);
Catalin Marinasb3901d52012-03-05 11:49:28 +0000352
353 /* the actual thread switch */
354 last = cpu_switch_to(prev, next);
355
356 return last;
357}
358
Catalin Marinasb3901d52012-03-05 11:49:28 +0000359unsigned long get_wchan(struct task_struct *p)
360{
361 struct stackframe frame;
Konstantin Khlebnikov408c3652013-12-05 13:30:10 +0000362 unsigned long stack_page;
Catalin Marinasb3901d52012-03-05 11:49:28 +0000363 int count = 0;
364 if (!p || p == current || p->state == TASK_RUNNING)
365 return 0;
366
367 frame.fp = thread_saved_fp(p);
368 frame.sp = thread_saved_sp(p);
369 frame.pc = thread_saved_pc(p);
AKASHI Takahiro20380bb2015-12-15 17:33:41 +0900370#ifdef CONFIG_FUNCTION_GRAPH_TRACER
371 frame.graph = p->curr_ret_stack;
372#endif
Konstantin Khlebnikov408c3652013-12-05 13:30:10 +0000373 stack_page = (unsigned long)task_stack_page(p);
Catalin Marinasb3901d52012-03-05 11:49:28 +0000374 do {
Konstantin Khlebnikov408c3652013-12-05 13:30:10 +0000375 if (frame.sp < stack_page ||
376 frame.sp >= stack_page + THREAD_SIZE ||
AKASHI Takahirofe13f952015-12-15 17:33:40 +0900377 unwind_frame(p, &frame))
Catalin Marinasb3901d52012-03-05 11:49:28 +0000378 return 0;
379 if (!in_sched_functions(frame.pc))
380 return frame.pc;
381 } while (count ++ < 16);
382 return 0;
383}
384
385unsigned long arch_align_stack(unsigned long sp)
386{
387 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
388 sp -= get_random_int() & ~PAGE_MASK;
389 return sp & ~0xf;
390}
391
Catalin Marinasb3901d52012-03-05 11:49:28 +0000392unsigned long arch_randomize_brk(struct mm_struct *mm)
393{
Kees Cook61462c82016-05-10 10:55:49 -0700394 if (is_compat_task())
Jason Cooperfa5114c2016-10-11 13:54:02 -0700395 return randomize_page(mm->brk, 0x02000000);
Kees Cook61462c82016-05-10 10:55:49 -0700396 else
Jason Cooperfa5114c2016-10-11 13:54:02 -0700397 return randomize_page(mm->brk, 0x40000000);
Catalin Marinasb3901d52012-03-05 11:49:28 +0000398}