Catalin Marinas | 382266a | 2007-02-05 14:48:19 +0100 | [diff] [blame] | 1 | /* |
| 2 | * arch/arm/mm/cache-l2x0.c - L210/L220 cache controller support |
| 3 | * |
| 4 | * Copyright (C) 2007 ARM Limited |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 18 | */ |
| 19 | #include <linux/init.h> |
Catalin Marinas | 0762097 | 2007-07-20 11:42:40 +0100 | [diff] [blame] | 20 | #include <linux/spinlock.h> |
Russell King | fced80c | 2008-09-06 12:10:45 +0100 | [diff] [blame] | 21 | #include <linux/io.h> |
Catalin Marinas | 382266a | 2007-02-05 14:48:19 +0100 | [diff] [blame] | 22 | |
| 23 | #include <asm/cacheflush.h> |
Catalin Marinas | 382266a | 2007-02-05 14:48:19 +0100 | [diff] [blame] | 24 | #include <asm/hardware/cache-l2x0.h> |
| 25 | |
| 26 | #define CACHE_LINE_SIZE 32 |
| 27 | |
| 28 | static void __iomem *l2x0_base; |
Catalin Marinas | 0762097 | 2007-07-20 11:42:40 +0100 | [diff] [blame] | 29 | static DEFINE_SPINLOCK(l2x0_lock); |
Catalin Marinas | 382266a | 2007-02-05 14:48:19 +0100 | [diff] [blame] | 30 | |
| 31 | static inline void sync_writel(unsigned long val, unsigned long reg, |
| 32 | unsigned long complete_mask) |
| 33 | { |
| 34 | writel(val, l2x0_base + reg); |
| 35 | /* wait for the operation to complete */ |
| 36 | while (readl(l2x0_base + reg) & complete_mask) |
| 37 | ; |
Catalin Marinas | 382266a | 2007-02-05 14:48:19 +0100 | [diff] [blame] | 38 | } |
| 39 | |
| 40 | static inline void cache_sync(void) |
| 41 | { |
| 42 | sync_writel(0, L2X0_CACHE_SYNC, 1); |
| 43 | } |
| 44 | |
| 45 | static inline void l2x0_inv_all(void) |
| 46 | { |
Russell King | 0eb948d | 2009-11-19 11:12:15 +0000 | [diff] [blame^] | 47 | unsigned long flags; |
| 48 | |
Catalin Marinas | 382266a | 2007-02-05 14:48:19 +0100 | [diff] [blame] | 49 | /* invalidate all ways */ |
Russell King | 0eb948d | 2009-11-19 11:12:15 +0000 | [diff] [blame^] | 50 | spin_lock_irqsave(&l2x0_lock, flags); |
Catalin Marinas | 382266a | 2007-02-05 14:48:19 +0100 | [diff] [blame] | 51 | sync_writel(0xff, L2X0_INV_WAY, 0xff); |
| 52 | cache_sync(); |
Russell King | 0eb948d | 2009-11-19 11:12:15 +0000 | [diff] [blame^] | 53 | spin_unlock_irqrestore(&l2x0_lock, flags); |
Catalin Marinas | 382266a | 2007-02-05 14:48:19 +0100 | [diff] [blame] | 54 | } |
| 55 | |
| 56 | static void l2x0_inv_range(unsigned long start, unsigned long end) |
| 57 | { |
Russell King | 0eb948d | 2009-11-19 11:12:15 +0000 | [diff] [blame^] | 58 | unsigned long flags; |
Catalin Marinas | 382266a | 2007-02-05 14:48:19 +0100 | [diff] [blame] | 59 | |
Russell King | 0eb948d | 2009-11-19 11:12:15 +0000 | [diff] [blame^] | 60 | spin_lock_irqsave(&l2x0_lock, flags); |
Rui Sousa | 4f6627a | 2007-09-15 00:56:19 +0100 | [diff] [blame] | 61 | if (start & (CACHE_LINE_SIZE - 1)) { |
| 62 | start &= ~(CACHE_LINE_SIZE - 1); |
| 63 | sync_writel(start, L2X0_CLEAN_INV_LINE_PA, 1); |
| 64 | start += CACHE_LINE_SIZE; |
| 65 | } |
| 66 | |
| 67 | if (end & (CACHE_LINE_SIZE - 1)) { |
| 68 | end &= ~(CACHE_LINE_SIZE - 1); |
| 69 | sync_writel(end, L2X0_CLEAN_INV_LINE_PA, 1); |
| 70 | } |
| 71 | |
Russell King | 0eb948d | 2009-11-19 11:12:15 +0000 | [diff] [blame^] | 72 | while (start < end) { |
| 73 | unsigned long blk_end = start + min(end - start, 4096UL); |
| 74 | |
| 75 | while (start < blk_end) { |
| 76 | sync_writel(start, L2X0_INV_LINE_PA, 1); |
| 77 | start += CACHE_LINE_SIZE; |
| 78 | } |
| 79 | |
| 80 | if (blk_end < end) { |
| 81 | spin_unlock_irqrestore(&l2x0_lock, flags); |
| 82 | spin_lock_irqsave(&l2x0_lock, flags); |
| 83 | } |
| 84 | } |
Catalin Marinas | 382266a | 2007-02-05 14:48:19 +0100 | [diff] [blame] | 85 | cache_sync(); |
Russell King | 0eb948d | 2009-11-19 11:12:15 +0000 | [diff] [blame^] | 86 | spin_unlock_irqrestore(&l2x0_lock, flags); |
Catalin Marinas | 382266a | 2007-02-05 14:48:19 +0100 | [diff] [blame] | 87 | } |
| 88 | |
| 89 | static void l2x0_clean_range(unsigned long start, unsigned long end) |
| 90 | { |
Russell King | 0eb948d | 2009-11-19 11:12:15 +0000 | [diff] [blame^] | 91 | unsigned long flags; |
Catalin Marinas | 382266a | 2007-02-05 14:48:19 +0100 | [diff] [blame] | 92 | |
Russell King | 0eb948d | 2009-11-19 11:12:15 +0000 | [diff] [blame^] | 93 | spin_lock_irqsave(&l2x0_lock, flags); |
Catalin Marinas | 382266a | 2007-02-05 14:48:19 +0100 | [diff] [blame] | 94 | start &= ~(CACHE_LINE_SIZE - 1); |
Russell King | 0eb948d | 2009-11-19 11:12:15 +0000 | [diff] [blame^] | 95 | while (start < end) { |
| 96 | unsigned long blk_end = start + min(end - start, 4096UL); |
| 97 | |
| 98 | while (start < blk_end) { |
| 99 | sync_writel(start, L2X0_CLEAN_LINE_PA, 1); |
| 100 | start += CACHE_LINE_SIZE; |
| 101 | } |
| 102 | |
| 103 | if (blk_end < end) { |
| 104 | spin_unlock_irqrestore(&l2x0_lock, flags); |
| 105 | spin_lock_irqsave(&l2x0_lock, flags); |
| 106 | } |
| 107 | } |
Catalin Marinas | 382266a | 2007-02-05 14:48:19 +0100 | [diff] [blame] | 108 | cache_sync(); |
Russell King | 0eb948d | 2009-11-19 11:12:15 +0000 | [diff] [blame^] | 109 | spin_unlock_irqrestore(&l2x0_lock, flags); |
Catalin Marinas | 382266a | 2007-02-05 14:48:19 +0100 | [diff] [blame] | 110 | } |
| 111 | |
| 112 | static void l2x0_flush_range(unsigned long start, unsigned long end) |
| 113 | { |
Russell King | 0eb948d | 2009-11-19 11:12:15 +0000 | [diff] [blame^] | 114 | unsigned long flags; |
Catalin Marinas | 382266a | 2007-02-05 14:48:19 +0100 | [diff] [blame] | 115 | |
Russell King | 0eb948d | 2009-11-19 11:12:15 +0000 | [diff] [blame^] | 116 | spin_lock_irqsave(&l2x0_lock, flags); |
Catalin Marinas | 382266a | 2007-02-05 14:48:19 +0100 | [diff] [blame] | 117 | start &= ~(CACHE_LINE_SIZE - 1); |
Russell King | 0eb948d | 2009-11-19 11:12:15 +0000 | [diff] [blame^] | 118 | while (start < end) { |
| 119 | unsigned long blk_end = start + min(end - start, 4096UL); |
| 120 | |
| 121 | while (start < blk_end) { |
| 122 | sync_writel(start, L2X0_CLEAN_INV_LINE_PA, 1); |
| 123 | start += CACHE_LINE_SIZE; |
| 124 | } |
| 125 | |
| 126 | if (blk_end < end) { |
| 127 | spin_unlock_irqrestore(&l2x0_lock, flags); |
| 128 | spin_lock_irqsave(&l2x0_lock, flags); |
| 129 | } |
| 130 | } |
Catalin Marinas | 382266a | 2007-02-05 14:48:19 +0100 | [diff] [blame] | 131 | cache_sync(); |
Russell King | 0eb948d | 2009-11-19 11:12:15 +0000 | [diff] [blame^] | 132 | spin_unlock_irqrestore(&l2x0_lock, flags); |
Catalin Marinas | 382266a | 2007-02-05 14:48:19 +0100 | [diff] [blame] | 133 | } |
| 134 | |
| 135 | void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask) |
| 136 | { |
| 137 | __u32 aux; |
| 138 | |
| 139 | l2x0_base = base; |
| 140 | |
| 141 | /* disable L2X0 */ |
| 142 | writel(0, l2x0_base + L2X0_CTRL); |
| 143 | |
| 144 | aux = readl(l2x0_base + L2X0_AUX_CTRL); |
| 145 | aux &= aux_mask; |
| 146 | aux |= aux_val; |
| 147 | writel(aux, l2x0_base + L2X0_AUX_CTRL); |
| 148 | |
| 149 | l2x0_inv_all(); |
| 150 | |
| 151 | /* enable L2X0 */ |
| 152 | writel(1, l2x0_base + L2X0_CTRL); |
| 153 | |
| 154 | outer_cache.inv_range = l2x0_inv_range; |
| 155 | outer_cache.clean_range = l2x0_clean_range; |
| 156 | outer_cache.flush_range = l2x0_flush_range; |
| 157 | |
| 158 | printk(KERN_INFO "L2X0 cache controller enabled\n"); |
| 159 | } |