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gerrit-public.fairphone.software / kernel / msm-4.9 / 0ee4c1a87b5c2a1b4a2b951212a1524152556004 / . / drivers / power / supply / qcom / fg-reg.h
blob: 8ca437698e458f3d96548a751b565dcb924b996c [file] [log] [blame]
Subbaraman Narayanamurthyfb4997c2017-01-05 10:59:03 -0800[diff] [blame]1/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
Subbaraman Narayanamurthy6accb262016-03-14 16:41:16 -0700[diff] [blame]2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#ifndef __FG_REG_H__
14#define __FG_REG_H__
15
Subbaraman Narayanamurthy243fc3f2016-11-28 16:05:09 -0800[diff] [blame]16/* FG_ADC_RR register definitions used only for READ */
17#define ADC_RR_FAKE_BATT_LOW_LSB(chip) (chip->rradc_base + 0x58)
18#define ADC_RR_FAKE_BATT_HIGH_LSB(chip) (chip->rradc_base + 0x5A)
19
Subbaraman Narayanamurthy6accb262016-03-14 16:41:16 -0700[diff] [blame]20/* FG_BATT_SOC register definitions */
21#define BATT_SOC_FG_ALG_STS(chip) (chip->batt_soc_base + 0x06)
22#define BATT_SOC_FG_ALG_AUX_STS0(chip) (chip->batt_soc_base + 0x07)
23#define BATT_SOC_SLEEP_SHUTDOWN_STS(chip) (chip->batt_soc_base + 0x08)
24#define BATT_SOC_FG_MONOTONIC_SOC(chip) (chip->batt_soc_base + 0x09)
25#define BATT_SOC_FG_MONOTONIC_SOC_CP(chip) (chip->batt_soc_base + 0x0A)
26#define BATT_SOC_INT_RT_STS(chip) (chip->batt_soc_base + 0x10)
27#define BATT_SOC_EN_CTL(chip) (chip->batt_soc_base + 0x46)
28#define BATT_SOC_RESTART(chip) (chip->batt_soc_base + 0x48)
29#define BATT_SOC_STS_CLR(chip) (chip->batt_soc_base + 0x4A)
30#define BATT_SOC_LOW_PWR_CFG(chip) (chip->batt_soc_base + 0x52)
31#define BATT_SOC_LOW_PWR_STS(chip) (chip->batt_soc_base + 0x56)
32
Subbaraman Narayanamurthy03e6c612016-11-09 16:40:27 -0800[diff] [blame]33/* BATT_SOC_INT_RT_STS */
Subbaraman Narayanamurthy2d62e9e2017-06-02 17:40:28 -0700[diff] [blame]34#define SOC_READY_BIT BIT(1)
Subbaraman Narayanamurthy03e6c612016-11-09 16:40:27 -0800[diff] [blame]35#define MSOC_EMPTY_BIT BIT(5)
36
Subbaraman Narayanamurthy6accb262016-03-14 16:41:16 -0700[diff] [blame]37/* BATT_SOC_EN_CTL */
38#define FG_ALGORITHM_EN_BIT BIT(7)
39
40/* BATT_SOC_RESTART */
41#define RESTART_GO_BIT BIT(0)
42
43/* FG_BATT_INFO register definitions */
44#define BATT_INFO_BATT_TEMP_STS(chip) (chip->batt_info_base + 0x06)
45#define BATT_INFO_SYS_BATT(chip) (chip->batt_info_base + 0x07)
46#define BATT_INFO_FG_STS(chip) (chip->batt_info_base + 0x09)
47#define BATT_INFO_INT_RT_STS(chip) (chip->batt_info_base + 0x10)
48#define BATT_INFO_BATT_REM_LATCH(chip) (chip->batt_info_base + 0x4F)
49#define BATT_INFO_BATT_TEMP_LSB(chip) (chip->batt_info_base + 0x50)
50#define BATT_INFO_BATT_TEMP_MSB(chip) (chip->batt_info_base + 0x51)
51#define BATT_INFO_BATT_TEMP_CFG(chip) (chip->batt_info_base + 0x56)
52#define BATT_INFO_BATT_TMPR_INTR(chip) (chip->batt_info_base + 0x59)
53#define BATT_INFO_THERM_C1(chip) (chip->batt_info_base + 0x5C)
54#define BATT_INFO_THERM_C2(chip) (chip->batt_info_base + 0x5D)
55#define BATT_INFO_THERM_C3(chip) (chip->batt_info_base + 0x5E)
56#define BATT_INFO_THERM_HALF_RANGE(chip) (chip->batt_info_base + 0x5F)
57#define BATT_INFO_JEITA_CTLS(chip) (chip->batt_info_base + 0x61)
58#define BATT_INFO_JEITA_TOO_COLD(chip) (chip->batt_info_base + 0x62)
59#define BATT_INFO_JEITA_COLD(chip) (chip->batt_info_base + 0x63)
60#define BATT_INFO_JEITA_HOT(chip) (chip->batt_info_base + 0x64)
61#define BATT_INFO_JEITA_TOO_HOT(chip) (chip->batt_info_base + 0x65)
62
63/* only for v1.1 */
64#define BATT_INFO_ESR_CFG(chip) (chip->batt_info_base + 0x69)
65/* starting from v2.0 */
66#define BATT_INFO_ESR_GENERAL_CFG(chip) (chip->batt_info_base + 0x68)
67#define BATT_INFO_ESR_PULL_DN_CFG(chip) (chip->batt_info_base + 0x69)
68#define BATT_INFO_ESR_FAST_CRG_CFG(chip) (chip->batt_info_base + 0x6A)
69
70#define BATT_INFO_BATT_MISS_CFG(chip) (chip->batt_info_base + 0x6B)
71#define BATT_INFO_WATCHDOG_COUNT(chip) (chip->batt_info_base + 0x70)
72#define BATT_INFO_WATCHDOG_CFG(chip) (chip->batt_info_base + 0x71)
73#define BATT_INFO_IBATT_SENSING_CFG(chip) (chip->batt_info_base + 0x73)
74#define BATT_INFO_QNOVO_CFG(chip) (chip->batt_info_base + 0x74)
75#define BATT_INFO_QNOVO_SCALER(chip) (chip->batt_info_base + 0x75)
76
77/* starting from v2.0 */
78#define BATT_INFO_CRG_SERVICES(chip) (chip->batt_info_base + 0x90)
79
80/* Following LSB/MSB address are for v2.0 and above; v1.1 have them swapped */
81#define BATT_INFO_VBATT_LSB(chip) (chip->batt_info_base + 0xA0)
82#define BATT_INFO_VBATT_MSB(chip) (chip->batt_info_base + 0xA1)
83#define BATT_INFO_IBATT_LSB(chip) (chip->batt_info_base + 0xA2)
84#define BATT_INFO_IBATT_MSB(chip) (chip->batt_info_base + 0xA3)
85#define BATT_INFO_ESR_LSB(chip) (chip->batt_info_base + 0xA4)
86#define BATT_INFO_ESR_MSB(chip) (chip->batt_info_base + 0xA5)
87#define BATT_INFO_VBATT_LSB_CP(chip) (chip->batt_info_base + 0xA6)
88#define BATT_INFO_VBATT_MSB_CP(chip) (chip->batt_info_base + 0xA7)
89#define BATT_INFO_IBATT_LSB_CP(chip) (chip->batt_info_base + 0xA8)
90#define BATT_INFO_IBATT_MSB_CP(chip) (chip->batt_info_base + 0xA9)
91#define BATT_INFO_ESR_LSB_CP(chip) (chip->batt_info_base + 0xAA)
92#define BATT_INFO_ESR_MSB_CP(chip) (chip->batt_info_base + 0xAB)
93#define BATT_INFO_VADC_LSB(chip) (chip->batt_info_base + 0xAC)
94#define BATT_INFO_VADC_MSB(chip) (chip->batt_info_base + 0xAD)
95#define BATT_INFO_IADC_LSB(chip) (chip->batt_info_base + 0xAE)
96#define BATT_INFO_IADC_MSB(chip) (chip->batt_info_base + 0xAF)
97#define BATT_INFO_TM_MISC(chip) (chip->batt_info_base + 0xE5)
98#define BATT_INFO_TM_MISC1(chip) (chip->batt_info_base + 0xE6)
99
100/* BATT_INFO_BATT_TEMP_STS */
101#define JEITA_TOO_HOT_STS_BIT BIT(7)
102#define JEITA_HOT_STS_BIT BIT(6)
103#define JEITA_COLD_STS_BIT BIT(5)
104#define JEITA_TOO_COLD_STS_BIT BIT(4)
105#define BATT_TEMP_DELTA_BIT BIT(1)
106#define BATT_TEMP_AVAIL_BIT BIT(0)
107
108/* BATT_INFO_SYS_BATT */
109#define BATT_REM_LATCH_STS_BIT BIT(4)
110#define BATT_MISSING_HW_BIT BIT(2)
111#define BATT_MISSING_ALG_BIT BIT(1)
112#define BATT_MISSING_CMP_BIT BIT(0)
113
114/* BATT_INFO_FG_STS */
115#define FG_WD_RESET_BIT BIT(7)
116/* This bit is not present in v1.1 */
117#define FG_CRG_TRM_BIT BIT(0)
118
119/* BATT_INFO_INT_RT_STS */
120#define BT_TMPR_DELTA_BIT BIT(6)
121#define WDOG_EXP_BIT BIT(5)
122#define BT_ATTN_BIT BIT(4)
123#define BT_MISS_BIT BIT(3)
124#define ESR_DELTA_BIT BIT(2)
125#define VBT_LOW_BIT BIT(1)
126#define VBT_PRD_DELTA_BIT BIT(0)
127
128/* BATT_INFO_INT_RT_STS */
129#define BATT_REM_LATCH_CLR_BIT BIT(7)
130
131/* BATT_INFO_BATT_TEMP_LSB/MSB */
132#define BATT_TEMP_LSB_MASK GENMASK(7, 0)
133#define BATT_TEMP_MSB_MASK GENMASK(2, 0)
134
135/* BATT_INFO_BATT_TEMP_CFG */
136#define JEITA_TEMP_HYST_MASK GENMASK(5, 4)
Subbaraman Narayanamurthy65ff45e2016-09-23 19:11:17 -0700[diff] [blame]137#define JEITA_TEMP_HYST_SHIFT 4
Subbaraman Narayanamurthy6accb262016-03-14 16:41:16 -0700[diff] [blame]138#define JEITA_TEMP_NO_HYST 0x0
139#define JEITA_TEMP_HYST_1C 0x1
140#define JEITA_TEMP_HYST_2C 0x2
141#define JEITA_TEMP_HYST_3C 0x3
142
143/* BATT_INFO_BATT_TMPR_INTR */
144#define CHANGE_THOLD_MASK GENMASK(1, 0)
145#define BTEMP_DELTA_2K 0x0
146#define BTEMP_DELTA_4K 0x1
147#define BTEMP_DELTA_6K 0x2
148#define BTEMP_DELTA_10K 0x3
149
150/* BATT_INFO_THERM_C1/C2/C3 */
151#define BATT_INFO_THERM_COEFF_MASK GENMASK(7, 0)
152
153/* BATT_INFO_THERM_HALF_RANGE */
154#define BATT_INFO_THERM_TEMP_MASK GENMASK(7, 0)
155
156/* BATT_INFO_JEITA_CTLS */
157#define JEITA_STS_CLEAR_BIT BIT(0)
158
159/* BATT_INFO_JEITA_TOO_COLD/COLD/HOT/TOO_HOT */
160#define JEITA_THOLD_MASK GENMASK(7, 0)
161
162/* BATT_INFO_ESR_CFG */
163#define CFG_ACTIVE_PD_MASK GENMASK(2, 1)
164#define CFG_FCC_DEC_MASK GENMASK(4, 3)
165
166/* BATT_INFO_ESR_GENERAL_CFG */
167#define ESR_DEEP_TAPER_EN_BIT BIT(0)
168
169/* BATT_INFO_ESR_PULL_DN_CFG */
170#define ESR_PULL_DOWN_IVAL_MASK GENMASK(3, 2)
Subbaraman Narayanamurthye14037f2017-03-16 19:14:58 -0700[diff] [blame]171#define ESR_PULL_DOWN_IVAL_SHIFT 2
Subbaraman Narayanamurthy6accb262016-03-14 16:41:16 -0700[diff] [blame]172#define ESR_MEAS_CUR_60MA 0x0
173#define ESR_MEAS_CUR_120MA 0x1
174#define ESR_MEAS_CUR_180MA 0x2
175#define ESR_MEAS_CUR_240MA 0x3
176#define ESR_PULL_DOWN_MODE_MASK GENMASK(1, 0)
177#define ESR_NO_PULL_DOWN 0x0
178#define ESR_STATIC_PULL_DOWN 0x1
179#define ESR_CRG_DSC_PULL_DOWN 0x2
180#define ESR_DSC_PULL_DOWN 0x3
181
182/* BATT_INFO_ESR_FAST_CRG_CFG */
183#define ESR_FAST_CRG_IVAL_MASK GENMASK(3, 1)
184#define ESR_FCC_300MA 0x0
185#define ESR_FCC_600MA 0x1
186#define ESR_FCC_1A 0x2
187#define ESR_FCC_2A 0x3
188#define ESR_FCC_3A 0x4
189#define ESR_FCC_4A 0x5
190#define ESR_FCC_5A 0x6
191#define ESR_FCC_6A 0x7
192#define ESR_FAST_CRG_CTL_EN_BIT BIT(0)
193
194/* BATT_INFO_BATT_MISS_CFG */
195#define BM_THERM_TH_MASK GENMASK(5, 4)
196#define RES_TH_0P75_MOHM 0x0
197#define RES_TH_1P00_MOHM 0x1
198#define RES_TH_1P50_MOHM 0x2
199#define RES_TH_3P00_MOHM 0x3
200#define BM_BATT_ID_TH_MASK GENMASK(3, 2)
201#define BM_FROM_THERM_BIT BIT(1)
202#define BM_FROM_BATT_ID_BIT BIT(0)
203
204/* BATT_INFO_WATCHDOG_COUNT */
205#define WATCHDOG_COUNTER GENMASK(7, 0)
206
207/* BATT_INFO_WATCHDOG_CFG */
208#define RESET_CAPABLE_BIT BIT(2)
209#define PET_CTRL_BIT BIT(1)
210#define ENABLE_CTRL_BIT BIT(0)
211
212/* BATT_INFO_IBATT_SENSING_CFG */
213#define ADC_BITSTREAM_INV_BIT BIT(4)
214#define SOURCE_SELECT_MASK GENMASK(1, 0)
215#define SRC_SEL_BATFET 0x0
Subbaraman Narayanamurthy6accb262016-03-14 16:41:16 -0700[diff] [blame]216#define SRC_SEL_BATFET_SMB 0x2
217#define SRC_SEL_RESERVED 0x3
218
219/* BATT_INFO_QNOVO_CFG */
220#define LD_REG_FORCE_CTL_BIT BIT(2)
221#define LD_REG_CTRL_FORCE_HIGH LD_REG_FORCE_CTL_BIT
222#define LD_REG_CTRL_FORCE_LOW 0
223#define LD_REG_CTRL_BIT BIT(1)
224#define LD_REG_CTRL_REGISTER LD_REG_CTRL_BIT
225#define LD_REG_CTRL_LOGIC 0
226#define BIT_STREAM_CFG_BIT BIT(0)
227
228/* BATT_INFO_QNOVO_SCALER */
229#define QNOVO_SCALER_MASK GENMASK(7, 0)
230
231/* BATT_INFO_CRG_SERVICES */
232#define FG_CRC_TRM_EN_BIT BIT(0)
233
234/* BATT_INFO_VBATT_LSB/MSB */
235#define VBATT_MASK GENMASK(7, 0)
236
237/* BATT_INFO_IBATT_LSB/MSB */
238#define IBATT_MASK GENMASK(7, 0)
239
240/* BATT_INFO_ESR_LSB/MSB */
241#define ESR_LSB_MASK GENMASK(7, 0)
242#define ESR_MSB_MASK GENMASK(5, 0)
243
244/* BATT_INFO_VADC_LSB/MSB */
245#define VADC_LSB_MASK GENMASK(7, 0)
246#define VADC_MSB_MASK GENMASK(6, 0)
247
248/* BATT_INFO_IADC_LSB/MSB */
249#define IADC_LSB_MASK GENMASK(7, 0)
250#define IADC_MSB_MASK GENMASK(6, 0)
251
252/* BATT_INFO_TM_MISC */
253#define FORCE_SEQ_RESP_TOGGLE_BIT BIT(6)
254#define ALG_DIRECT_VALID_DATA_BIT BIT(5)
255#define ALG_DIRECT_MODE_EN_BIT BIT(4)
256#define BATT_VADC_CONV_BIT BIT(3)
257#define BATT_IADC_CONV_BIT BIT(2)
258#define ADC_ENABLE_REG_CTRL_BIT BIT(1)
259#define WDOG_FORCE_EXP_BIT BIT(0)
260/* only for v1.1 */
261#define ESR_PULSE_FORCE_CTRL_BIT BIT(7)
262
263/* BATT_INFO_TM_MISC1 */
264/* for v2.0 and above */
265#define ESR_REQ_CTL_BIT BIT(1)
266#define ESR_REQ_CTL_EN_BIT BIT(0)
267
268/* FG_MEM_IF register and bit definitions */
Subbaraman Narayanamurthya71c9dd2016-10-14 19:38:05 -0700[diff] [blame]269#define MEM_IF_INT_RT_STS(chip) ((chip->mem_if_base) + 0x10)
Subbaraman Narayanamurthy2d62e9e2017-06-02 17:40:28 -0700[diff] [blame]270#define MEM_IF_MEM_ARB_CFG(chip) ((chip->mem_if_base) + 0x40)
Subbaraman Narayanamurthy6accb262016-03-14 16:41:16 -0700[diff] [blame]271#define MEM_IF_MEM_INTF_CFG(chip) ((chip->mem_if_base) + 0x50)
272#define MEM_IF_IMA_CTL(chip) ((chip->mem_if_base) + 0x51)
273#define MEM_IF_IMA_CFG(chip) ((chip->mem_if_base) + 0x52)
274#define MEM_IF_IMA_OPR_STS(chip) ((chip->mem_if_base) + 0x54)
275#define MEM_IF_IMA_EXP_STS(chip) ((chip->mem_if_base) + 0x55)
276#define MEM_IF_IMA_HW_STS(chip) ((chip->mem_if_base) + 0x56)
277#define MEM_IF_FG_BEAT_COUNT(chip) ((chip->mem_if_base) + 0x57)
278#define MEM_IF_IMA_ERR_STS(chip) ((chip->mem_if_base) + 0x5F)
279#define MEM_IF_IMA_BYTE_EN(chip) ((chip->mem_if_base) + 0x60)
280#define MEM_IF_ADDR_LSB(chip) ((chip->mem_if_base) + 0x61)
281#define MEM_IF_ADDR_MSB(chip) ((chip->mem_if_base) + 0x62)
282#define MEM_IF_WR_DATA0(chip) ((chip->mem_if_base) + 0x63)
283#define MEM_IF_WR_DATA3(chip) ((chip->mem_if_base) + 0x66)
284#define MEM_IF_RD_DATA0(chip) ((chip->mem_if_base) + 0x67)
285#define MEM_IF_RD_DATA3(chip) ((chip->mem_if_base) + 0x6A)
Subbaraman Narayanamurthya71c9dd2016-10-14 19:38:05 -0700[diff] [blame]286#define MEM_IF_DMA_STS(chip) ((chip->mem_if_base) + 0x70)
287#define MEM_IF_DMA_CTL(chip) ((chip->mem_if_base) + 0x71)
288
289/* MEM_IF_INT_RT_STS */
290#define MEM_XCP_BIT BIT(1)
Subbaraman Narayanamurthy2d62e9e2017-06-02 17:40:28 -0700[diff] [blame]291#define MEM_GNT_BIT BIT(2)
292
293/* MEM_IF_MEM_ARB_CFG */
294#define MEM_ARB_LO_LATENCY_EN_BIT BIT(1)
295#define MEM_ARB_REQ_BIT BIT(0)
Subbaraman Narayanamurthy6accb262016-03-14 16:41:16 -0700[diff] [blame]296
297/* MEM_IF_MEM_INTF_CFG */
298#define MEM_ACCESS_REQ_BIT BIT(7)
299#define IACS_SLCT_BIT BIT(5)
300
301/* MEM_IF_IMA_CTL */
302#define MEM_ACS_BURST_BIT BIT(7)
303#define IMA_WR_EN_BIT BIT(6)
304#define IMA_CTL_MASK GENMASK(7, 6)
305
306/* MEM_IF_IMA_CFG */
307#define IACS_CLR_BIT BIT(2)
308#define IACS_INTR_SRC_SLCT_BIT BIT(3)
Subbaraman Narayanamurthya71c9dd2016-10-14 19:38:05 -0700[diff] [blame]309#define STATIC_CLK_EN_BIT BIT(4)
Subbaraman Narayanamurthy6accb262016-03-14 16:41:16 -0700[diff] [blame]310
311/* MEM_IF_IMA_OPR_STS */
312#define IACS_RDY_BIT BIT(1)
313
Subbaraman Narayanamurthya71c9dd2016-10-14 19:38:05 -0700[diff] [blame]314/* MEM_IF_IMA_EXP_STS */
315#define IACS_ERR_BIT BIT(0)
316#define XCT_TYPE_ERR_BIT BIT(1)
317#define DATA_RD_ERR_BIT BIT(3)
318#define DATA_WR_ERR_BIT BIT(4)
319#define ADDR_BURST_WRAP_BIT BIT(5)
320#define ADDR_STABLE_ERR_BIT BIT(7)
321
Subbaraman Narayanamurthy6accb262016-03-14 16:41:16 -0700[diff] [blame]322/* MEM_IF_IMA_ERR_STS */
323#define ADDR_STBL_ERR_BIT BIT(7)
324#define WR_ACS_ERR_BIT BIT(6)
325#define RD_ACS_ERR_BIT BIT(5)
326
327/* MEM_IF_FG_BEAT_COUNT */
328#define BEAT_COUNT_MASK GENMASK(3, 0)
Subbaraman Narayanamurthya71c9dd2016-10-14 19:38:05 -0700[diff] [blame]329
330/* MEM_IF_DMA_STS */
331#define DMA_WRITE_ERROR_BIT BIT(1)
332#define DMA_READ_ERROR_BIT BIT(2)
333
334/* MEM_IF_DMA_CTL */
Subbaraman Narayanamurthy2d62e9e2017-06-02 17:40:28 -0700[diff] [blame]335#define ADDR_KIND_BIT BIT(1)
Subbaraman Narayanamurthya71c9dd2016-10-14 19:38:05 -0700[diff] [blame]336#define DMA_CLEAR_LOG_BIT BIT(0)
Subbaraman Narayanamurthy2d62e9e2017-06-02 17:40:28 -0700[diff] [blame]337
338/* FG_DMAx */
339#define FG_DMA0_BASE 0x4800
340#define FG_DMA1_BASE 0x4900
341#define FG_DMA2_BASE 0x4A00
342#define FG_DMA3_BASE 0x4B00
343#define SRAM_ADDR_OFFSET 0x20
Subbaraman Narayanamurthy6accb262016-03-14 16:41:16 -0700[diff] [blame]344#endif