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Florian Meier96286b52014-01-06 20:18:24 +01001/*
2 * BCM2835 DMA engine support
3 *
4 * This driver only supports cyclic DMA transfers
5 * as needed for the I2S module.
6 *
7 * Author: Florian Meier <florian.meier@koalo.de>
8 * Copyright 2013
9 *
10 * Based on
11 * OMAP DMAengine support by Russell King
12 *
13 * BCM2708 DMA Driver
14 * Copyright (C) 2010 Broadcom
15 *
16 * Raspberry Pi PCM I2S ALSA Driver
17 * Copyright (c) by Phil Poole 2013
18 *
19 * MARVELL MMP Peripheral DMA Driver
20 * Copyright 2012 Marvell International Ltd.
21 *
22 * This program is free software; you can redistribute it and/or modify
23 * it under the terms of the GNU General Public License as published by
24 * the Free Software Foundation; either version 2 of the License, or
25 * (at your option) any later version.
26 *
27 * This program is distributed in the hope that it will be useful,
28 * but WITHOUT ANY WARRANTY; without even the implied warranty of
29 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
30 * GNU General Public License for more details.
31 */
32#include <linux/dmaengine.h>
33#include <linux/dma-mapping.h>
Peter Ujfalusi27bc9442015-11-16 13:09:03 +020034#include <linux/dmapool.h>
Florian Meier96286b52014-01-06 20:18:24 +010035#include <linux/err.h>
36#include <linux/init.h>
37#include <linux/interrupt.h>
38#include <linux/list.h>
39#include <linux/module.h>
40#include <linux/platform_device.h>
41#include <linux/slab.h>
42#include <linux/io.h>
43#include <linux/spinlock.h>
44#include <linux/of.h>
45#include <linux/of_dma.h>
46
47#include "virt-dma.h"
48
Martin Sperle2eca632016-04-11 13:29:08 +000049#define BCM2835_DMA_MAX_DMA_CHAN_SUPPORTED 14
50#define BCM2835_DMA_CHAN_NAME_SIZE 8
51
Florian Meier96286b52014-01-06 20:18:24 +010052struct bcm2835_dmadev {
53 struct dma_device ddev;
54 spinlock_t lock;
55 void __iomem *base;
56 struct device_dma_parameters dma_parms;
57};
58
59struct bcm2835_dma_cb {
60 uint32_t info;
61 uint32_t src;
62 uint32_t dst;
63 uint32_t length;
64 uint32_t stride;
65 uint32_t next;
66 uint32_t pad[2];
67};
68
Peter Ujfalusi27bc9442015-11-16 13:09:03 +020069struct bcm2835_cb_entry {
70 struct bcm2835_dma_cb *cb;
71 dma_addr_t paddr;
72};
73
Florian Meier96286b52014-01-06 20:18:24 +010074struct bcm2835_chan {
75 struct virt_dma_chan vc;
76 struct list_head node;
77
78 struct dma_slave_config cfg;
Florian Meier96286b52014-01-06 20:18:24 +010079 unsigned int dreq;
80
81 int ch;
82 struct bcm2835_desc *desc;
Peter Ujfalusi27bc9442015-11-16 13:09:03 +020083 struct dma_pool *cb_pool;
Florian Meier96286b52014-01-06 20:18:24 +010084
85 void __iomem *chan_base;
86 int irq_number;
Martin Sperle2eca632016-04-11 13:29:08 +000087 unsigned int irq_flags;
Martin Sperl40874122016-03-16 12:25:00 -070088
89 bool is_lite_channel;
Florian Meier96286b52014-01-06 20:18:24 +010090};
91
92struct bcm2835_desc {
Peter Ujfalusi27bc9442015-11-16 13:09:03 +020093 struct bcm2835_chan *c;
Florian Meier96286b52014-01-06 20:18:24 +010094 struct virt_dma_desc vd;
95 enum dma_transfer_direction dir;
96
Florian Meier96286b52014-01-06 20:18:24 +010097 unsigned int frames;
98 size_t size;
Martin Sperla4dcdd82016-03-16 12:24:58 -070099
100 bool cyclic;
Martin Sperl92153bb2016-03-16 12:24:59 -0700101
102 struct bcm2835_cb_entry cb_list[];
Florian Meier96286b52014-01-06 20:18:24 +0100103};
104
105#define BCM2835_DMA_CS 0x00
106#define BCM2835_DMA_ADDR 0x04
Martin Sperle42685d2016-03-16 12:24:57 -0700107#define BCM2835_DMA_TI 0x08
Florian Meier96286b52014-01-06 20:18:24 +0100108#define BCM2835_DMA_SOURCE_AD 0x0c
109#define BCM2835_DMA_DEST_AD 0x10
Martin Sperle42685d2016-03-16 12:24:57 -0700110#define BCM2835_DMA_LEN 0x14
111#define BCM2835_DMA_STRIDE 0x18
112#define BCM2835_DMA_NEXTCB 0x1c
113#define BCM2835_DMA_DEBUG 0x20
Florian Meier96286b52014-01-06 20:18:24 +0100114
115/* DMA CS Control and Status bits */
Martin Sperle42685d2016-03-16 12:24:57 -0700116#define BCM2835_DMA_ACTIVE BIT(0) /* activate the DMA */
117#define BCM2835_DMA_END BIT(1) /* current CB has ended */
118#define BCM2835_DMA_INT BIT(2) /* interrupt status */
119#define BCM2835_DMA_DREQ BIT(3) /* DREQ state */
Florian Meier96286b52014-01-06 20:18:24 +0100120#define BCM2835_DMA_ISPAUSED BIT(4) /* Pause requested or not active */
121#define BCM2835_DMA_ISHELD BIT(5) /* Is held by DREQ flow control */
Martin Sperle42685d2016-03-16 12:24:57 -0700122#define BCM2835_DMA_WAITING_FOR_WRITES BIT(6) /* waiting for last
123 * AXI-write to ack
124 */
125#define BCM2835_DMA_ERR BIT(8)
126#define BCM2835_DMA_PRIORITY(x) ((x & 15) << 16) /* AXI priority */
127#define BCM2835_DMA_PANIC_PRIORITY(x) ((x & 15) << 20) /* panic priority */
128/* current value of TI.BCM2835_DMA_WAIT_RESP */
129#define BCM2835_DMA_WAIT_FOR_WRITES BIT(28)
130#define BCM2835_DMA_DIS_DEBUG BIT(29) /* disable debug pause signal */
Florian Meier96286b52014-01-06 20:18:24 +0100131#define BCM2835_DMA_ABORT BIT(30) /* Stop current CB, go to next, WO */
132#define BCM2835_DMA_RESET BIT(31) /* WO, self clearing */
133
Martin Sperle42685d2016-03-16 12:24:57 -0700134/* Transfer information bits - also bcm2835_cb.info field */
Florian Meier96286b52014-01-06 20:18:24 +0100135#define BCM2835_DMA_INT_EN BIT(0)
Martin Sperle42685d2016-03-16 12:24:57 -0700136#define BCM2835_DMA_TDMODE BIT(1) /* 2D-Mode */
137#define BCM2835_DMA_WAIT_RESP BIT(3) /* wait for AXI-write to be acked */
Florian Meier96286b52014-01-06 20:18:24 +0100138#define BCM2835_DMA_D_INC BIT(4)
Martin Sperle42685d2016-03-16 12:24:57 -0700139#define BCM2835_DMA_D_WIDTH BIT(5) /* 128bit writes if set */
140#define BCM2835_DMA_D_DREQ BIT(6) /* enable DREQ for destination */
141#define BCM2835_DMA_D_IGNORE BIT(7) /* ignore destination writes */
Florian Meier96286b52014-01-06 20:18:24 +0100142#define BCM2835_DMA_S_INC BIT(8)
Martin Sperle42685d2016-03-16 12:24:57 -0700143#define BCM2835_DMA_S_WIDTH BIT(9) /* 128bit writes if set */
144#define BCM2835_DMA_S_DREQ BIT(10) /* enable SREQ for source */
145#define BCM2835_DMA_S_IGNORE BIT(11) /* ignore source reads - read 0 */
146#define BCM2835_DMA_BURST_LENGTH(x) ((x & 15) << 12)
147#define BCM2835_DMA_PER_MAP(x) ((x & 31) << 16) /* REQ source */
148#define BCM2835_DMA_WAIT(x) ((x & 31) << 21) /* add DMA-wait cycles */
149#define BCM2835_DMA_NO_WIDE_BURSTS BIT(26) /* no 2 beat write bursts */
Florian Meier96286b52014-01-06 20:18:24 +0100150
Martin Sperle42685d2016-03-16 12:24:57 -0700151/* debug register bits */
152#define BCM2835_DMA_DEBUG_LAST_NOT_SET_ERR BIT(0)
153#define BCM2835_DMA_DEBUG_FIFO_ERR BIT(1)
154#define BCM2835_DMA_DEBUG_READ_ERR BIT(2)
155#define BCM2835_DMA_DEBUG_OUTSTANDING_WRITES_SHIFT 4
156#define BCM2835_DMA_DEBUG_OUTSTANDING_WRITES_BITS 4
157#define BCM2835_DMA_DEBUG_ID_SHIFT 16
158#define BCM2835_DMA_DEBUG_ID_BITS 9
159#define BCM2835_DMA_DEBUG_STATE_SHIFT 16
160#define BCM2835_DMA_DEBUG_STATE_BITS 9
161#define BCM2835_DMA_DEBUG_VERSION_SHIFT 25
162#define BCM2835_DMA_DEBUG_VERSION_BITS 3
163#define BCM2835_DMA_DEBUG_LITE BIT(28)
164
165/* shared registers for all dma channels */
166#define BCM2835_DMA_INT_STATUS 0xfe0
167#define BCM2835_DMA_ENABLE 0xff0
Florian Meier96286b52014-01-06 20:18:24 +0100168
169#define BCM2835_DMA_DATA_TYPE_S8 1
170#define BCM2835_DMA_DATA_TYPE_S16 2
171#define BCM2835_DMA_DATA_TYPE_S32 4
172#define BCM2835_DMA_DATA_TYPE_S128 16
173
Florian Meier96286b52014-01-06 20:18:24 +0100174/* Valid only for channels 0 - 14, 15 has its own base address */
175#define BCM2835_DMA_CHAN(n) ((n) << 8) /* Base address */
176#define BCM2835_DMA_CHANIO(base, n) ((base) + BCM2835_DMA_CHAN(n))
177
Martin Sperl40874122016-03-16 12:25:00 -0700178/* the max dma length for different channels */
179#define MAX_DMA_LEN SZ_1G
180#define MAX_LITE_DMA_LEN (SZ_64K - 4)
181
182static inline size_t bcm2835_dma_max_frame_length(struct bcm2835_chan *c)
183{
184 /* lite and normal channels have different max frame length */
185 return c->is_lite_channel ? MAX_LITE_DMA_LEN : MAX_DMA_LEN;
186}
187
Martin Sperl92153bb2016-03-16 12:24:59 -0700188/* how many frames of max_len size do we need to transfer len bytes */
189static inline size_t bcm2835_dma_frames_for_length(size_t len,
190 size_t max_len)
191{
192 return DIV_ROUND_UP(len, max_len);
193}
194
Florian Meier96286b52014-01-06 20:18:24 +0100195static inline struct bcm2835_dmadev *to_bcm2835_dma_dev(struct dma_device *d)
196{
197 return container_of(d, struct bcm2835_dmadev, ddev);
198}
199
200static inline struct bcm2835_chan *to_bcm2835_dma_chan(struct dma_chan *c)
201{
202 return container_of(c, struct bcm2835_chan, vc.chan);
203}
204
205static inline struct bcm2835_desc *to_bcm2835_dma_desc(
206 struct dma_async_tx_descriptor *t)
207{
208 return container_of(t, struct bcm2835_desc, vd.tx);
209}
210
Martin Sperl92153bb2016-03-16 12:24:59 -0700211static void bcm2835_dma_free_cb_chain(struct bcm2835_desc *desc)
Florian Meier96286b52014-01-06 20:18:24 +0100212{
Martin Sperl92153bb2016-03-16 12:24:59 -0700213 size_t i;
Peter Ujfalusi27bc9442015-11-16 13:09:03 +0200214
215 for (i = 0; i < desc->frames; i++)
216 dma_pool_free(desc->c->cb_pool, desc->cb_list[i].cb,
217 desc->cb_list[i].paddr);
218
Florian Meier96286b52014-01-06 20:18:24 +0100219 kfree(desc);
220}
221
Martin Sperl92153bb2016-03-16 12:24:59 -0700222static void bcm2835_dma_desc_free(struct virt_dma_desc *vd)
223{
224 bcm2835_dma_free_cb_chain(
225 container_of(vd, struct bcm2835_desc, vd));
226}
227
228static void bcm2835_dma_create_cb_set_length(
229 struct bcm2835_chan *chan,
230 struct bcm2835_dma_cb *control_block,
231 size_t len,
232 size_t period_len,
233 size_t *total_len,
234 u32 finalextrainfo)
235{
Martin Sperl40874122016-03-16 12:25:00 -0700236 size_t max_len = bcm2835_dma_max_frame_length(chan);
237
238 /* set the length taking lite-channel limitations into account */
239 control_block->length = min_t(u32, len, max_len);
Martin Sperl92153bb2016-03-16 12:24:59 -0700240
241 /* finished if we have no period_length */
242 if (!period_len)
243 return;
244
245 /*
246 * period_len means: that we need to generate
247 * transfers that are terminating at every
248 * multiple of period_len - this is typically
249 * used to set the interrupt flag in info
250 * which is required during cyclic transfers
251 */
252
253 /* have we filled in period_length yet? */
254 if (*total_len + control_block->length < period_len)
255 return;
256
257 /* calculate the length that remains to reach period_length */
258 control_block->length = period_len - *total_len;
259
260 /* reset total_length for next period */
261 *total_len = 0;
262
263 /* add extrainfo bits in info */
264 control_block->info |= finalextrainfo;
265}
266
Martin Sperl388cc7a2016-03-16 12:25:01 -0700267static inline size_t bcm2835_dma_count_frames_for_sg(
268 struct bcm2835_chan *c,
269 struct scatterlist *sgl,
270 unsigned int sg_len)
271{
272 size_t frames = 0;
273 struct scatterlist *sgent;
274 unsigned int i;
275 size_t plength = bcm2835_dma_max_frame_length(c);
276
277 for_each_sg(sgl, sgent, sg_len, i)
278 frames += bcm2835_dma_frames_for_length(
279 sg_dma_len(sgent), plength);
280
281 return frames;
282}
283
Martin Sperl92153bb2016-03-16 12:24:59 -0700284/**
285 * bcm2835_dma_create_cb_chain - create a control block and fills data in
286 *
287 * @chan: the @dma_chan for which we run this
288 * @direction: the direction in which we transfer
289 * @cyclic: it is a cyclic transfer
290 * @info: the default info bits to apply per controlblock
291 * @frames: number of controlblocks to allocate
292 * @src: the src address to assign (if the S_INC bit is set
293 * in @info, then it gets incremented)
294 * @dst: the dst address to assign (if the D_INC bit is set
295 * in @info, then it gets incremented)
296 * @buf_len: the full buffer length (may also be 0)
297 * @period_len: the period length when to apply @finalextrainfo
298 * in addition to the last transfer
299 * this will also break some control-blocks early
300 * @finalextrainfo: additional bits in last controlblock
301 * (or when period_len is reached in case of cyclic)
302 * @gfp: the GFP flag to use for allocation
303 */
304static struct bcm2835_desc *bcm2835_dma_create_cb_chain(
305 struct dma_chan *chan, enum dma_transfer_direction direction,
306 bool cyclic, u32 info, u32 finalextrainfo, size_t frames,
307 dma_addr_t src, dma_addr_t dst, size_t buf_len,
308 size_t period_len, gfp_t gfp)
309{
310 struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
311 size_t len = buf_len, total_len;
312 size_t frame;
313 struct bcm2835_desc *d;
314 struct bcm2835_cb_entry *cb_entry;
315 struct bcm2835_dma_cb *control_block;
316
Martin Sperld9f094a2016-03-16 12:25:02 -0700317 if (!frames)
318 return NULL;
319
Martin Sperl92153bb2016-03-16 12:24:59 -0700320 /* allocate and setup the descriptor. */
321 d = kzalloc(sizeof(*d) + frames * sizeof(struct bcm2835_cb_entry),
322 gfp);
323 if (!d)
324 return NULL;
325
326 d->c = c;
327 d->dir = direction;
328 d->cyclic = cyclic;
329
330 /*
331 * Iterate over all frames, create a control block
332 * for each frame and link them together.
333 */
334 for (frame = 0, total_len = 0; frame < frames; d->frames++, frame++) {
335 cb_entry = &d->cb_list[frame];
336 cb_entry->cb = dma_pool_alloc(c->cb_pool, gfp,
337 &cb_entry->paddr);
338 if (!cb_entry->cb)
339 goto error_cb;
340
341 /* fill in the control block */
342 control_block = cb_entry->cb;
343 control_block->info = info;
344 control_block->src = src;
345 control_block->dst = dst;
346 control_block->stride = 0;
347 control_block->next = 0;
348 /* set up length in control_block if requested */
349 if (buf_len) {
350 /* calculate length honoring period_length */
351 bcm2835_dma_create_cb_set_length(
352 c, control_block,
353 len, period_len, &total_len,
354 cyclic ? finalextrainfo : 0);
355
356 /* calculate new remaining length */
357 len -= control_block->length;
358 }
359
360 /* link this the last controlblock */
361 if (frame)
362 d->cb_list[frame - 1].cb->next = cb_entry->paddr;
363
364 /* update src and dst and length */
365 if (src && (info & BCM2835_DMA_S_INC))
366 src += control_block->length;
367 if (dst && (info & BCM2835_DMA_D_INC))
368 dst += control_block->length;
369
370 /* Length of total transfer */
371 d->size += control_block->length;
372 }
373
374 /* the last frame requires extra flags */
375 d->cb_list[d->frames - 1].cb->info |= finalextrainfo;
376
377 /* detect a size missmatch */
378 if (buf_len && (d->size != buf_len))
379 goto error_cb;
380
381 return d;
382error_cb:
383 bcm2835_dma_free_cb_chain(d);
384
385 return NULL;
386}
387
Martin Sperl388cc7a2016-03-16 12:25:01 -0700388static void bcm2835_dma_fill_cb_chain_with_sg(
389 struct dma_chan *chan,
390 enum dma_transfer_direction direction,
391 struct bcm2835_cb_entry *cb,
392 struct scatterlist *sgl,
393 unsigned int sg_len)
394{
395 struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
396 size_t max_len = bcm2835_dma_max_frame_length(c);
397 unsigned int i, len;
398 dma_addr_t addr;
399 struct scatterlist *sgent;
400
401 for_each_sg(sgl, sgent, sg_len, i) {
402 for (addr = sg_dma_address(sgent), len = sg_dma_len(sgent);
403 len > 0;
404 addr += cb->cb->length, len -= cb->cb->length, cb++) {
405 if (direction == DMA_DEV_TO_MEM)
406 cb->cb->dst = addr;
407 else
408 cb->cb->src = addr;
409 cb->cb->length = min(len, max_len);
410 }
411 }
412}
413
Florian Meier96286b52014-01-06 20:18:24 +0100414static int bcm2835_dma_abort(void __iomem *chan_base)
415{
416 unsigned long cs;
417 long int timeout = 10000;
418
419 cs = readl(chan_base + BCM2835_DMA_CS);
420 if (!(cs & BCM2835_DMA_ACTIVE))
421 return 0;
422
423 /* Write 0 to the active bit - Pause the DMA */
424 writel(0, chan_base + BCM2835_DMA_CS);
425
426 /* Wait for any current AXI transfer to complete */
427 while ((cs & BCM2835_DMA_ISPAUSED) && --timeout) {
428 cpu_relax();
429 cs = readl(chan_base + BCM2835_DMA_CS);
430 }
431
432 /* We'll un-pause when we set of our next DMA */
433 if (!timeout)
434 return -ETIMEDOUT;
435
436 if (!(cs & BCM2835_DMA_ACTIVE))
437 return 0;
438
439 /* Terminate the control block chain */
440 writel(0, chan_base + BCM2835_DMA_NEXTCB);
441
442 /* Abort the whole DMA */
443 writel(BCM2835_DMA_ABORT | BCM2835_DMA_ACTIVE,
444 chan_base + BCM2835_DMA_CS);
445
446 return 0;
447}
448
449static void bcm2835_dma_start_desc(struct bcm2835_chan *c)
450{
451 struct virt_dma_desc *vd = vchan_next_desc(&c->vc);
452 struct bcm2835_desc *d;
453
454 if (!vd) {
455 c->desc = NULL;
456 return;
457 }
458
459 list_del(&vd->node);
460
461 c->desc = d = to_bcm2835_dma_desc(&vd->tx);
462
Peter Ujfalusi27bc9442015-11-16 13:09:03 +0200463 writel(d->cb_list[0].paddr, c->chan_base + BCM2835_DMA_ADDR);
Florian Meier96286b52014-01-06 20:18:24 +0100464 writel(BCM2835_DMA_ACTIVE, c->chan_base + BCM2835_DMA_CS);
465}
466
467static irqreturn_t bcm2835_dma_callback(int irq, void *data)
468{
469 struct bcm2835_chan *c = data;
470 struct bcm2835_desc *d;
471 unsigned long flags;
472
Martin Sperle2eca632016-04-11 13:29:08 +0000473 /* check the shared interrupt */
474 if (c->irq_flags & IRQF_SHARED) {
475 /* check if the interrupt is enabled */
476 flags = readl(c->chan_base + BCM2835_DMA_CS);
477 /* if not set then we are not the reason for the irq */
478 if (!(flags & BCM2835_DMA_INT))
479 return IRQ_NONE;
480 }
481
Florian Meier96286b52014-01-06 20:18:24 +0100482 spin_lock_irqsave(&c->vc.lock, flags);
483
484 /* Acknowledge interrupt */
485 writel(BCM2835_DMA_INT, c->chan_base + BCM2835_DMA_CS);
486
487 d = c->desc;
488
489 if (d) {
Martin Sperl388cc7a2016-03-16 12:25:01 -0700490 if (d->cyclic) {
491 /* call the cyclic callback */
492 vchan_cyclic_callback(&d->vd);
Florian Meier96286b52014-01-06 20:18:24 +0100493
Martin Sperl388cc7a2016-03-16 12:25:01 -0700494 /* Keep the DMA engine running */
495 writel(BCM2835_DMA_ACTIVE,
496 c->chan_base + BCM2835_DMA_CS);
497 } else {
498 vchan_cookie_complete(&c->desc->vd);
499 bcm2835_dma_start_desc(c);
500 }
501 }
Florian Meier96286b52014-01-06 20:18:24 +0100502
503 spin_unlock_irqrestore(&c->vc.lock, flags);
504
505 return IRQ_HANDLED;
506}
507
508static int bcm2835_dma_alloc_chan_resources(struct dma_chan *chan)
509{
510 struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
Peter Ujfalusi27bc9442015-11-16 13:09:03 +0200511 struct device *dev = c->vc.chan.device->dev;
Florian Meier96286b52014-01-06 20:18:24 +0100512
Peter Ujfalusi27bc9442015-11-16 13:09:03 +0200513 dev_dbg(dev, "Allocating DMA channel %d\n", c->ch);
514
515 c->cb_pool = dma_pool_create(dev_name(dev), dev,
516 sizeof(struct bcm2835_dma_cb), 0, 0);
517 if (!c->cb_pool) {
518 dev_err(dev, "unable to allocate descriptor pool\n");
519 return -ENOMEM;
520 }
Florian Meier96286b52014-01-06 20:18:24 +0100521
Martin Sperle2eca632016-04-11 13:29:08 +0000522 return request_irq(c->irq_number, bcm2835_dma_callback,
523 c->irq_flags, "DMA IRQ", c);
Florian Meier96286b52014-01-06 20:18:24 +0100524}
525
526static void bcm2835_dma_free_chan_resources(struct dma_chan *chan)
527{
528 struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
529
530 vchan_free_chan_resources(&c->vc);
531 free_irq(c->irq_number, c);
Peter Ujfalusi27bc9442015-11-16 13:09:03 +0200532 dma_pool_destroy(c->cb_pool);
Florian Meier96286b52014-01-06 20:18:24 +0100533
534 dev_dbg(c->vc.chan.device->dev, "Freeing DMA channel %u\n", c->ch);
535}
536
537static size_t bcm2835_dma_desc_size(struct bcm2835_desc *d)
538{
539 return d->size;
540}
541
542static size_t bcm2835_dma_desc_size_pos(struct bcm2835_desc *d, dma_addr_t addr)
543{
544 unsigned int i;
545 size_t size;
546
547 for (size = i = 0; i < d->frames; i++) {
Peter Ujfalusi27bc9442015-11-16 13:09:03 +0200548 struct bcm2835_dma_cb *control_block = d->cb_list[i].cb;
Florian Meier96286b52014-01-06 20:18:24 +0100549 size_t this_size = control_block->length;
550 dma_addr_t dma;
551
552 if (d->dir == DMA_DEV_TO_MEM)
553 dma = control_block->dst;
554 else
555 dma = control_block->src;
556
557 if (size)
558 size += this_size;
559 else if (addr >= dma && addr < dma + this_size)
560 size += dma + this_size - addr;
561 }
562
563 return size;
564}
565
566static enum dma_status bcm2835_dma_tx_status(struct dma_chan *chan,
567 dma_cookie_t cookie, struct dma_tx_state *txstate)
568{
569 struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
570 struct virt_dma_desc *vd;
571 enum dma_status ret;
572 unsigned long flags;
573
574 ret = dma_cookie_status(chan, cookie, txstate);
575 if (ret == DMA_COMPLETE || !txstate)
576 return ret;
577
578 spin_lock_irqsave(&c->vc.lock, flags);
579 vd = vchan_find_desc(&c->vc, cookie);
580 if (vd) {
581 txstate->residue =
582 bcm2835_dma_desc_size(to_bcm2835_dma_desc(&vd->tx));
583 } else if (c->desc && c->desc->vd.tx.cookie == cookie) {
584 struct bcm2835_desc *d = c->desc;
585 dma_addr_t pos;
586
587 if (d->dir == DMA_MEM_TO_DEV)
588 pos = readl(c->chan_base + BCM2835_DMA_SOURCE_AD);
589 else if (d->dir == DMA_DEV_TO_MEM)
590 pos = readl(c->chan_base + BCM2835_DMA_DEST_AD);
591 else
592 pos = 0;
593
594 txstate->residue = bcm2835_dma_desc_size_pos(d, pos);
595 } else {
596 txstate->residue = 0;
597 }
598
599 spin_unlock_irqrestore(&c->vc.lock, flags);
600
601 return ret;
602}
603
604static void bcm2835_dma_issue_pending(struct dma_chan *chan)
605{
606 struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
607 unsigned long flags;
608
Florian Meier96286b52014-01-06 20:18:24 +0100609 spin_lock_irqsave(&c->vc.lock, flags);
610 if (vchan_issue_pending(&c->vc) && !c->desc)
611 bcm2835_dma_start_desc(c);
612
613 spin_unlock_irqrestore(&c->vc.lock, flags);
614}
615
Martin Sperld9f094a2016-03-16 12:25:02 -0700616struct dma_async_tx_descriptor *bcm2835_dma_prep_dma_memcpy(
617 struct dma_chan *chan, dma_addr_t dst, dma_addr_t src,
618 size_t len, unsigned long flags)
619{
620 struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
621 struct bcm2835_desc *d;
622 u32 info = BCM2835_DMA_D_INC | BCM2835_DMA_S_INC;
623 u32 extra = BCM2835_DMA_INT_EN | BCM2835_DMA_WAIT_RESP;
624 size_t max_len = bcm2835_dma_max_frame_length(c);
625 size_t frames;
626
627 /* if src, dst or len is not given return with an error */
628 if (!src || !dst || !len)
629 return NULL;
630
631 /* calculate number of frames */
632 frames = bcm2835_dma_frames_for_length(len, max_len);
633
634 /* allocate the CB chain - this also fills in the pointers */
635 d = bcm2835_dma_create_cb_chain(chan, DMA_MEM_TO_MEM, false,
636 info, extra, frames,
637 src, dst, len, 0, GFP_KERNEL);
638 if (!d)
639 return NULL;
640
641 return vchan_tx_prep(&c->vc, &d->vd, flags);
642}
643
Martin Sperl388cc7a2016-03-16 12:25:01 -0700644static struct dma_async_tx_descriptor *bcm2835_dma_prep_slave_sg(
645 struct dma_chan *chan,
646 struct scatterlist *sgl, unsigned int sg_len,
647 enum dma_transfer_direction direction,
648 unsigned long flags, void *context)
649{
650 struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
651 struct bcm2835_desc *d;
652 dma_addr_t src = 0, dst = 0;
653 u32 info = BCM2835_DMA_WAIT_RESP;
654 u32 extra = BCM2835_DMA_INT_EN;
655 size_t frames;
656
657 if (!is_slave_direction(direction)) {
658 dev_err(chan->device->dev,
659 "%s: bad direction?\n", __func__);
660 return NULL;
661 }
662
663 if (c->dreq != 0)
664 info |= BCM2835_DMA_PER_MAP(c->dreq);
665
666 if (direction == DMA_DEV_TO_MEM) {
667 if (c->cfg.src_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES)
668 return NULL;
669 src = c->cfg.src_addr;
670 info |= BCM2835_DMA_S_DREQ | BCM2835_DMA_D_INC;
671 } else {
672 if (c->cfg.dst_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES)
673 return NULL;
674 dst = c->cfg.dst_addr;
675 info |= BCM2835_DMA_D_DREQ | BCM2835_DMA_S_INC;
676 }
677
678 /* count frames in sg list */
679 frames = bcm2835_dma_count_frames_for_sg(c, sgl, sg_len);
680
681 /* allocate the CB chain */
682 d = bcm2835_dma_create_cb_chain(chan, direction, false,
683 info, extra,
684 frames, src, dst, 0, 0,
685 GFP_KERNEL);
686 if (!d)
687 return NULL;
688
689 /* fill in frames with scatterlist pointers */
690 bcm2835_dma_fill_cb_chain_with_sg(chan, direction, d->cb_list,
691 sgl, sg_len);
692
693 return vchan_tx_prep(&c->vc, &d->vd, flags);
694}
695
Florian Meier96286b52014-01-06 20:18:24 +0100696static struct dma_async_tx_descriptor *bcm2835_dma_prep_dma_cyclic(
697 struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
698 size_t period_len, enum dma_transfer_direction direction,
Laurent Pinchart31c1e5a2014-08-01 12:20:10 +0200699 unsigned long flags)
Florian Meier96286b52014-01-06 20:18:24 +0100700{
701 struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
Florian Meier96286b52014-01-06 20:18:24 +0100702 struct bcm2835_desc *d;
Martin Sperl92153bb2016-03-16 12:24:59 -0700703 dma_addr_t src, dst;
704 u32 info = BCM2835_DMA_WAIT_RESP;
705 u32 extra = BCM2835_DMA_INT_EN;
Martin Sperl40874122016-03-16 12:25:00 -0700706 size_t max_len = bcm2835_dma_max_frame_length(c);
Martin Sperl92153bb2016-03-16 12:24:59 -0700707 size_t frames;
Florian Meier96286b52014-01-06 20:18:24 +0100708
709 /* Grab configuration */
710 if (!is_slave_direction(direction)) {
711 dev_err(chan->device->dev, "%s: bad direction?\n", __func__);
712 return NULL;
713 }
714
Martin Sperl92153bb2016-03-16 12:24:59 -0700715 if (!buf_len) {
716 dev_err(chan->device->dev,
717 "%s: bad buffer length (= 0)\n", __func__);
Florian Meier96286b52014-01-06 20:18:24 +0100718 return NULL;
719 }
720
Florian Meier96286b52014-01-06 20:18:24 +0100721 /*
Martin Sperl92153bb2016-03-16 12:24:59 -0700722 * warn if buf_len is not a multiple of period_len - this may leed
723 * to unexpected latencies for interrupts and thus audiable clicks
Florian Meier96286b52014-01-06 20:18:24 +0100724 */
Martin Sperl92153bb2016-03-16 12:24:59 -0700725 if (buf_len % period_len)
726 dev_warn_once(chan->device->dev,
727 "%s: buffer_length (%zd) is not a multiple of period_len (%zd)\n",
728 __func__, buf_len, period_len);
Florian Meier96286b52014-01-06 20:18:24 +0100729
Martin Sperl92153bb2016-03-16 12:24:59 -0700730 /* Setup DREQ channel */
731 if (c->dreq != 0)
732 info |= BCM2835_DMA_PER_MAP(c->dreq);
Florian Meier96286b52014-01-06 20:18:24 +0100733
Martin Sperl92153bb2016-03-16 12:24:59 -0700734 if (direction == DMA_DEV_TO_MEM) {
735 if (c->cfg.src_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES)
736 return NULL;
737 src = c->cfg.src_addr;
738 dst = buf_addr;
739 info |= BCM2835_DMA_S_DREQ | BCM2835_DMA_D_INC;
740 } else {
741 if (c->cfg.dst_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES)
742 return NULL;
743 dst = c->cfg.dst_addr;
744 src = buf_addr;
745 info |= BCM2835_DMA_D_DREQ | BCM2835_DMA_S_INC;
Florian Meier96286b52014-01-06 20:18:24 +0100746 }
747
Martin Sperl92153bb2016-03-16 12:24:59 -0700748 /* calculate number of frames */
Martin Sperl40874122016-03-16 12:25:00 -0700749 frames = /* number of periods */
750 DIV_ROUND_UP(buf_len, period_len) *
751 /* number of frames per period */
752 bcm2835_dma_frames_for_length(period_len, max_len);
Martin Sperl92153bb2016-03-16 12:24:59 -0700753
754 /*
755 * allocate the CB chain
756 * note that we need to use GFP_NOWAIT, as the ALSA i2s dmaengine
757 * implementation calls prep_dma_cyclic with interrupts disabled.
758 */
759 d = bcm2835_dma_create_cb_chain(chan, direction, true,
760 info, extra,
761 frames, src, dst, buf_len,
762 period_len, GFP_NOWAIT);
763 if (!d)
764 return NULL;
765
766 /* wrap around into a loop */
767 d->cb_list[d->frames - 1].cb->next = d->cb_list[0].paddr;
768
Florian Meier96286b52014-01-06 20:18:24 +0100769 return vchan_tx_prep(&c->vc, &d->vd, flags);
770}
771
Maxime Ripard39159be2014-11-17 14:42:08 +0100772static int bcm2835_dma_slave_config(struct dma_chan *chan,
773 struct dma_slave_config *cfg)
Florian Meier96286b52014-01-06 20:18:24 +0100774{
Maxime Ripard39159be2014-11-17 14:42:08 +0100775 struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
776
Florian Meier96286b52014-01-06 20:18:24 +0100777 if ((cfg->direction == DMA_DEV_TO_MEM &&
778 cfg->src_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) ||
779 (cfg->direction == DMA_MEM_TO_DEV &&
780 cfg->dst_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) ||
781 !is_slave_direction(cfg->direction)) {
782 return -EINVAL;
783 }
784
785 c->cfg = *cfg;
786
787 return 0;
788}
789
Maxime Ripard39159be2014-11-17 14:42:08 +0100790static int bcm2835_dma_terminate_all(struct dma_chan *chan)
Florian Meier96286b52014-01-06 20:18:24 +0100791{
Maxime Ripard39159be2014-11-17 14:42:08 +0100792 struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
Florian Meier96286b52014-01-06 20:18:24 +0100793 struct bcm2835_dmadev *d = to_bcm2835_dma_dev(c->vc.chan.device);
794 unsigned long flags;
795 int timeout = 10000;
796 LIST_HEAD(head);
797
798 spin_lock_irqsave(&c->vc.lock, flags);
799
800 /* Prevent this channel being scheduled */
801 spin_lock(&d->lock);
802 list_del_init(&c->node);
803 spin_unlock(&d->lock);
804
805 /*
806 * Stop DMA activity: we assume the callback will not be called
807 * after bcm_dma_abort() returns (even if it does, it will see
808 * c->desc is NULL and exit.)
809 */
810 if (c->desc) {
Peter Ujfalusif9317822015-03-27 13:35:53 +0200811 bcm2835_dma_desc_free(&c->desc->vd);
Florian Meier96286b52014-01-06 20:18:24 +0100812 c->desc = NULL;
813 bcm2835_dma_abort(c->chan_base);
814
815 /* Wait for stopping */
816 while (--timeout) {
817 if (!(readl(c->chan_base + BCM2835_DMA_CS) &
818 BCM2835_DMA_ACTIVE))
819 break;
820
821 cpu_relax();
822 }
823
824 if (!timeout)
825 dev_err(d->ddev.dev, "DMA transfer could not be terminated\n");
826 }
827
828 vchan_get_all_descriptors(&c->vc, &head);
829 spin_unlock_irqrestore(&c->vc.lock, flags);
830 vchan_dma_desc_free_list(&c->vc, &head);
831
832 return 0;
833}
834
Martin Sperle2eca632016-04-11 13:29:08 +0000835static int bcm2835_dma_chan_init(struct bcm2835_dmadev *d, int chan_id,
836 int irq, unsigned int irq_flags)
Florian Meier96286b52014-01-06 20:18:24 +0100837{
838 struct bcm2835_chan *c;
839
840 c = devm_kzalloc(d->ddev.dev, sizeof(*c), GFP_KERNEL);
841 if (!c)
842 return -ENOMEM;
843
844 c->vc.desc_free = bcm2835_dma_desc_free;
845 vchan_init(&c->vc, &d->ddev);
846 INIT_LIST_HEAD(&c->node);
847
Florian Meier96286b52014-01-06 20:18:24 +0100848 c->chan_base = BCM2835_DMA_CHANIO(d->base, chan_id);
849 c->ch = chan_id;
850 c->irq_number = irq;
Martin Sperle2eca632016-04-11 13:29:08 +0000851 c->irq_flags = irq_flags;
Florian Meier96286b52014-01-06 20:18:24 +0100852
Martin Sperl40874122016-03-16 12:25:00 -0700853 /* check in DEBUG register if this is a LITE channel */
854 if (readl(c->chan_base + BCM2835_DMA_DEBUG) &
855 BCM2835_DMA_DEBUG_LITE)
856 c->is_lite_channel = true;
857
Florian Meier96286b52014-01-06 20:18:24 +0100858 return 0;
859}
860
861static void bcm2835_dma_free(struct bcm2835_dmadev *od)
862{
863 struct bcm2835_chan *c, *next;
864
865 list_for_each_entry_safe(c, next, &od->ddev.channels,
866 vc.chan.device_node) {
867 list_del(&c->vc.chan.device_node);
868 tasklet_kill(&c->vc.task);
869 }
870}
871
872static const struct of_device_id bcm2835_dma_of_match[] = {
873 { .compatible = "brcm,bcm2835-dma", },
874 {},
875};
876MODULE_DEVICE_TABLE(of, bcm2835_dma_of_match);
877
878static struct dma_chan *bcm2835_dma_xlate(struct of_phandle_args *spec,
879 struct of_dma *ofdma)
880{
881 struct bcm2835_dmadev *d = ofdma->of_dma_data;
882 struct dma_chan *chan;
883
884 chan = dma_get_any_slave_channel(&d->ddev);
885 if (!chan)
886 return NULL;
887
888 /* Set DREQ from param */
889 to_bcm2835_dma_chan(chan)->dreq = spec->args[0];
890
891 return chan;
892}
893
Florian Meier96286b52014-01-06 20:18:24 +0100894static int bcm2835_dma_probe(struct platform_device *pdev)
895{
896 struct bcm2835_dmadev *od;
897 struct resource *res;
898 void __iomem *base;
899 int rc;
Martin Sperle2eca632016-04-11 13:29:08 +0000900 int i, j;
901 int irq[BCM2835_DMA_MAX_DMA_CHAN_SUPPORTED + 1];
902 int irq_flags;
Florian Meier96286b52014-01-06 20:18:24 +0100903 uint32_t chans_available;
Martin Sperle2eca632016-04-11 13:29:08 +0000904 char chan_name[BCM2835_DMA_CHAN_NAME_SIZE];
Florian Meier96286b52014-01-06 20:18:24 +0100905
906 if (!pdev->dev.dma_mask)
907 pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
908
909 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
910 if (rc)
911 return rc;
912
913 od = devm_kzalloc(&pdev->dev, sizeof(*od), GFP_KERNEL);
914 if (!od)
915 return -ENOMEM;
916
917 pdev->dev.dma_parms = &od->dma_parms;
918 dma_set_max_seg_size(&pdev->dev, 0x3FFFFFFF);
919
920 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
921 base = devm_ioremap_resource(&pdev->dev, res);
922 if (IS_ERR(base))
923 return PTR_ERR(base);
924
925 od->base = base;
926
927 dma_cap_set(DMA_SLAVE, od->ddev.cap_mask);
Florian Meier7f5ae352014-01-17 18:06:29 +0100928 dma_cap_set(DMA_PRIVATE, od->ddev.cap_mask);
Florian Meier96286b52014-01-06 20:18:24 +0100929 dma_cap_set(DMA_CYCLIC, od->ddev.cap_mask);
Martin Sperl388cc7a2016-03-16 12:25:01 -0700930 dma_cap_set(DMA_SLAVE, od->ddev.cap_mask);
Martin Sperld9f094a2016-03-16 12:25:02 -0700931 dma_cap_set(DMA_MEMCPY, od->ddev.cap_mask);
Florian Meier96286b52014-01-06 20:18:24 +0100932 od->ddev.device_alloc_chan_resources = bcm2835_dma_alloc_chan_resources;
933 od->ddev.device_free_chan_resources = bcm2835_dma_free_chan_resources;
934 od->ddev.device_tx_status = bcm2835_dma_tx_status;
935 od->ddev.device_issue_pending = bcm2835_dma_issue_pending;
Florian Meier96286b52014-01-06 20:18:24 +0100936 od->ddev.device_prep_dma_cyclic = bcm2835_dma_prep_dma_cyclic;
Martin Sperl388cc7a2016-03-16 12:25:01 -0700937 od->ddev.device_prep_slave_sg = bcm2835_dma_prep_slave_sg;
Martin Sperld9f094a2016-03-16 12:25:02 -0700938 od->ddev.device_prep_dma_memcpy = bcm2835_dma_prep_dma_memcpy;
Maxime Ripard39159be2014-11-17 14:42:08 +0100939 od->ddev.device_config = bcm2835_dma_slave_config;
940 od->ddev.device_terminate_all = bcm2835_dma_terminate_all;
Maxime Ripardb5743682014-11-17 14:42:45 +0100941 od->ddev.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
942 od->ddev.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
Martin Sperld9f094a2016-03-16 12:25:02 -0700943 od->ddev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV) |
944 BIT(DMA_MEM_TO_MEM);
Martin Sperl0fa58672016-03-16 12:24:55 -0700945 od->ddev.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
Florian Meier96286b52014-01-06 20:18:24 +0100946 od->ddev.dev = &pdev->dev;
947 INIT_LIST_HEAD(&od->ddev.channels);
948 spin_lock_init(&od->lock);
949
950 platform_set_drvdata(pdev, od);
951
952 /* Request DMA channel mask from device tree */
953 if (of_property_read_u32(pdev->dev.of_node,
954 "brcm,dma-channel-mask",
955 &chans_available)) {
956 dev_err(&pdev->dev, "Failed to get channel mask\n");
957 rc = -EINVAL;
958 goto err_no_dma;
959 }
960
Martin Sperle2eca632016-04-11 13:29:08 +0000961 /* get irqs for each channel that we support */
962 for (i = 0; i <= BCM2835_DMA_MAX_DMA_CHAN_SUPPORTED; i++) {
963 /* skip masked out channels */
964 if (!(chans_available & (1 << i))) {
965 irq[i] = -1;
966 continue;
Florian Meier96286b52014-01-06 20:18:24 +0100967 }
Martin Sperle2eca632016-04-11 13:29:08 +0000968
969 /* get the named irq */
970 snprintf(chan_name, sizeof(chan_name), "dma%i", i);
971 irq[i] = platform_get_irq_byname(pdev, chan_name);
972 if (irq[i] >= 0)
973 continue;
974
975 /* legacy device tree case handling */
976 dev_warn_once(&pdev->dev,
Martin Sperl0eef7272016-04-22 07:12:48 +0000977 "missing interrupt-names property in device tree - legacy interpretation is used\n");
Martin Sperle2eca632016-04-11 13:29:08 +0000978 /*
979 * in case of channel >= 11
980 * use the 11th interrupt and that is shared
981 */
982 irq[i] = platform_get_irq(pdev, i < 11 ? i : 11);
983 }
984
985 /* get irqs for each channel */
986 for (i = 0; i <= BCM2835_DMA_MAX_DMA_CHAN_SUPPORTED; i++) {
987 /* skip channels without irq */
988 if (irq[i] < 0)
989 continue;
990
991 /* check if there are other channels that also use this irq */
992 irq_flags = 0;
993 for (j = 0; j <= BCM2835_DMA_MAX_DMA_CHAN_SUPPORTED; j++)
994 if ((i != j) && (irq[j] == irq[i])) {
995 irq_flags = IRQF_SHARED;
996 break;
997 }
998
999 /* initialize the channel */
1000 rc = bcm2835_dma_chan_init(od, i, irq[i], irq_flags);
1001 if (rc)
1002 goto err_no_dma;
Florian Meier96286b52014-01-06 20:18:24 +01001003 }
1004
1005 dev_dbg(&pdev->dev, "Initialized %i DMA channels\n", i);
1006
1007 /* Device-tree DMA controller registration */
1008 rc = of_dma_controller_register(pdev->dev.of_node,
1009 bcm2835_dma_xlate, od);
1010 if (rc) {
1011 dev_err(&pdev->dev, "Failed to register DMA controller\n");
1012 goto err_no_dma;
1013 }
1014
1015 rc = dma_async_device_register(&od->ddev);
1016 if (rc) {
1017 dev_err(&pdev->dev,
1018 "Failed to register slave DMA engine device: %d\n", rc);
1019 goto err_no_dma;
1020 }
1021
1022 dev_dbg(&pdev->dev, "Load BCM2835 DMA engine driver\n");
1023
1024 return 0;
1025
1026err_no_dma:
1027 bcm2835_dma_free(od);
1028 return rc;
1029}
1030
1031static int bcm2835_dma_remove(struct platform_device *pdev)
1032{
1033 struct bcm2835_dmadev *od = platform_get_drvdata(pdev);
1034
1035 dma_async_device_unregister(&od->ddev);
1036 bcm2835_dma_free(od);
1037
1038 return 0;
1039}
1040
1041static struct platform_driver bcm2835_dma_driver = {
1042 .probe = bcm2835_dma_probe,
1043 .remove = bcm2835_dma_remove,
1044 .driver = {
1045 .name = "bcm2835-dma",
Florian Meier96286b52014-01-06 20:18:24 +01001046 .of_match_table = of_match_ptr(bcm2835_dma_of_match),
1047 },
1048};
1049
1050module_platform_driver(bcm2835_dma_driver);
1051
1052MODULE_ALIAS("platform:bcm2835-dma");
1053MODULE_DESCRIPTION("BCM2835 DMA engine driver");
1054MODULE_AUTHOR("Florian Meier <florian.meier@koalo.de>");
1055MODULE_LICENSE("GPL v2");